twa(4): Sync with FreeBSD (twa(4) version 3.80.06.003).
[dragonfly.git] / sys / dev / raid / twa / tw_osl.h
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1/*
2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
4fbf05f9 27 * $FreeBSD: src/sys/dev/twa/tw_osl.h,v 1.9 2010/08/30 19:15:04 delphij Exp $
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28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 * Modifications by: Manjunath Ranganathaiah
36 */
37
38
39
40#ifndef TW_OSL_H
41
42#define TW_OSL_H
43
44
45/*
46 * OS Layer internal macros, structures and functions.
47 */
48
49
50#define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
51
52#define TW_OSLI_MALLOC_CLASS M_TWA
53#define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
54/* Reserve two command packets. One for ioctls and one for AENs */
55#define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
56#define TW_OSLI_MAX_NUM_AENS 0x100
57
58#ifdef PAE
59#define TW_OSLI_DMA_BOUNDARY (1u << 31)
60#else
61#define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
62#endif
63
64/* Possible values of req->state. */
65#define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
66#define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
67#define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
68#define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
69
70/* Possible values of req->flags. */
71#define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
72#define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
73#define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
74 have to copy to/from private buffer */
75#define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
76#define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
77 EINPROGRESS */
78#define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
79#define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
4fbf05f9 80#define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
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81
82
83#ifdef TW_OSL_DEBUG
84struct tw_osli_q_stats {
85 TW_UINT32 cur_len; /* current # of items in q */
86 TW_UINT32 max_len; /* max value reached by q_length */
87};
88#endif /* TW_OSL_DEBUG */
89
90
91/* Queues of OSL internal request context packets. */
92#define TW_OSLI_FREE_Q 0 /* free q */
93#define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
94#define TW_OSLI_Q_COUNT 2 /* total number of queues */
95
96/* Driver's request packet. */
97struct tw_osli_req_context {
98 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
99 struct lock ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
100 struct lock *ioctl_wake_timeout_lock;/* ptr to above lock */
101 struct twa_softc *ctlr; /* ptr to OSL's controller context */
102 TW_VOID *data; /* ptr to data being passed to CL */
103 TW_UINT32 length; /* length of buf being passed to CL */
4fbf05f9 104 TW_UINT64 deadline;/* request timeout (in absolute time) */
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105
106 /*
107 * ptr to, and length of data passed to us from above, in case a buffer
108 * copy was done due to non-compliance to alignment requirements
109 */
110 TW_VOID *real_data;
111 TW_UINT32 real_length;
112
113 TW_UINT32 state; /* request state */
114 TW_UINT32 flags; /* request flags */
115
116 /* error encountered before request submission to CL */
117 TW_UINT32 error_code;
118
119 /* ptr to orig req for use during callback */
120 TW_VOID *orig_req;
121
122 struct tw_cl_link link; /* to link this request in a list */
123 bus_dmamap_t dma_map;/* DMA map for data */
124 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
125};
126
127
128/* Per-controller structure. */
129struct twa_softc {
130 struct tw_cl_ctlr_handle ctlr_handle;
131 struct tw_osli_req_context *req_ctx_buf;
132
133 /* Controller state. */
134 TW_UINT8 open;
135 TW_UINT32 flags;
136
137 TW_INT32 device_id;
138 TW_UINT32 alignment;
139 TW_UINT32 sg_size_factor;
140
141 TW_VOID *non_dma_mem;
142 TW_VOID *dma_mem;
143 TW_UINT64 dma_mem_phys;
144
145 /* Request queues and arrays. */
146 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
147
148 struct task deferred_intr_callback;/* taskqueue function */
149 struct spinlock io_lock_handle;/* general purpose lock */
150 struct spinlock *io_lock;/* ptr to general purpose lock */
151 struct spinlock q_lock_handle; /* queue manipulation lock */
152 struct spinlock *q_lock;/* ptr to queue manipulation lock */
153 struct lock sim_lock_handle;/* sim lock shared with cam */
154 struct lock *sim_lock;/* ptr to sim lock */
155
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156 struct callout watchdog_callout[2]; /* For command timout */
157 TW_UINT32 watchdog_index;
158
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159#ifdef TW_OSL_DEBUG
160 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
161#endif /* TW_OSL_DEBUG */
162
163 device_t bus_dev; /* bus device */
164 struct cdev *ctrl_dev; /* control device */
165 struct resource *reg_res; /* register interface window */
166 TW_INT32 reg_res_id; /* register resource id */
167 bus_space_handle_t bus_handle; /* bus space handle */
168 bus_space_tag_t bus_tag; /* bus space tag */
169 bus_dma_tag_t parent_tag; /* parent DMA tag */
170 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
171 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
172 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
173 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
174 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
175 struct resource *irq_res; /* interrupt resource */
176 TW_INT32 irq_res_id; /* register resource id */
177 TW_VOID *intr_handle; /* interrupt handle */
178
179 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
180 struct sysctl_oid *sysctl_tree; /* sysctl oid */
181
182 struct cam_sim *sim; /* sim for this controller */
183 struct cam_path *path; /* peripheral, path, tgt, lun
184 associated with this controller */
185};
186
187
188
189/*
190 * Queue primitives.
191 */
192
193#ifdef TW_OSL_DEBUG
194
195#define TW_OSLI_Q_INIT(sc, q_type) do { \
196 (sc)->q_stats[q_type].cur_len = 0; \
197 (sc)->q_stats[q_type].max_len = 0; \
198} while(0)
199
200
201#define TW_OSLI_Q_INSERT(sc, q_type) do { \
202 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
203 \
204 if (++(q_stats->cur_len) > q_stats->max_len) \
205 q_stats->max_len = q_stats->cur_len; \
206} while(0)
207
208
209#define TW_OSLI_Q_REMOVE(sc, q_type) \
210 (sc)->q_stats[q_type].cur_len--
211
212
213#else /* TW_OSL_DEBUG */
214
215#define TW_OSLI_Q_INIT(sc, q_index)
216#define TW_OSLI_Q_INSERT(sc, q_index)
217#define TW_OSLI_Q_REMOVE(sc, q_index)
218
219#endif /* TW_OSL_DEBUG */
220
221
222
223/* Initialize a queue of requests. */
224static __inline TW_VOID
225tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
226{
227 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
228 TW_OSLI_Q_INIT(sc, q_type);
229}
230
231
232
233/* Insert the given request at the head of the given queue (q_type). */
234static __inline TW_VOID
235tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
236{
287a8577 237 spin_lock(req->ctlr->q_lock);
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238 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
239 TW_OSLI_Q_INSERT(req->ctlr, q_type);
287a8577 240 spin_unlock(req->ctlr->q_lock);
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241}
242
243
244
245/* Insert the given request at the tail of the given queue (q_type). */
246static __inline TW_VOID
247tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
248{
287a8577 249 spin_lock(req->ctlr->q_lock);
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250 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
251 TW_OSLI_Q_INSERT(req->ctlr, q_type);
287a8577 252 spin_unlock(req->ctlr->q_lock);
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253}
254
255
256
257/* Remove and return the request at the head of the given queue (q_type). */
258static __inline struct tw_osli_req_context *
259tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
260{
261 struct tw_osli_req_context *req = NULL;
262 struct tw_cl_link *link;
263
287a8577 264 spin_lock(sc->q_lock);
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265 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
266 TW_CL_NULL) {
267 req = TW_CL_STRUCT_HEAD(link,
268 struct tw_osli_req_context, link);
269 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
270 TW_OSLI_Q_REMOVE(sc, q_type);
271 }
287a8577 272 spin_unlock(sc->q_lock);
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273 return(req);
274}
275
276
277
278/* Remove the given request from the given queue (q_type). */
279static __inline TW_VOID
280tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
281{
287a8577 282 spin_lock(req->ctlr->q_lock);
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283 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
284 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
287a8577 285 spin_unlock(req->ctlr->q_lock);
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286}
287
288
289
290#ifdef TW_OSL_DEBUG
291
292extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
293
294#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
295 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
296 device_printf(sc->bus_dev, "%s: " fmt "\n", \
297 __func__, ##args)
298
299
300#define tw_osli_dbg_printf(dbg_level, fmt, args...) \
301 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
302 kprintf("%s: " fmt "\n", __func__, ##args)
303
304#else /* TW_OSL_DEBUG */
305
306#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
307#define tw_osli_dbg_printf(dbg_level, fmt, args...)
308
309#endif /* TW_OSL_DEBUG */
310
311
312/* For regular printing. */
313#define twa_printf(sc, fmt, args...) \
314 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
315
316/* For printing in the "consistent error reporting" format. */
317#define tw_osli_printf(sc, err_specific_desc, args...) \
318 device_printf((sc)->bus_dev, \
319 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
320
321
322
323#endif /* TW_OSL_H */