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ig_hal/em/emx: Add I219 (Skylake) support
[dragonfly.git] / sys / dev / netif / em / if_em.c
CommitLineData
78195a76 1/*
78195a76
MD		 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4765c386 4 * Copyright (c) 2001-2014, Intel Corporation
78195a76
MD		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
78195a76
MD		 10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
78195a76
MD		 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
78195a76
MD		 17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
78195a76
MD		 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
78195a76
MD		 36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
78195a76
MD		 39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
78195a76
MD		 43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
78195a76
MD		 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
78195a76
MD		 66 */
67/*
68 * SERIALIZATION API RULES:
69 *
9c80d176
SZ		 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the
71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
72 * the hardware interrupt in order to avoid handler execution races from
73 * scheduled interrupt threads.
78195a76 74 */
2b71c8f1 75
350d9c84 76#include "opt_ifpoll.h"
87307ba1
SZ		 77
78#include <sys/param.h>
79#include <sys/bus.h>
80#include <sys/endian.h>
9db4b353 81#include <sys/interrupt.h>
87307ba1
SZ		 82#include <sys/kernel.h>
83#include <sys/ktr.h>
84#include <sys/malloc.h>
85#include <sys/mbuf.h>
9c80d176 86#include <sys/proc.h>
87307ba1
SZ		 87#include <sys/rman.h>
88#include <sys/serialize.h>
89#include <sys/socket.h>
90#include <sys/sockio.h>
91#include <sys/sysctl.h>
9c80d176 92#include <sys/systm.h>
87307ba1
SZ		 93
94#include <net/bpf.h>
95#include <net/ethernet.h>
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/if_dl.h>
99#include <net/if_media.h>
350d9c84 100#include <net/if_poll.h>
87307ba1
SZ		 101#include <net/ifq_var.h>
102#include <net/vlan/if_vlan_var.h>
b637f170 103#include <net/vlan/if_vlan_ether.h>
87307ba1 104
87307ba1
SZ		 105#include <netinet/ip.h>
106#include <netinet/tcp.h>
107#include <netinet/udp.h>
984263bc 108
9c80d176
SZ		 109#include <bus/pci/pcivar.h>
110#include <bus/pci/pcireg.h>
984263bc 111
9c80d176
SZ		 112#include <dev/netif/ig_hal/e1000_api.h>
113#include <dev/netif/ig_hal/e1000_82571.h>
efd6aee8 114#include <dev/netif/ig_hal/e1000_dragonfly.h>
9c80d176 115#include <dev/netif/em/if_em.h>
984263bc 116
b2653751
SW		 117#define DEBUG_HW 0
118
9c80d176 119#define EM_NAME "Intel(R) PRO/1000 Network Connection "
4765c386 120#define EM_VER " 7.4.2"
9c80d176 121
96ced48a
SZ		 122#define _EM_DEVICE(id, ret) \
123 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
124#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
125#define EM_DEVICE(id) _EM_DEVICE(id, 0)
126#define EM_DEVICE_NULL { 0, 0, 0, NULL }
9c80d176
SZ		 127
128static const struct em_vendor_info em_vendor_info_array[] = {
129 EM_DEVICE(82540EM),
130 EM_DEVICE(82540EM_LOM),
131 EM_DEVICE(82540EP),
132 EM_DEVICE(82540EP_LOM),
133 EM_DEVICE(82540EP_LP),
134
135 EM_DEVICE(82541EI),
136 EM_DEVICE(82541ER),
137 EM_DEVICE(82541ER_LOM),
138 EM_DEVICE(82541EI_MOBILE),
139 EM_DEVICE(82541GI),
140 EM_DEVICE(82541GI_LF),
141 EM_DEVICE(82541GI_MOBILE),
142
143 EM_DEVICE(82542),
144
145 EM_DEVICE(82543GC_FIBER),
146 EM_DEVICE(82543GC_COPPER),
147
148 EM_DEVICE(82544EI_COPPER),
149 EM_DEVICE(82544EI_FIBER),
150 EM_DEVICE(82544GC_COPPER),
151 EM_DEVICE(82544GC_LOM),
152
153 EM_DEVICE(82545EM_COPPER),
154 EM_DEVICE(82545EM_FIBER),
155 EM_DEVICE(82545GM_COPPER),
156 EM_DEVICE(82545GM_FIBER),
157 EM_DEVICE(82545GM_SERDES),
158
159 EM_DEVICE(82546EB_COPPER),
160 EM_DEVICE(82546EB_FIBER),
161 EM_DEVICE(82546EB_QUAD_COPPER),
162 EM_DEVICE(82546GB_COPPER),
163 EM_DEVICE(82546GB_FIBER),
164 EM_DEVICE(82546GB_SERDES),
165 EM_DEVICE(82546GB_PCIE),
166 EM_DEVICE(82546GB_QUAD_COPPER),
167 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
168
169 EM_DEVICE(82547EI),
170 EM_DEVICE(82547EI_MOBILE),
171 EM_DEVICE(82547GI),
172
96ced48a
SZ		 173 EM_EMX_DEVICE(82571EB_COPPER),
174 EM_EMX_DEVICE(82571EB_FIBER),
175 EM_EMX_DEVICE(82571EB_SERDES),
176 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
177 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
178 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
96ced48a
SZ		 180 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
181 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
182 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
183
184 EM_EMX_DEVICE(82572EI_COPPER),
185 EM_EMX_DEVICE(82572EI_FIBER),
186 EM_EMX_DEVICE(82572EI_SERDES),
187 EM_EMX_DEVICE(82572EI),
188
189 EM_EMX_DEVICE(82573E),
190 EM_EMX_DEVICE(82573E_IAMT),
191 EM_EMX_DEVICE(82573L),
192
2d0e5700
SZ		 193 EM_DEVICE(82583V),
194
96ced48a
SZ		 195 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
196 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
197 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
198 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
9c80d176
SZ		 199
200 EM_DEVICE(ICH8_IGP_M_AMT),
201 EM_DEVICE(ICH8_IGP_AMT),
202 EM_DEVICE(ICH8_IGP_C),
203 EM_DEVICE(ICH8_IFE),
204 EM_DEVICE(ICH8_IFE_GT),
205 EM_DEVICE(ICH8_IFE_G),
206 EM_DEVICE(ICH8_IGP_M),
2d0e5700 207 EM_DEVICE(ICH8_82567V_3),
9c80d176
SZ		 208
209 EM_DEVICE(ICH9_IGP_M_AMT),
210 EM_DEVICE(ICH9_IGP_AMT),
211 EM_DEVICE(ICH9_IGP_C),
212 EM_DEVICE(ICH9_IGP_M),
213 EM_DEVICE(ICH9_IGP_M_V),
214 EM_DEVICE(ICH9_IFE),
215 EM_DEVICE(ICH9_IFE_GT),
216 EM_DEVICE(ICH9_IFE_G),
217 EM_DEVICE(ICH9_BM),
218
96ced48a 219 EM_EMX_DEVICE(82574L),
2d0e5700 220 EM_EMX_DEVICE(82574LA),
9c80d176
SZ		 221
222 EM_DEVICE(ICH10_R_BM_LM),
223 EM_DEVICE(ICH10_R_BM_LF),
224 EM_DEVICE(ICH10_R_BM_V),
225 EM_DEVICE(ICH10_D_BM_LM),
226 EM_DEVICE(ICH10_D_BM_LF),
2d0e5700
SZ		 227 EM_DEVICE(ICH10_D_BM_V),
228
229 EM_DEVICE(PCH_M_HV_LM),
230 EM_DEVICE(PCH_M_HV_LC),
231 EM_DEVICE(PCH_D_HV_DM),
232 EM_DEVICE(PCH_D_HV_DC),
233
234 EM_DEVICE(PCH2_LV_LM),
235 EM_DEVICE(PCH2_LV_V),
984263bc 236
a5807b81
SZ		 237 EM_EMX_DEVICE(PCH_LPT_I217_LM),
238 EM_EMX_DEVICE(PCH_LPT_I217_V),
239 EM_EMX_DEVICE(PCH_LPTLP_I218_LM),
240 EM_EMX_DEVICE(PCH_LPTLP_I218_V),
4765c386
MN		 241 EM_EMX_DEVICE(PCH_I218_LM2),
242 EM_EMX_DEVICE(PCH_I218_V2),
243 EM_EMX_DEVICE(PCH_I218_LM3),
244 EM_EMX_DEVICE(PCH_I218_V3),
524ce499
SZ		 245 EM_EMX_DEVICE(PCH_SPT_I219_LM),
246 EM_EMX_DEVICE(PCH_SPT_I219_V),
247 EM_EMX_DEVICE(PCH_SPT_I219_LM2),
248 EM_EMX_DEVICE(PCH_SPT_I219_V2),
91c72bdc 249
f647ad3d 250 /* required last entry */
9c80d176 251 EM_DEVICE_NULL
984263bc
MD		 252};
253
f647ad3d
JS		 254static int em_probe(device_t);
255static int em_attach(device_t);
256static int em_detach(device_t);
257static int em_shutdown(device_t);
87307ba1
SZ		 258static int em_suspend(device_t);
259static int em_resume(device_t);
9c80d176
SZ		 260
261static void em_init(void *);
262static void em_stop(struct adapter *);
f647ad3d 263static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
f0a26983 264static void em_start(struct ifnet *, struct ifaltq_subque *);
350d9c84
SZ		 265#ifdef IFPOLL_ENABLE
266static void em_npoll(struct ifnet *, struct ifpoll_info *);
267static void em_npoll_compat(struct ifnet *, void *, int);
9c80d176 268#endif
f647ad3d 269static void em_watchdog(struct ifnet *);
f647ad3d
JS		 270static void em_media_status(struct ifnet *, struct ifmediareq *);
271static int em_media_change(struct ifnet *);
9c80d176
SZ		 272static void em_timer(void *);
273
274static void em_intr(void *);
87ab432b
SZ		 275static void em_intr_mask(void *);
276static void em_intr_body(struct adapter *, boolean_t);
9c80d176
SZ		 277static void em_rxeof(struct adapter *, int);
278static void em_txeof(struct adapter *);
9f60d74b 279static void em_tx_collect(struct adapter *);
9c80d176 280static void em_tx_purge(struct adapter *);
f647ad3d
JS		 281static void em_enable_intr(struct adapter *);
282static void em_disable_intr(struct adapter *);
9c80d176
SZ		 283
284static int em_dma_malloc(struct adapter *, bus_size_t,
285 struct em_dma_alloc *);
286static void em_dma_free(struct adapter *, struct em_dma_alloc *);
287static void em_init_tx_ring(struct adapter *);
288static int em_init_rx_ring(struct adapter *);
289static int em_create_tx_ring(struct adapter *);
290static int em_create_rx_ring(struct adapter *);
291static void em_destroy_tx_ring(struct adapter *, int);
292static void em_destroy_rx_ring(struct adapter *, int);
293static int em_newbuf(struct adapter *, int, int);
893bb181 294static int em_encap(struct adapter *, struct mbuf **, int *, int *);
9c80d176
SZ		 295static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
296 struct mbuf *);
9f60d74b 297static int em_txcsum(struct adapter *, struct mbuf *,
9c80d176 298 uint32_t *, uint32_t *);
0bbb59f3
SZ		 299static int em_tso_pullup(struct adapter *, struct mbuf **);
300static int em_tso_setup(struct adapter *, struct mbuf *,
301 uint32_t *, uint32_t *);
9c80d176
SZ		 302
303static int em_get_hw_info(struct adapter *);
304static int em_is_valid_eaddr(const uint8_t *);
305static int em_alloc_pci_res(struct adapter *);
306static void em_free_pci_res(struct adapter *);
2d0e5700 307static int em_reset(struct adapter *);
9c80d176
SZ		 308static void em_setup_ifp(struct adapter *);
309static void em_init_tx_unit(struct adapter *);
310static void em_init_rx_unit(struct adapter *);
311static void em_update_stats(struct adapter *);
f647ad3d
JS		 312static void em_set_promisc(struct adapter *);
313static void em_disable_promisc(struct adapter *);
314static void em_set_multi(struct adapter *);
87307ba1 315static void em_update_link_status(struct adapter *);
f647ad3d 316static void em_smartspeed(struct adapter *);
2d0e5700 317static void em_set_itr(struct adapter *, uint32_t);
6d5e2922 318static void em_disable_aspm(struct adapter *);
9c80d176
SZ		 319
320/* Hardware workarounds */
f647ad3d
JS		 321static int em_82547_fifo_workaround(struct adapter *, int);
322static void em_82547_update_fifo_head(struct adapter *, int);
323static int em_82547_tx_fifo_reset(struct adapter *);
1eca7b82
SZ		 324static void em_82547_move_tail(void *);
325static void em_82547_move_tail_serialized(struct adapter *);
9c80d176
SZ		 326static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
327
f647ad3d 328static void em_print_debug_info(struct adapter *);
9c80d176
SZ		 329static void em_print_nvm_info(struct adapter *);
330static void em_print_hw_stats(struct adapter *);
331
f647ad3d
JS		 332static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
333static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 334static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 335static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 336static void em_add_sysctl(struct adapter *adapter);
984263bc 337
9c80d176
SZ		 338/* Management and WOL Support */
339static void em_get_mgmt(struct adapter *);
340static void em_rel_mgmt(struct adapter *);
341static void em_get_hw_control(struct adapter *);
342static void em_rel_hw_control(struct adapter *);
343static void em_enable_wol(device_t);
984263bc
MD		 344
345static device_method_t em_methods[] = {
346 /* Device interface */
9c80d176
SZ		 347 DEVMETHOD(device_probe, em_probe),
348 DEVMETHOD(device_attach, em_attach),
349 DEVMETHOD(device_detach, em_detach),
350 DEVMETHOD(device_shutdown, em_shutdown),
351 DEVMETHOD(device_suspend, em_suspend),
352 DEVMETHOD(device_resume, em_resume),
d3c9c58e 353 DEVMETHOD_END
984263bc
MD		 354};
355
356static driver_t em_driver = {
9c80d176
SZ		 357 "em",
358 em_methods,
359 sizeof(struct adapter),
984263bc
MD		 360};
361
362static devclass_t em_devclass;
32832096
MD		 363
364DECLARE_DUMMY_MODULE(if_em);
9c80d176 365MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 366DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 367
91e8debf
SZ		 368/*
369 * Tunables
370 */
9c80d176
SZ		 371static int em_int_throttle_ceil = EM_DEFAULT_ITR;
372static int em_rxd = EM_DEFAULT_RXD;
373static int em_txd = EM_DEFAULT_TXD;
053f3ae6 374static int em_smart_pwr_down = 0;
0d366ee7 375
9c80d176
SZ		 376/* Controls whether promiscuous also shows bad packets */
377static int em_debug_sbp = FALSE;
0d366ee7 378
053f3ae6
SZ		 379static int em_82573_workaround = 1;
380static int em_msi_enable = 1;
05580856 381
81ac62f7 382static char em_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
d76227df 383
d0870c72 384TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
1eca7b82
SZ		 385TUNABLE_INT("hw.em.rxd", &em_rxd);
386TUNABLE_INT("hw.em.txd", &em_txd);
387TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 388TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 389TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
053f3ae6 390TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
d76227df 391TUNABLE_STR("hw.em.flow_ctrl", em_flowctrl, sizeof(em_flowctrl));
9c80d176
SZ		 392
393/* Global used in WOL setup with multiport cards */
394static int em_global_quad_port_a = 0;
395
396/* Set this to one to display debug statistics */
397static int em_display_debug_stats = 0;
0d366ee7 398
07855a48
MD		 399#if !defined(KTR_IF_EM)
400#define KTR_IF_EM KTR_ALL
401#endif
402KTR_INFO_MASTER(if_em);
5bf48697
AE		 403KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
404KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
405KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
406KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
407KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
07855a48
MD		 408#define logif(name) KTR_LOG(if_em_ ## name)
409
984263bc
MD		 410static int
411em_probe(device_t dev)
412{
9c80d176
SZ		 413 const struct em_vendor_info *ent;
414 uint16_t vid, did;
984263bc 415
9c80d176
SZ		 416 vid = pci_get_vendor(dev);
417 did = pci_get_device(dev);
984263bc 418
9c80d176
SZ		 419 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
420 if (vid == ent->vendor_id && did == ent->device_id) {
421 device_set_desc(dev, ent->desc);
dbcd0c9b 422 device_set_async_attach(dev, TRUE);
96ced48a 423 return (ent->ret);
984263bc 424 }
984263bc 425 }
87307ba1 426 return (ENXIO);
984263bc
MD		 427}
428
984263bc
MD		 429static int
430em_attach(device_t dev)
431{
9c80d176
SZ		 432 struct adapter *adapter = device_get_softc(dev);
433 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d
JS		 434 int tsize, rsize;
435 int error = 0;
2d0e5700 436 uint16_t eeprom_data, device_id, apme_mask;
87ab432b 437 driver_intr_t *intr_func;
81ac62f7 438 char flowctrl[IFM_ETH_FC_STRLEN];
984263bc 439
9c80d176 440 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 441
bf0ecf68
MD		 442 callout_init_mp(&adapter->timer);
443 callout_init_mp(&adapter->tx_fifo_timer);
af82d4bb 444
81ac62f7 445 ifmedia_init(&adapter->media, IFM_IMASK | IFM_ETH_FCMASK,
d2811227
SZ		 446 em_media_change, em_media_status);
447
9c80d176
SZ		 448 /* Determine hardware and mac info */
449 error = em_get_hw_info(adapter);
450 if (error) {
451 device_printf(dev, "Identify hardware failed\n");
452 goto fail;
f647ad3d
JS		 453 }
454
9c80d176
SZ		 455 /* Setup PCI resources */
456 error = em_alloc_pci_res(adapter);
457 if (error) {
458 device_printf(dev, "Allocation of PCI resources failed\n");
459 goto fail;
460 }
984263bc 461
9c80d176
SZ		 462 /*
463 * For ICH8 and family we need to map the flash memory,
464 * and this must happen after the MAC is identified.
524ce499
SZ		 465 *
466 * (SPT does not map the flash with a separate BAR)
9c80d176
SZ		 467 */
468 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 469 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 470 adapter->hw.mac.type == e1000_ich10lan ||
2d0e5700 471 adapter->hw.mac.type == e1000_pchlan ||
91c72bdc
SZ		 472 adapter->hw.mac.type == e1000_pch2lan ||
473 adapter->hw.mac.type == e1000_pch_lpt) {
9c80d176
SZ		 474 adapter->flash_rid = EM_BAR_FLASH;
475
476 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
477 &adapter->flash_rid, RF_ACTIVE);
478 if (adapter->flash == NULL) {
479 device_printf(dev, "Mapping of Flash failed\n");
480 error = ENXIO;
481 goto fail;
482 }
483 adapter->osdep.flash_bus_space_tag =
484 rman_get_bustag(adapter->flash);
485 adapter->osdep.flash_bus_space_handle =
486 rman_get_bushandle(adapter->flash);
984263bc 487
9c80d176
SZ		 488 /*
489 * This is used in the shared code
490 * XXX this goof is actually not used.
491 */
492 adapter->hw.flash_address = (uint8_t *)adapter->flash;
493 }
0d366ee7 494
0bbb59f3
SZ		 495 switch (adapter->hw.mac.type) {
496 case e1000_82571:
497 case e1000_82572:
1fabd251 498 case e1000_pch_lpt:
524ce499 499 case e1000_pch_spt:
0bbb59f3 500 /*
1fabd251
SZ		 501 * Pullup extra 4bytes into the first data segment for
502 * TSO, see:
0bbb59f3
SZ		 503 * 82571/82572 specification update errata #7
504 *
524ce499 505 * Same applies to I217 (and maybe I218 and I219).
1fabd251 506 *
0bbb59f3
SZ		 507 * NOTE:
508 * 4bytes instead of 2bytes, which are mentioned in the
509 * errata, are pulled; mainly to keep rest of the data
510 * properly aligned.
511 */
512 adapter->flags |= EM_FLAG_TSO_PULLEX;
513 /* FALL THROUGH */
514
0bbb59f3 515 default:
4c67d01d
SZ		 516 if (pci_is_pcie(dev))
517 adapter->flags |= EM_FLAG_TSO;
0bbb59f3
SZ		 518 break;
519 }
520
9c80d176
SZ		 521 /* Do Shared Code initialization */
522 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
523 device_printf(dev, "Setup of Shared code failed\n");
524 error = ENXIO;
525 goto fail;
f647ad3d 526 }
7ea52455 527
9c80d176
SZ		 528 e1000_get_bus_info(&adapter->hw);
529
1eca7b82 530 /*
9c80d176 531 * Validate number of transmit and receive descriptors. It
1eca7b82 532 * must not exceed hardware maximum, and must be multiple
9c80d176 533 * of E1000_DBA_ALIGN.
1eca7b82 534 */
9c80d176
SZ		 535 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
536 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
537 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
538 em_txd < EM_MIN_TXD) {
bccf0cdc
SZ		 539 if (adapter->hw.mac.type < e1000_82544)
540 adapter->num_tx_desc = EM_MAX_TXD_82543;
541 else
542 adapter->num_tx_desc = EM_DEFAULT_TXD;
1eca7b82 543 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
bccf0cdc 544 adapter->num_tx_desc, em_txd);
1eca7b82
SZ		 545 } else {
546 adapter->num_tx_desc = em_txd;
547 }
9c80d176
SZ		 548 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
549 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
550 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
551 em_rxd < EM_MIN_RXD) {
bccf0cdc
SZ		 552 if (adapter->hw.mac.type < e1000_82544)
553 adapter->num_rx_desc = EM_MAX_RXD_82543;
554 else
555 adapter->num_rx_desc = EM_DEFAULT_RXD;
1eca7b82 556 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
bccf0cdc 557 adapter->num_rx_desc, em_rxd);
1eca7b82
SZ		 558 } else {
559 adapter->num_rx_desc = em_rxd;
560 }
561
9c80d176
SZ		 562 adapter->hw.mac.autoneg = DO_AUTO_NEG;
563 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
564 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
565 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 566
9c80d176
SZ		 567 /*
568 * Interrupt throttle rate
569 */
570 if (em_int_throttle_ceil == 0) {
571 adapter->int_throttle_ceil = 0;
572 } else {
573 int throttle = em_int_throttle_ceil;
f647ad3d 574
9c80d176
SZ		 575 if (throttle < 0)
576 throttle = EM_DEFAULT_ITR;
0d366ee7 577
9c80d176
SZ		 578 /* Recalculate the tunable value to get the exact frequency. */
579 throttle = 1000000000 / 256 / throttle;
664c7645
SZ		 580
581 /* Upper 16bits of ITR is reserved and should be zero */
582 if (throttle & 0xffff0000)
583 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
584
9c80d176
SZ		 585 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
586 }
984263bc 587
9c80d176
SZ		 588 e1000_init_script_state_82541(&adapter->hw, TRUE);
589 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
590
591 /* Copper options */
592 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
593 adapter->hw.phy.mdix = AUTO_ALL_MODES;
594 adapter->hw.phy.disable_polarity_correction = FALSE;
595 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
596 }
597
598 /* Set the frame limits assuming standard ethernet sized frames. */
c29e94c0
SZ		 599 adapter->hw.mac.max_frame_size =
600 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
9c80d176 601 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 602
9c80d176
SZ		 603 /* This controls when hardware reports transmit completion status. */
604 adapter->hw.mac.report_tx_early = 1;
984263bc 605
87307ba1 606 /*
9c80d176 607 * Create top level busdma tag
984263bc 608 */
9c80d176
SZ		 609 error = bus_dma_tag_create(NULL, 1, 0,
610 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
611 NULL, NULL,
612 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
613 0, &adapter->parent_dtag);
614 if (error) {
615 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 616 goto fail;
9c80d176 617 }
af82d4bb 618
9c80d176
SZ		 619 /*
620 * Allocate Transmit Descriptor ring
621 */
622 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 623 EM_DBA_ALIGN);
87307ba1
SZ		 624 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
625 if (error) {
9c80d176 626 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 627 goto fail;
984263bc 628 }
9c80d176 629 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 630
9c80d176
SZ		 631 /*
632 * Allocate Receive Descriptor ring
633 */
634 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 635 EM_DBA_ALIGN);
87307ba1
SZ		 636 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
637 if (error) {
9ccd8c1f 638 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 639 goto fail;
984263bc 640 }
9c80d176
SZ		 641 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
642
2d0e5700
SZ		 643 /* Allocate multicast array memory. */
644 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
645 M_DEVBUF, M_WAITOK);
646
647 /* Indicate SOL/IDER usage */
648 if (e1000_check_reset_block(&adapter->hw)) {
649 device_printf(dev,
650 "PHY reset is blocked due to SOL/IDER session.\n");
651 }
652
d7f70105
SZ		 653 /* Disable EEE */
654 adapter->hw.dev_spec.ich8lan.eee_disable = 1;
655
2d0e5700
SZ		 656 /*
657 * Start from a known state, this is important in reading the
658 * nvm and mac from that.
659 */
660 e1000_reset_hw(&adapter->hw);
661
9c80d176
SZ		 662 /* Make sure we have a good EEPROM before we read from it */
663 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
664 /*
665 * Some PCI-E parts fail the first check due to
666 * the link being in sleep state, call it again,
667 * if it fails a second time its a real issue.
668 */
669 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
670 device_printf(dev,
671 "The EEPROM Checksum Is Not Valid\n");
672 error = EIO;
673 goto fail;
674 }
675 }
984263bc 676
984263bc 677 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ		 678 if (e1000_read_mac_addr(&adapter->hw) < 0) {
679 device_printf(dev, "EEPROM read error while reading MAC"
680 " address\n");
984263bc 681 error = EIO;
af82d4bb 682 goto fail;
984263bc 683 }
9c80d176 684 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 685 device_printf(dev, "Invalid MAC address\n");
984263bc 686 error = EIO;
af82d4bb 687 goto fail;
984263bc
MD		 688 }
689
4765c386
MN		 690 /* Disable ULP support */
691 e1000_disable_ulp_lpt_lp(&adapter->hw, TRUE);
692
9c80d176
SZ		 693 /* Allocate transmit descriptors and buffers */
694 error = em_create_tx_ring(adapter);
695 if (error) {
696 device_printf(dev, "Could not setup transmit structures\n");
697 goto fail;
698 }
699
700 /* Allocate receive descriptors and buffers */
701 error = em_create_rx_ring(adapter);
702 if (error) {
703 device_printf(dev, "Could not setup receive structures\n");
704 goto fail;
705 }
706
707 /* Manually turn off all interrupts */
708 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
709
9c80d176 710 /* Determine if we have to control management hardware */
79878f87
SZ		 711 if (e1000_enable_mng_pass_thru(&adapter->hw))
712 adapter->flags |= EM_FLAG_HAS_MGMT;
9c80d176
SZ		 713
714 /*
715 * Setup Wake-on-Lan
716 */
2d0e5700
SZ		 717 apme_mask = EM_EEPROM_APME;
718 eeprom_data = 0;
9c80d176
SZ		 719 switch (adapter->hw.mac.type) {
720 case e1000_82542:
721 case e1000_82543:
722 break;
723
2d0e5700
SZ		 724 case e1000_82573:
725 case e1000_82583:
79878f87 726 adapter->flags |= EM_FLAG_HAS_AMT;
2d0e5700
SZ		 727 /* FALL THROUGH */
728
9c80d176
SZ		 729 case e1000_82546:
730 case e1000_82546_rev_3:
731 case e1000_82571:
2d0e5700 732 case e1000_82572:
9c80d176
SZ		 733 case e1000_80003es2lan:
734 if (adapter->hw.bus.func == 1) {
735 e1000_read_nvm(&adapter->hw,
736 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
737 } else {
738 e1000_read_nvm(&adapter->hw,
739 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
740 }
2d0e5700
SZ		 741 break;
742
743 case e1000_ich8lan:
744 case e1000_ich9lan:
745 case e1000_ich10lan:
746 case e1000_pchlan:
747 case e1000_pch2lan:
748 apme_mask = E1000_WUC_APME;
79878f87 749 adapter->flags |= EM_FLAG_HAS_AMT;
2d0e5700 750 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ		 751 break;
752
753 default:
2d0e5700
SZ		 754 e1000_read_nvm(&adapter->hw,
755 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ		 756 break;
757 }
2d0e5700
SZ		 758 if (eeprom_data & apme_mask)
759 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
760
9c80d176
SZ		 761 /*
762 * We have the eeprom settings, now apply the special cases
763 * where the eeprom may be wrong or the board won't support
764 * wake on lan on a particular port
765 */
766 device_id = pci_get_device(dev);
767 switch (device_id) {
768 case E1000_DEV_ID_82546GB_PCIE:
769 adapter->wol = 0;
770 break;
771
772 case E1000_DEV_ID_82546EB_FIBER:
773 case E1000_DEV_ID_82546GB_FIBER:
774 case E1000_DEV_ID_82571EB_FIBER:
775 /*
776 * Wake events only supported on port A for dual fiber
777 * regardless of eeprom setting
778 */
779 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
780 E1000_STATUS_FUNC_1)
781 adapter->wol = 0;
782 break;
783
784 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
785 case E1000_DEV_ID_82571EB_QUAD_COPPER:
786 case E1000_DEV_ID_82571EB_QUAD_FIBER:
787 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
788 /* if quad port adapter, disable WoL on all but port A */
789 if (em_global_quad_port_a != 0)
790 adapter->wol = 0;
791 /* Reset for multiple quad port adapters */
792 if (++em_global_quad_port_a == 4)
793 em_global_quad_port_a = 0;
794 break;
795 }
796
797 /* XXX disable wol */
798 adapter->wol = 0;
799
d76227df
SZ		 800 /* Setup flow control. */
801 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
802 em_flowctrl);
81ac62f7 803 adapter->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
d76227df 804 if (adapter->hw.mac.type == e1000_pchlan) {
81ac62f7
SZ		 805 /* Only PAUSE reception is supported on PCH */
806 adapter->ifm_flowctrl &= ~IFM_ETH_TXPAUSE;
d76227df
SZ		 807 }
808
2d0e5700
SZ		 809 /* Setup OS specific network interface */
810 em_setup_ifp(adapter);
811
812 /* Add sysctl tree, must after em_setup_ifp() */
813 em_add_sysctl(adapter);
814
b5de76b1
SZ		 815#ifdef IFPOLL_ENABLE
816 /* Polling setup */
817 ifpoll_compat_setup(&adapter->npoll,
26595b18
SW		 818 device_get_sysctl_ctx(dev), device_get_sysctl_tree(dev),
819 device_get_unit(dev), ifp->if_serializer);
b5de76b1
SZ		 820#endif
821
2d0e5700
SZ		 822 /* Reset the hardware */
823 error = em_reset(adapter);
824 if (error) {
bacca38f
SZ		 825 /*
826 * Some 82573 parts fail the first reset, call it again,
827 * if it fails a second time its a real issue.
828 */
829 error = em_reset(adapter);
830 if (error) {
831 device_printf(dev, "Unable to reset the hardware\n");
832 ether_ifdetach(ifp);
833 goto fail;
834 }
2d0e5700
SZ		 835 }
836
837 /* Initialize statistics */
838 em_update_stats(adapter);
839
840 adapter->hw.mac.get_link_status = 1;
841 em_update_link_status(adapter);
842
9c80d176
SZ		 843 /* Do we need workaround for 82544 PCI-X adapter? */
844 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
845 adapter->hw.mac.type == e1000_82544)
f647ad3d 846 adapter->pcix_82544 = TRUE;
87307ba1 847 else
f647ad3d 848 adapter->pcix_82544 = FALSE;
af82d4bb 849
9c80d176
SZ		 850 if (adapter->pcix_82544) {
851 /*
852 * 82544 on PCI-X may split one TX segment
853 * into two TX descs, so we double its number
854 * of spare TX desc here.
855 */
856 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
857 } else {
858 adapter->spare_tx_desc = EM_TX_SPARE;
859 }
0bbb59f3
SZ		 860 if (adapter->flags & EM_FLAG_TSO)
861 adapter->spare_tx_desc = EM_TX_SPARE_TSO;
55471c55 862 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG;
9c80d176 863
9f60d74b
SZ		 864 /*
865 * Keep following relationship between spare_tx_desc, oact_tx_desc
866 * and tx_int_nsegs:
867 * (spare_tx_desc + EM_TX_RESERVED) <=
868 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
869 */
870 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
871 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
872 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
873 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
874 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
875
876 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
877 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
878 adapter->tx_int_nsegs = adapter->oact_tx_desc;
879
2d0e5700 880 /* Non-AMT based hardware can now take control from firmware */
79878f87
SZ		 881 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
882 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571)
2d0e5700
SZ		 883 em_get_hw_control(adapter);
884
4c77af2d
SZ		 885 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
886
87ab432b
SZ		 887 /*
888 * Missing Interrupt Following ICR read:
889 *
a835687d
SZ		 890 * 82571/82572 specification update errata #76
891 * 82573 specification update errata #31
892 * 82574 specification update errata #12
893 * 82583 specification update errata #4
87ab432b
SZ		 894 */
895 intr_func = em_intr;
896 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
897 (adapter->hw.mac.type == e1000_82571 ||
898 adapter->hw.mac.type == e1000_82572 ||
899 adapter->hw.mac.type == e1000_82573 ||
900 adapter->hw.mac.type == e1000_82574 ||
901 adapter->hw.mac.type == e1000_82583))
902 intr_func = em_intr_mask;
903
9c80d176 904 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
87ab432b 905 intr_func, adapter, &adapter->intr_tag,
9c80d176 906 ifp->if_serializer);
af82d4bb 907 if (error) {
9c80d176 908 device_printf(dev, "Failed to register interrupt handler");
d2811227 909 ether_ifdetach(ifp);
af82d4bb
JS		 910 goto fail;
911 }
9c80d176 912 return (0);
af82d4bb
JS		 913fail:
914 em_detach(dev);
9c80d176 915 return (error);
984263bc
MD		 916}
917
984263bc
MD		 918static int
919em_detach(device_t dev)
920{
78195a76 921 struct adapter *adapter = device_get_softc(dev);
984263bc 922
af82d4bb 923 if (device_is_attached(dev)) {
9c80d176 924 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ		 925
926 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 927
af82d4bb 928 em_stop(adapter);
9c80d176
SZ		 929
930 e1000_phy_hw_reset(&adapter->hw);
931
932 em_rel_mgmt(adapter);
2d0e5700 933 em_rel_hw_control(adapter);
9c80d176
SZ		 934
935 if (adapter->wol) {
936 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
937 E1000_WUC_PME_EN);
938 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
939 em_enable_wol(dev);
940 }
941
942 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
943
cdf89432
SZ		 944 lwkt_serialize_exit(ifp->if_serializer);
945
946 ether_ifdetach(ifp);
a19a8754 947 } else if (adapter->memory != NULL) {
2d0e5700 948 em_rel_hw_control(adapter);
7ea52455 949 }
d2811227
SZ		 950
951 ifmedia_removeall(&adapter->media);
cdf89432
SZ		 952 bus_generic_detach(dev);
953
9c80d176
SZ		 954 em_free_pci_res(adapter);
955
956 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
957 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 958
984263bc 959 /* Free Transmit Descriptor ring */
9c80d176 960 if (adapter->tx_desc_base)
9ccd8c1f 961 em_dma_free(adapter, &adapter->txdma);
984263bc 962
984263bc 963 /* Free Receive Descriptor ring */
9c80d176 964 if (adapter->rx_desc_base)
9ccd8c1f 965 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ		 966
967 /* Free top level busdma tag */
968 if (adapter->parent_dtag != NULL)
969 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 970
a19a8754
SZ		 971 if (adapter->mta != NULL)
972 kfree(adapter->mta, M_DEVBUF);
973
87307ba1 974 return (0);
984263bc
MD		 975}
976
984263bc
MD		 977static int
978em_shutdown(device_t dev)
979{
9c80d176 980 return em_suspend(dev);
87307ba1
SZ		 981}
982
87307ba1
SZ		 983static int
984em_suspend(device_t dev)
985{
986 struct adapter *adapter = device_get_softc(dev);
9c80d176 987 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ		 988
989 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 990
87307ba1 991 em_stop(adapter);
9c80d176
SZ		 992
993 em_rel_mgmt(adapter);
2d0e5700 994 em_rel_hw_control(adapter);
9c80d176 995
2d0e5700 996 if (adapter->wol) {
9c80d176
SZ		 997 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
998 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
999 em_enable_wol(dev);
2d0e5700 1000 }
9c80d176 1001
87307ba1 1002 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ		 1003
1004 return bus_generic_suspend(dev);
87307ba1
SZ		 1005}
1006
1007static int
1008em_resume(device_t dev)
1009{
1010 struct adapter *adapter = device_get_softc(dev);
9c80d176 1011 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ		 1012
1013 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 1014
4f87d70c
SZ		 1015 if (adapter->hw.mac.type == e1000_pch2lan)
1016 e1000_resume_workarounds_pchlan(&adapter->hw);
1017
87307ba1 1018 em_init(adapter);
9c80d176 1019 em_get_mgmt(adapter);
9db4b353 1020 if_devstart(ifp);
9c80d176 1021
87307ba1
SZ		 1022 lwkt_serialize_exit(ifp->if_serializer);
1023
1024 return bus_generic_resume(dev);
984263bc
MD		 1025}
1026
984263bc 1027static void
f0a26983 1028em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
9c095379 1029{
f647ad3d 1030 struct adapter *adapter = ifp->if_softc;
9c80d176 1031 struct mbuf *m_head;
893bb181 1032 int idx = -1, nsegs = 0;
984263bc 1033
f0a26983 1034 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1eca7b82 1035 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 1036
9ed293e0 1037 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
87307ba1 1038 return;
9c80d176 1039
9db4b353
SZ		 1040 if (!adapter->link_active) {
1041 ifq_purge(&ifp->if_snd);
f647ad3d 1042 return;
9db4b353 1043 }
9c80d176 1044
e26dc3e9 1045 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ		 1046 /* Now do we at least have a minimal? */
1047 if (EM_IS_OACTIVE(adapter)) {
1048 em_tx_collect(adapter);
9c80d176 1049 if (EM_IS_OACTIVE(adapter)) {
9ed293e0 1050 ifq_set_oactive(&ifp->if_snd);
9f60d74b 1051 adapter->no_tx_desc_avail1++;
9c80d176
SZ		 1052 break;
1053 }
1054 }
1055
1056 logif(pkt_txqueue);
ac9843a1 1057 m_head = ifq_dequeue(&ifp->if_snd);
f647ad3d
JS		 1058 if (m_head == NULL)
1059 break;
984263bc 1060
893bb181 1061 if (em_encap(adapter, &m_head, &nsegs, &idx)) {
d40991ef 1062 IFNET_STAT_INC(ifp, oerrors, 1);
9f60d74b
SZ		 1063 em_tx_collect(adapter);
1064 continue;
f647ad3d 1065 }
984263bc 1066
608dda76
SZ		 1067 /*
1068 * TX interrupt are aggressively aggregated, so increasing
1069 * opackets at TX interrupt time will make the opackets
1070 * statistics vastly inaccurate; we do the opackets increment
1071 * now.
1072 */
1073 IFNET_STAT_INC(ifp, opackets, 1);
1074
893bb181
SZ		 1075 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) {
1076 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
1077 nsegs = 0;
1078 idx = -1;
1079 }
1080
984263bc 1081 /* Send a copy of the frame to the BPF listener */
b637f170 1082 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ		 1083
1084 /* Set timeout in case hardware has problems transmitting. */
1085 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 1086 }
893bb181
SZ		 1087 if (idx >= 0)
1088 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
984263bc
MD		 1089}
1090
984263bc 1091static int
bd4539cc 1092em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1093{
f647ad3d 1094 struct adapter *adapter = ifp->if_softc;
9c80d176 1095 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 1096 uint16_t eeprom_data = 0;
9c80d176
SZ		 1097 int max_frame_size, mask, reinit;
1098 int error = 0;
0d366ee7 1099
9c80d176 1100 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 1101
984263bc 1102 switch (command) {
984263bc 1103 case SIOCSIFMTU:
9c80d176
SZ		 1104 switch (adapter->hw.mac.type) {
1105 case e1000_82573:
1eca7b82
SZ		 1106 /*
1107 * 82573 only supports jumbo frames
1108 * if ASPM is disabled.
1109 */
9c80d176
SZ		 1110 e1000_read_nvm(&adapter->hw,
1111 NVM_INIT_3GIO_3, 1, &eeprom_data);
1112 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ		 1113 max_frame_size = ETHER_MAX_LEN;
1114 break;
1115 }
9c80d176
SZ		 1116 /* FALL THROUGH */
1117
1118 /* Limit Jumbo Frame size */
1119 case e1000_82571:
1120 case e1000_82572:
1121 case e1000_ich9lan:
1122 case e1000_ich10lan:
2d0e5700 1123 case e1000_pch2lan:
91c72bdc 1124 case e1000_pch_lpt:
524ce499 1125 case e1000_pch_spt:
9c80d176 1126 case e1000_82574:
6d5e2922 1127 case e1000_82583:
9c80d176 1128 case e1000_80003es2lan:
1eca7b82 1129 max_frame_size = 9234;
7ea52455 1130 break;
9c80d176 1131
2d0e5700
SZ		 1132 case e1000_pchlan:
1133 max_frame_size = 4096;
1134 break;
1135
9c80d176
SZ		 1136 /* Adapters that do not support jumbo frames */
1137 case e1000_82542:
1138 case e1000_ich8lan:
7ea52455
SZ		 1139 max_frame_size = ETHER_MAX_LEN;
1140 break;
9c80d176 1141
7ea52455
SZ		 1142 default:
1143 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1144 break;
1145 }
9c80d176
SZ		 1146 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1147 ETHER_CRC_LEN) {
984263bc 1148 error = EINVAL;
9c80d176 1149 break;
984263bc 1150 }
9c80d176
SZ		 1151
1152 ifp->if_mtu = ifr->ifr_mtu;
c29e94c0 1153 adapter->hw.mac.max_frame_size =
9c80d176
SZ		 1154 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1155
1156 if (ifp->if_flags & IFF_RUNNING)
1157 em_init(adapter);
984263bc 1158 break;
9c80d176 1159
984263bc 1160 case SIOCSIFFLAGS:
984263bc 1161 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ		 1162 if ((ifp->if_flags & IFF_RUNNING)) {
1163 if ((ifp->if_flags ^ adapter->if_flags) &
1164 (IFF_PROMISC | IFF_ALLMULTI)) {
1165 em_disable_promisc(adapter);
1166 em_set_promisc(adapter);
1167 }
1168 } else {
78195a76 1169 em_init(adapter);
87307ba1 1170 }
9c80d176
SZ		 1171 } else if (ifp->if_flags & IFF_RUNNING) {
1172 em_stop(adapter);
984263bc 1173 }
87307ba1 1174 adapter->if_flags = ifp->if_flags;
984263bc 1175 break;
9c80d176 1176
984263bc
MD		 1177 case SIOCADDMULTI:
1178 case SIOCDELMULTI:
984263bc
MD		 1179 if (ifp->if_flags & IFF_RUNNING) {
1180 em_disable_intr(adapter);
1181 em_set_multi(adapter);
9c80d176
SZ		 1182 if (adapter->hw.mac.type == e1000_82542 &&
1183 adapter->hw.revision_id == E1000_REVISION_2)
1184 em_init_rx_unit(adapter);
350d9c84
SZ		 1185#ifdef IFPOLL_ENABLE
1186 if (!(ifp->if_flags & IFF_NPOLLING))
1eca7b82 1187#endif
9c80d176 1188 em_enable_intr(adapter);
984263bc
MD		 1189 }
1190 break;
9c80d176 1191
984263bc 1192 case SIOCSIFMEDIA:
87307ba1 1193 /* Check SOL/IDER usage */
9c80d176
SZ		 1194 if (e1000_check_reset_block(&adapter->hw)) {
1195 device_printf(adapter->dev, "Media change is"
1196 " blocked due to SOL/IDER session.\n");
87307ba1
SZ		 1197 break;
1198 }
9c80d176
SZ		 1199 /* FALL THROUGH */
1200
984263bc 1201 case SIOCGIFMEDIA:
984263bc
MD		 1202 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1203 break;
9c80d176 1204
984263bc 1205 case SIOCSIFCAP:
9c80d176 1206 reinit = 0;
984263bc 1207 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
f54de229
SZ		 1208 if (mask & IFCAP_RXCSUM) {
1209 ifp->if_capenable ^= IFCAP_RXCSUM;
1eca7b82 1210 reinit = 1;
984263bc 1211 }
f54de229
SZ		 1212 if (mask & IFCAP_TXCSUM) {
1213 ifp->if_capenable ^= IFCAP_TXCSUM;
1214 if (ifp->if_capenable & IFCAP_TXCSUM)
1215 ifp->if_hwassist |= EM_CSUM_FEATURES;
1216 else
1217 ifp->if_hwassist &= ~EM_CSUM_FEATURES;
1218 }
0bbb59f3
SZ		 1219 if (mask & IFCAP_TSO) {
1220 ifp->if_capenable ^= IFCAP_TSO;
1221 if (ifp->if_capenable & IFCAP_TSO)
1222 ifp->if_hwassist |= CSUM_TSO;
1223 else
1224 ifp->if_hwassist &= ~CSUM_TSO;
1225 }
1eca7b82
SZ		 1226 if (mask & IFCAP_VLAN_HWTAGGING) {
1227 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1228 reinit = 1;
1229 }
9c80d176 1230 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1231 em_init(adapter);
984263bc 1232 break;
9c80d176 1233
984263bc 1234 default:
1eca7b82
SZ		 1235 error = ether_ioctl(ifp, command, data);
1236 break;
984263bc 1237 }
87307ba1 1238 return (error);
984263bc
MD		 1239}
1240
984263bc
MD		 1241static void
1242em_watchdog(struct ifnet *ifp)
1243{
1eca7b82 1244 struct adapter *adapter = ifp->if_softc;
984263bc 1245
9c80d176
SZ		 1246 ASSERT_SERIALIZED(ifp->if_serializer);
1247
1248 /*
1249 * The timer is set to 5 every time start queues a packet.
1250 * Then txeof keeps resetting it as long as it cleans at
1251 * least one descriptor.
1252 * Finally, anytime all descriptors are clean the timer is
1253 * set to 0.
1254 */
1255
9f60d74b
SZ		 1256 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1257 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1258 /*
1259 * If we reach here, all TX jobs are completed and
1260 * the TX engine should have been idled for some time.
1261 * We don't need to call if_devstart() here.
1262 */
9ed293e0 1263 ifq_clr_oactive(&ifp->if_snd);
9f60d74b
SZ		 1264 ifp->if_timer = 0;
1265 return;
1266 }
1267
1eca7b82
SZ		 1268 /*
1269 * If we are in this routine because of pause frames, then
984263bc
MD		 1270 * don't reset the hardware.
1271 */
9c80d176
SZ		 1272 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1273 E1000_STATUS_TXOFF) {
984263bc
MD		 1274 ifp->if_timer = EM_TX_TIMEOUT;
1275 return;
1276 }
1277
9c80d176 1278 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1279 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1280
d40991ef 1281 IFNET_STAT_INC(ifp, oerrors, 1);
9c80d176
SZ		 1282 adapter->watchdog_events++;
1283
984263bc
MD		 1284 em_init(adapter);
1285
9c80d176
SZ		 1286 if (!ifq_is_empty(&ifp->if_snd))
1287 if_devstart(ifp);
984263bc
MD		 1288}
1289
984263bc 1290static void
9c80d176 1291em_init(void *xsc)
9c095379 1292{
9c80d176
SZ		 1293 struct adapter *adapter = xsc;
1294 struct ifnet *ifp = &adapter->arpcom.ac_if;
1295 device_t dev = adapter->dev;
984263bc 1296
87307ba1
SZ		 1297 ASSERT_SERIALIZED(ifp->if_serializer);
1298
984263bc
MD		 1299 em_stop(adapter);
1300
0d366ee7 1301 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ		 1302 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1303
1304 /* Put the address into the Receive Address Array */
1305 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1306
1307 /*
1308 * With the 82571 adapter, RAR[0] may be overwritten
1309 * when the other port is reset, we make a duplicate
1310 * in RAR[14] for that eventuality, this assures
1311 * the interface continues to function.
1312 */
1313 if (adapter->hw.mac.type == e1000_82571) {
1314 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1315 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1316 E1000_RAR_ENTRIES - 1);
1317 }
0d366ee7 1318
2d0e5700
SZ		 1319 /* Reset the hardware */
1320 if (em_reset(adapter)) {
1321 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1322 /* XXX em_stop()? */
984263bc
MD		 1323 return;
1324 }
87307ba1 1325 em_update_link_status(adapter);
984263bc 1326
9c80d176
SZ		 1327 /* Setup VLAN support, basic and offload if available */
1328 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1329
9c80d176
SZ		 1330 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1331 uint32_t ctrl;
1332
1333 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1334 ctrl |= E1000_CTRL_VME;
1335 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ		 1336 }
1337
9c80d176
SZ		 1338 /* Configure for OS presence */
1339 em_get_mgmt(adapter);
1340
984263bc 1341 /* Prepare transmit descriptors and buffers */
9c80d176
SZ		 1342 em_init_tx_ring(adapter);
1343 em_init_tx_unit(adapter);
984263bc
MD		 1344
1345 /* Setup Multicast table */
1346 em_set_multi(adapter);
1347
1348 /* Prepare receive descriptors and buffers */
9c80d176
SZ		 1349 if (em_init_rx_ring(adapter)) {
1350 device_printf(dev, "Could not setup receive structures\n");
984263bc 1351 em_stop(adapter);
984263bc
MD		 1352 return;
1353 }
9c80d176 1354 em_init_rx_unit(adapter);
7ea52455 1355
87307ba1 1356 /* Don't lose promiscuous settings */
0d366ee7 1357 em_set_promisc(adapter);
984263bc 1358
984263bc 1359 ifp->if_flags |= IFF_RUNNING;
9ed293e0 1360 ifq_clr_oactive(&ifp->if_snd);
984263bc 1361
9c80d176
SZ		 1362 callout_reset(&adapter->timer, hz, em_timer, adapter);
1363 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1364
1365 /* MSI/X configuration for 82574 */
1366 if (adapter->hw.mac.type == e1000_82574) {
1367 int tmp;
1368
1369 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1370 tmp |= E1000_CTRL_EXT_PBA_CLR;
1371 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1372 /*
2d0e5700 1373 * XXX MSIX
9c80d176
SZ		 1374 * Set the IVAR - interrupt vector routing.
1375 * Each nibble represents a vector, high bit
1376 * is enable, other 3 bits are the MSIX table
1377 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1378 * Link (other) to 2, hence the magic number.
1379 */
1380 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1381 }
1eca7b82 1382
b5de76b1 1383#ifdef IFPOLL_ENABLE
9c80d176
SZ		 1384 /*
1385 * Only enable interrupts if we are not polling, make sure
1386 * they are off otherwise.
1387 */
350d9c84 1388 if (ifp->if_flags & IFF_NPOLLING)
1eca7b82
SZ		 1389 em_disable_intr(adapter);
1390 else
350d9c84 1391#endif /* IFPOLL_ENABLE */
9c80d176 1392 em_enable_intr(adapter);
0d366ee7 1393
2d0e5700 1394 /* AMT based hardware can now take control from firmware */
79878f87
SZ		 1395 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
1396 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) &&
2d0e5700
SZ		 1397 adapter->hw.mac.type >= e1000_82571)
1398 em_get_hw_control(adapter);
984263bc
MD		 1399}
1400
350d9c84 1401#ifdef IFPOLL_ENABLE
f647ad3d
JS		 1402
1403static void
350d9c84 1404em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
984263bc 1405{
f647ad3d 1406 struct adapter *adapter = ifp->if_softc;
984263bc 1407
78195a76
MD		 1408 ASSERT_SERIALIZED(ifp->if_serializer);
1409
b5de76b1 1410 if (adapter->npoll.ifpc_stcount-- == 0) {
350d9c84 1411 uint32_t reg_icr;
9c80d176 1412
b5de76b1 1413 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac;
9c80d176 1414
9c80d176 1415 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1416 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1417 callout_stop(&adapter->timer);
9c80d176 1418 adapter->hw.mac.get_link_status = 1;
87307ba1 1419 em_update_link_status(adapter);
9c80d176 1420 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1421 }
350d9c84 1422 }
1eca7b82 1423
350d9c84
SZ		 1424 em_rxeof(adapter, count);
1425 em_txeof(adapter);
1426
1427 if (!ifq_is_empty(&ifp->if_snd))
1428 if_devstart(ifp);
1429}
1430
1431static void
1432em_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1433{
1434 struct adapter *adapter = ifp->if_softc;
1435
1436 ASSERT_SERIALIZED(ifp->if_serializer);
1437
1438 if (info != NULL) {
b5de76b1 1439 int cpuid = adapter->npoll.ifpc_cpuid;
350d9c84
SZ		 1440
1441 info->ifpi_rx[cpuid].poll_func = em_npoll_compat;
1442 info->ifpi_rx[cpuid].arg = NULL;
1443 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1444
1445 if (ifp->if_flags & IFF_RUNNING)
1446 em_disable_intr(adapter);
dfd3b18b 1447 ifq_set_cpuid(&ifp->if_snd, cpuid);
350d9c84
SZ		 1448 } else {
1449 if (ifp->if_flags & IFF_RUNNING)
1450 em_enable_intr(adapter);
dfd3b18b 1451 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
f647ad3d 1452 }
984263bc 1453}
9c095379 1454
350d9c84 1455#endif /* IFPOLL_ENABLE */
984263bc 1456
984263bc 1457static void
9c80d176 1458em_intr(void *xsc)
984263bc 1459{
87ab432b
SZ		 1460 em_intr_body(xsc, TRUE);
1461}
1462
1463static void
1464em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1465{
9c80d176 1466 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1467 uint32_t reg_icr;
984263bc 1468
07855a48 1469 logif(intr_beg);
78195a76
MD		 1470 ASSERT_SERIALIZED(ifp->if_serializer);
1471
9c80d176
SZ		 1472 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1473
87ab432b
SZ		 1474 if (chk_asserted &&
1475 ((adapter->hw.mac.type >= e1000_82571 &&
1476 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1477 reg_icr == 0)) {
07855a48 1478 logif(intr_end);
984263bc 1479 return;
07855a48 1480 }
984263bc 1481
87307ba1 1482 /*
9c80d176
SZ		 1483 * XXX: some laptops trigger several spurious interrupts
1484 * on em(4) when in the resume cycle. The ICR register
1485 * reports all-ones value in this case. Processing such
1486 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ		 1487 */
1488 if (reg_icr == 0xffffffff) {
1489 logif(intr_end);
1490 return;
984263bc
MD		 1491 }
1492
79938e61 1493 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1494 if (reg_icr &
6643d744 1495 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1496 em_rxeof(adapter, -1);
6643d744 1497 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ		 1498 em_txeof(adapter);
1499 if (!ifq_is_empty(&ifp->if_snd))
1500 if_devstart(ifp);
1501 }
f647ad3d 1502 }
984263bc 1503
87307ba1
SZ		 1504 /* Link status change */
1505 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1506 callout_stop(&adapter->timer);
9c80d176 1507 adapter->hw.mac.get_link_status = 1;
87307ba1 1508 em_update_link_status(adapter);
9c80d176
SZ		 1509
1510 /* Deal with TX cruft when link lost */
1511 em_tx_purge(adapter);
1512
1513 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ		 1514 }
1515
1516 if (reg_icr & E1000_ICR_RXO)
1517 adapter->rx_overruns++;
1518
07855a48 1519 logif(intr_end);
984263bc
MD		 1520}
1521
87ab432b
SZ		 1522static void
1523em_intr_mask(void *xsc)
1524{
1525 struct adapter *adapter = xsc;
1526
1527 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1528 /*
1529 * NOTE:
1530 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1531 * so don't check it.
1532 */
1533 em_intr_body(adapter, FALSE);
1534 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1535}
1536
984263bc
MD		 1537static void
1538em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1539{
87307ba1 1540 struct adapter *adapter = ifp->if_softc;
984263bc 1541
78195a76
MD		 1542 ASSERT_SERIALIZED(ifp->if_serializer);
1543
87307ba1 1544 em_update_link_status(adapter);
984263bc
MD		 1545
1546 ifmr->ifm_status = IFM_AVALID;
1547 ifmr->ifm_active = IFM_ETHER;
1548
81ac62f7 1549 if (!adapter->link_active) {
05297aca
SZ		 1550 if (adapter->hw.mac.autoneg)
1551 ifmr->ifm_active |= IFM_NONE;
1552 else
1553 ifmr->ifm_active = adapter->media.ifm_media;
984263bc 1554 return;
81ac62f7 1555 }
984263bc
MD		 1556
1557 ifmr->ifm_status |= IFM_ACTIVE;
81ac62f7 1558 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
05297aca 1559 ifmr->ifm_active |= adapter->ifm_flowctrl;
984263bc 1560
9c80d176
SZ		 1561 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1562 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
05297aca
SZ		 1563 u_char fiber_type = IFM_1000_SX;
1564
9c80d176 1565 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ		 1566 fiber_type = IFM_1000_LX;
1567 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD		 1568 } else {
1569 switch (adapter->link_speed) {
1570 case 10:
1571 ifmr->ifm_active |= IFM_10_T;
1572 break;
1573 case 100:
1574 ifmr->ifm_active |= IFM_100_TX;
1575 break;
9c80d176 1576
984263bc 1577 case 1000:
7f259627 1578 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD		 1579 break;
1580 }
1581 if (adapter->link_duplex == FULL_DUPLEX)
1582 ifmr->ifm_active |= IFM_FDX;
1583 else
1584 ifmr->ifm_active |= IFM_HDX;
1585 }
81ac62f7
SZ		 1586 if (ifmr->ifm_active & IFM_FDX) {
1587 ifmr->ifm_active |=
1588 e1000_fc2ifmedia(adapter->hw.fc.current_mode);
1589 }
984263bc
MD		 1590}
1591
984263bc
MD		 1592static int
1593em_media_change(struct ifnet *ifp)
1594{
87307ba1
SZ		 1595 struct adapter *adapter = ifp->if_softc;
1596 struct ifmedia *ifm = &adapter->media;
984263bc 1597
78195a76 1598 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1599
87307ba1
SZ		 1600 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1601 return (EINVAL);
1602
81ac62f7
SZ		 1603 if (adapter->hw.mac.type == e1000_pchlan &&
1604 (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)) {
1605 if (bootverbose)
1606 if_printf(ifp, "TX PAUSE is not supported on PCH\n");
1607 return EINVAL;
1608 }
1609
984263bc
MD		 1610 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1611 case IFM_AUTO:
9c80d176
SZ		 1612 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1613 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1614 break;
9c80d176 1615
1eca7b82 1616 case IFM_1000_LX:
984263bc 1617 case IFM_1000_SX:
7f259627 1618 case IFM_1000_T:
9c80d176
SZ		 1619 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1620 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1621 break;
9c80d176 1622
984263bc 1623 case IFM_100_TX:
81ac62f7 1624 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
9c80d176 1625 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
81ac62f7
SZ		 1626 } else {
1627 if (IFM_OPTIONS(ifm->ifm_media) &
1628 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1629 if (bootverbose) {
1630 if_printf(ifp, "Flow control is not "
1631 "allowed for half-duplex\n");
1632 }
1633 return EINVAL;
1634 }
9c80d176 1635 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
81ac62f7
SZ		 1636 }
1637 adapter->hw.mac.autoneg = FALSE;
1638 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1639 break;
9c80d176 1640
984263bc 1641 case IFM_10_T:
81ac62f7 1642 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
9c80d176 1643 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
81ac62f7
SZ		 1644 } else {
1645 if (IFM_OPTIONS(ifm->ifm_media) &
1646 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1647 if (bootverbose) {
1648 if_printf(ifp, "Flow control is not "
1649 "allowed for half-duplex\n");
1650 }
1651 return EINVAL;
1652 }
9c80d176 1653 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
81ac62f7
SZ		 1654 }
1655 adapter->hw.mac.autoneg = FALSE;
1656 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1657 break;
9c80d176 1658
984263bc 1659 default:
81ac62f7
SZ		 1660 if (bootverbose) {
1661 if_printf(ifp, "Unsupported media type %d\n",
1662 IFM_SUBTYPE(ifm->ifm_media));
1663 }
1664 return EINVAL;
984263bc 1665 }
81ac62f7 1666 adapter->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
9c80d176 1667
81ac62f7
SZ		 1668 if (ifp->if_flags & IFF_RUNNING)
1669 em_init(adapter);
984263bc 1670
9c80d176 1671 return (0);
9ccd8c1f
JS		 1672}
1673
984263bc 1674static int
893bb181
SZ		 1675em_encap(struct adapter *adapter, struct mbuf **m_headp,
1676 int *segs_used, int *idx)
9ccd8c1f 1677{
9c80d176 1678 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1679 bus_dmamap_t map;
9c80d176
SZ		 1680 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1681 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1682 struct mbuf *m_head = *m_headp;
9f60d74b 1683 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1684 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1685
0bbb59f3
SZ		 1686 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1687 error = em_tso_pullup(adapter, m_headp);
1688 if (error)
1689 return error;
1690 m_head = *m_headp;
1691 }
1692
9c80d176
SZ		 1693 txd_upper = txd_lower = 0;
1694 txd_used = 0;
87307ba1
SZ		 1695
1696 /*
9c80d176
SZ		 1697 * Capture the first descriptor index, this descriptor
1698 * will have the index of the EOP which is the only one
1699 * that now gets a DONE bit writeback.
87307ba1 1700 */
9c80d176
SZ		 1701 first = adapter->next_avail_tx_desc;
1702 tx_buffer = &adapter->tx_buffer_area[first];
1703 tx_buffer_mapped = tx_buffer;
1704 map = tx_buffer->map;
87307ba1 1705
9c80d176
SZ		 1706 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1707 KASSERT(maxsegs >= adapter->spare_tx_desc,
ed20d0e3 1708 ("not enough spare TX desc"));
9c80d176
SZ		 1709 if (adapter->pcix_82544) {
1710 /* Half it; see the comment in em_attach() */
1711 maxsegs >>= 1;
9ccd8c1f 1712 }
9c80d176
SZ		 1713 if (maxsegs > EM_MAX_SCATTER)
1714 maxsegs = EM_MAX_SCATTER;
984263bc 1715
9c80d176
SZ		 1716 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1717 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1718 if (error) {
1719 if (error == ENOBUFS)
1720 adapter->mbuf_alloc_failed++;
1721 else
1722 adapter->no_tx_dma_setup++;
984263bc 1723
9c80d176
SZ		 1724 m_freem(*m_headp);
1725 *m_headp = NULL;
1726 return error;
7ea52455 1727 }
9c80d176 1728 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1729
9c80d176 1730 m_head = *m_headp;
9f60d74b 1731 adapter->tx_nsegs += nsegs;
893bb181 1732 *segs_used += nsegs;
9c80d176 1733
0bbb59f3
SZ		 1734 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1735 /* TSO will consume one TX desc */
893bb181
SZ		 1736 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower);
1737 adapter->tx_nsegs += i;
1738 *segs_used += i;
0bbb59f3 1739 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1740 /* TX csum offloading will consume one TX desc */
893bb181
SZ		 1741 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower);
1742 adapter->tx_nsegs += i;
1743 *segs_used += i;
9c80d176 1744 }
d37cc902
SZ		 1745
1746 /* Handle VLAN tag */
1747 if (m_head->m_flags & M_VLANTAG) {
1748 /* Set the vlan id. */
1749 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1750 /* Tell hardware to add tag */
1751 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1752 }
1753
984263bc 1754 i = adapter->next_avail_tx_desc;
87307ba1
SZ		 1755
1756 /* Set up our transmit descriptors */
9c80d176 1757 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS		 1758 /* If adapter is 82544 and on PCIX bus */
1759 if(adapter->pcix_82544) {
87307ba1
SZ		 1760 DESC_ARRAY desc_array;
1761 uint32_t array_elements, counter;
1762
9c80d176 1763 /*
f647ad3d
JS		 1764 * Check the Address and Length combination and
1765 * split the data accordingly
9ccd8c1f 1766 */
9c80d176
SZ		 1767 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1768 segs[j].ds_len, &desc_array);
9ccd8c1f 1769 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ		 1770 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1771
9ccd8c1f 1772 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ		 1773 ctxd = &adapter->tx_desc_base[i];
1774
1775 ctxd->buffer_addr = htole64(
1776 desc_array.descriptor[counter].address);
1777 ctxd->lower.data = htole32(
2af74b85 1778 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ		 1779 desc_array.descriptor[counter].length);
1780 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ		 1781
1782 last = i;
9ccd8c1f
JS		 1783 if (++i == adapter->num_tx_desc)
1784 i = 0;
1785
9ccd8c1f 1786 txd_used++;
9c80d176 1787 }
9ccd8c1f 1788 } else {
0d366ee7 1789 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1790 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1791
9c80d176 1792 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1793 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ		 1794 txd_lower | segs[j].ds_len);
1795 ctxd->upper.data = htole32(txd_upper);
984263bc 1796
87307ba1 1797 last = i;
0d366ee7
MD		 1798 if (++i == adapter->num_tx_desc)
1799 i = 0;
0d366ee7 1800 }
984263bc 1801 }
9ccd8c1f 1802
984263bc 1803 adapter->next_avail_tx_desc = i;
9c80d176
SZ		 1804 if (adapter->pcix_82544) {
1805 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1806 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ		 1807 } else {
1808 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1809 adapter->num_tx_desc_avail -= nsegs;
1810 }
984263bc 1811
984263bc 1812 tx_buffer->m_head = m_head;
9c80d176 1813 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1814 tx_buffer->map = map;
9ccd8c1f 1815
9f60d74b
SZ		 1816 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1817 adapter->tx_nsegs = 0;
4e4e8481
SZ		 1818
1819 /*
1820 * Report Status (RS) is turned on
1821 * every tx_int_nsegs descriptors.
1822 */
9f60d74b
SZ		 1823 cmd = E1000_TXD_CMD_RS;
1824
b4b0a2b4
SZ		 1825 /*
1826 * Keep track of the descriptor, which will
1827 * be written back by hardware.
1828 */
9f60d74b
SZ		 1829 adapter->tx_dd[adapter->tx_dd_tail] = last;
1830 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1831 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1832 }
1833
9ccd8c1f 1834 /*
984263bc 1835 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1836 */
9f60d74b 1837 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1 1838
893bb181
SZ		 1839 if (adapter->hw.mac.type == e1000_82547) {
1840 /*
1841 * Advance the Transmit Descriptor Tail (TDT), this tells the
1842 * E1000 that this frame is available to transmit.
1843 */
1844 if (adapter->link_duplex == HALF_DUPLEX) {
1845 em_82547_move_tail_serialized(adapter);
1846 } else {
1847 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
cfefda96 1848 em_82547_update_fifo_head(adapter,
9c80d176 1849 m_head->m_pkthdr.len);
984263bc 1850 }
893bb181
SZ		 1851 } else {
1852 /*
1853 * Defer TDT updating, until enough descriptors are setup
1854 */
1855 *idx = i;
984263bc 1856 }
87307ba1 1857 return (0);
984263bc
MD		 1858}
1859
9c80d176 1860/*
984263bc 1861 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1862 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ		 1863 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1864 * in this case. We do that only when FIFO is quiescent.
1865 */
9c095379 1866static void
1eca7b82 1867em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1868{
9c80d176
SZ		 1869 struct e1000_tx_desc *tx_desc;
1870 uint16_t hw_tdt, sw_tdt, length = 0;
1871 bool eop = 0;
984263bc 1872
9c80d176
SZ		 1873 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1874
1875 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1876 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1877
984263bc
MD		 1878 while (hw_tdt != sw_tdt) {
1879 tx_desc = &adapter->tx_desc_base[hw_tdt];
1880 length += tx_desc->lower.flags.length;
1881 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1882 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD		 1883 hw_tdt = 0;
1884
87307ba1 1885 if (eop) {
984263bc 1886 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1887 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS		 1888 callout_reset(&adapter->tx_fifo_timer, 1,
1889 em_82547_move_tail, adapter);
1890 break;
984263bc 1891 }
9c80d176 1892 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS		 1893 em_82547_update_fifo_head(adapter, length);
1894 length = 0;
984263bc 1895 }
9c80d176
SZ		 1896 }
1897}
1898
1899static void
1900em_82547_move_tail(void *xsc)
1901{
1902 struct adapter *adapter = xsc;
1903 struct ifnet *ifp = &adapter->arpcom.ac_if;
1904
1905 lwkt_serialize_enter(ifp->if_serializer);
1906 em_82547_move_tail_serialized(adapter);
1907 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD		 1908}
1909
1910static int
1911em_82547_fifo_workaround(struct adapter *adapter, int len)
1912{
1913 int fifo_space, fifo_pkt_len;
1914
1eca7b82 1915 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD		 1916
1917 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1918 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD		 1919
1920 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1921 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1922 return (0);
f647ad3d 1923 else
87307ba1 1924 return (1);
984263bc
MD		 1925 }
1926 }
87307ba1 1927 return (0);
984263bc
MD		 1928}
1929
1930static void
1931em_82547_update_fifo_head(struct adapter *adapter, int len)
1932{
1eca7b82 1933 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1934
984263bc
MD		 1935 /* tx_fifo_head is always 16 byte aligned */
1936 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ		 1937 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1938 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD		 1939}
1940
984263bc
MD		 1941static int
1942em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1943{
984263bc
MD		 1944 uint32_t tctl;
1945
9c80d176
SZ		 1946 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1947 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1948 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1949 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1950 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1951 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1952 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1953 /* Disable TX unit */
9c80d176
SZ		 1954 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1955 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1956 tctl & ~E1000_TCTL_EN);
984263bc
MD		 1957
1958 /* Reset FIFO pointers */
9c80d176
SZ		 1959 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1960 adapter->tx_head_addr);
1961 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1962 adapter->tx_head_addr);
1963 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1964 adapter->tx_head_addr);
1965 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1966 adapter->tx_head_addr);
984263bc
MD		 1967
1968 /* Re-enable TX unit */
9c80d176 1969 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD		 1970 E1000_WRITE_FLUSH(&adapter->hw);
1971
1972 adapter->tx_fifo_head = 0;
eac00e59 1973 adapter->tx_fifo_reset_cnt++;
984263bc 1974
87307ba1 1975 return (TRUE);
eac00e59 1976 } else {
87307ba1 1977 return (FALSE);
984263bc
MD		 1978 }
1979}
1980
1981static void
f647ad3d 1982em_set_promisc(struct adapter *adapter)
984263bc 1983{
9c80d176 1984 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1985 uint32_t reg_rctl;
984263bc 1986
9c80d176 1987 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD		 1988
1989 if (ifp->if_flags & IFF_PROMISC) {
1990 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ		 1991 /* Turn this on if you want to see bad packets */
1992 if (em_debug_sbp)
1993 reg_rctl |= E1000_RCTL_SBP;
1994 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD		 1995 } else if (ifp->if_flags & IFF_ALLMULTI) {
1996 reg_rctl |= E1000_RCTL_MPE;
1997 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1998 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1999 }
984263bc
MD		 2000}
2001
2002static void
f647ad3d 2003em_disable_promisc(struct adapter *adapter)
984263bc 2004{
f647ad3d 2005 uint32_t reg_rctl;
984263bc 2006
9c80d176 2007 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 2008
9c80d176
SZ		 2009 reg_rctl &= ~E1000_RCTL_UPE;
2010 reg_rctl &= ~E1000_RCTL_MPE;
2011 reg_rctl &= ~E1000_RCTL_SBP;
2012 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD		 2013}
2014
984263bc 2015static void
f647ad3d 2016em_set_multi(struct adapter *adapter)
984263bc 2017{
9c80d176 2018 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 2019 struct ifmultiaddr *ifma;
9c80d176 2020 uint32_t reg_rctl = 0;
2d0e5700 2021 uint8_t *mta;
f647ad3d 2022 int mcnt = 0;
f647ad3d 2023
2d0e5700
SZ		 2024 mta = adapter->mta;
2025 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
2026
9c80d176
SZ		 2027 if (adapter->hw.mac.type == e1000_82542 &&
2028 adapter->hw.revision_id == E1000_REVISION_2) {
2029 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
2030 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2031 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 2032 reg_rctl |= E1000_RCTL_RST;
9c80d176 2033 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS		 2034 msec_delay(5);
2035 }
984263bc 2036
441d34b2 2037 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS		 2038 if (ifma->ifma_addr->sa_family != AF_LINK)
2039 continue;
2040
2041 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
2042 break;
984263bc 2043
f647ad3d 2044 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 2045 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS		 2046 mcnt++;
2047 }
2048
2049 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 2050 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 2051 reg_rctl |= E1000_RCTL_MPE;
9c80d176 2052 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 2053 } else {
6a5a645e 2054 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 2055 }
f647ad3d 2056
9c80d176
SZ		 2057 if (adapter->hw.mac.type == e1000_82542 &&
2058 adapter->hw.revision_id == E1000_REVISION_2) {
2059 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 2060 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 2061 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 2062 msec_delay(5);
9c80d176
SZ		 2063 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2064 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS		 2065 }
2066}
984263bc 2067
9c80d176
SZ		 2068/*
2069 * This routine checks for link status and updates statistics.
2070 */
984263bc 2071static void
9c80d176 2072em_timer(void *xsc)
984263bc 2073{
9c80d176
SZ		 2074 struct adapter *adapter = xsc;
2075 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2076
78195a76 2077 lwkt_serialize_enter(ifp->if_serializer);
984263bc 2078
87307ba1 2079 em_update_link_status(adapter);
9c80d176
SZ		 2080 em_update_stats(adapter);
2081
2082 /* Reset LAA into RAR[0] on 82571 */
2083 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
2084 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2085
2086 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 2087 em_print_hw_stats(adapter);
9c80d176 2088
984263bc
MD		 2089 em_smartspeed(adapter);
2090
9c80d176 2091 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 2092
78195a76 2093 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD		 2094}
2095
2096static void
87307ba1 2097em_update_link_status(struct adapter *adapter)
984263bc 2098{
9c80d176
SZ		 2099 struct e1000_hw *hw = &adapter->hw;
2100 struct ifnet *ifp = &adapter->arpcom.ac_if;
2101 device_t dev = adapter->dev;
2102 uint32_t link_check = 0;
2103
2104 /* Get the cached link value or read phy for real */
2105 switch (hw->phy.media_type) {
2106 case e1000_media_type_copper:
2107 if (hw->mac.get_link_status) {
2108 /* Do the work to read phy */
2109 e1000_check_for_link(hw);
2110 link_check = !hw->mac.get_link_status;
2111 if (link_check) /* ESB2 fix */
2112 e1000_cfg_on_link_up(hw);
2113 } else {
2114 link_check = TRUE;
984263bc 2115 }
9c80d176
SZ		 2116 break;
2117
2118 case e1000_media_type_fiber:
2119 e1000_check_for_link(hw);
2120 link_check =
2121 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2122 break;
2123
2124 case e1000_media_type_internal_serdes:
2125 e1000_check_for_link(hw);
2126 link_check = adapter->hw.mac.serdes_has_link;
2127 break;
2128
2129 case e1000_media_type_unknown:
2130 default:
2131 break;
2132 }
2133
2134 /* Now check for a transition */
2135 if (link_check && adapter->link_active == 0) {
2136 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2137 &adapter->link_duplex);
cb5a6be6
SZ		 2138
2139 /*
2140 * Check if we should enable/disable SPEED_MODE bit on
2141 * 82571/82572
2142 */
2d0e5700
SZ		 2143 if (adapter->link_speed != SPEED_1000 &&
2144 (hw->mac.type == e1000_82571 ||
2145 hw->mac.type == e1000_82572)) {
9c80d176
SZ		 2146 int tarc0;
2147
2148 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2149 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2150 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2151 }
9c80d176 2152 if (bootverbose) {
81ac62f7
SZ		 2153 char flowctrl[IFM_ETH_FC_STRLEN];
2154
2155 e1000_fc2str(hw->fc.current_mode, flowctrl,
2156 sizeof(flowctrl));
2157 device_printf(dev, "Link is up %d Mbps %s, "
2158 "Flow control: %s\n",
9c80d176 2159 adapter->link_speed,
81ac62f7
SZ		 2160 (adapter->link_duplex == FULL_DUPLEX) ?
2161 "Full Duplex" : "Half Duplex",
2162 flowctrl);
2163 }
9b8968bb
SZ		 2164 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
2165 e1000_force_flowctrl(hw, adapter->ifm_flowctrl);
9c80d176
SZ		 2166 adapter->link_active = 1;
2167 adapter->smartspeed = 0;
2168 ifp->if_baudrate = adapter->link_speed * 1000000;
2169 ifp->if_link_state = LINK_STATE_UP;
2170 if_link_state_change(ifp);
2171 } else if (!link_check && adapter->link_active == 1) {
2172 ifp->if_baudrate = adapter->link_speed = 0;
2173 adapter->link_duplex = 0;
2174 if (bootverbose)
2175 device_printf(dev, "Link is Down\n");
2176 adapter->link_active = 0;
2177#if 0
2178 /* Link down, disable watchdog */
2179 if->if_timer = 0;
2180#endif
2181 ifp->if_link_state = LINK_STATE_DOWN;
2182 if_link_state_change(ifp);
984263bc 2183 }
984263bc
MD		 2184}
2185
984263bc 2186static void
9c80d176 2187em_stop(struct adapter *adapter)
984263bc 2188{
9c80d176
SZ		 2189 struct ifnet *ifp = &adapter->arpcom.ac_if;
2190 int i;
984263bc 2191
1eca7b82
SZ		 2192 ASSERT_SERIALIZED(ifp->if_serializer);
2193
984263bc 2194 em_disable_intr(adapter);
9c80d176 2195
9ccd8c1f
JS		 2196 callout_stop(&adapter->timer);
2197 callout_stop(&adapter->tx_fifo_timer);
984263bc 2198
9ed293e0
SZ		 2199 ifp->if_flags &= ~IFF_RUNNING;
2200 ifq_clr_oactive(&ifp->if_snd);
af82d4bb 2201 ifp->if_timer = 0;
9c80d176
SZ		 2202
2203 e1000_reset_hw(&adapter->hw);
2204 if (adapter->hw.mac.type >= e1000_82544)
2205 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2206
2207 for (i = 0; i < adapter->num_tx_desc; i++) {
2208 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2209
2210 if (tx_buffer->m_head != NULL) {
2211 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2212 m_freem(tx_buffer->m_head);
2213 tx_buffer->m_head = NULL;
2214 }
9c80d176
SZ		 2215 }
2216
2217 for (i = 0; i < adapter->num_rx_desc; i++) {
2218 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2219
2220 if (rx_buffer->m_head != NULL) {
2221 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2222 m_freem(rx_buffer->m_head);
2223 rx_buffer->m_head = NULL;
2224 }
2225 }
c9ff32cc
SZ		 2226
2227 if (adapter->fmp != NULL)
2228 m_freem(adapter->fmp);
2229 adapter->fmp = NULL;
2230 adapter->lmp = NULL;
51e6819f
SZ		 2231
2232 adapter->csum_flags = 0;
ed4fc0fe 2233 adapter->csum_lhlen = 0;
51e6819f 2234 adapter->csum_iphlen = 0;
0bbb59f3
SZ		 2235 adapter->csum_thlen = 0;
2236 adapter->csum_mss = 0;
2237 adapter->csum_pktlen = 0;
9f60d74b
SZ		 2238
2239 adapter->tx_dd_head = 0;
2240 adapter->tx_dd_tail = 0;
2241 adapter->tx_nsegs = 0;
984263bc
MD		 2242}
2243
9c80d176
SZ		 2244static int
2245em_get_hw_info(struct adapter *adapter)
984263bc
MD		 2246{
2247 device_t dev = adapter->dev;
2248
984263bc
MD		 2249 /* Save off the information about this board */
2250 adapter->hw.vendor_id = pci_get_vendor(dev);
2251 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS		 2252 adapter->hw.revision_id = pci_get_revid(dev);
2253 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2254 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2255
9c80d176
SZ		 2256 /* Do Shared Code Init and Setup */
2257 if (e1000_set_mac_type(&adapter->hw))
2258 return ENXIO;
2259 return 0;
984263bc
MD		 2260}
2261
1eca7b82 2262static int
9c80d176 2263em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2264{
9c80d176 2265 device_t dev = adapter->dev;
053f3ae6 2266 u_int intr_flags;
84e26aaa 2267 int val, rid, msi_enable;
9c80d176
SZ		 2268
2269 /* Enable bus mastering */
2270 pci_enable_busmaster(dev);
1eca7b82 2271
9c80d176
SZ		 2272 adapter->memory_rid = EM_BAR_MEM;
2273 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2274 &adapter->memory_rid, RF_ACTIVE);
2275 if (adapter->memory == NULL) {
1eca7b82 2276 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2277 return (ENXIO);
1eca7b82
SZ		 2278 }
2279 adapter->osdep.mem_bus_space_tag =
9c80d176 2280 rman_get_bustag(adapter->memory);
1eca7b82 2281 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ		 2282 rman_get_bushandle(adapter->memory);
2283
2284 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ		 2285 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2286
9c80d176
SZ		 2287 /* Only older adapters use IO mapping */
2288 if (adapter->hw.mac.type > e1000_82543 &&
2289 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2290 /* Figure our where our IO BAR is ? */
9c80d176 2291 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2292 val = pci_read_config(dev, rid, 4);
87307ba1 2293 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ		 2294 adapter->io_rid = rid;
2295 break;
2296 }
2297 rid += 4;
87307ba1
SZ		 2298 /* check for 64bit BAR */
2299 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2300 rid += 4;
1eca7b82 2301 }
9c80d176 2302 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ		 2303 device_printf(dev, "Unable to locate IO BAR\n");
2304 return (ENXIO);
9c80d176
SZ		 2305 }
2306 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2307 &adapter->io_rid, RF_ACTIVE);
2308 if (adapter->ioport == NULL) {
1eca7b82 2309 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ		 2310 "ioport\n");
2311 return (ENXIO);
1eca7b82 2312 }
87307ba1
SZ		 2313 adapter->hw.io_base = 0;
2314 adapter->osdep.io_bus_space_tag =
9c80d176 2315 rman_get_bustag(adapter->ioport);
87307ba1 2316 adapter->osdep.io_bus_space_handle =
9c80d176 2317 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ		 2318 }
2319
84e26aaa 2320 /*
a835687d
SZ		 2321 * Don't enable MSI-X on 82574, see:
2322 * 82574 specification update errata #15
2323 *
84e26aaa 2324 * Don't enable MSI on PCI/PCI-X chips, see:
a835687d
SZ		 2325 * 82540 specification update errata #6
2326 * 82545 specification update errata #4
84e26aaa
SZ		 2327 *
2328 * Don't enable MSI on 82571/82572, see:
a835687d 2329 * 82571/82572 specification update errata #63
84e26aaa
SZ		 2330 */
2331 msi_enable = em_msi_enable;
2332 if (msi_enable &&
2333 (!pci_is_pcie(dev) ||
2334 adapter->hw.mac.type == e1000_82571 ||
2335 adapter->hw.mac.type == e1000_82572))
2336 msi_enable = 0;
2337
2338 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
053f3ae6
SZ		 2339 &adapter->intr_rid, &intr_flags);
2340
87ab432b
SZ		 2341 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2342 int unshared;
2343
2344 unshared = device_getenv_int(dev, "irq.unshared", 0);
2345 if (!unshared) {
2346 adapter->flags |= EM_FLAG_SHARED_INTR;
2347 if (bootverbose)
2348 device_printf(dev, "IRQ shared\n");
2349 } else {
2350 intr_flags &= ~RF_SHAREABLE;
2351 if (bootverbose)
2352 device_printf(dev, "IRQ unshared\n");
2353 }
2354 }
2355
9c80d176 2356 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
053f3ae6 2357 &adapter->intr_rid, intr_flags);
9c80d176 2358 if (adapter->intr_res == NULL) {
1eca7b82 2359 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ		 2360 "interrupt\n");
2361 return (ENXIO);
1eca7b82
SZ		 2362 }
2363
9c80d176 2364 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2365 adapter->hw.back = &adapter->osdep;
a483bd34 2366 return (0);
1eca7b82
SZ		 2367}
2368
2369static void
9c80d176 2370em_free_pci_res(struct adapter *adapter)
1eca7b82 2371{
9c80d176 2372 device_t dev = adapter->dev;
1eca7b82 2373
9c80d176
SZ		 2374 if (adapter->intr_res != NULL) {
2375 bus_release_resource(dev, SYS_RES_IRQ,
2376 adapter->intr_rid, adapter->intr_res);
1eca7b82 2377 }
9c80d176 2378
053f3ae6
SZ		 2379 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2380 pci_release_msi(dev);
2381
9c80d176
SZ		 2382 if (adapter->memory != NULL) {
2383 bus_release_resource(dev, SYS_RES_MEMORY,
2384 adapter->memory_rid, adapter->memory);
1eca7b82
SZ		 2385 }
2386
9c80d176
SZ		 2387 if (adapter->flash != NULL) {
2388 bus_release_resource(dev, SYS_RES_MEMORY,
2389 adapter->flash_rid, adapter->flash);
1eca7b82
SZ		 2390 }
2391
9c80d176
SZ		 2392 if (adapter->ioport != NULL) {
2393 bus_release_resource(dev, SYS_RES_IOPORT,
2394 adapter->io_rid, adapter->ioport);
1eca7b82
SZ		 2395 }
2396}
2397
984263bc 2398static int
2d0e5700 2399em_reset(struct adapter *adapter)
984263bc 2400{
9c80d176
SZ		 2401 device_t dev = adapter->dev;
2402 uint16_t rx_buffer_size;
4f87d70c 2403 uint32_t pba;
7ea52455 2404
984263bc
MD		 2405 /* When hardware is reset, fifo_head is also reset */
2406 adapter->tx_fifo_head = 0;
2407
87307ba1 2408 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2409 if (!em_smart_pwr_down &&
9c80d176
SZ		 2410 (adapter->hw.mac.type == e1000_82571 ||
2411 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ		 2412 uint16_t phy_tmp = 0;
2413
87307ba1 2414 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ		 2415 e1000_read_phy_reg(&adapter->hw,
2416 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2417 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ		 2418 e1000_write_phy_reg(&adapter->hw,
2419 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ		 2420 }
2421
4f87d70c
SZ		 2422 /*
2423 * Packet Buffer Allocation (PBA)
2424 * Writing PBA sets the receive portion of the buffer
2425 * the remainder is used for the transmit buffer.
2426 *
2427 * Devices before the 82547 had a Packet Buffer of 64K.
2428 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
2429 * After the 82547 the buffer was reduced to 40K.
2430 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
2431 * Note: default does not leave enough room for Jumbo Frame >10k.
2432 */
2433 switch (adapter->hw.mac.type) {
2434 case e1000_82547:
2435 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
c29e94c0 2436 if (adapter->hw.mac.max_frame_size > 8192)
4f87d70c
SZ		 2437 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2438 else
2439 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2440 adapter->tx_fifo_head = 0;
2441 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
2442 adapter->tx_fifo_size =
2443 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
2444 break;
2445
2446 /* Total Packet Buffer on these is 48K */
2447 case e1000_82571:
2448 case e1000_82572:
2449 case e1000_80003es2lan:
2450 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2451 break;
2452
2453 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2454 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2455 break;
2456
2457 case e1000_82574:
2458 case e1000_82583:
2459 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2460 break;
2461
2462 case e1000_ich8lan:
2463 pba = E1000_PBA_8K;
2464 break;
2465
2466 case e1000_ich9lan:
2467 case e1000_ich10lan:
2468#define E1000_PBA_10K 0x000A
2469 pba = E1000_PBA_10K;
2470 break;
2471
2472 case e1000_pchlan:
2473 case e1000_pch2lan:
91c72bdc 2474 case e1000_pch_lpt:
524ce499 2475 case e1000_pch_spt:
4f87d70c
SZ		 2476 pba = E1000_PBA_26K;
2477 break;
2478
2479 default:
2480 /* Devices before 82547 had a Packet Buffer of 64K. */
c29e94c0 2481 if (adapter->hw.mac.max_frame_size > 8192)
4f87d70c
SZ		 2482 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2483 else
2484 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2485 }
2486 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2487
7ea52455 2488 /*
87307ba1
SZ		 2489 * These parameters control the automatic generation (Tx) and
2490 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ		 2491 * - High water mark should allow for at least two frames to be
2492 * received after sending an XOFF.
2493 * - Low water mark works best when it is very near the high water mark.
2494 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ		 2495 * drained a bit. Here we use an arbitary value of 1500 which will
2496 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ		 2497 * could be several smaller frames in the buffer and if so they will
2498 * not trigger the XON until their total number reduces the buffer
2499 * by 1500.
2500 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2501 */
9c80d176
SZ		 2502 rx_buffer_size =
2503 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2504
9c80d176 2505 adapter->hw.fc.high_water = rx_buffer_size -
c29e94c0 2506 roundup2(adapter->hw.mac.max_frame_size, 1024);
9c80d176
SZ		 2507 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2508
2509 if (adapter->hw.mac.type == e1000_80003es2lan)
2510 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2511 else
9c80d176 2512 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2513
9c80d176 2514 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2515
81ac62f7 2516 adapter->hw.fc.requested_mode = e1000_ifmedia2fc(adapter->ifm_flowctrl);
7ea52455 2517
4f87d70c
SZ		 2518 /*
2519 * Device specific overrides/settings
2520 */
2521 switch (adapter->hw.mac.type) {
2522 case e1000_pchlan:
81ac62f7
SZ		 2523 KASSERT(adapter->hw.fc.requested_mode == e1000_fc_rx_pause ||
2524 adapter->hw.fc.requested_mode == e1000_fc_none,
2525 ("unsupported flow control on PCH %d",
2526 adapter->hw.fc.requested_mode));
4f87d70c
SZ		 2527 adapter->hw.fc.pause_time = 0xFFFF; /* override */
2528 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) {
2529 adapter->hw.fc.high_water = 0x3500;
2530 adapter->hw.fc.low_water = 0x1500;
2531 } else {
2532 adapter->hw.fc.high_water = 0x5000;
2533 adapter->hw.fc.low_water = 0x3000;
2534 }
2535 adapter->hw.fc.refresh_time = 0x1000;
2536 break;
2d0e5700 2537
4f87d70c 2538 case e1000_pch2lan:
91c72bdc 2539 case e1000_pch_lpt:
524ce499 2540 case e1000_pch_spt:
2d0e5700
SZ		 2541 adapter->hw.fc.high_water = 0x5C20;
2542 adapter->hw.fc.low_water = 0x5048;
2543 adapter->hw.fc.pause_time = 0x0650;
2544 adapter->hw.fc.refresh_time = 0x0400;
2d0e5700
SZ		 2545 /* Jumbos need adjusted PBA */
2546 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2547 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2548 else
2549 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
4f87d70c
SZ		 2550 break;
2551
2552 case e1000_ich9lan:
2553 case e1000_ich10lan:
2554 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) {
2555 adapter->hw.fc.high_water = 0x2800;
2556 adapter->hw.fc.low_water =
2557 adapter->hw.fc.high_water - 8;
2558 break;
2559 }
2560 /* FALL THROUGH */
2561 default:
2562 if (adapter->hw.mac.type == e1000_80003es2lan)
2563 adapter->hw.fc.pause_time = 0xFFFF;
2564 break;
2d0e5700
SZ		 2565 }
2566
2567 /* Issue a global reset */
2568 e1000_reset_hw(&adapter->hw);
2569 if (adapter->hw.mac.type >= e1000_82544)
2570 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
6d5e2922 2571 em_disable_aspm(adapter);
2d0e5700 2572
9c80d176
SZ		 2573 if (e1000_init_hw(&adapter->hw) < 0) {
2574 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2575 return (EIO);
984263bc
MD		 2576 }
2577
2d0e5700
SZ		 2578 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2579 e1000_get_phy_info(&adapter->hw);
9c80d176 2580 e1000_check_for_link(&adapter->hw);
984263bc 2581
87307ba1 2582 return (0);
984263bc
MD		 2583}
2584
984263bc 2585static void
9c80d176 2586em_setup_ifp(struct adapter *adapter)
984263bc 2587{
9c80d176 2588 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2589
9c80d176
SZ		 2590 if_initname(ifp, device_get_name(adapter->dev),
2591 device_get_unit(adapter->dev));
984263bc
MD		 2592 ifp->if_softc = adapter;
2593 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2594 ifp->if_init = em_init;
984263bc
MD		 2595 ifp->if_ioctl = em_ioctl;
2596 ifp->if_start = em_start;
350d9c84
SZ		 2597#ifdef IFPOLL_ENABLE
2598 ifp->if_npoll = em_npoll;
9c095379 2599#endif
984263bc 2600 ifp->if_watchdog = em_watchdog;
14929979 2601 ifp->if_nmbclusters = adapter->num_rx_desc;
e26dc3e9 2602 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2603 ifq_set_ready(&ifp->if_snd);
984263bc 2604
9c80d176 2605 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2606
0bbb59f3 2607 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
9c80d176 2608 if (adapter->hw.mac.type >= e1000_82543)
0bbb59f3
SZ		 2609 ifp->if_capabilities |= IFCAP_HWCSUM;
2610 if (adapter->flags & EM_FLAG_TSO)
2611 ifp->if_capabilities |= IFCAP_TSO;
9c80d176 2612 ifp->if_capenable = ifp->if_capabilities;
984263bc 2613
9c80d176 2614 if (ifp->if_capenable & IFCAP_TXCSUM)
0bbb59f3
SZ		 2615 ifp->if_hwassist |= EM_CSUM_FEATURES;
2616 if (ifp->if_capenable & IFCAP_TSO)
2617 ifp->if_hwassist |= CSUM_TSO;
21fa6062 2618
f647ad3d
JS		 2619 /*
2620 * Tell the upper layer(s) we support long frames.
2621 */
2622 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2623
87307ba1 2624 /*
984263bc
MD		 2625 * Specify the media types supported by this adapter and register
2626 * callbacks to update media and link information
2627 */
9c80d176
SZ		 2628 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2629 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2630 u_char fiber_type = IFM_1000_SX; /* default type */
2631
2632 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ		 2633 fiber_type = IFM_1000_LX;
2634 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2635 0, NULL);
984263bc
MD		 2636 } else {
2637 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2638 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2639 0, NULL);
87307ba1 2640 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2641 0, NULL);
87307ba1 2642 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2643 0, NULL);
9c80d176
SZ		 2644 if (adapter->hw.phy.type != e1000_phy_ife) {
2645 ifmedia_add(&adapter->media,
2646 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
9c80d176 2647 }
984263bc
MD		 2648 }
2649 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
81ac62f7
SZ		 2650 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO |
2651 adapter->ifm_flowctrl);
984263bc
MD		 2652}
2653
9c80d176
SZ		 2654
2655/*
2656 * Workaround for SmartSpeed on 82541 and 82547 controllers
2657 */
984263bc
MD		 2658static void
2659em_smartspeed(struct adapter *adapter)
2660{
f647ad3d
JS		 2661 uint16_t phy_tmp;
2662
9c80d176
SZ		 2663 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2664 adapter->hw.mac.autoneg == 0 ||
2665 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD		 2666 return;
2667
f647ad3d
JS		 2668 if (adapter->smartspeed == 0) {
2669 /*
2670 * If Master/Slave config fault is asserted twice,
9c80d176 2671 * we assume back-to-back
f647ad3d 2672 */
9c80d176 2673 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS		 2674 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2675 return;
9c80d176 2676 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2677 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ		 2678 e1000_read_phy_reg(&adapter->hw,
2679 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS		 2680 if (phy_tmp & CR_1000T_MS_ENABLE) {
2681 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ		 2682 e1000_write_phy_reg(&adapter->hw,
2683 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2684 adapter->smartspeed++;
9c80d176
SZ		 2685 if (adapter->hw.mac.autoneg &&
2686 !e1000_phy_setup_autoneg(&adapter->hw) &&
2687 !e1000_read_phy_reg(&adapter->hw,
2688 PHY_CONTROL, &phy_tmp)) {
2689 phy_tmp |= MII_CR_AUTO_NEG_EN |
2690 MII_CR_RESTART_AUTO_NEG;
2691 e1000_write_phy_reg(&adapter->hw,
2692 PHY_CONTROL, phy_tmp);
f647ad3d
JS		 2693 }
2694 }
2695 }
87307ba1 2696 return;
f647ad3d
JS		 2697 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2698 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2699 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2700 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ		 2701 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2702 if (adapter->hw.mac.autoneg &&
2703 !e1000_phy_setup_autoneg(&adapter->hw) &&
2704 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2705 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2706 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS		 2707 }
2708 }
9c80d176 2709
f647ad3d
JS		 2710 /* Restart process after EM_SMARTSPEED_MAX iterations */
2711 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2712 adapter->smartspeed = 0;
984263bc
MD		 2713}
2714
9ccd8c1f
JS		 2715static int
2716em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2717 struct em_dma_alloc *dma)
9ccd8c1f 2718{
9c80d176
SZ		 2719 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2720 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2721 &dma->dma_tag, &dma->dma_map,
2722 &dma->dma_paddr);
2723 if (dma->dma_vaddr == NULL)
2724 return ENOMEM;
2725 else
2726 return 0;
9ccd8c1f
JS		 2727}
2728
2729static void
2730em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2731{
9c80d176
SZ		 2732 if (dma->dma_tag == NULL)
2733 return;
2734 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2735 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2736 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD		 2737}
2738
984263bc 2739static int
9c80d176 2740em_create_tx_ring(struct adapter *adapter)
984263bc 2741{
9c80d176 2742 device_t dev = adapter->dev;
1eca7b82 2743 struct em_buffer *tx_buffer;
1eca7b82
SZ		 2744 int error, i;
2745
87307ba1
SZ		 2746 adapter->tx_buffer_area =
2747 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2748 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2749
9c80d176
SZ		 2750 /*
2751 * Create DMA tags for tx buffers
2752 */
2753 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2754 1, 0, /* alignment, bounds */
2755 BUS_SPACE_MAXADDR, /* lowaddr */
2756 BUS_SPACE_MAXADDR, /* highaddr */
2757 NULL, NULL, /* filter, filterarg */
2758 EM_TSO_SIZE, /* maxsize */
2759 EM_MAX_SCATTER, /* nsegments */
0bbb59f3 2760 PAGE_SIZE, /* maxsegsize */
9c80d176
SZ		 2761 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2762 BUS_DMA_ONEBPAGE, /* flags */
2763 &adapter->txtag);
2764 if (error) {
2765 device_printf(dev, "Unable to allocate TX DMA tag\n");
2766 kfree(adapter->tx_buffer_area, M_DEVBUF);
2767 adapter->tx_buffer_area = NULL;
2768 return error;
2769 }
2770
2771 /*
2772 * Create DMA maps for tx buffers
2773 */
1eca7b82 2774 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ		 2775 tx_buffer = &adapter->tx_buffer_area[i];
2776
2777 error = bus_dmamap_create(adapter->txtag,
2778 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2779 &tx_buffer->map);
1eca7b82 2780 if (error) {
9c80d176
SZ		 2781 device_printf(dev, "Unable to create TX DMA map\n");
2782 em_destroy_tx_ring(adapter, i);
2783 return error;
1eca7b82 2784 }
1eca7b82 2785 }
9c80d176
SZ		 2786 return (0);
2787}
9ccd8c1f 2788
9c80d176
SZ		 2789static void
2790em_init_tx_ring(struct adapter *adapter)
2791{
2792 /* Clear the old ring contents */
2793 bzero(adapter->tx_desc_base,
2794 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2795
2796 /* Reset state */
87307ba1
SZ		 2797 adapter->next_avail_tx_desc = 0;
2798 adapter->next_tx_to_clean = 0;
984263bc 2799 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD		 2800}
2801
984263bc 2802static void
9c80d176 2803em_init_tx_unit(struct adapter *adapter)
984263bc 2804{
9c80d176 2805 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS		 2806 uint64_t bus_addr;
2807
984263bc 2808 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2809 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ		 2810 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2811 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2812 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2813 (uint32_t)(bus_addr >> 32));
2814 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2815 (uint32_t)bus_addr);
984263bc 2816 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ		 2817 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2818 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2819
984263bc 2820 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ		 2821 switch (adapter->hw.mac.type) {
2822 case e1000_82542:
2823 tipg = DEFAULT_82542_TIPG_IPGT;
2824 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2825 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2826 break;
9c80d176
SZ		 2827
2828 case e1000_80003es2lan:
2829 tipg = DEFAULT_82543_TIPG_IPGR1;
2830 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2831 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2832 break;
9c80d176 2833
984263bc 2834 default:
9c80d176
SZ		 2835 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2836 adapter->hw.phy.media_type ==
2837 e1000_media_type_internal_serdes)
2838 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2839 else
9c80d176
SZ		 2840 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2841 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2842 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2843 break;
2844 }
2845
2846 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ		 2847
2848 /* NOTE: 0 is not allowed for TIDV */
2849 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2850 if(adapter->hw.mac.type >= e1000_82540)
2851 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2852
9c80d176
SZ		 2853 if (adapter->hw.mac.type == e1000_82571 ||
2854 adapter->hw.mac.type == e1000_82572) {
2855 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2856 tarc |= SPEED_MODE_BIT;
2857 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2858 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2859 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2860 tarc |= 1;
2861 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2862 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2863 tarc |= 1;
2864 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ		 2865 }
2866
984263bc 2867 /* Program the Transmit Control Register */
9c80d176
SZ		 2868 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2869 tctl &= ~E1000_TCTL_CT;
2870 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2871 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2872
2873 if (adapter->hw.mac.type >= e1000_82571)
2874 tctl |= E1000_TCTL_MULR;
1eca7b82 2875
87307ba1 2876 /* This write will effectively turn on the transmit unit. */
9c80d176 2877 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
01058531
SZ		 2878
2879 if (adapter->hw.mac.type == e1000_82571 ||
2880 adapter->hw.mac.type == e1000_82572 ||
2881 adapter->hw.mac.type == e1000_80003es2lan) {
2882 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2883 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2884 tarc &= ~(1 << 28);
2885 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2886 }
984263bc
MD		 2887}
2888
984263bc 2889static void
9c80d176 2890em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2891{
f647ad3d
JS		 2892 struct em_buffer *tx_buffer;
2893 int i;
984263bc 2894
9c80d176
SZ		 2895 if (adapter->tx_buffer_area == NULL)
2896 return;
984263bc 2897
9c80d176
SZ		 2898 for (i = 0; i < ndesc; i++) {
2899 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2900
9c80d176
SZ		 2901 KKASSERT(tx_buffer->m_head == NULL);
2902 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2903 }
9c80d176
SZ		 2904 bus_dma_tag_destroy(adapter->txtag);
2905
2906 kfree(adapter->tx_buffer_area, M_DEVBUF);
2907 adapter->tx_buffer_area = NULL;
984263bc
MD		 2908}
2909
9c80d176
SZ		 2910/*
2911 * The offload context needs to be set when we transfer the first
2912 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2913 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ		 2914 *
2915 * If the new packet's ether header length, ip header length and
2916 * csum offloading type are same as the previous packet, we should
2917 * avoid allocating a new csum context descriptor; mainly to take
2918 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ		 2919 *
2920 * This function returns number of TX descrptors allocated for
2921 * csum context.
9c80d176 2922 */
9f60d74b 2923static int
9c80d176
SZ		 2924em_txcsum(struct adapter *adapter, struct mbuf *mp,
2925 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2926{
9c80d176 2927 struct e1000_context_desc *TXD;
51e6819f 2928 int curr_txd, ehdrlen, csum_flags;
9c80d176 2929 uint32_t cmd, hdr_len, ip_hlen;
984263bc 2930
51e6819f 2931 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
ed4fc0fe
SZ		 2932 ip_hlen = mp->m_pkthdr.csum_iphlen;
2933 ehdrlen = mp->m_pkthdr.csum_lhlen;
51e6819f 2934
ed4fc0fe 2935 if (adapter->csum_lhlen == ehdrlen &&
51e6819f
SZ		 2936 adapter->csum_iphlen == ip_hlen &&
2937 adapter->csum_flags == csum_flags) {
2938 /*
2939 * Same csum offload context as the previous packets;
2940 * just return.
2941 */
2942 *txd_upper = adapter->csum_txd_upper;
2943 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2944 return 0;
984263bc
MD		 2945 }
2946
51e6819f
SZ		 2947 /*
2948 * Setup a new csum offload context.
2949 */
2950
2951 curr_txd = adapter->next_avail_tx_desc;
51e6819f
SZ		 2952 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2953
2954 cmd = 0;
2955
2956 /* Setup of IP header checksum. */
2957 if (csum_flags & CSUM_IP) {
2958 /*
2959 * Start offset for header checksum calculation.
2960 * End offset for header checksum calculation.
2961 * Offset of place to put the checksum.
2962 */
2963 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2964 TXD->lower_setup.ip_fields.ipcse =
2965 htole16(ehdrlen + ip_hlen - 1);
2966 TXD->lower_setup.ip_fields.ipcso =
2967 ehdrlen + offsetof(struct ip, ip_sum);
2968 cmd |= E1000_TXD_CMD_IP;
2969 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2970 }
2971 hdr_len = ehdrlen + ip_hlen;
2972
2973 if (csum_flags & CSUM_TCP) {
002b3a05
SZ		 2974 /*
2975 * Start offset for payload checksum calculation.
2976 * End offset for payload checksum calculation.
2977 * Offset of place to put the checksum.
2978 */
2979 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2980 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2981 TXD->upper_setup.tcp_fields.tucso =
2982 hdr_len + offsetof(struct tcphdr, th_sum);
2983 cmd |= E1000_TXD_CMD_TCP;
2984 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2985 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ		 2986 /*
2987 * Start offset for header checksum calculation.
2988 * End offset for header checksum calculation.
2989 * Offset of place to put the checksum.
2990 */
2991 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2992 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2993 TXD->upper_setup.tcp_fields.tucso =
2994 hdr_len + offsetof(struct udphdr, uh_sum);
2995 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ		 2996 }
2997
2998 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2999 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ		 3000
3001 /* Save the information for this csum offloading context */
ed4fc0fe 3002 adapter->csum_lhlen = ehdrlen;
51e6819f
SZ		 3003 adapter->csum_iphlen = ip_hlen;
3004 adapter->csum_flags = csum_flags;
3005 adapter->csum_txd_upper = *txd_upper;
3006 adapter->csum_txd_lower = *txd_lower;
3007
9c80d176
SZ		 3008 TXD->tcp_seg_setup.data = htole32(0);
3009 TXD->cmd_and_length =
2af74b85 3010 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD		 3011
3012 if (++curr_txd == adapter->num_tx_desc)
3013 curr_txd = 0;
3014
9c80d176 3015 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 3016 adapter->num_tx_desc_avail--;
9c80d176 3017
984263bc 3018 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 3019 return 1;
984263bc
MD		 3020}
3021
984263bc 3022static void
87307ba1 3023em_txeof(struct adapter *adapter)
984263bc 3024{
9c80d176 3025 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ		 3026 struct em_buffer *tx_buffer;
3027 int first, num_avail;
3028
3029 if (adapter->tx_dd_head == adapter->tx_dd_tail)
3030 return;
984263bc 3031
f647ad3d
JS		 3032 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3033 return;
984263bc 3034
9c80d176 3035 num_avail = adapter->num_tx_desc_avail;
87307ba1 3036 first = adapter->next_tx_to_clean;
9c80d176 3037
9f60d74b 3038 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 3039 struct e1000_tx_desc *tx_desc;
9f60d74b 3040 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 3041
9f60d74b 3042 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ		 3043 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
3044 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 3045
9f60d74b
SZ		 3046 if (++dd_idx == adapter->num_tx_desc)
3047 dd_idx = 0;
9c80d176 3048
9f60d74b 3049 while (first != dd_idx) {
edbfa193
SZ		 3050 logif(pkt_txclean);
3051
9f60d74b
SZ		 3052 num_avail++;
3053
4e499730 3054 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b 3055 if (tx_buffer->m_head) {
9f60d74b
SZ		 3056 bus_dmamap_unload(adapter->txtag,
3057 tx_buffer->map);
3058 m_freem(tx_buffer->m_head);
3059 tx_buffer->m_head = NULL;
3060 }
3061
3062 if (++first == adapter->num_tx_desc)
3063 first = 0;
3064 }
87307ba1
SZ		 3065 } else {
3066 break;
3067 }
f647ad3d 3068 }
9f60d74b
SZ		 3069 adapter->next_tx_to_clean = first;
3070 adapter->num_tx_desc_avail = num_avail;
3071
3072 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3073 adapter->tx_dd_head = 0;
3074 adapter->tx_dd_tail = 0;
3075 }
3076
3077 if (!EM_IS_OACTIVE(adapter)) {
9ed293e0 3078 ifq_clr_oactive(&ifp->if_snd);
9f60d74b
SZ		 3079
3080 /* All clean, turn off the timer */
3081 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3082 ifp->if_timer = 0;
3083 }
3084}
3085
3086static void
3087em_tx_collect(struct adapter *adapter)
3088{
3089 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ		 3090 struct em_buffer *tx_buffer;
3091 int tdh, first, num_avail, dd_idx = -1;
3092
3093 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3094 return;
3095
3096 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
3097 if (tdh == adapter->next_tx_to_clean)
3098 return;
3099
3100 if (adapter->tx_dd_head != adapter->tx_dd_tail)
3101 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3102
3103 num_avail = adapter->num_tx_desc_avail;
3104 first = adapter->next_tx_to_clean;
3105
3106 while (first != tdh) {
edbfa193
SZ		 3107 logif(pkt_txclean);
3108
9f60d74b
SZ		 3109 num_avail++;
3110
4e499730 3111 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b 3112 if (tx_buffer->m_head) {
9f60d74b
SZ		 3113 bus_dmamap_unload(adapter->txtag,
3114 tx_buffer->map);
3115 m_freem(tx_buffer->m_head);
3116 tx_buffer->m_head = NULL;
3117 }
3118
3119 if (first == dd_idx) {
3120 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3121 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3122 adapter->tx_dd_head = 0;
3123 adapter->tx_dd_tail = 0;
3124 dd_idx = -1;
3125 } else {
3126 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3127 }
3128 }
3129
3130 if (++first == adapter->num_tx_desc)
3131 first = 0;
3132 }
3133 adapter->next_tx_to_clean = first;
9c80d176 3134 adapter->num_tx_desc_avail = num_avail;
984263bc 3135
9f60d74b 3136 if (!EM_IS_OACTIVE(adapter)) {
9ed293e0 3137 ifq_clr_oactive(&ifp->if_snd);
afa68aa1 3138
9c80d176
SZ		 3139 /* All clean, turn off the timer */
3140 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3141 ifp->if_timer = 0;
3142 }
3143}
984263bc 3144
9c80d176
SZ		 3145/*
3146 * When Link is lost sometimes there is work still in the TX ring
3147 * which will result in a watchdog, rather than allow that do an
3148 * attempted cleanup and then reinit here. Note that this has been
3149 * seens mostly with fiber adapters.
3150 */
3151static void
3152em_tx_purge(struct adapter *adapter)
3153{
3154 struct ifnet *ifp = &adapter->arpcom.ac_if;
3155
3156 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 3157 em_tx_collect(adapter);
9c80d176
SZ		 3158 if (ifp->if_timer) {
3159 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 3160 ifp->if_timer = 0;
9c80d176
SZ		 3161 em_init(adapter);
3162 }
f647ad3d 3163 }
984263bc
MD		 3164}
3165
984263bc 3166static int
9c80d176 3167em_newbuf(struct adapter *adapter, int i, int init)
984263bc 3168{
9c80d176
SZ		 3169 struct mbuf *m;
3170 bus_dma_segment_t seg;
3171 bus_dmamap_t map;
9ccd8c1f 3172 struct em_buffer *rx_buffer;
9c80d176
SZ		 3173 int error, nseg;
3174
b5523eac 3175 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
9c80d176
SZ		 3176 if (m == NULL) {
3177 adapter->mbuf_cluster_failed++;
3178 if (init) {
3179 if_printf(&adapter->arpcom.ac_if,
3180 "Unable to allocate RX mbuf\n");
984263bc 3181 }
9c80d176 3182 return (ENOBUFS);
984263bc 3183 }
9c80d176 3184 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 3185
c29e94c0 3186 if (adapter->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
9c80d176 3187 m_adj(m, ETHER_ALIGN);
9ccd8c1f 3188
9c80d176
SZ		 3189 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3190 adapter->rx_sparemap, m,
3191 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 3192 if (error) {
9c80d176
SZ		 3193 m_freem(m);
3194 if (init) {
3195 if_printf(&adapter->arpcom.ac_if,
3196 "Unable to load RX mbuf\n");
3197 }
87307ba1 3198 return (error);
9ccd8c1f 3199 }
984263bc 3200
9c80d176
SZ		 3201 rx_buffer = &adapter->rx_buffer_area[i];
3202 if (rx_buffer->m_head != NULL)
3203 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3204
3205 map = rx_buffer->map;
3206 rx_buffer->map = adapter->rx_sparemap;
3207 adapter->rx_sparemap = map;
3208
3209 rx_buffer->m_head = m;
3210
3211 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3212 return (0);
984263bc
MD		 3213}
3214
984263bc 3215static int
9c80d176 3216em_create_rx_ring(struct adapter *adapter)
984263bc 3217{
9c80d176 3218 device_t dev = adapter->dev;
9ccd8c1f 3219 struct em_buffer *rx_buffer;
9c80d176
SZ		 3220 int i, error;
3221
3222 adapter->rx_buffer_area =
3223 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3224 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3225
9c80d176
SZ		 3226 /*
3227 * Create DMA tag for rx buffers
3228 */
3229 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3230 1, 0, /* alignment, bounds */
3231 BUS_SPACE_MAXADDR, /* lowaddr */
3232 BUS_SPACE_MAXADDR, /* highaddr */
3233 NULL, NULL, /* filter, filterarg */
3234 MCLBYTES, /* maxsize */
3235 1, /* nsegments */
3236 MCLBYTES, /* maxsegsize */
3237 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3238 &adapter->rxtag);
87307ba1 3239 if (error) {
9c80d176
SZ		 3240 device_printf(dev, "Unable to allocate RX DMA tag\n");
3241 kfree(adapter->rx_buffer_area, M_DEVBUF);
3242 adapter->rx_buffer_area = NULL;
3243 return error;
3244 }
3245