ig_hal/em/emx: Add I219 (Skylake) support
[dragonfly.git] / sys / dev / netif / ig_hal / e1000_hw.h
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1/******************************************************************************
2
4765c386 3 Copyright (c) 2001-2014, Intel Corporation
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4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
379ebbe7 33/*$FreeBSD:$*/
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34
35#ifndef _E1000_HW_H_
36#define _E1000_HW_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41
42struct e1000_hw;
43
6a5a645e 44#ifndef NO_82542_SUPPORT
4be59a01 45#define E1000_DEV_ID_82542 0x1000
6a5a645e 46#endif
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47#define E1000_DEV_ID_82543GC_FIBER 0x1001
48#define E1000_DEV_ID_82543GC_COPPER 0x1004
49#define E1000_DEV_ID_82544EI_COPPER 0x1008
50#define E1000_DEV_ID_82544EI_FIBER 0x1009
51#define E1000_DEV_ID_82544GC_COPPER 0x100C
52#define E1000_DEV_ID_82544GC_LOM 0x100D
53#define E1000_DEV_ID_82540EM 0x100E
54#define E1000_DEV_ID_82540EM_LOM 0x1015
55#define E1000_DEV_ID_82540EP_LOM 0x1016
56#define E1000_DEV_ID_82540EP 0x1017
57#define E1000_DEV_ID_82540EP_LP 0x101E
58#define E1000_DEV_ID_82545EM_COPPER 0x100F
59#define E1000_DEV_ID_82545EM_FIBER 0x1011
60#define E1000_DEV_ID_82545GM_COPPER 0x1026
61#define E1000_DEV_ID_82545GM_FIBER 0x1027
62#define E1000_DEV_ID_82545GM_SERDES 0x1028
63#define E1000_DEV_ID_82546EB_COPPER 0x1010
64#define E1000_DEV_ID_82546EB_FIBER 0x1012
65#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
66#define E1000_DEV_ID_82546GB_COPPER 0x1079
67#define E1000_DEV_ID_82546GB_FIBER 0x107A
68#define E1000_DEV_ID_82546GB_SERDES 0x107B
69#define E1000_DEV_ID_82546GB_PCIE 0x108A
70#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
71#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
72#define E1000_DEV_ID_82541EI 0x1013
73#define E1000_DEV_ID_82541EI_MOBILE 0x1018
74#define E1000_DEV_ID_82541ER_LOM 0x1014
75#define E1000_DEV_ID_82541ER 0x1078
76#define E1000_DEV_ID_82541GI 0x1076
77#define E1000_DEV_ID_82541GI_LF 0x107C
78#define E1000_DEV_ID_82541GI_MOBILE 0x1077
79#define E1000_DEV_ID_82547EI 0x1019
80#define E1000_DEV_ID_82547EI_MOBILE 0x101A
81#define E1000_DEV_ID_82547GI 0x1075
82#define E1000_DEV_ID_82571EB_COPPER 0x105E
83#define E1000_DEV_ID_82571EB_FIBER 0x105F
84#define E1000_DEV_ID_82571EB_SERDES 0x1060
85#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
86#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
87#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
88#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
89#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
90#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
91#define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0
92#define E1000_DEV_ID_82572EI_COPPER 0x107D
93#define E1000_DEV_ID_82572EI_FIBER 0x107E
94#define E1000_DEV_ID_82572EI_SERDES 0x107F
95#define E1000_DEV_ID_82572EI 0x10B9
96#define E1000_DEV_ID_82573E 0x108B
97#define E1000_DEV_ID_82573E_IAMT 0x108C
98#define E1000_DEV_ID_82573L 0x109A
99#define E1000_DEV_ID_82574L 0x10D3
100#define E1000_DEV_ID_82574LA 0x10F6
101#define E1000_DEV_ID_82583V 0x150C
102#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
103#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
104#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
105#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
106#define E1000_DEV_ID_ICH8_82567V_3 0x1501
107#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
108#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
109#define E1000_DEV_ID_ICH8_IGP_C 0x104B
110#define E1000_DEV_ID_ICH8_IFE 0x104C
111#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
112#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
113#define E1000_DEV_ID_ICH8_IGP_M 0x104D
114#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
115#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
116#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
117#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
118#define E1000_DEV_ID_ICH9_BM 0x10E5
119#define E1000_DEV_ID_ICH9_IGP_C 0x294C
120#define E1000_DEV_ID_ICH9_IFE 0x10C0
121#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
122#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
123#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
124#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
125#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
126#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
127#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
128#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
129
130#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
131#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
132#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
133#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
134#define E1000_DEV_ID_PCH2_LV_LM 0x1502
135#define E1000_DEV_ID_PCH2_LV_V 0x1503
136
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137#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
138#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
139#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
140#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
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141#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
142#define E1000_DEV_ID_PCH_I218_V2 0x15A1
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143#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
144#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
145#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT */
146#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570
147#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7
148#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8
379ebbe7 149
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150#define E1000_DEV_ID_82576 0x10C9
151#define E1000_DEV_ID_82576_FIBER 0x10E6
152#define E1000_DEV_ID_82576_SERDES 0x10E7
153#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
154#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
155#define E1000_DEV_ID_82576_NS 0x150A
156#define E1000_DEV_ID_82576_NS_SERDES 0x1518
157#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
158#define E1000_DEV_ID_82576_VF 0x10CA
379ebbe7 159#define E1000_DEV_ID_82576_VF_HV 0x152D
4be59a01 160#define E1000_DEV_ID_I350_VF 0x1520
379ebbe7 161#define E1000_DEV_ID_I350_VF_HV 0x152F
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162#define E1000_DEV_ID_82575EB_COPPER 0x10A7
163#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
164#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
165#define E1000_DEV_ID_82580_COPPER 0x150E
166#define E1000_DEV_ID_82580_FIBER 0x150F
167#define E1000_DEV_ID_82580_SERDES 0x1510
168#define E1000_DEV_ID_82580_SGMII 0x1511
169#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
170#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
171#define E1000_DEV_ID_I350_COPPER 0x1521
172#define E1000_DEV_ID_I350_FIBER 0x1522
173#define E1000_DEV_ID_I350_SERDES 0x1523
174#define E1000_DEV_ID_I350_SGMII 0x1524
175#define E1000_DEV_ID_I350_DA4 0x1546
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176#define E1000_DEV_ID_I210_COPPER 0x1533
177#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
178#define E1000_DEV_ID_I210_COPPER_IT 0x1535
179#define E1000_DEV_ID_I210_FIBER 0x1536
180#define E1000_DEV_ID_I210_SERDES 0x1537
181#define E1000_DEV_ID_I210_SGMII 0x1538
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182#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
183#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
4be59a01 184#define E1000_DEV_ID_I211_COPPER 0x1539
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185#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
186#define E1000_DEV_ID_I354_SGMII 0x1F41
ba0123e0 187#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
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188#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
189#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
190#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
191#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
192
193#define E1000_REVISION_0 0
194#define E1000_REVISION_1 1
195#define E1000_REVISION_2 2
196#define E1000_REVISION_3 3
197#define E1000_REVISION_4 4
198
199#define E1000_FUNC_0 0
200#define E1000_FUNC_1 1
201#define E1000_FUNC_2 2
202#define E1000_FUNC_3 3
203
204#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
205#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
206#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
207#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
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208
209enum e1000_mac_type {
210 e1000_undefined = 0,
6a5a645e 211#ifndef NO_82542_SUPPORT
9c80d176 212 e1000_82542,
6a5a645e 213#endif
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214 e1000_82543,
215 e1000_82544,
216 e1000_82540,
217 e1000_82545,
218 e1000_82545_rev_3,
219 e1000_82546,
220 e1000_82546_rev_3,
221 e1000_82541,
222 e1000_82541_rev_2,
223 e1000_82547,
224 e1000_82547_rev_2,
225 e1000_82571,
226 e1000_82572,
227 e1000_82573,
228 e1000_82574,
6a5a645e 229 e1000_82583,
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230 e1000_80003es2lan,
231 e1000_ich8lan,
232 e1000_ich9lan,
233 e1000_ich10lan,
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234 e1000_pchlan,
235 e1000_pch2lan,
379ebbe7 236 e1000_pch_lpt,
524ce499 237 e1000_pch_spt,
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238 e1000_82575,
239 e1000_82576,
240 e1000_82580,
241 e1000_i350,
379ebbe7 242 e1000_i354,
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243 e1000_i210,
244 e1000_i211,
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245 e1000_vfadapt,
246 e1000_vfadapt_i350,
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247 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
248};
249
250enum e1000_media_type {
251 e1000_media_type_unknown = 0,
252 e1000_media_type_copper = 1,
253 e1000_media_type_fiber = 2,
254 e1000_media_type_internal_serdes = 3,
255 e1000_num_media_types
256};
257
258enum e1000_nvm_type {
259 e1000_nvm_unknown = 0,
260 e1000_nvm_none,
261 e1000_nvm_eeprom_spi,
262 e1000_nvm_eeprom_microwire,
263 e1000_nvm_flash_hw,
379ebbe7 264 e1000_nvm_invm,
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265 e1000_nvm_flash_sw
266};
267
268enum e1000_nvm_override {
269 e1000_nvm_override_none = 0,
270 e1000_nvm_override_spi_small,
271 e1000_nvm_override_spi_large,
272 e1000_nvm_override_microwire_small,
273 e1000_nvm_override_microwire_large
274};
275
276enum e1000_phy_type {
277 e1000_phy_unknown = 0,
278 e1000_phy_none,
279 e1000_phy_m88,
280 e1000_phy_igp,
281 e1000_phy_igp_2,
282 e1000_phy_gg82563,
283 e1000_phy_igp_3,
284 e1000_phy_ife,
285 e1000_phy_bm,
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286 e1000_phy_82578,
287 e1000_phy_82577,
288 e1000_phy_82579,
51d2b0a7 289 e1000_phy_i217,
6a5a645e 290 e1000_phy_82580,
62583d18 291 e1000_phy_vf,
4be59a01 292 e1000_phy_i210,
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293};
294
295enum e1000_bus_type {
296 e1000_bus_type_unknown = 0,
297 e1000_bus_type_pci,
298 e1000_bus_type_pcix,
299 e1000_bus_type_pci_express,
300 e1000_bus_type_reserved
301};
302
303enum e1000_bus_speed {
304 e1000_bus_speed_unknown = 0,
305 e1000_bus_speed_33,
306 e1000_bus_speed_66,
307 e1000_bus_speed_100,
308 e1000_bus_speed_120,
309 e1000_bus_speed_133,
310 e1000_bus_speed_2500,
311 e1000_bus_speed_5000,
312 e1000_bus_speed_reserved
313};
314
315enum e1000_bus_width {
316 e1000_bus_width_unknown = 0,
317 e1000_bus_width_pcie_x1,
318 e1000_bus_width_pcie_x2,
319 e1000_bus_width_pcie_x4 = 4,
320 e1000_bus_width_pcie_x8 = 8,
321 e1000_bus_width_32,
322 e1000_bus_width_64,
323 e1000_bus_width_reserved
324};
325
326enum e1000_1000t_rx_status {
327 e1000_1000t_rx_status_not_ok = 0,
328 e1000_1000t_rx_status_ok,
329 e1000_1000t_rx_status_undefined = 0xFF
330};
331
332enum e1000_rev_polarity {
333 e1000_rev_polarity_normal = 0,
334 e1000_rev_polarity_reversed,
335 e1000_rev_polarity_undefined = 0xFF
336};
337
338enum e1000_fc_mode {
339 e1000_fc_none = 0,
340 e1000_fc_rx_pause,
341 e1000_fc_tx_pause,
342 e1000_fc_full,
343 e1000_fc_default = 0xFF
344};
345
346enum e1000_ffe_config {
347 e1000_ffe_config_enabled = 0,
348 e1000_ffe_config_active,
349 e1000_ffe_config_blocked
350};
351
352enum e1000_dsp_config {
353 e1000_dsp_config_disabled = 0,
354 e1000_dsp_config_enabled,
355 e1000_dsp_config_activated,
356 e1000_dsp_config_undefined = 0xFF
357};
358
359enum e1000_ms_type {
360 e1000_ms_hw_default = 0,
361 e1000_ms_force_master,
362 e1000_ms_force_slave,
363 e1000_ms_auto
364};
365
366enum e1000_smart_speed {
367 e1000_smart_speed_default = 0,
368 e1000_smart_speed_on,
369 e1000_smart_speed_off
370};
371
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372enum e1000_serdes_link_state {
373 e1000_serdes_link_down = 0,
374 e1000_serdes_link_autoneg_progress,
375 e1000_serdes_link_autoneg_complete,
376 e1000_serdes_link_forced_up
377};
378
379#define __le16 u16
380#define __le32 u32
381#define __le64 u64
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382/* Receive Descriptor */
383struct e1000_rx_desc {
384 __le64 buffer_addr; /* Address of the descriptor's data buffer */
385 __le16 length; /* Length of data DMAed into data buffer */
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386 __le16 csum; /* Packet checksum */
387 u8 status; /* Descriptor status */
388 u8 errors; /* Descriptor Errors */
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389 __le16 special;
390};
391
392/* Receive Descriptor - Extended */
393union e1000_rx_desc_extended {
394 struct {
395 __le64 buffer_addr;
396 __le64 reserved;
397 } read;
398 struct {
399 struct {
4be59a01 400 __le32 mrq; /* Multiple Rx Queues */
9c80d176 401 union {
4be59a01 402 __le32 rss; /* RSS Hash */
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403 struct {
404 __le16 ip_id; /* IP id */
405 __le16 csum; /* Packet Checksum */
406 } csum_ip;
407 } hi_dword;
408 } lower;
409 struct {
410 __le32 status_error; /* ext status/error */
411 __le16 length;
4be59a01 412 __le16 vlan; /* VLAN tag */
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413 } upper;
414 } wb; /* writeback */
415};
416
417#define MAX_PS_BUFFERS 4
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418
419/* Number of packet split data buffers (not including the header buffer) */
420#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
421
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422/* Receive Descriptor - Packet Split */
423union e1000_rx_desc_packet_split {
424 struct {
425 /* one buffer for protocol header(s), three data buffers */
426 __le64 buffer_addr[MAX_PS_BUFFERS];
427 } read;
428 struct {
429 struct {
4be59a01 430 __le32 mrq; /* Multiple Rx Queues */
9c80d176 431 union {
4be59a01 432 __le32 rss; /* RSS Hash */
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433 struct {
434 __le16 ip_id; /* IP id */
435 __le16 csum; /* Packet Checksum */
436 } csum_ip;
437 } hi_dword;
438 } lower;
439 struct {
440 __le32 status_error; /* ext status/error */
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441 __le16 length0; /* length of buffer 0 */
442 __le16 vlan; /* VLAN tag */
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443 } middle;
444 struct {
445 __le16 header_status;
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446 /* length of buffers 1-3 */
447 __le16 length[PS_PAGE_BUFFERS];
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448 } upper;
449 __le64 reserved;
450 } wb; /* writeback */
451};
452
453/* Transmit Descriptor */
454struct e1000_tx_desc {
455 __le64 buffer_addr; /* Address of the descriptor's data buffer */
456 union {
457 __le32 data;
458 struct {
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459 __le16 length; /* Data buffer length */
460 u8 cso; /* Checksum offset */
461 u8 cmd; /* Descriptor control */
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462 } flags;
463 } lower;
464 union {
465 __le32 data;
466 struct {
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467 u8 status; /* Descriptor status */
468 u8 css; /* Checksum start */
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469 __le16 special;
470 } fields;
471 } upper;
472};
473
474/* Offload Context Descriptor */
475struct e1000_context_desc {
476 union {
477 __le32 ip_config;
478 struct {
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479 u8 ipcss; /* IP checksum start */
480 u8 ipcso; /* IP checksum offset */
481 __le16 ipcse; /* IP checksum end */
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482 } ip_fields;
483 } lower_setup;
484 union {
485 __le32 tcp_config;
486 struct {
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487 u8 tucss; /* TCP checksum start */
488 u8 tucso; /* TCP checksum offset */
489 __le16 tucse; /* TCP checksum end */
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490 } tcp_fields;
491 } upper_setup;
492 __le32 cmd_and_length;
493 union {
494 __le32 data;
495 struct {
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496 u8 status; /* Descriptor status */
497 u8 hdr_len; /* Header length */
498 __le16 mss; /* Maximum segment size */
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499 } fields;
500 } tcp_seg_setup;
501};
502
503/* Offload data descriptor */
504struct e1000_data_desc {
4be59a01 505 __le64 buffer_addr; /* Address of the descriptor's buffer address */
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506 union {
507 __le32 data;
508 struct {
4be59a01 509 __le16 length; /* Data buffer length */
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510 u8 typ_len_ext;
511 u8 cmd;
512 } flags;
513 } lower;
514 union {
515 __le32 data;
516 struct {
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517 u8 status; /* Descriptor status */
518 u8 popts; /* Packet Options */
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519 __le16 special;
520 } fields;
521 } upper;
522};
523
524/* Statistics counters collected by the MAC */
525struct e1000_hw_stats {
526 u64 crcerrs;
527 u64 algnerrc;
528 u64 symerrs;
529 u64 rxerrc;
530 u64 mpc;
531 u64 scc;
532 u64 ecol;
533 u64 mcc;
534 u64 latecol;
535 u64 colc;
536 u64 dc;
537 u64 tncrs;
538 u64 sec;
539 u64 cexterr;
540 u64 rlec;
541 u64 xonrxc;
542 u64 xontxc;
543 u64 xoffrxc;
544 u64 xofftxc;
545 u64 fcruc;
546 u64 prc64;
547 u64 prc127;
548 u64 prc255;
549 u64 prc511;
550 u64 prc1023;
551 u64 prc1522;
552 u64 gprc;
553 u64 bprc;
554 u64 mprc;
555 u64 gptc;
556 u64 gorc;
557 u64 gotc;
558 u64 rnbc;
559 u64 ruc;
560 u64 rfc;
561 u64 roc;
562 u64 rjc;
563 u64 mgprc;
564 u64 mgpdc;
565 u64 mgptc;
566 u64 tor;
567 u64 tot;
568 u64 tpr;
569 u64 tpt;
570 u64 ptc64;
571 u64 ptc127;
572 u64 ptc255;
573 u64 ptc511;
574 u64 ptc1023;
575 u64 ptc1522;
576 u64 mptc;
577 u64 bptc;
578 u64 tsctc;
579 u64 tsctfc;
580 u64 iac;
581 u64 icrxptc;
582 u64 icrxatc;
583 u64 ictxptc;
584 u64 ictxatc;
585 u64 ictxqec;
586 u64 ictxqmtc;
587 u64 icrxdmtc;
588 u64 icrxoc;
589 u64 cbtmpc;
590 u64 htdpmc;
591 u64 cbrdpc;
592 u64 cbrmpc;
593 u64 rpthc;
594 u64 hgptc;
595 u64 htcbdpc;
596 u64 hgorc;
597 u64 hgotc;
598 u64 lenerrs;
599 u64 scvpc;
600 u64 hrmpc;
601 u64 doosync;
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602 u64 o2bgptc;
603 u64 o2bspc;
604 u64 b2ospc;
605 u64 b2ogprc;
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606};
607
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608struct e1000_vf_stats {
609 u64 base_gprc;
610 u64 base_gptc;
611 u64 base_gorc;
612 u64 base_gotc;
613 u64 base_mprc;
614 u64 base_gotlbc;
615 u64 base_gptlbc;
616 u64 base_gorlbc;
617 u64 base_gprlbc;
618
619 u32 last_gprc;
620 u32 last_gptc;
621 u32 last_gorc;
622 u32 last_gotc;
623 u32 last_mprc;
624 u32 last_gotlbc;
625 u32 last_gptlbc;
626 u32 last_gorlbc;
627 u32 last_gprlbc;
628
629 u64 gprc;
630 u64 gptc;
631 u64 gorc;
632 u64 gotc;
633 u64 mprc;
634 u64 gotlbc;
635 u64 gptlbc;
636 u64 gorlbc;
637 u64 gprlbc;
638};
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639
640struct e1000_phy_stats {
641 u32 idle_errors;
642 u32 receive_errors;
643};
644
645struct e1000_host_mng_dhcp_cookie {
646 u32 signature;
647 u8 status;
648 u8 reserved0;
649 u16 vlan_id;
650 u32 reserved1;
651 u16 reserved2;
652 u8 reserved3;
653 u8 checksum;
654};
655
656/* Host Interface "Rev 1" */
657struct e1000_host_command_header {
658 u8 command_id;
659 u8 command_length;
660 u8 command_options;
661 u8 checksum;
662};
663
4be59a01 664#define E1000_HI_MAX_DATA_LENGTH 252
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665struct e1000_host_command_info {
666 struct e1000_host_command_header command_header;
667 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
668};
669
670/* Host Interface "Rev 2" */
671struct e1000_host_mng_command_header {
672 u8 command_id;
673 u8 checksum;
674 u16 reserved1;
675 u16 reserved2;
676 u16 command_length;
677};
678
4be59a01 679#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
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680struct e1000_host_mng_command_info {
681 struct e1000_host_mng_command_header command_header;
682 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
683};
684
685#include "e1000_mac.h"
686#include "e1000_phy.h"
687#include "e1000_nvm.h"
688#include "e1000_manage.h"
62583d18 689#include "e1000_mbx.h"
9c80d176 690
379ebbe7 691/* Function pointers for the MAC. */
9c80d176 692struct e1000_mac_operations {
9c80d176 693 s32 (*init_params)(struct e1000_hw *);
6a5a645e 694 s32 (*id_led_init)(struct e1000_hw *);
9c80d176 695 s32 (*blink_led)(struct e1000_hw *);
379ebbe7 696 bool (*check_mng_mode)(struct e1000_hw *);
9c80d176 697 s32 (*check_for_link)(struct e1000_hw *);
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698 s32 (*cleanup_led)(struct e1000_hw *);
699 void (*clear_hw_cntrs)(struct e1000_hw *);
700 void (*clear_vfta)(struct e1000_hw *);
701 s32 (*get_bus_info)(struct e1000_hw *);
702 void (*set_lan_id)(struct e1000_hw *);
703 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
704 s32 (*led_on)(struct e1000_hw *);
705 s32 (*led_off)(struct e1000_hw *);
6a5a645e 706 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
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707 s32 (*reset_hw)(struct e1000_hw *);
708 s32 (*init_hw)(struct e1000_hw *);
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709 void (*shutdown_serdes)(struct e1000_hw *);
710 void (*power_up_serdes)(struct e1000_hw *);
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711 s32 (*setup_link)(struct e1000_hw *);
712 s32 (*setup_physical_interface)(struct e1000_hw *);
713 s32 (*setup_led)(struct e1000_hw *);
714 void (*write_vfta)(struct e1000_hw *, u32, u32);
9c80d176 715 void (*config_collision_dist)(struct e1000_hw *);
4765c386 716 int (*rar_set)(struct e1000_hw *, u8*, u32);
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717 s32 (*read_mac_addr)(struct e1000_hw *);
718 s32 (*validate_mdi_setting)(struct e1000_hw *);
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719 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
720 void (*release_swfw_sync)(struct e1000_hw *, u16);
379ebbe7 721 s32 (*set_obff_timer)(struct e1000_hw *, u32);
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722};
723
379ebbe7 724/* When to use various PHY register access functions:
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725 *
726 * Func Caller
727 * Function Does Does When to use
728 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
729 * X_reg L,P,A n/a for simple PHY reg accesses
730 * X_reg_locked P,A L for multiple accesses of different regs
731 * on different pages
732 * X_reg_page A L,P for multiple accesses of different regs
733 * on the same page
734 *
735 * Where X=[read|write], L=locking, P=sets page, A=register access
736 *
737 */
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738struct e1000_phy_operations {
739 s32 (*init_params)(struct e1000_hw *);
740 s32 (*acquire)(struct e1000_hw *);
741 s32 (*cfg_on_link_up)(struct e1000_hw *);
742 s32 (*check_polarity)(struct e1000_hw *);
743 s32 (*check_reset_block)(struct e1000_hw *);
744 s32 (*commit)(struct e1000_hw *);
745 s32 (*force_speed_duplex)(struct e1000_hw *);
746 s32 (*get_cfg_done)(struct e1000_hw *hw);
747 s32 (*get_cable_length)(struct e1000_hw *);
748 s32 (*get_info)(struct e1000_hw *);
6d5e2922 749 s32 (*set_page)(struct e1000_hw *, u16);
9c80d176 750 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
6a5a645e 751 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
6d5e2922 752 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
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753 void (*release)(struct e1000_hw *);
754 s32 (*reset)(struct e1000_hw *);
755 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
756 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
757 s32 (*write_reg)(struct e1000_hw *, u32, u16);
6a5a645e 758 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
6d5e2922 759 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
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760 void (*power_up)(struct e1000_hw *);
761 void (*power_down)(struct e1000_hw *);
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762 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
763 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
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764};
765
379ebbe7 766/* Function pointers for the NVM. */
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767struct e1000_nvm_operations {
768 s32 (*init_params)(struct e1000_hw *);
769 s32 (*acquire)(struct e1000_hw *);
770 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
771 void (*release)(struct e1000_hw *);
772 void (*reload)(struct e1000_hw *);
773 s32 (*update)(struct e1000_hw *);
774 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
775 s32 (*validate)(struct e1000_hw *);
776 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
777};
778
779struct e1000_mac_info {
780 struct e1000_mac_operations ops;
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781 u8 addr[ETH_ADDR_LEN];
782 u8 perm_addr[ETH_ADDR_LEN];
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783
784 enum e1000_mac_type type;
785
786 u32 collision_delta;
787 u32 ledctl_default;
788 u32 ledctl_mode1;
789 u32 ledctl_mode2;
790 u32 mc_filter_type;
791 u32 tx_packet_delta;
792 u32 txcw;
793
794 u16 current_ifs_val;
795 u16 ifs_max_val;
796 u16 ifs_min_val;
797 u16 ifs_ratio;
798 u16 ifs_step_size;
799 u16 mta_reg_count;
62583d18 800 u16 uta_reg_count;
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801
802 /* Maximum size of the MTA register table in all supported adapters */
ba0123e0 803#define MAX_MTA_REG 128
6a5a645e 804 u32 mta_shadow[MAX_MTA_REG];
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805 u16 rar_entry_count;
806
807 u8 forced_speed_duplex;
808
809 bool adaptive_ifs;
6a5a645e 810 bool has_fwsm;
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811 bool arc_subsystem_valid;
812 bool asf_firmware_present;
813 bool autoneg;
814 bool autoneg_failed;
815 bool get_link_status;
816 bool in_ifs_mode;
6a5a645e 817#ifndef NO_82542_SUPPORT
9c80d176 818 bool report_tx_early;
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819#endif
820 enum e1000_serdes_link_state serdes_link_state;
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821 bool serdes_has_link;
822 bool tx_pkt_filtering;
379ebbe7 823 u32 max_frame_size;
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824};
825
826struct e1000_phy_info {
827 struct e1000_phy_operations ops;
828 enum e1000_phy_type type;
829
830 enum e1000_1000t_rx_status local_rx;
831 enum e1000_1000t_rx_status remote_rx;
832 enum e1000_ms_type ms_type;
833 enum e1000_ms_type original_ms_type;
834 enum e1000_rev_polarity cable_polarity;
835 enum e1000_smart_speed smart_speed;
836
837 u32 addr;
838 u32 id;
839 u32 reset_delay_us; /* in usec */
840 u32 revision;
841
842 enum e1000_media_type media_type;
843
844 u16 autoneg_advertised;
845 u16 autoneg_mask;
846 u16 cable_length;
847 u16 max_cable_length;
848 u16 min_cable_length;
849
850 u8 mdix;
851
852 bool disable_polarity_correction;
853 bool is_mdix;
854 bool polarity_correction;
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855 bool speed_downgraded;
856 bool autoneg_wait_to_complete;
857};
858
859struct e1000_nvm_info {
860 struct e1000_nvm_operations ops;
861 enum e1000_nvm_type type;
862 enum e1000_nvm_override override;
863
864 u32 flash_bank_size;
865 u32 flash_base_addr;
866
867 u16 word_size;
868 u16 delay_usec;
869 u16 address_bits;
870 u16 opcode_bits;
871 u16 page_size;
872};
873
874struct e1000_bus_info {
875 enum e1000_bus_type type;
876 enum e1000_bus_speed speed;
877 enum e1000_bus_width width;
878
879 u16 func;
880 u16 pci_cmd_word;
881};
882
883struct e1000_fc_info {
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884 u32 high_water; /* Flow control high-water mark */
885 u32 low_water; /* Flow control low-water mark */
886 u16 pause_time; /* Flow control pause timer */
887 u16 refresh_time; /* Flow control refresh timer */
888 bool send_xon; /* Flow control send XON */
889 bool strict_ieee; /* Strict IEEE mode */
890 enum e1000_fc_mode current_mode; /* FC mode in effect */
891 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
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892};
893
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894struct e1000_dev_spec_82541 {
895 enum e1000_dsp_config dsp_config;
896 enum e1000_ffe_config ffe_config;
897 u16 spd_default;
898 bool phy_init_script;
899};
900
6a5a645e 901#ifndef NO_82542_SUPPORT
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902struct e1000_dev_spec_82542 {
903 bool dma_fairness;
904};
905
6a5a645e 906#endif /* NO_82542_SUPPORT */
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907struct e1000_dev_spec_82543 {
908 u32 tbi_compatibility;
909 bool dma_fairness;
910 bool init_phy_disabled;
911};
912
913struct e1000_dev_spec_82571 {
914 bool laa_is_present;
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915 u32 smb_counter;
916};
917
918struct e1000_dev_spec_80003es2lan {
919 bool mdic_wa_enable;
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920};
921
922struct e1000_shadow_ram {
923 u16 value;
924 bool modified;
925};
926
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927struct e1000_mbx_operations {
928 s32 (*init_params)(struct e1000_hw *hw);
929 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
930 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
931 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
932 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
933 s32 (*check_for_msg)(struct e1000_hw *, u16);
934 s32 (*check_for_ack)(struct e1000_hw *, u16);
935 s32 (*check_for_rst)(struct e1000_hw *, u16);
936};
9c80d176 937
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938struct e1000_mbx_stats {
939 u32 msgs_tx;
940 u32 msgs_rx;
941
942 u32 acks;
943 u32 reqs;
944 u32 rsts;
945};
946
947struct e1000_mbx_info {
948 struct e1000_mbx_operations ops;
949 struct e1000_mbx_stats stats;
950 u32 timeout;
951 u32 usec_delay;
952 u16 size;
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953};
954
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955struct e1000_dev_spec_82575 {
956 bool sgmii_active;
957 bool global_device_reset;
958 bool eee_disable;
4be59a01 959 bool module_plugged;
379ebbe7 960 bool clear_semaphore_once;
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961 u32 mtu;
962 struct sfp_e1000_flags eth_flags;
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963 u8 media_port;
964 bool media_changed;
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965};
966
967#define E1000_SHADOW_RAM_WORDS 2048
968
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969/* I218 PHY Ultra Low Power (ULP) states */
970enum e1000_ulp_state {
971 e1000_ulp_state_unknown,
972 e1000_ulp_state_off,
973 e1000_ulp_state_on,
974};
975
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976struct e1000_dev_spec_ich8lan {
977 bool kmrn_lock_loss_workaround_enabled;
978 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
979 bool nvm_k1_enabled;
980 bool eee_disable;
379ebbe7 981 u16 eee_lp_ability;
4765c386 982 enum e1000_ulp_state ulp_state;
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983};
984
985struct e1000_dev_spec_vf {
986 u32 vf_number;
987 u32 v2p_mailbox;
988};
989
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990struct e1000_hw {
991 void *back;
992
993 u8 *hw_addr;
994 u8 *flash_address;
995 unsigned long io_base;
996
997 struct e1000_mac_info mac;
998 struct e1000_fc_info fc;
999 struct e1000_phy_info phy;
1000 struct e1000_nvm_info nvm;
1001 struct e1000_bus_info bus;
62583d18 1002 struct e1000_mbx_info mbx;
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1003 struct e1000_host_mng_dhcp_cookie mng_cookie;
1004
1005 union {
6d5e2922 1006 struct e1000_dev_spec_82541 _82541;
6a5a645e 1007#ifndef NO_82542_SUPPORT
6d5e2922 1008 struct e1000_dev_spec_82542 _82542;
6a5a645e 1009#endif
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1010 struct e1000_dev_spec_82543 _82543;
1011 struct e1000_dev_spec_82571 _82571;
6a5a645e 1012 struct e1000_dev_spec_80003es2lan _80003es2lan;
6d5e2922 1013 struct e1000_dev_spec_ich8lan ich8lan;
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1014 struct e1000_dev_spec_82575 _82575;
1015 struct e1000_dev_spec_vf vf;
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1016 } dev_spec;
1017
1018 u16 device_id;
1019 u16 subsystem_vendor_id;
1020 u16 subsystem_device_id;
1021 u16 vendor_id;
1022
1023 u8 revision_id;
1024};
1025
1026#include "e1000_82541.h"
1027#include "e1000_82543.h"
1028#include "e1000_82571.h"
1029#include "e1000_80003es2lan.h"
1030#include "e1000_ich8lan.h"
62583d18 1031#include "e1000_82575.h"
4be59a01 1032#include "e1000_i210.h"
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1033
1034/* These functions must be implemented by drivers */
6a5a645e 1035#ifndef NO_82542_SUPPORT
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1036void e1000_pci_clear_mwi(struct e1000_hw *hw);
1037void e1000_pci_set_mwi(struct e1000_hw *hw);
6a5a645e 1038#endif
9c80d176 1039s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
6d5e2922 1040s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
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1041void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1042void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1043
1044#endif