kernel: Add descriptions to the intrhooks that miss them.
[dragonfly.git] / sys / dev / sound / pci / ich.c
CommitLineData
558a398b 1/*-
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2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
25 * SUCH DAMAGE.
1de703da 26 *
61182420 27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.53.2.12 2007/07/12 06:39:38 ariff Exp $
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28 */
29
30#include <dev/sound/pcm/sound.h>
31#include <dev/sound/pcm/ac97.h>
32#include <dev/sound/pci/ich.h>
33
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34#include <bus/pci/pcireg.h>
35#include <bus/pci/pcivar.h>
984263bc 36
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37/* -------------------------------------------------------------------- */
38
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39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
40#define ICH_DTBL_LENGTH 32
41#define ICH_DEFAULT_BUFSZ 16384
42#define ICH_MAX_BUFSZ 65536
43#define ICH_MIN_BUFSZ 4096
44#define ICH_DEFAULT_BLKCNT 2
45#define ICH_MAX_BLKCNT 32
46#define ICH_MIN_BLKCNT 2
47#define ICH_MIN_BLKSZ 64
984263bc 48
558a398b
SS
49#define INTEL_VENDORID 0x8086
50#define SIS_VENDORID 0x1039
51#define NVIDIA_VENDORID 0x10de
52#define AMD_VENDORID 0x1022
53
54#define INTEL_82440MX 0x7195
55#define INTEL_82801AA 0x2415
56#define INTEL_82801AB 0x2425
57#define INTEL_82801BA 0x2445
58#define INTEL_82801CA 0x2485
59#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
60#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
61#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
62#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
63#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
64#define SIS_7012 0x7012 /* SiS 7012 needs special handling */
65#define NVIDIA_NFORCE 0x01b1
66#define NVIDIA_NFORCE2 0x006a
67#define NVIDIA_NFORCE2_400 0x008a
68#define NVIDIA_NFORCE3 0x00da
69#define NVIDIA_NFORCE3_250 0x00ea
70#define NVIDIA_NFORCE4 0x0059
71#define NVIDIA_NFORCE_410_MCP 0x026b
e2339ccc 72#define NVIDIA_NFORCE4_MCP 0x003a
558a398b
SS
73#define AMD_768 0x7445
74#define AMD_8111 0x746d
75
76#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
77#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
78#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
79
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80#if 0
81#define ICH_DEBUG(stmt) do { \
82 stmt \
83} while(0)
84#else
85#define ICH_DEBUG(...)
86#endif
87
88#define ICH_CALIBRATE_DONE (1 << 0)
89#define ICH_IGNORE_PCR (1 << 1)
90#define ICH_IGNORE_RESET (1 << 2)
91#define ICH_FIXED_RATE (1 << 3)
92#define ICH_DMA_NOCACHE (1 << 4)
93#define ICH_HIGH_LATENCY (1 << 5)
94
95#if 0 /* TODO: No uncacheable DMA support in DragonFly. */
96#include <machine/specialreg.h>
97#define ICH_DMA_ATTR(sc, v, s, attr) do { \
98 vm_offset_t va = (vm_offset_t)(v); \
99 vm_size_t sz = (vm_size_t)(s); \
100 if ((sc) != NULL && ((sc)->flags & ICH_DMA_NOCACHE) && \
101 va != 0 && sz != 0) \
102 (void)pmap_change_attr(va, sz, (attr)); \
103} while(0)
104#else
105#define ICH_DMA_ATTR(...)
106#endif
107
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108static const struct ich_type {
109 uint16_t vendor;
110 uint16_t devid;
111 uint32_t options;
112#define PROBE_LOW 0x01
113 char *name;
114} ich_devs[] = {
115 { INTEL_VENDORID, INTEL_82440MX, 0,
116 "Intel 440MX" },
117 { INTEL_VENDORID, INTEL_82801AA, 0,
118 "Intel ICH (82801AA)" },
119 { INTEL_VENDORID, INTEL_82801AB, 0,
120 "Intel ICH (82801AB)" },
121 { INTEL_VENDORID, INTEL_82801BA, 0,
122 "Intel ICH2 (82801BA)" },
123 { INTEL_VENDORID, INTEL_82801CA, 0,
124 "Intel ICH3 (82801CA)" },
125 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
126 "Intel ICH4 (82801DB)" },
127 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
128 "Intel ICH5 (82801EB)" },
129 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
130 "Intel 6300ESB" },
131 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
132 "Intel ICH6 (82801FB)" },
133 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
134 "Intel ICH7 (82801GB)" },
135 { SIS_VENDORID, SIS_7012, 0,
136 "SiS 7012" },
137 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
138 "nVidia nForce" },
139 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
140 "nVidia nForce2" },
141 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
142 "nVidia nForce2 400" },
143 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
144 "nVidia nForce3" },
145 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
146 "nVidia nForce3 250" },
147 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
148 "nVidia nForce4" },
149 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0,
150 "nVidia nForce 410 MCP" },
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151 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0,
152 "nVidia nForce 4 MCP" },
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153 { AMD_VENDORID, AMD_768, 0,
154 "AMD-768" },
155 { AMD_VENDORID, AMD_8111, 0,
156 "AMD-8111" }
157};
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158
159/* buffer descriptor */
160struct ich_desc {
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161 volatile uint32_t buffer;
162 volatile uint32_t length;
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163};
164
165struct sc_info;
166
167/* channel registers */
168struct sc_chinfo {
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169 uint32_t num:8, run:1, run_save:1;
170 uint32_t blksz, blkcnt, spd;
171 uint32_t regbase, spdreg;
172 uint32_t imask;
173 uint32_t civ;
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174
175 struct snd_dbuf *buffer;
176 struct pcm_channel *channel;
177 struct sc_info *parent;
178
179 struct ich_desc *dtbl;
558a398b 180 bus_addr_t desc_addr;
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181};
182
183/* device private data */
184struct sc_info {
185 device_t dev;
186 int hasvra, hasvrm, hasmic;
4886ec58 187 unsigned int chnum, bufsz, blkcnt;
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188 int sample_size, swap_reg;
189
190 struct resource *nambar, *nabmbar, *irq;
858c6592 191 int regtype, nambarid, nabmbarid, irqid;
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192 bus_space_tag_t nambart, nabmbart;
193 bus_space_handle_t nambarh, nabmbarh;
4886ec58 194 bus_dma_tag_t dmat, chan_dmat;
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195 bus_dmamap_t dtmap;
196 void *ih;
197
198 struct ac97_info *codec;
199 struct sc_chinfo ch[3];
200 int ac97rate;
201 struct ich_desc *dtbl;
4886ec58 202 unsigned int dtbl_size;
558a398b 203 bus_addr_t desc_addr;
984263bc 204 struct intr_config_hook intrhook;
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205 uint16_t vendor;
206 uint16_t devid;
207 uint32_t flags;
cad195a6 208 sndlock_t ich_lock;
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209};
210
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211#define IGNORE_PCR 0x01
212
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213/* -------------------------------------------------------------------- */
214
4886ec58 215static uint32_t ich_fmt[] = {
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216 AFMT_STEREO | AFMT_S16_LE,
217 0
218};
219static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
220static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
221
222/* -------------------------------------------------------------------- */
223/* Hardware */
4886ec58 224static __inline uint32_t
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225ich_rd(struct sc_info *sc, int regno, int size)
226{
227 switch (size) {
228 case 1:
4886ec58 229 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno));
984263bc 230 case 2:
4886ec58 231 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno));
984263bc 232 case 4:
4886ec58 233 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno));
984263bc 234 default:
4886ec58 235 return (0xffffffff);
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236 }
237}
238
558a398b 239static __inline void
4886ec58 240ich_wr(struct sc_info *sc, int regno, uint32_t data, int size)
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241{
242 switch (size) {
243 case 1:
244 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
245 break;
246 case 2:
247 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
248 break;
249 case 4:
250 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
251 break;
252 }
253}
254
255/* ac97 codec */
256static int
257ich_waitcd(void *devinfo)
258{
984263bc 259 struct sc_info *sc = (struct sc_info *)devinfo;
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260 uint32_t data;
261 int i;
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262
263 for (i = 0; i < ICH_TIMEOUT; i++) {
264 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
265 if ((data & 0x01) == 0)
4886ec58 266 return (0);
558a398b 267 DELAY(1);
984263bc 268 }
4886ec58 269 if ((sc->flags & ICH_IGNORE_PCR) != 0)
558a398b 270 return (0);
984263bc 271 device_printf(sc->dev, "CODEC semaphore timeout\n");
4886ec58 272 return (ETIMEDOUT);
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273}
274
275static int
276ich_rdcd(kobj_t obj, void *devinfo, int regno)
277{
278 struct sc_info *sc = (struct sc_info *)devinfo;
279
280 regno &= 0xff;
281 ich_waitcd(sc);
282
4886ec58 283 return (bus_space_read_2(sc->nambart, sc->nambarh, regno));
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284}
285
286static int
4886ec58 287ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data)
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288{
289 struct sc_info *sc = (struct sc_info *)devinfo;
290
291 regno &= 0xff;
292 ich_waitcd(sc);
293 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
294
4886ec58 295 return (0);
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296}
297
298static kobj_method_t ich_ac97_methods[] = {
299 KOBJMETHOD(ac97_read, ich_rdcd),
300 KOBJMETHOD(ac97_write, ich_wrcd),
301 { 0, 0 }
302};
303AC97_DECLARE(ich_ac97);
304
305/* -------------------------------------------------------------------- */
306/* common routines */
307
308static void
309ich_filldtbl(struct sc_chinfo *ch)
310{
558a398b 311 struct sc_info *sc = ch->parent;
4886ec58 312 uint32_t base;
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313 int i;
314
558a398b 315 base = sndbuf_getbufaddr(ch->buffer);
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316 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer))
317 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
318 if ((sndbuf_getblksz(ch->buffer) != ch->blksz ||
319 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) &&
320 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0)
321 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
322 __func__, ch->blksz, ch->blkcnt);
558a398b 323 ch->blksz = sndbuf_getblksz(ch->buffer);
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324
325 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
326 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
327 ch->dtbl[i].length = ICH_BDC_IOC
328 | (ch->blksz / ch->parent->sample_size);
329 }
330}
331
332static int
333ich_resetchan(struct sc_info *sc, int num)
334{
335 int i, cr, regbase;
336
337 if (num == 0)
338 regbase = ICH_REG_PO_BASE;
339 else if (num == 1)
340 regbase = ICH_REG_PI_BASE;
341 else if (num == 2)
342 regbase = ICH_REG_MC_BASE;
343 else
4886ec58 344 return (ENXIO);
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345
346 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
558a398b
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347#if 1
348 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */
984263bc 349 DELAY(100);
558a398b
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350#else
351 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);
352#endif
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353 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
354 for (i = 0; i < ICH_TIMEOUT; i++) {
355 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
356 if (cr == 0)
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357 return (0);
358 DELAY(1);
984263bc
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359 }
360
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361 if (sc->flags & ICH_IGNORE_RESET)
362 return (0);
363#if 0
364 else if (sc->vendor == NVIDIA_VENDORID) {
365 sc->flags |= ICH_IGNORE_RESET;
366 device_printf(sc->dev, "ignoring reset failure!\n");
367 return (0);
368 }
369#endif
370
984263bc 371 device_printf(sc->dev, "cannot reset channel %d\n", num);
4886ec58 372 return (ENXIO);
984263bc
MD
373}
374
375/* -------------------------------------------------------------------- */
376/* channel interface */
377
378static void *
379ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
380{
381 struct sc_info *sc = devinfo;
382 struct sc_chinfo *ch;
383 unsigned int num;
384
558a398b 385 ICH_LOCK(sc);
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MD
386 num = sc->chnum++;
387 ch = &sc->ch[num];
388 ch->num = num;
389 ch->buffer = b;
390 ch->channel = c;
391 ch->parent = sc;
392 ch->run = 0;
393 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
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394 ch->desc_addr = sc->desc_addr +
395 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc));
396 ch->blkcnt = sc->blkcnt;
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397 ch->blksz = sc->bufsz / ch->blkcnt;
398
399 switch(ch->num) {
400 case 0: /* play */
401 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
402 ch->regbase = ICH_REG_PO_BASE;
4886ec58 403 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0;
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404 ch->imask = ICH_GLOB_STA_POINT;
405 break;
406
407 case 1: /* record */
408 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
409 ch->regbase = ICH_REG_PI_BASE;
4886ec58 410 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0;
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411 ch->imask = ICH_GLOB_STA_PIINT;
412 break;
413
414 case 2: /* mic */
415 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
416 ch->regbase = ICH_REG_MC_BASE;
4886ec58 417 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0;
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418 ch->imask = ICH_GLOB_STA_MINT;
419 break;
420
421 default:
4886ec58 422 return (NULL);
984263bc
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423 }
424
4886ec58
HT
425 if (sc->flags & ICH_FIXED_RATE)
426 ch->spdreg = 0;
427
558a398b 428 ICH_UNLOCK(sc);
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429 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, sc->bufsz) != 0)
430 return (NULL);
431
432 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer),
433 sndbuf_getmaxsize(ch->buffer), PAT_UNCACHEABLE);
984263bc 434
558a398b 435 ICH_LOCK(sc);
4886ec58 436 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
558a398b 437 ICH_UNLOCK(sc);
984263bc 438
4886ec58 439 return (ch);
984263bc
MD
440}
441
442static int
4886ec58 443ichchan_free(kobj_t obj, void *data)
984263bc 444{
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445 struct sc_chinfo *ch;
446 struct sc_info *sc;
447
448 ch = (struct sc_chinfo *)data;
449 sc = (ch != NULL) ? ch->parent : NULL;
450 if (ch != NULL && sc != NULL) {
451 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer),
452 sndbuf_getmaxsize(ch->buffer), PAT_WRITE_BACK);
453 }
454
455 return (1);
984263bc
MD
456}
457
458static int
4886ec58
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459ichchan_setformat(kobj_t obj, void *data, uint32_t format)
460{
461
462 ICH_DEBUG(
463 struct sc_chinfo *ch = data;
464 struct sc_info *sc = ch->parent;
465 if (!(sc->flags & ICH_CALIBRATE_DONE))
466 device_printf(sc->dev,
467 "WARNING: %s() called before calibration!\n",
468 __func__);
469 );
470
471 return (0);
472}
473
474static int
475ichchan_setspeed(kobj_t obj, void *data, uint32_t speed)
984263bc
MD
476{
477 struct sc_chinfo *ch = data;
478 struct sc_info *sc = ch->parent;
479
4886ec58
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480 ICH_DEBUG(
481 if (!(sc->flags & ICH_CALIBRATE_DONE))
482 device_printf(sc->dev,
483 "WARNING: %s() called before calibration!\n",
484 __func__);
485 );
486
984263bc 487 if (ch->spdreg) {
558a398b
SS
488 int r, ac97rate;
489
490 ICH_LOCK(sc);
984263bc
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491 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
492 sc->ac97rate = 48000;
558a398b
SS
493 ac97rate = sc->ac97rate;
494 ICH_UNLOCK(sc);
495 r = (speed * 48000) / ac97rate;
984263bc 496 /*
4886ec58 497 * Cast the return value of ac97_setrate() to uint64 so that
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498 * the math don't overflow into the negative range.
499 */
4886ec58 500 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) *
558a398b 501 ac97rate) / 48000;
984263bc
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502 } else {
503 ch->spd = 48000;
504 }
4886ec58 505 return (ch->spd);
984263bc
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506}
507
508static int
4886ec58 509ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
984263bc
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510{
511 struct sc_chinfo *ch = data;
512 struct sc_info *sc = ch->parent;
513
4886ec58
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514 ICH_DEBUG(
515 if (!(sc->flags & ICH_CALIBRATE_DONE))
516 device_printf(sc->dev,
517 "WARNING: %s() called before calibration!\n",
518 __func__);
519 );
520
521 if (sc->flags & ICH_HIGH_LATENCY)
522 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
523
524 if (blocksize < ICH_MIN_BLKSZ)
525 blocksize = ICH_MIN_BLKSZ;
526 blocksize &= ~(ICH_MIN_BLKSZ - 1);
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527 ch->blksz = blocksize;
528 ich_filldtbl(ch);
558a398b 529 ICH_LOCK(sc);
984263bc 530 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
558a398b 531 ICH_UNLOCK(sc);
984263bc 532
4886ec58 533 return (ch->blksz);
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534}
535
536static int
537ichchan_trigger(kobj_t obj, void *data, int go)
538{
539 struct sc_chinfo *ch = data;
540 struct sc_info *sc = ch->parent;
541
4886ec58
HT
542 ICH_DEBUG(
543 if (!(sc->flags & ICH_CALIBRATE_DONE))
544 device_printf(sc->dev,
545 "WARNING: %s() called before calibration!\n",
546 __func__);
547 );
548
984263bc
MD
549 switch (go) {
550 case PCMTRIG_START:
551 ch->run = 1;
558a398b 552 ICH_LOCK(sc);
4886ec58 553 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
984263bc 554 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
558a398b 555 ICH_UNLOCK(sc);
984263bc 556 break;
61182420 557 case PCMTRIG_STOP:
984263bc 558 case PCMTRIG_ABORT:
558a398b 559 ICH_LOCK(sc);
984263bc 560 ich_resetchan(sc, ch->num);
558a398b 561 ICH_UNLOCK(sc);
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562 ch->run = 0;
563 break;
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564 default:
565 break;
984263bc 566 }
4886ec58 567 return (0);
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568}
569
570static int
571ichchan_getptr(kobj_t obj, void *data)
572{
573 struct sc_chinfo *ch = data;
574 struct sc_info *sc = ch->parent;
4886ec58
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575 uint32_t pos;
576
577 ICH_DEBUG(
578 if (!(sc->flags & ICH_CALIBRATE_DONE))
579 device_printf(sc->dev,
580 "WARNING: %s() called before calibration!\n",
581 __func__);
582 );
984263bc 583
558a398b 584 ICH_LOCK(sc);
984263bc 585 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
558a398b 586 ICH_UNLOCK(sc);
984263bc
MD
587
588 pos = ch->civ * ch->blksz;
589
4886ec58 590 return (pos);
984263bc
MD
591}
592
593static struct pcmchan_caps *
594ichchan_getcaps(kobj_t obj, void *data)
595{
596 struct sc_chinfo *ch = data;
597
4886ec58
HT
598 ICH_DEBUG(
599 struct sc_info *sc = ch->parent;
600
601 if (!(sc->flags & ICH_CALIBRATE_DONE))
602 device_printf(ch->parent->dev,
603 "WARNING: %s() called before calibration!\n",
604 __func__);
605 );
606
607 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps);
984263bc
MD
608}
609
610static kobj_method_t ichchan_methods[] = {
611 KOBJMETHOD(channel_init, ichchan_init),
4886ec58 612 KOBJMETHOD(channel_free, ichchan_free),
984263bc
MD
613 KOBJMETHOD(channel_setformat, ichchan_setformat),
614 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
615 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
616 KOBJMETHOD(channel_trigger, ichchan_trigger),
617 KOBJMETHOD(channel_getptr, ichchan_getptr),
618 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
619 { 0, 0 }
620};
621CHANNEL_DECLARE(ichchan);
622
623/* -------------------------------------------------------------------- */
624/* The interrupt handler */
625
626static void
627ich_intr(void *p)
628{
629 struct sc_info *sc = (struct sc_info *)p;
630 struct sc_chinfo *ch;
4886ec58 631 uint32_t cbi, lbi, lvi, st, gs;
984263bc
MD
632 int i;
633
558a398b 634 ICH_LOCK(sc);
4886ec58
HT
635
636 ICH_DEBUG(
637 if (!(sc->flags & ICH_CALIBRATE_DONE))
638 device_printf(sc->dev,
639 "WARNING: %s() called before calibration!\n",
640 __func__);
641 );
642
984263bc
MD
643 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
644 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
645 /* Clear resume interrupt(s) - nothing doing with them */
646 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
647 }
648 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
649
650 for (i = 0; i < 3; i++) {
651 ch = &sc->ch[i];
858c6592 652 if ((ch->imask & gs) == 0)
984263bc
MD
653 continue;
654 gs &= ~ch->imask;
858c6592 655 st = ich_rd(sc, ch->regbase +
4886ec58 656 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
984263bc
MD
657 2);
658 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
659 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
660 /* block complete - update buffer */
558a398b
SS
661 if (ch->run) {
662 ICH_UNLOCK(sc);
984263bc 663 chn_intr(ch->channel);
558a398b
SS
664 ICH_LOCK(sc);
665 }
984263bc
MD
666 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
667 cbi = ch->civ % ch->blkcnt;
668 if (cbi == 0)
669 cbi = ch->blkcnt - 1;
670 else
671 cbi--;
672 lbi = lvi % ch->blkcnt;
673 if (cbi >= lbi)
674 lvi += cbi - lbi;
675 else
676 lvi += cbi + ch->blkcnt - lbi;
677 lvi %= ICH_DTBL_LENGTH;
678 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
679
680 }
681 /* clear status bit */
858c6592 682 ich_wr(sc, ch->regbase +
4886ec58 683 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
984263bc
MD
684 st, 2);
685 }
558a398b 686 ICH_UNLOCK(sc);
984263bc 687 if (gs != 0) {
858c6592 688 device_printf(sc->dev,
984263bc
MD
689 "Unhandled interrupt, gs_intr = %x\n", gs);
690 }
691}
692
693/* ------------------------------------------------------------------------- */
0833cfa2 694/* Sysctl to control ac97 speed (some boards appear to end up using
858c6592
DR
695 * XTAL_IN rather than BIT_CLK for link timing).
696 */
697
984263bc
MD
698static int
699ich_initsys(struct sc_info* sc)
700{
701#ifdef SND_DYNSYSCTL
858c6592 702 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
984263bc 703 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
858c6592
DR
704 OID_AUTO, "ac97rate", CTLFLAG_RW,
705 &sc->ac97rate, 48000,
984263bc
MD
706 "AC97 link rate (default = 48000)");
707#endif /* SND_DYNSYSCTL */
4886ec58
HT
708 return (0);
709}
710
711static void
712ich_setstatus(struct sc_info *sc)
713{
714 char status[SND_STATUSLEN];
715
716 ksnprintf(status, SND_STATUSLEN,
717 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s",
718 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar),
719 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich));
720
721 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE))
722 device_printf(sc->dev,
723 "PCI Master abort workaround enabled\n");
724
725 pcm_setstatus(sc->dev, status);
984263bc
MD
726}
727
728/* -------------------------------------------------------------------- */
858c6592
DR
729/* Calibrate card to determine the clock source. The source maybe a
730 * function of the ac97 codec initialization code (to be investigated).
731 */
984263bc 732
4886ec58
HT
733static void
734ich_calibrate(void *arg)
984263bc
MD
735{
736 struct sc_info *sc;
737 struct sc_chinfo *ch;
738 struct timeval t1, t2;
4886ec58
HT
739 uint8_t ociv, nciv;
740 uint32_t wait_us, actual_48k_rate, oblkcnt;
984263bc
MD
741
742 sc = (struct sc_info *)arg;
4886ec58 743 ICH_LOCK(sc);
984263bc
MD
744 ch = &sc->ch[1];
745
4886ec58 746 if (sc->intrhook.ich_func != NULL) {
984263bc 747 config_intrhook_disestablish(&sc->intrhook);
4886ec58
HT
748 sc->intrhook.ich_func = NULL;
749 }
984263bc
MD
750
751 /*
752 * Grab audio from input for fixed interval and compare how
753 * much we actually get with what we expect. Interval needs
754 * to be sufficiently short that no interrupts are
755 * generated.
756 */
757
758 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
759
4886ec58
HT
760 oblkcnt = ch->blkcnt;
761 ch->blkcnt = 2;
762 sc->flags |= ICH_CALIBRATE_DONE;
763 ICH_UNLOCK(sc);
764 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1);
765 ICH_LOCK(sc);
766 sc->flags &= ~ICH_CALIBRATE_DONE;
984263bc
MD
767
768 /*
769 * our data format is stereo, 16 bit so each sample is 4 bytes.
770 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
771 * we're going to start recording with interrupts disabled and measure
772 * the time taken for one block to complete. we know the block size,
773 * we know the time in microseconds, we calculate the sample rate:
774 *
775 * actual_rate [bps] = bytes / (time [s] * 4)
776 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
777 * actual_rate [Hz] = (bytes * 250000) / time [us]
778 */
779
780 /* prepare */
781 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
782 nciv = ociv;
4886ec58 783 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
984263bc
MD
784
785 /* start */
786 microtime(&t1);
787 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
788
789 /* wait */
4886ec58 790 do {
984263bc
MD
791 microtime(&t2);
792 if (t2.tv_sec - t1.tv_sec > 1)
793 break;
794 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
4886ec58 795 } while (nciv == ociv);
984263bc
MD
796
797 /* stop */
798 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
799
800 /* reset */
801 DELAY(100);
802 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
4886ec58 803 ch->blkcnt = oblkcnt;
984263bc
MD
804
805 /* turn time delta into us */
806 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
807
808 if (nciv == ociv) {
809 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
4886ec58
HT
810 sc->flags |= ICH_CALIBRATE_DONE;
811 ICH_UNLOCK(sc);
812 ich_setstatus(sc);
984263bc
MD
813 return;
814 }
815
61182420
HT
816 /* Just in case the timecounter screwed. It is possible, really. */
817 if (wait_us > 0)
818 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us;
819 else
820 actual_48k_rate = 48000;
984263bc
MD
821
822 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
823 sc->ac97rate = actual_48k_rate;
824 } else {
825 sc->ac97rate = 48000;
826 }
827
828 if (bootverbose || sc->ac97rate != 48000) {
829 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
830 if (sc->ac97rate != actual_48k_rate)
e3869ec7 831 kprintf(", will use %d Hz", sc->ac97rate);
8f706258 832 kprintf("\n");
984263bc 833 }
4886ec58
HT
834 sc->flags |= ICH_CALIBRATE_DONE;
835 ICH_UNLOCK(sc);
836
837 ich_setstatus(sc);
0833cfa2 838
984263bc
MD
839 return;
840}
841
842/* -------------------------------------------------------------------- */
843/* Probe and attach the card */
844
845static void
846ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
847{
558a398b
SS
848 struct sc_info *sc = (struct sc_info *)arg;
849 sc->desc_addr = segs->ds_addr;
984263bc
MD
850 return;
851}
852
853static int
854ich_init(struct sc_info *sc)
855{
4886ec58 856 uint32_t stat;
984263bc
MD
857
858 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
859 DELAY(600000);
860 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
861
862 if ((stat & ICH_GLOB_STA_PCR) == 0) {
858c6592 863 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
558a398b
SS
864 if (sc->vendor == INTEL_VENDORID && (
865 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
866 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
867 sc->devid == INTEL_82801GB)) {
4886ec58 868 sc->flags |= ICH_IGNORE_PCR;
558a398b 869 device_printf(sc->dev, "primary codec not ready!\n");
984263bc
MD
870 }
871 }
872
558a398b 873#if 0
984263bc 874 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
558a398b
SS
875#else
876 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
877#endif
984263bc
MD
878
879 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
4886ec58 880 return (ENXIO);
984263bc 881 if (sc->hasmic && ich_resetchan(sc, 2))
4886ec58 882 return (ENXIO);
984263bc 883
4886ec58 884 return (0);
984263bc
MD
885}
886
887static int
888ich_pci_probe(device_t dev)
889{
558a398b
SS
890 int i;
891 uint16_t devid, vendor;
892
893 vendor = pci_get_vendor(dev);
894 devid = pci_get_device(dev);
c157ff7a 895 for (i = 0; i < NELEM(ich_devs); i++) {
558a398b
SS
896 if (vendor == ich_devs[i].vendor &&
897 devid == ich_devs[i].devid) {
898 device_set_desc(dev, ich_devs[i].name);
899 /* allow a better driver to override us */
900 if ((ich_devs[i].options & PROBE_LOW) != 0)
901 return (BUS_PROBE_LOW_PRIORITY);
902 return (BUS_PROBE_DEFAULT);
903 }
984263bc 904 }
558a398b 905 return (ENXIO);
984263bc
MD
906}
907
908static int
909ich_pci_attach(device_t dev)
910{
558a398b 911 uint32_t subdev;
4886ec58 912 uint16_t extcaps;
558a398b 913 uint16_t devid, vendor;
984263bc 914 struct sc_info *sc;
4886ec58 915 int i;
984263bc 916
61182420 917 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
4886ec58 918 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc");
984263bc
MD
919 sc->dev = dev;
920
558a398b
SS
921 vendor = sc->vendor = pci_get_vendor(dev);
922 devid = sc->devid = pci_get_device(dev);
923 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
984263bc
MD
924 /*
925 * The SiS 7012 register set isn't quite like the standard ich.
926 * There really should be a general "quirks" mechanism.
927 */
558a398b 928 if (vendor == SIS_VENDORID && devid == SIS_7012) {
984263bc
MD
929 sc->swap_reg = 1;
930 sc->sample_size = 1;
931 } else {
932 sc->swap_reg = 0;
933 sc->sample_size = 2;
934 }
935
936 /*
4886ec58
HT
937 * Intel 440MX Errata #36
938 * - AC97 Soft Audio and Soft Modem Master Abort Errata
939 *
940 * http://www.intel.com/design/chipsets/specupdt/245051.htm
941 */
942 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX)
943 sc->flags |= ICH_DMA_NOCACHE;
944
945 /*
558a398b
SS
946 * Enable bus master. On ich4/5 this may prevent the detection of
947 * the primary codec becoming ready in ich_init().
948 */
949 pci_enable_busmaster(dev);
950
951 /*
0833cfa2
JS
952 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
953 * read-only. Need to enable "legacy support", by poking into
954 * pci config space. The driver should use MMBAR and MBBAR,
955 * but doing so will mess things up here. ich4 has enough new
956 * features it warrants it's own driver.
957 */
558a398b
SS
958 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB ||
959 devid == INTEL_82801EB || devid == INTEL_6300ESB ||
960 devid == INTEL_82801FB || devid == INTEL_82801GB)) {
858c6592
DR
961 sc->nambarid = PCIR_MMBAR;
962 sc->nabmbarid = PCIR_MBBAR;
963 sc->regtype = SYS_RES_MEMORY;
558a398b 964 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
858c6592
DR
965 } else {
966 sc->nambarid = PCIR_NAMBAR;
967 sc->nabmbarid = PCIR_NABMBAR;
968 sc->regtype = SYS_RES_IOPORT;
858c6592
DR
969 }
970
558a398b
SS
971 sc->nambar = bus_alloc_resource_any(dev, sc->regtype,
972 &sc->nambarid, RF_ACTIVE);
973 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype,
974 &sc->nabmbarid, RF_ACTIVE);
984263bc
MD
975
976 if (!sc->nambar || !sc->nabmbar) {
977 device_printf(dev, "unable to map IO port space\n");
978 goto bad;
979 }
980
981 sc->nambart = rman_get_bustag(sc->nambar);
982 sc->nambarh = rman_get_bushandle(sc->nambar);
983 sc->nabmbart = rman_get_bustag(sc->nabmbar);
984 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
985
4886ec58
HT
986 sc->bufsz = pcm_getbuffersize(dev,
987 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
988
989 if (resource_int_value(device_get_name(dev),
990 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
991 sc->blkcnt = sc->bufsz / i;
992 i = 0;
993 while (sc->blkcnt >> i)
994 i++;
995 sc->blkcnt = 1 << (i - 1);
996 if (sc->blkcnt < ICH_MIN_BLKCNT)
997 sc->blkcnt = ICH_MIN_BLKCNT;
998 else if (sc->blkcnt > ICH_MAX_BLKCNT)
999 sc->blkcnt = ICH_MAX_BLKCNT;
1000 } else
1001 sc->blkcnt = ICH_DEFAULT_BLKCNT;
1002
1003 if (resource_int_value(device_get_name(dev),
1004 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) {
1005 sc->flags |= ICH_HIGH_LATENCY;
1006 sc->blkcnt = ICH_MIN_BLKCNT;
984263bc
MD
1007 }
1008
4886ec58
HT
1009 if (resource_int_value(device_get_name(dev),
1010 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0)
1011 sc->flags |= ICH_FIXED_RATE;
1012
984263bc 1013 sc->irqid = 0;
558a398b 1014 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
4886ec58
HT
1015 RF_ACTIVE | RF_SHAREABLE);
1016 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr,
1017 sc, &sc->ih)) {
984263bc
MD
1018 device_printf(dev, "unable to map interrupt\n");
1019 goto bad;
1020 }
1021
1022 if (ich_init(sc)) {
1023 device_printf(dev, "unable to initialize the card\n");
1024 goto bad;
1025 }
1026
1027 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
1028 if (sc->codec == NULL)
1029 goto bad;
558a398b
SS
1030
1031 /*
1032 * Turn on inverted external amplifier sense flags for few
1033 * 'special' boards.
1034 */
1035 switch (subdev) {
1036 case 0x202f161f: /* Gateway 7326GZ */
1037 case 0x203a161f: /* Gateway 4028GZ */
1038 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */
1039 case 0x8144104d: /* Sony VAIO PCG-TR* */
1040 case 0x8197104d: /* Sony S1XP */
1041 case 0x81c0104d: /* Sony VAIO type T */
1042 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */
1043 case 0x3089103c: /* Compaq Presario B3800 */
e2339ccc
SW
1044 case 0x309a103c: /* HP Compaq nx4300 */
1045 case 0x82131033: /* NEC VersaPro VJ10F/BH */
1046 case 0x82be1033: /* NEC VersaPro VJ12F/CH */
558a398b
SS
1047 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV);
1048 break;
1049 default:
1050 break;
1051 }
1052
984263bc
MD
1053 mixer_init(dev, ac97_getmixerclass(), sc->codec);
1054
1055 /* check and set VRA function */
1056 extcaps = ac97_getextcaps(sc->codec);
1057 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
1058 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
1059 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
1060 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1061
4886ec58
HT
1062 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH *
1063 ((sc->hasmic) ? 3 : 2);
1064
1065 /* BDL tag */
1066 if (bus_dma_tag_create(NULL, 8, 0,
1067 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1068 sc->dtbl_size, 1, 0x3ffff, 0, &sc->dmat) != 0) {
1069 device_printf(dev, "unable to create dma tag\n");
1070 goto bad;
1071 }
1072
1073 /* PCM channel tag */
1074 if (bus_dma_tag_create(NULL, ICH_MIN_BLKSZ, 0,
1075 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1076 sc->bufsz, 1, 0x3ffff, 0, &sc->chan_dmat) != 0) {
1077 device_printf(dev, "unable to create dma tag\n");
1078 goto bad;
1079 }
1080#if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1081 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT |
1082 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1083 &sc->dtmap))
1084#else
1085 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT,
1086 &sc->dtmap))
1087#endif
1088 goto bad;
1089
1090 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size,
1091 ich_setmap, sc, 0))
1092 goto bad;
1093
1094 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1))
984263bc
MD
1095 goto bad;
1096
1097 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
1098 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
1099 if (sc->hasmic)
1100 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
1101
4886ec58
HT
1102 if (sc->flags & ICH_FIXED_RATE) {
1103 sc->flags |= ICH_CALIBRATE_DONE;
1104 ich_setstatus(sc);
1105 } else {
1106 ich_initsys(sc);
1107
1108 sc->intrhook.ich_func = ich_calibrate;
1109 sc->intrhook.ich_arg = sc;
52800c9d 1110 sc->intrhook.ich_desc = "snd_ich";
4886ec58
HT
1111 if (cold == 0 ||
1112 config_intrhook_establish(&sc->intrhook) != 0) {
1113 sc->intrhook.ich_func = NULL;
1114 ich_calibrate(sc);
1115 }
984263bc
MD
1116 }
1117
4886ec58 1118 return (0);
984263bc
MD
1119
1120bad:
1121 if (sc->codec)
1122 ac97_destroy(sc->codec);
1123 if (sc->ih)
1124 bus_teardown_intr(dev, sc->irq, sc->ih);
1125 if (sc->irq)
1126 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1127 if (sc->nambar)
858c6592 1128 bus_release_resource(dev, sc->regtype,
984263bc
MD
1129 sc->nambarid, sc->nambar);
1130 if (sc->nabmbar)
858c6592 1131 bus_release_resource(dev, sc->regtype,
984263bc 1132 sc->nabmbarid, sc->nabmbar);
558a398b
SS
1133 if (sc->dtmap)
1134 bus_dmamap_unload(sc->dmat, sc->dtmap);
4886ec58
HT
1135 if (sc->dtbl)
1136 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1137 if (sc->chan_dmat)
1138 bus_dma_tag_destroy(sc->chan_dmat);
558a398b
SS
1139 if (sc->dmat)
1140 bus_dma_tag_destroy(sc->dmat);
1141 if (sc->ich_lock)
1142 snd_mtxfree(sc->ich_lock);
efda3bd0 1143 kfree(sc, M_DEVBUF);
4886ec58 1144 return (ENXIO);
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1145}
1146
1147static int
1148ich_pci_detach(device_t dev)
1149{
1150 struct sc_info *sc;
1151 int r;
1152
1153 r = pcm_unregister(dev);
1154 if (r)
4886ec58 1155 return (r);
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MD
1156 sc = pcm_getdevinfo(dev);
1157
1158 bus_teardown_intr(dev, sc->irq, sc->ih);
1159 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
858c6592
DR
1160 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
1161 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
558a398b 1162 bus_dmamap_unload(sc->dmat, sc->dtmap);
4886ec58
HT
1163 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1164 bus_dma_tag_destroy(sc->chan_dmat);
984263bc 1165 bus_dma_tag_destroy(sc->dmat);
558a398b 1166 snd_mtxfree(sc->ich_lock);
efda3bd0 1167 kfree(sc, M_DEVBUF);
4886ec58 1168 return (0);
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MD
1169}
1170
558a398b
SS
1171static void
1172ich_pci_codec_reset(struct sc_info *sc)
1173{
1174 int i;
1175 uint32_t control;
1176
1177 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
1178 control &= ~(ICH_GLOB_CTL_SHUT);
1179 control |= (control & ICH_GLOB_CTL_COLD) ?
1180 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
1181 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
1182
1183 for (i = 500000; i; i--) {
1184 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
1185 break; /* or ICH_SCR? */
1186 DELAY(1);
1187 }
1188
1189 if (i <= 0)
1190 kprintf("%s: time out\n", __func__);
1191}
1192
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MD
1193static int
1194ich_pci_suspend(device_t dev)
1195{
1196 struct sc_info *sc;
1197 int i;
1198
858c6592 1199 sc = pcm_getdevinfo(dev);
558a398b 1200 ICH_LOCK(sc);
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MD
1201 for (i = 0 ; i < 3; i++) {
1202 sc->ch[i].run_save = sc->ch[i].run;
1203 if (sc->ch[i].run) {
558a398b 1204 ICH_UNLOCK(sc);
984263bc 1205 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
558a398b 1206 ICH_LOCK(sc);
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MD
1207 }
1208 }
558a398b 1209 ICH_UNLOCK(sc);
4886ec58 1210 return (0);
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MD
1211}
1212
1213static int
1214ich_pci_resume(device_t dev)
1215{
1216 struct sc_info *sc;
1217 int i;
1218
1219 sc = pcm_getdevinfo(dev);
1220
558a398b
SS
1221 if (sc->regtype == SYS_RES_IOPORT)
1222 pci_enable_io(dev, SYS_RES_IOPORT);
1223 else
1224 pci_enable_io(dev, SYS_RES_MEMORY);
1225 pci_enable_busmaster(dev);
1226
1227 ICH_LOCK(sc);
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MD
1228 /* Reinit audio device */
1229 if (ich_init(sc) == -1) {
1230 device_printf(dev, "unable to reinitialize the card\n");
558a398b 1231 ICH_UNLOCK(sc);
4886ec58 1232 return (ENXIO);
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MD
1233 }
1234 /* Reinit mixer */
558a398b
SS
1235 ich_pci_codec_reset(sc);
1236 ICH_UNLOCK(sc);
1237 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
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MD
1238 if (mixer_reinit(dev) == -1) {
1239 device_printf(dev, "unable to reinitialize the mixer\n");
4886ec58 1240 return (ENXIO);
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MD
1241 }
1242 /* Re-start DMA engines */
1243 for (i = 0 ; i < 3; i++) {
1244 struct sc_chinfo *ch = &sc->ch[i];
1245 if (sc->ch[i].run_save) {
1246 ichchan_setblocksize(0, ch, ch->blksz);
1247 ichchan_setspeed(0, ch, ch->spd);
1248 ichchan_trigger(0, ch, PCMTRIG_START);
1249 }
1250 }
4886ec58 1251 return (0);
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MD
1252}
1253
1254static device_method_t ich_methods[] = {
1255 /* Device interface */
1256 DEVMETHOD(device_probe, ich_pci_probe),
1257 DEVMETHOD(device_attach, ich_pci_attach),
1258 DEVMETHOD(device_detach, ich_pci_detach),
1259 DEVMETHOD(device_suspend, ich_pci_suspend),
1260 DEVMETHOD(device_resume, ich_pci_resume),
1261 { 0, 0 }
1262};
1263
1264static driver_t ich_driver = {
1265 "pcm",
1266 ich_methods,
1267 PCM_SOFTC_SIZE,
1268};
1269
aa2b9d05 1270DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, NULL, NULL);
558a398b 1271MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc 1272MODULE_VERSION(snd_ich, 1);