Hardwire i386 instead of using the borken machine variable
[dragonfly.git] / sys / dev / netif / rl / if_rl.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
3d0f5f54 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.3 2003/07/26 21:56:10 rob Exp $
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34 *
35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
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36 */
37
38/*
39 * RealTek 8129/8139 PCI NIC driver
40 *
41 * Supports several extremely cheap PCI 10/100 adapters based on
42 * the RealTek chipset. Datasheets can be obtained from
43 * www.realtek.com.tw.
44 *
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
48 */
49
50/*
51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
52 * probably the worst PCI ethernet controller ever made, with the possible
53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
54 * DMA, but it has a terrible interface that nullifies any performance
55 * gains that bus-master DMA usually offers.
56 *
57 * For transmission, the chip offers a series of four TX descriptor
58 * registers. Each transmit frame must be in a contiguous buffer, aligned
59 * on a longword (32-bit) boundary. This means we almost always have to
60 * do mbuf copies in order to transmit a frame, except in the unlikely
61 * case where a) the packet fits into a single mbuf, and b) the packet
62 * is 32-bit aligned within the mbuf's data area. The presence of only
63 * four descriptor registers means that we can never have more than four
64 * packets queued for transmission at any one time.
65 *
66 * Reception is not much better. The driver has to allocate a single large
67 * buffer area (up to 64K in size) into which the chip will DMA received
68 * frames. Because we don't know where within this region received packets
69 * will begin or end, we have no choice but to copy data from the buffer
70 * area into mbufs in order to pass the packets up to the higher protocol
71 * levels.
72 *
73 * It's impossible given this rotten design to really achieve decent
74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
75 * some equally overmuscled CPU to drive it.
76 *
77 * On the bright side, the 8139 does have a built-in PHY, although
78 * rather than using an MDIO serial interface like most other NICs, the
79 * PHY registers are directly accessible through the 8139's register
80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
81 * filter.
82 *
83 * The 8129 chip is an older version of the 8139 that uses an external PHY
84 * chip. The 8129 has a serial MDIO interface for accessing the MII where
85 * the 8139 lets you directly access the on-board PHY registers. We need
86 * to select which interface to use depending on the chip type.
87 */
88
89#include <sys/param.h>
90#include <sys/systm.h>
91#include <sys/sockio.h>
92#include <sys/mbuf.h>
93#include <sys/malloc.h>
94#include <sys/kernel.h>
95#include <sys/socket.h>
96
97#include <net/if.h>
98#include <net/if_arp.h>
99#include <net/ethernet.h>
100#include <net/if_dl.h>
101#include <net/if_media.h>
102
103#include <net/bpf.h>
104
105#include <vm/vm.h> /* for vtophys */
106#include <vm/pmap.h> /* for vtophys */
107#include <machine/clock.h> /* for DELAY */
108#include <machine/bus_pio.h>
109#include <machine/bus_memio.h>
110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
115#include <dev/mii/mii.h>
116#include <dev/mii/miivar.h>
117
118#include <pci/pcireg.h>
119#include <pci/pcivar.h>
120
121/* "controller miibus0" required. See GENERIC if you get errors here. */
122#include "miibus_if.h"
123
124/*
125 * Default to using PIO access for this driver. On SMP systems,
126 * there appear to be problems with memory mapped mode: it looks like
127 * doing too many memory mapped access back to back in rapid succession
128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
131 */
132#define RL_USEIOSPACE
133
134#include <pci/if_rlreg.h>
135
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136/*
137 * Various supported device vendors/types and their names.
138 */
139static struct rl_type rl_devs[] = {
140 { RT_VENDORID, RT_DEVICEID_8129,
141 "RealTek 8129 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8139,
143 "RealTek 8139 10/100BaseTX" },
144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
145 "Accton MPX 5030/5038 10/100BaseTX" },
146 { DELTA_VENDORID, DELTA_DEVICEID_8139,
147 "Delta Electronics 8139 10/100BaseTX" },
148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
149 "Addtron Technolgy 8139 10/100BaseTX" },
150 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
151 "D-Link DFE-530TX+ 10/100BaseTX" },
152 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
153 "Nortel Networks 10/100BaseTX" },
154 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
155 "Peppercon AG ROL/F" },
156 { 0, 0, NULL }
157};
158
159static int rl_probe __P((device_t));
160static int rl_attach __P((device_t));
161static int rl_detach __P((device_t));
162
163static int rl_encap __P((struct rl_softc *, struct mbuf * ));
164
165static void rl_rxeof __P((struct rl_softc *));
166static void rl_txeof __P((struct rl_softc *));
167static void rl_intr __P((void *));
168static void rl_tick __P((void *));
169static void rl_start __P((struct ifnet *));
170static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
171static void rl_init __P((void *));
172static void rl_stop __P((struct rl_softc *));
173static void rl_watchdog __P((struct ifnet *));
174static int rl_suspend __P((device_t));
175static int rl_resume __P((device_t));
176static void rl_shutdown __P((device_t));
177static int rl_ifmedia_upd __P((struct ifnet *));
178static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
179
180static void rl_eeprom_putbyte __P((struct rl_softc *, int));
181static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
182static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
183 int, int, int));
184static void rl_mii_sync __P((struct rl_softc *));
185static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
186static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
187static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
188
189static int rl_miibus_readreg __P((device_t, int, int));
190static int rl_miibus_writereg __P((device_t, int, int, int));
191static void rl_miibus_statchg __P((device_t));
192
193static u_int8_t rl_calchash __P((caddr_t));
194static void rl_setmulti __P((struct rl_softc *));
195static void rl_reset __P((struct rl_softc *));
196static int rl_list_tx_init __P((struct rl_softc *));
197
198#ifdef RL_USEIOSPACE
199#define RL_RES SYS_RES_IOPORT
200#define RL_RID RL_PCI_LOIO
201#else
202#define RL_RES SYS_RES_MEMORY
203#define RL_RID RL_PCI_LOMEM
204#endif
205
206static device_method_t rl_methods[] = {
207 /* Device interface */
208 DEVMETHOD(device_probe, rl_probe),
209 DEVMETHOD(device_attach, rl_attach),
210 DEVMETHOD(device_detach, rl_detach),
211 DEVMETHOD(device_suspend, rl_suspend),
212 DEVMETHOD(device_resume, rl_resume),
213 DEVMETHOD(device_shutdown, rl_shutdown),
214
215 /* bus interface */
216 DEVMETHOD(bus_print_child, bus_generic_print_child),
217 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
218
219 /* MII interface */
220 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
221 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
222 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
223
224 { 0, 0 }
225};
226
227static driver_t rl_driver = {
228 "rl",
229 rl_methods,
230 sizeof(struct rl_softc)
231};
232
233static devclass_t rl_devclass;
234
235DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
236DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
237
238#define EE_SET(x) \
239 CSR_WRITE_1(sc, RL_EECMD, \
240 CSR_READ_1(sc, RL_EECMD) | x)
241
242#define EE_CLR(x) \
243 CSR_WRITE_1(sc, RL_EECMD, \
244 CSR_READ_1(sc, RL_EECMD) & ~x)
245
246/*
247 * Send a read command and address to the EEPROM, check for ACK.
248 */
249static void rl_eeprom_putbyte(sc, addr)
250 struct rl_softc *sc;
251 int addr;
252{
3d0f5f54 253 int d, i;
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254
255 d = addr | RL_EECMD_READ;
256
257 /*
258 * Feed in each bit and strobe the clock.
259 */
260 for (i = 0x400; i; i >>= 1) {
261 if (d & i) {
262 EE_SET(RL_EE_DATAIN);
263 } else {
264 EE_CLR(RL_EE_DATAIN);
265 }
266 DELAY(100);
267 EE_SET(RL_EE_CLK);
268 DELAY(150);
269 EE_CLR(RL_EE_CLK);
270 DELAY(100);
271 }
272
273 return;
274}
275
276/*
277 * Read a word of data stored in the EEPROM at address 'addr.'
278 */
279static void rl_eeprom_getword(sc, addr, dest)
280 struct rl_softc *sc;
281 int addr;
282 u_int16_t *dest;
283{
3d0f5f54 284 int i;
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285 u_int16_t word = 0;
286
287 /* Enter EEPROM access mode. */
288 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
289
290 /*
291 * Send address of word we want to read.
292 */
293 rl_eeprom_putbyte(sc, addr);
294
295 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
296
297 /*
298 * Start reading bits from EEPROM.
299 */
300 for (i = 0x8000; i; i >>= 1) {
301 EE_SET(RL_EE_CLK);
302 DELAY(100);
303 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
304 word |= i;
305 EE_CLR(RL_EE_CLK);
306 DELAY(100);
307 }
308
309 /* Turn off EEPROM access mode. */
310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
311
312 *dest = word;
313
314 return;
315}
316
317/*
318 * Read a sequence of words from the EEPROM.
319 */
320static void rl_read_eeprom(sc, dest, off, cnt, swap)
321 struct rl_softc *sc;
322 caddr_t dest;
323 int off;
324 int cnt;
325 int swap;
326{
327 int i;
328 u_int16_t word = 0, *ptr;
329
330 for (i = 0; i < cnt; i++) {
331 rl_eeprom_getword(sc, off + i, &word);
332 ptr = (u_int16_t *)(dest + (i * 2));
333 if (swap)
334 *ptr = ntohs(word);
335 else
336 *ptr = word;
337 }
338
339 return;
340}
341
342
343/*
344 * MII access routines are provided for the 8129, which
345 * doesn't have a built-in PHY. For the 8139, we fake things
346 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
347 * direct access PHY registers.
348 */
349#define MII_SET(x) \
350 CSR_WRITE_1(sc, RL_MII, \
351 CSR_READ_1(sc, RL_MII) | x)
352
353#define MII_CLR(x) \
354 CSR_WRITE_1(sc, RL_MII, \
355 CSR_READ_1(sc, RL_MII) & ~x)
356
357/*
358 * Sync the PHYs by setting data bit and strobing the clock 32 times.
359 */
360static void rl_mii_sync(sc)
361 struct rl_softc *sc;
362{
3d0f5f54 363 int i;
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364
365 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
366
367 for (i = 0; i < 32; i++) {
368 MII_SET(RL_MII_CLK);
369 DELAY(1);
370 MII_CLR(RL_MII_CLK);
371 DELAY(1);
372 }
373
374 return;
375}
376
377/*
378 * Clock a series of bits through the MII.
379 */
380static void rl_mii_send(sc, bits, cnt)
381 struct rl_softc *sc;
382 u_int32_t bits;
383 int cnt;
384{
385 int i;
386
387 MII_CLR(RL_MII_CLK);
388
389 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
390 if (bits & i) {
391 MII_SET(RL_MII_DATAOUT);
392 } else {
393 MII_CLR(RL_MII_DATAOUT);
394 }
395 DELAY(1);
396 MII_CLR(RL_MII_CLK);
397 DELAY(1);
398 MII_SET(RL_MII_CLK);
399 }
400}
401
402/*
403 * Read an PHY register through the MII.
404 */
405static int rl_mii_readreg(sc, frame)
406 struct rl_softc *sc;
407 struct rl_mii_frame *frame;
408
409{
410 int i, ack, s;
411
412 s = splimp();
413
414 /*
415 * Set up frame for RX.
416 */
417 frame->mii_stdelim = RL_MII_STARTDELIM;
418 frame->mii_opcode = RL_MII_READOP;
419 frame->mii_turnaround = 0;
420 frame->mii_data = 0;
421
422 CSR_WRITE_2(sc, RL_MII, 0);
423
424 /*
425 * Turn on data xmit.
426 */
427 MII_SET(RL_MII_DIR);
428
429 rl_mii_sync(sc);
430
431 /*
432 * Send command/address info.
433 */
434 rl_mii_send(sc, frame->mii_stdelim, 2);
435 rl_mii_send(sc, frame->mii_opcode, 2);
436 rl_mii_send(sc, frame->mii_phyaddr, 5);
437 rl_mii_send(sc, frame->mii_regaddr, 5);
438
439 /* Idle bit */
440 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
441 DELAY(1);
442 MII_SET(RL_MII_CLK);
443 DELAY(1);
444
445 /* Turn off xmit. */
446 MII_CLR(RL_MII_DIR);
447
448 /* Check for ack */
449 MII_CLR(RL_MII_CLK);
450 DELAY(1);
451 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
452 MII_SET(RL_MII_CLK);
453 DELAY(1);
454
455 /*
456 * Now try reading data bits. If the ack failed, we still
457 * need to clock through 16 cycles to keep the PHY(s) in sync.
458 */
459 if (ack) {
460 for(i = 0; i < 16; i++) {
461 MII_CLR(RL_MII_CLK);
462 DELAY(1);
463 MII_SET(RL_MII_CLK);
464 DELAY(1);
465 }
466 goto fail;
467 }
468
469 for (i = 0x8000; i; i >>= 1) {
470 MII_CLR(RL_MII_CLK);
471 DELAY(1);
472 if (!ack) {
473 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
474 frame->mii_data |= i;
475 DELAY(1);
476 }
477 MII_SET(RL_MII_CLK);
478 DELAY(1);
479 }
480
481fail:
482
483 MII_CLR(RL_MII_CLK);
484 DELAY(1);
485 MII_SET(RL_MII_CLK);
486 DELAY(1);
487
488 splx(s);
489
490 if (ack)
491 return(1);
492 return(0);
493}
494
495/*
496 * Write to a PHY register through the MII.
497 */
498static int rl_mii_writereg(sc, frame)
499 struct rl_softc *sc;
500 struct rl_mii_frame *frame;
501
502{
503 int s;
504
505 s = splimp();
506 /*
507 * Set up frame for TX.
508 */
509
510 frame->mii_stdelim = RL_MII_STARTDELIM;
511 frame->mii_opcode = RL_MII_WRITEOP;
512 frame->mii_turnaround = RL_MII_TURNAROUND;
513
514 /*
515 * Turn on data output.
516 */
517 MII_SET(RL_MII_DIR);
518
519 rl_mii_sync(sc);
520
521 rl_mii_send(sc, frame->mii_stdelim, 2);
522 rl_mii_send(sc, frame->mii_opcode, 2);
523 rl_mii_send(sc, frame->mii_phyaddr, 5);
524 rl_mii_send(sc, frame->mii_regaddr, 5);
525 rl_mii_send(sc, frame->mii_turnaround, 2);
526 rl_mii_send(sc, frame->mii_data, 16);
527
528 /* Idle bit. */
529 MII_SET(RL_MII_CLK);
530 DELAY(1);
531 MII_CLR(RL_MII_CLK);
532 DELAY(1);
533
534 /*
535 * Turn off xmit.
536 */
537 MII_CLR(RL_MII_DIR);
538
539 splx(s);
540
541 return(0);
542}
543
544static int rl_miibus_readreg(dev, phy, reg)
545 device_t dev;
546 int phy, reg;
547{
548 struct rl_softc *sc;
549 struct rl_mii_frame frame;
550 u_int16_t rval = 0;
551 u_int16_t rl8139_reg = 0;
552
553 sc = device_get_softc(dev);
554
555 if (sc->rl_type == RL_8139) {
556 /* Pretend the internal PHY is only at address 0 */
557 if (phy)
558 return(0);
559 switch(reg) {
560 case MII_BMCR:
561 rl8139_reg = RL_BMCR;
562 break;
563 case MII_BMSR:
564 rl8139_reg = RL_BMSR;
565 break;
566 case MII_ANAR:
567 rl8139_reg = RL_ANAR;
568 break;
569 case MII_ANER:
570 rl8139_reg = RL_ANER;
571 break;
572 case MII_ANLPAR:
573 rl8139_reg = RL_LPAR;
574 break;
575 case MII_PHYIDR1:
576 case MII_PHYIDR2:
577 return(0);
578 break;
579 /*
580 * Allow the rlphy driver to read the media status
581 * register. If we have a link partner which does not
582 * support NWAY, this is the register which will tell
583 * us the results of parallel detection.
584 */
585 case RL_MEDIASTAT:
586 rval = CSR_READ_1(sc, RL_MEDIASTAT);
587 return(rval);
588 break;
589 default:
590 printf("rl%d: bad phy register\n", sc->rl_unit);
591 return(0);
592 }
593 rval = CSR_READ_2(sc, rl8139_reg);
594 return(rval);
595 }
596
597 bzero((char *)&frame, sizeof(frame));
598
599 frame.mii_phyaddr = phy;
600 frame.mii_regaddr = reg;
601 rl_mii_readreg(sc, &frame);
602
603 return(frame.mii_data);
604}
605
606static int rl_miibus_writereg(dev, phy, reg, data)
607 device_t dev;
608 int phy, reg, data;
609{
610 struct rl_softc *sc;
611 struct rl_mii_frame frame;
612 u_int16_t rl8139_reg = 0;
613
614 sc = device_get_softc(dev);
615
616 if (sc->rl_type == RL_8139) {
617 /* Pretend the internal PHY is only at address 0 */
618 if (phy)
619 return(0);
620 switch(reg) {
621 case MII_BMCR:
622 rl8139_reg = RL_BMCR;
623 break;
624 case MII_BMSR:
625 rl8139_reg = RL_BMSR;
626 break;
627 case MII_ANAR:
628 rl8139_reg = RL_ANAR;
629 break;
630 case MII_ANER:
631 rl8139_reg = RL_ANER;
632 break;
633 case MII_ANLPAR:
634 rl8139_reg = RL_LPAR;
635 break;
636 case MII_PHYIDR1:
637 case MII_PHYIDR2:
638 return(0);
639 break;
640 default:
641 printf("rl%d: bad phy register\n", sc->rl_unit);
642 return(0);
643 }
644 CSR_WRITE_2(sc, rl8139_reg, data);
645 return(0);
646 }
647
648 bzero((char *)&frame, sizeof(frame));
649
650 frame.mii_phyaddr = phy;
651 frame.mii_regaddr = reg;
652 frame.mii_data = data;
653
654 rl_mii_writereg(sc, &frame);
655
656 return(0);
657}
658
659static void rl_miibus_statchg(dev)
660 device_t dev;
661{
662 return;
663}
664
665/*
666 * Calculate CRC of a multicast group address, return the upper 6 bits.
667 */
668static u_int8_t rl_calchash(addr)
669 caddr_t addr;
670{
671 u_int32_t crc, carry;
672 int i, j;
673 u_int8_t c;
674
675 /* Compute CRC for the address value. */
676 crc = 0xFFFFFFFF; /* initial value */
677
678 for (i = 0; i < 6; i++) {
679 c = *(addr + i);
680 for (j = 0; j < 8; j++) {
681 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
682 crc <<= 1;
683 c >>= 1;
684 if (carry)
685 crc = (crc ^ 0x04c11db6) | carry;
686 }
687 }
688
689 /* return the filter bit position */
690 return(crc >> 26);
691}
692
693/*
694 * Program the 64-bit multicast hash filter.
695 */
696static void rl_setmulti(sc)
697 struct rl_softc *sc;
698{
699 struct ifnet *ifp;
700 int h = 0;
701 u_int32_t hashes[2] = { 0, 0 };
702 struct ifmultiaddr *ifma;
703 u_int32_t rxfilt;
704 int mcnt = 0;
705
706 ifp = &sc->arpcom.ac_if;
707
708 rxfilt = CSR_READ_4(sc, RL_RXCFG);
709
710 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
711 rxfilt |= RL_RXCFG_RX_MULTI;
712 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
713 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
714 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
715 return;
716 }
717
718 /* first, zot all the existing hash bits */
719 CSR_WRITE_4(sc, RL_MAR0, 0);
720 CSR_WRITE_4(sc, RL_MAR4, 0);
721
722 /* now program new ones */
723 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
724 ifma = ifma->ifma_link.le_next) {
725 if (ifma->ifma_addr->sa_family != AF_LINK)
726 continue;
727 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
728 if (h < 32)
729 hashes[0] |= (1 << h);
730 else
731 hashes[1] |= (1 << (h - 32));
732 mcnt++;
733 }
734
735 if (mcnt)
736 rxfilt |= RL_RXCFG_RX_MULTI;
737 else
738 rxfilt &= ~RL_RXCFG_RX_MULTI;
739
740 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
741 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
742 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
743
744 return;
745}
746
747static void rl_reset(sc)
748 struct rl_softc *sc;
749{
3d0f5f54 750 int i;
984263bc
MD
751
752 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
753
754 for (i = 0; i < RL_TIMEOUT; i++) {
755 DELAY(10);
756 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
757 break;
758 }
759 if (i == RL_TIMEOUT)
760 printf("rl%d: reset never completed!\n", sc->rl_unit);
761
762 return;
763}
764
765/*
766 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
767 * IDs against our list and return a device name if we find a match.
768 */
769static int rl_probe(dev)
770 device_t dev;
771{
772 struct rl_type *t;
773
774 t = rl_devs;
775
776 while(t->rl_name != NULL) {
777 if ((pci_get_vendor(dev) == t->rl_vid) &&
778 (pci_get_device(dev) == t->rl_did)) {
779 device_set_desc(dev, t->rl_name);
780 return(0);
781 }
782 t++;
783 }
784
785 return(ENXIO);
786}
787
788/*
789 * Attach the interface. Allocate softc structures, do ifmedia
790 * setup and ethernet/BPF attach.
791 */
792static int rl_attach(dev)
793 device_t dev;
794{
795 int s;
796 u_char eaddr[ETHER_ADDR_LEN];
797 u_int32_t command;
798 struct rl_softc *sc;
799 struct ifnet *ifp;
800 u_int16_t rl_did = 0;
801 int unit, error = 0, rid;
802
803 s = splimp();
804
805 sc = device_get_softc(dev);
806 unit = device_get_unit(dev);
807 bzero(sc, sizeof(struct rl_softc));
808
809 /*
810 * Handle power management nonsense.
811 */
812
813 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
814 if (command == 0x01) {
815
816 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
817 if (command & RL_PSTATE_MASK) {
818 u_int32_t iobase, membase, irq;
819
820 /* Save important PCI config data. */
821 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
822 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
823 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
824
825 /* Reset the power state. */
826 printf("rl%d: chip is is in D%d power mode "
827 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
828 command &= 0xFFFFFFFC;
829 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
830
831 /* Restore PCI config data. */
832 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
833 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
834 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
835 }
836 }
837
838 /*
839 * Map control/status registers.
840 */
841 command = pci_read_config(dev, PCIR_COMMAND, 4);
842 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
843 pci_write_config(dev, PCIR_COMMAND, command, 4);
844 command = pci_read_config(dev, PCIR_COMMAND, 4);
845
846#ifdef RL_USEIOSPACE
847 if (!(command & PCIM_CMD_PORTEN)) {
848 printf("rl%d: failed to enable I/O ports!\n", unit);
849 error = ENXIO;
850 goto fail;
851 }
852#else
853 if (!(command & PCIM_CMD_MEMEN)) {
854 printf("rl%d: failed to enable memory mapping!\n", unit);
855 error = ENXIO;
856 goto fail;
857 }
858#endif
859
860 rid = RL_RID;
861 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
862 0, ~0, 1, RF_ACTIVE);
863
864 if (sc->rl_res == NULL) {
865 printf ("rl%d: couldn't map ports/memory\n", unit);
866 error = ENXIO;
867 goto fail;
868 }
869
870 sc->rl_btag = rman_get_bustag(sc->rl_res);
871 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
872
873 rid = 0;
874 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
875 RF_SHAREABLE | RF_ACTIVE);
876
877 if (sc->rl_irq == NULL) {
878 printf("rl%d: couldn't map interrupt\n", unit);
879 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
880 error = ENXIO;
881 goto fail;
882 }
883
884 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
885 rl_intr, sc, &sc->rl_intrhand);
886
887 if (error) {
888 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
889 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
890 printf("rl%d: couldn't set up irq\n", unit);
891 goto fail;
892 }
893
894 callout_handle_init(&sc->rl_stat_ch);
895
896 /* Reset the adapter. */
897 rl_reset(sc);
898
899 /*
900 * Get station address from the EEPROM.
901 */
902 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
903
904 /*
905 * A RealTek chip was detected. Inform the world.
906 */
907 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
908
909 sc->rl_unit = unit;
910 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
911
912 /*
913 * Now read the exact device type from the EEPROM to find
914 * out if it's an 8129 or 8139.
915 */
916 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
917
918 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
919 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
920 rl_did == DLINK_DEVICEID_530TXPLUS)
921 sc->rl_type = RL_8139;
922 else if (rl_did == RT_DEVICEID_8129)
923 sc->rl_type = RL_8129;
924 else {
925 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
926 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
928 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
929 error = ENXIO;
930 goto fail;
931 }
932
933 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
934 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
935
936 if (sc->rl_cdata.rl_rx_buf == NULL) {
937 printf("rl%d: no memory for list buffers!\n", unit);
938 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
940 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
941 error = ENXIO;
942 goto fail;
943 }
944
945 /* Leave a few bytes before the start of the RX ring buffer. */
946 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
947 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
948
949 /* Do MII setup */
950 if (mii_phy_probe(dev, &sc->rl_miibus,
951 rl_ifmedia_upd, rl_ifmedia_sts)) {
952 printf("rl%d: MII without any phy!\n", sc->rl_unit);
953 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518,
954 M_DEVBUF);
955 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
956 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
957 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
958 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
959 error = ENXIO;
960 goto fail;
961 }
962
963 ifp = &sc->arpcom.ac_if;
964 ifp->if_softc = sc;
965 ifp->if_unit = unit;
966 ifp->if_name = "rl";
967 ifp->if_mtu = ETHERMTU;
968 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
969 ifp->if_ioctl = rl_ioctl;
970 ifp->if_output = ether_output;
971 ifp->if_start = rl_start;
972 ifp->if_watchdog = rl_watchdog;
973 ifp->if_init = rl_init;
974 ifp->if_baudrate = 10000000;
975 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
976
977 /*
978 * Call MI attach routine.
979 */
980 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
981
982fail:
983 splx(s);
984 return(error);
985}
986
987static int rl_detach(dev)
988 device_t dev;
989{
990 struct rl_softc *sc;
991 struct ifnet *ifp;
992 int s;
993
994 s = splimp();
995
996 sc = device_get_softc(dev);
997 ifp = &sc->arpcom.ac_if;
998
999 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1000 rl_stop(sc);
1001
1002 bus_generic_detach(dev);
1003 device_delete_child(dev, sc->rl_miibus);
1004
1005 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1007 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1008
1009 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, M_DEVBUF);
1010
1011 splx(s);
1012
1013 return(0);
1014}
1015
1016/*
1017 * Initialize the transmit descriptors.
1018 */
1019static int rl_list_tx_init(sc)
1020 struct rl_softc *sc;
1021{
1022 struct rl_chain_data *cd;
1023 int i;
1024
1025 cd = &sc->rl_cdata;
1026 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1027 cd->rl_tx_chain[i] = NULL;
1028 CSR_WRITE_4(sc,
1029 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1030 }
1031
1032 sc->rl_cdata.cur_tx = 0;
1033 sc->rl_cdata.last_tx = 0;
1034
1035 return(0);
1036}
1037
1038/*
1039 * A frame has been uploaded: pass the resulting mbuf chain up to
1040 * the higher level protocols.
1041 *
1042 * You know there's something wrong with a PCI bus-master chip design
1043 * when you have to use m_devget().
1044 *
1045 * The receive operation is badly documented in the datasheet, so I'll
1046 * attempt to document it here. The driver provides a buffer area and
1047 * places its base address in the RX buffer start address register.
1048 * The chip then begins copying frames into the RX buffer. Each frame
1049 * is preceeded by a 32-bit RX status word which specifies the length
1050 * of the frame and certain other status bits. Each frame (starting with
1051 * the status word) is also 32-bit aligned. The frame length is in the
1052 * first 16 bits of the status word; the lower 15 bits correspond with
1053 * the 'rx status register' mentioned in the datasheet.
1054 *
1055 * Note: to make the Alpha happy, the frame payload needs to be aligned
1056 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1057 * the ring buffer starting at an address two bytes before the actual
1058 * data location. We can then shave off the first two bytes using m_adj().
1059 * The reason we do this is because m_devget() doesn't let us specify an
1060 * offset into the mbuf storage space, so we have to artificially create
1061 * one. The ring is allocated in such a way that there are a few unused
1062 * bytes of space preceecing it so that it will be safe for us to do the
1063 * 2-byte backstep even if reading from the ring at offset 0.
1064 */
1065static void rl_rxeof(sc)
1066 struct rl_softc *sc;
1067{
1068 struct ether_header *eh;
1069 struct mbuf *m;
1070 struct ifnet *ifp;
1071 int total_len = 0;
1072 u_int32_t rxstat;
1073 caddr_t rxbufpos;
1074 int wrap = 0;
1075 u_int16_t cur_rx;
1076 u_int16_t limit;
1077 u_int16_t rx_bytes = 0, max_bytes;
1078
1079 ifp = &sc->arpcom.ac_if;
1080
1081 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1082
1083 /* Do not try to read past this point. */
1084 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1085
1086 if (limit < cur_rx)
1087 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1088 else
1089 max_bytes = limit - cur_rx;
1090
1091 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1092#ifdef DEVICE_POLLING
1093 if (ifp->if_ipending & IFF_POLLING) {
1094 if (sc->rxcycles <= 0)
1095 break;
1096 sc->rxcycles--;
1097 }
1098#endif /* DEVICE_POLLING */
1099 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1100 rxstat = *(u_int32_t *)rxbufpos;
1101
1102 /*
1103 * Here's a totally undocumented fact for you. When the
1104 * RealTek chip is in the process of copying a packet into
1105 * RAM for you, the length will be 0xfff0. If you spot a
1106 * packet header with this value, you need to stop. The
1107 * datasheet makes absolutely no mention of this and
1108 * RealTek should be shot for this.
1109 */
1110 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1111 break;
1112
1113 if (!(rxstat & RL_RXSTAT_RXOK)) {
1114 ifp->if_ierrors++;
1115 rl_init(sc);
1116 return;
1117 }
1118
1119 /* No errors; receive the packet. */
1120 total_len = rxstat >> 16;
1121 rx_bytes += total_len + 4;
1122
1123 /*
1124 * XXX The RealTek chip includes the CRC with every
1125 * received frame, and there's no way to turn this
1126 * behavior off (at least, I can't find anything in
1127 * the manual that explains how to do it) so we have
1128 * to trim off the CRC manually.
1129 */
1130 total_len -= ETHER_CRC_LEN;
1131
1132 /*
1133 * Avoid trying to read more bytes than we know
1134 * the chip has prepared for us.
1135 */
1136 if (rx_bytes > max_bytes)
1137 break;
1138
1139 rxbufpos = sc->rl_cdata.rl_rx_buf +
1140 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1141
1142 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1143 rxbufpos = sc->rl_cdata.rl_rx_buf;
1144
1145 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1146
1147 if (total_len > wrap) {
1148 /*
1149 * Fool m_devget() into thinking we want to copy
1150 * the whole buffer so we don't end up fragmenting
1151 * the data.
1152 */
1153 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1154 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1155 if (m == NULL) {
1156 ifp->if_ierrors++;
1157 } else {
1158 m_adj(m, RL_ETHER_ALIGN);
1159 m_copyback(m, wrap, total_len - wrap,
1160 sc->rl_cdata.rl_rx_buf);
1161 }
1162 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1163 } else {
1164 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1165 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1166 if (m == NULL) {
1167 ifp->if_ierrors++;
1168 } else
1169 m_adj(m, RL_ETHER_ALIGN);
1170 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1171 }
1172
1173 /*
1174 * Round up to 32-bit boundary.
1175 */
1176 cur_rx = (cur_rx + 3) & ~3;
1177 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1178
1179 if (m == NULL)
1180 continue;
1181
1182 eh = mtod(m, struct ether_header *);
1183 ifp->if_ipackets++;
1184
1185 /* Remove header from mbuf and pass it on. */
1186 m_adj(m, sizeof(struct ether_header));
1187 ether_input(ifp, eh, m);
1188 }
1189
1190 return;
1191}
1192
1193/*
1194 * A frame was downloaded to the chip. It's safe for us to clean up
1195 * the list buffers.
1196 */
1197static void rl_txeof(sc)
1198 struct rl_softc *sc;
1199{
1200 struct ifnet *ifp;
1201 u_int32_t txstat;
1202
1203 ifp = &sc->arpcom.ac_if;
1204
1205 /*
1206 * Go through our tx list and free mbufs for those
1207 * frames that have been uploaded.
1208 */
1209 do {
1210 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1211 if (!(txstat & (RL_TXSTAT_TX_OK|
1212 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1213 break;
1214
1215 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1216
1217 if (RL_LAST_TXMBUF(sc) != NULL) {
1218 m_freem(RL_LAST_TXMBUF(sc));
1219 RL_LAST_TXMBUF(sc) = NULL;
1220 }
1221 if (txstat & RL_TXSTAT_TX_OK)
1222 ifp->if_opackets++;
1223 else {
1224 int oldthresh;
1225 ifp->if_oerrors++;
1226 if ((txstat & RL_TXSTAT_TXABRT) ||
1227 (txstat & RL_TXSTAT_OUTOFWIN))
1228 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1229 oldthresh = sc->rl_txthresh;
1230 /* error recovery */
1231 rl_reset(sc);
1232 rl_init(sc);
1233 /*
1234 * If there was a transmit underrun,
1235 * bump the TX threshold.
1236 */
1237 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1238 sc->rl_txthresh = oldthresh + 32;
1239 return;
1240 }
1241 RL_INC(sc->rl_cdata.last_tx);
1242 ifp->if_flags &= ~IFF_OACTIVE;
1243 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1244
1245 ifp->if_timer =
1246 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
1247
1248 return;
1249}
1250
1251static void rl_tick(xsc)
1252 void *xsc;
1253{
1254 struct rl_softc *sc;
1255 struct mii_data *mii;
1256 int s;
1257
1258 s = splimp();
1259
1260 sc = xsc;
1261 mii = device_get_softc(sc->rl_miibus);
1262
1263 mii_tick(mii);
1264
1265 splx(s);
1266
1267 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1268
1269 return;
1270}
1271
1272#ifdef DEVICE_POLLING
1273static poll_handler_t rl_poll;
1274
1275static void
1276rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1277{
1278 struct rl_softc *sc = ifp->if_softc;
1279
1280 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1281 CSR_WRITE_4(sc, RL_IMR, RL_INTRS);
1282 return;
1283 }
1284
1285 sc->rxcycles = count;
1286 rl_rxeof(sc);
1287 rl_txeof(sc);
1288 if (ifp->if_snd.ifq_head != NULL)
1289 rl_start(ifp);
1290
1291 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1292 u_int16_t status;
1293
1294 status = CSR_READ_2(sc, RL_ISR);
1295 if (status)
1296 CSR_WRITE_2(sc, RL_ISR, status);
1297
1298 /*
1299 * XXX check behaviour on receiver stalls.
1300 */
1301
1302 if (status & RL_ISR_SYSTEM_ERR) {
1303 rl_reset(sc);
1304 rl_init(sc);
1305 }
1306 }
1307}
1308#endif /* DEVICE_POLLING */
1309
1310static void rl_intr(arg)
1311 void *arg;
1312{
1313 struct rl_softc *sc;
1314 struct ifnet *ifp;
1315 u_int16_t status;
1316
1317 sc = arg;
1318
1319 if (sc->suspended) {
1320 return;
1321 }
1322
1323 ifp = &sc->arpcom.ac_if;
1324#ifdef DEVICE_POLLING
1325 if (ifp->if_ipending & IFF_POLLING)
1326 return;
1327 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1328 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1329 rl_poll(ifp, 0, 1);
1330 return;
1331 }
1332#endif /* DEVICE_POLLING */
1333
1334 for (;;) {
1335
1336 status = CSR_READ_2(sc, RL_ISR);
1337 if (status)
1338 CSR_WRITE_2(sc, RL_ISR, status);
1339
1340 if ((status & RL_INTRS) == 0)
1341 break;
1342
1343 if (status & RL_ISR_RX_OK)
1344 rl_rxeof(sc);
1345
1346 if (status & RL_ISR_RX_ERR)
1347 rl_rxeof(sc);
1348
1349 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1350 rl_txeof(sc);
1351
1352 if (status & RL_ISR_SYSTEM_ERR) {
1353 rl_reset(sc);
1354 rl_init(sc);
1355 }
1356
1357 }
1358 if (ifp->if_snd.ifq_head != NULL)
1359 rl_start(ifp);
1360
1361 return;
1362}
1363
1364/*
1365 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1366 * pointers to the fragment pointers.
1367 */
1368static int rl_encap(sc, m_head)
1369 struct rl_softc *sc;
1370 struct mbuf *m_head;
1371{
1372 struct mbuf *m_new = NULL;
1373
1374 /*
1375 * The RealTek is brain damaged and wants longword-aligned
1376 * TX buffers, plus we can only have one fragment buffer
1377 * per packet. We have to copy pretty much all the time.
1378 */
1379
1380 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1381 if (m_new == NULL)
1382 return(1);
1383 if (m_head->m_pkthdr.len > MHLEN) {
1384 MCLGET(m_new, M_DONTWAIT);
1385 if (!(m_new->m_flags & M_EXT)) {
1386 m_freem(m_new);
1387 return(1);
1388 }
1389 }
1390 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1391 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1392 m_freem(m_head);
1393 m_head = m_new;
1394
1395 /* Pad frames to at least 60 bytes. */
1396 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1397 /*
1398 * Make security concious people happy: zero out the
1399 * bytes in the pad area, since we don't know what
1400 * this mbuf cluster buffer's previous user might
1401 * have left in it.
1402 */
1403 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1404 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1405 m_head->m_pkthdr.len +=
1406 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1407 m_head->m_len = m_head->m_pkthdr.len;
1408 }
1409
1410 RL_CUR_TXMBUF(sc) = m_head;
1411
1412 return(0);
1413}
1414
1415/*
1416 * Main transmit routine.
1417 */
1418
1419static void rl_start(ifp)
1420 struct ifnet *ifp;
1421{
1422 struct rl_softc *sc;
1423 struct mbuf *m_head = NULL;
1424
1425 sc = ifp->if_softc;
1426
1427 while(RL_CUR_TXMBUF(sc) == NULL) {
1428 IF_DEQUEUE(&ifp->if_snd, m_head);
1429 if (m_head == NULL)
1430 break;
1431
1432 if (rl_encap(sc, m_head)) {
1433 IF_PREPEND(&ifp->if_snd, m_head);
1434 ifp->if_flags |= IFF_OACTIVE;
1435 break;
1436 }
1437
1438 /*
1439 * If there's a BPF listener, bounce a copy of this frame
1440 * to him.
1441 */
1442 if (ifp->if_bpf)
1443 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1444
1445 /*
1446 * Transmit the frame.
1447 */
1448 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1449 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1450 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1451 RL_TXTHRESH(sc->rl_txthresh) |
1452 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1453
1454 RL_INC(sc->rl_cdata.cur_tx);
1455 }
1456
1457 /*
1458 * We broke out of the loop because all our TX slots are
1459 * full. Mark the NIC as busy until it drains some of the
1460 * packets from the queue.
1461 */
1462 if (RL_CUR_TXMBUF(sc) != NULL)
1463 ifp->if_flags |= IFF_OACTIVE;
1464
1465 /*
1466 * Set a timeout in case the chip goes out to lunch.
1467 */
1468 ifp->if_timer = 5;
1469
1470 return;
1471}
1472
1473static void rl_init(xsc)
1474 void *xsc;
1475{
1476 struct rl_softc *sc = xsc;
1477 struct ifnet *ifp = &sc->arpcom.ac_if;
1478 struct mii_data *mii;
1479 int s, i;
1480 u_int32_t rxcfg = 0;
1481
1482 s = splimp();
1483
1484 mii = device_get_softc(sc->rl_miibus);
1485
1486 /*
1487 * Cancel pending I/O and free all RX/TX buffers.
1488 */
1489 rl_stop(sc);
1490
1491 /* Init our MAC address */
1492 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1493 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1494 }
1495
1496 /* Init the RX buffer pointer register. */
1497 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1498
1499 /* Init TX descriptors. */
1500 rl_list_tx_init(sc);
1501
1502 /*
1503 * Enable transmit and receive.
1504 */
1505 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1506
1507 /*
1508 * Set the initial TX and RX configuration.
1509 */
1510 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1511 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1512
1513 /* Set the individual bit to receive frames for this host only. */
1514 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1515 rxcfg |= RL_RXCFG_RX_INDIV;
1516
1517 /* If we want promiscuous mode, set the allframes bit. */
1518 if (ifp->if_flags & IFF_PROMISC) {
1519 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1520 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1521 } else {
1522 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1523 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1524 }
1525
1526 /*
1527 * Set capture broadcast bit to capture broadcast frames.
1528 */
1529 if (ifp->if_flags & IFF_BROADCAST) {
1530 rxcfg |= RL_RXCFG_RX_BROAD;
1531 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1532 } else {
1533 rxcfg &= ~RL_RXCFG_RX_BROAD;
1534 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1535 }
1536
1537 /*
1538 * Program the multicast filter, if necessary.
1539 */
1540 rl_setmulti(sc);
1541
1542#ifdef DEVICE_POLLING
1543 /*
1544 * Only enable interrupts if we are polling, keep them off otherwise.
1545 */
1546 if (ifp->if_ipending & IFF_POLLING)
1547 CSR_WRITE_2(sc, RL_IMR, 0);
1548 else
1549#endif /* DEVICE_POLLING */
1550 /*
1551 * Enable interrupts.
1552 */
1553 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1554
1555 /* Set initial TX threshold */
1556 sc->rl_txthresh = RL_TX_THRESH_INIT;
1557
1558 /* Start RX/TX process. */
1559 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1560
1561 /* Enable receiver and transmitter. */
1562 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1563
1564 mii_mediachg(mii);
1565
1566 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1567
1568 ifp->if_flags |= IFF_RUNNING;
1569 ifp->if_flags &= ~IFF_OACTIVE;
1570
1571 (void)splx(s);
1572
1573 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1574
1575 return;
1576}
1577
1578/*
1579 * Set media options.
1580 */
1581static int rl_ifmedia_upd(ifp)
1582 struct ifnet *ifp;
1583{
1584 struct rl_softc *sc;
1585 struct mii_data *mii;
1586
1587 sc = ifp->if_softc;
1588 mii = device_get_softc(sc->rl_miibus);
1589 mii_mediachg(mii);
1590
1591 return(0);
1592}
1593
1594/*
1595 * Report current media status.
1596 */
1597static void rl_ifmedia_sts(ifp, ifmr)
1598 struct ifnet *ifp;
1599 struct ifmediareq *ifmr;
1600{
1601 struct rl_softc *sc;
1602 struct mii_data *mii;
1603
1604 sc = ifp->if_softc;
1605 mii = device_get_softc(sc->rl_miibus);
1606
1607 mii_pollstat(mii);
1608 ifmr->ifm_active = mii->mii_media_active;
1609 ifmr->ifm_status = mii->mii_media_status;
1610
1611 return;
1612}
1613
1614static int rl_ioctl(ifp, command, data)
1615 struct ifnet *ifp;
1616 u_long command;
1617 caddr_t data;
1618{
1619 struct rl_softc *sc = ifp->if_softc;
1620 struct ifreq *ifr = (struct ifreq *) data;
1621 struct mii_data *mii;
1622 int s, error = 0;
1623
1624 s = splimp();
1625
1626 switch(command) {
1627 case SIOCSIFADDR:
1628 case SIOCGIFADDR:
1629 case SIOCSIFMTU:
1630 error = ether_ioctl(ifp, command, data);
1631 break;
1632 case SIOCSIFFLAGS:
1633 if (ifp->if_flags & IFF_UP) {
1634 rl_init(sc);
1635 } else {
1636 if (ifp->if_flags & IFF_RUNNING)
1637 rl_stop(sc);
1638 }
1639 error = 0;
1640 break;
1641 case SIOCADDMULTI:
1642 case SIOCDELMULTI:
1643 rl_setmulti(sc);
1644 error = 0;
1645 break;
1646 case SIOCGIFMEDIA:
1647 case SIOCSIFMEDIA:
1648 mii = device_get_softc(sc->rl_miibus);
1649 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1650 break;
1651 default:
1652 error = EINVAL;
1653 break;
1654 }
1655
1656 (void)splx(s);
1657
1658 return(error);
1659}
1660
1661static void rl_watchdog(ifp)
1662 struct ifnet *ifp;
1663{
1664 struct rl_softc *sc;
1665
1666 sc = ifp->if_softc;
1667
1668 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1669 ifp->if_oerrors++;
1670
1671 rl_txeof(sc);
1672 rl_rxeof(sc);
1673 rl_init(sc);
1674
1675 return;
1676}
1677
1678/*
1679 * Stop the adapter and free any mbufs allocated to the
1680 * RX and TX lists.
1681 */
1682static void rl_stop(sc)
1683 struct rl_softc *sc;
1684{
3d0f5f54 1685 int i;
984263bc
MD
1686 struct ifnet *ifp;
1687
1688 ifp = &sc->arpcom.ac_if;
1689 ifp->if_timer = 0;
1690
1691 untimeout(rl_tick, sc, sc->rl_stat_ch);
1692 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1693#ifdef DEVICE_POLLING
1694 ether_poll_deregister(ifp);
1695#endif /* DEVICE_POLLING */
1696
1697 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1698 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1699
1700 /*
1701 * Free the TX list buffers.
1702 */
1703 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1704 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1705 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1706 sc->rl_cdata.rl_tx_chain[i] = NULL;
1707 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1708 }
1709 }
1710
1711
1712 return;
1713}
1714
1715/*
1716 * Stop all chip I/O so that the kernel's probe routines don't
1717 * get confused by errant DMAs when rebooting.
1718 */
1719static void rl_shutdown(dev)
1720 device_t dev;
1721{
1722 struct rl_softc *sc;
1723
1724 sc = device_get_softc(dev);
1725
1726 rl_stop(sc);
1727
1728 return;
1729}
1730
1731/*
1732 * Device suspend routine. Stop the interface and save some PCI
1733 * settings in case the BIOS doesn't restore them properly on
1734 * resume.
1735 */
1736static int rl_suspend(dev)
1737 device_t dev;
1738{
3d0f5f54 1739 int i;
984263bc
MD
1740 struct rl_softc *sc;
1741
1742 sc = device_get_softc(dev);
1743
1744 rl_stop(sc);
1745
1746 for (i = 0; i < 5; i++)
1747 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1748 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1749 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1750 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1751 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1752
1753 sc->suspended = 1;
1754
1755 return (0);
1756}
1757
1758/*
1759 * Device resume routine. Restore some PCI settings in case the BIOS
1760 * doesn't, re-enable busmastering, and restart the interface if
1761 * appropriate.
1762 */
1763static int rl_resume(dev)
1764 device_t dev;
1765{
3d0f5f54 1766 int i;
984263bc
MD
1767 struct rl_softc *sc;
1768 struct ifnet *ifp;
1769
1770 sc = device_get_softc(dev);
1771 ifp = &sc->arpcom.ac_if;
1772
1773 /* better way to do this? */
1774 for (i = 0; i < 5; i++)
1775 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1776 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1777 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1778 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1779 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1780
1781 /* reenable busmastering */
1782 pci_enable_busmaster(dev);
1783 pci_enable_io(dev, RL_RES);
1784
1785 /* reinitialize interface if necessary */
1786 if (ifp->if_flags & IFF_UP)
1787 rl_init(sc);
1788
1789 sc->suspended = 0;
1790
1791 return (0);
1792}