Merge from vendor branch GPERF:
[dragonfly.git] / sys / dev / netif / ray / if_rayreg.h
CommitLineData
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1/*
2 * Copyright (C) 2000
3 * Dr. Duncan McLennan Barclay, dmlb@ragnet.demon.co.uk.
4 *
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY DUNCAN BARCLAY AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL DUNCAN BARCLAY OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: src/sys/dev/ray/if_rayreg.h,v 1.10.2.3 2001/01/03 10:45:39 dmlb Exp $
1de703da 32 * $DragonFly: src/sys/dev/netif/ray/Attic/if_rayreg.h,v 1.2 2003/06/17 04:28:29 dillon Exp $
984263bc
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33 *
34 */
35
36/* $NetBSD: if_rayreg.h,v 1.1 2000/01/23 23:59:22 chopps Exp $ */
37/*
38 * Copyright (c) 2000 Christian E. Hopps
39 * All rights reserved.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. Neither the name of the author nor the names of any co-contributors
50 * may be used to endorse or promote products derived from this software
51 * without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 */
65
66/*
67 * CCR registers, appearing in the attribute memory space
68 */
69#define RAY_CCR 0xf00 /* CCR register offset */
70#define RAY_COR (RAY_CCR + 0x00) /* config option register */
71#define RAY_CCSR (RAY_CCR + 0x01) /* config/status register */
72#define RAY_PIN (RAY_CCR + 0x02) /* not used by hw */
73#define RAY_SOCKETCOPY (RAY_CCR + 0x03) /* not used by hw */
74#define RAY_HCSIR (RAY_CCR + 0x05) /* HCS intr register */
75#define RAY_ECFIR (RAY_CCR + 0x06) /* ECF intr register */
76/*
77 * We don't seem to be able to access these in a simple manner
78 */
79#define RAY_AR0 (RAY_CCR + 0x08) /* authorization register 0 (unused) */
80#define RAY_AR1 (RAY_CCR + 0x09) /* authorization register 1 (unused) */
81#define RAY_PMR (RAY_CCR + 0x0a) /* program mode register (unused) */
82#define RAY_TMR (RAY_CCR + 0x0b) /* pc test mode register (unused) */
83#define RAY_FCWR (RAY_CCR + 0x10) /* frequency control word register */
84#define RAY_TMC1 (RAY_CCR + 0x14) /* test mode control 1 (unused) */
85#define RAY_TMC2 (RAY_CCR + 0x15) /* test mode control 1 (unused) */
86#define RAY_TMC3 (RAY_CCR + 0x16) /* test mode control 1 (unused) */
87#define RAY_TMC4 (RAY_CCR + 0x17) /* test mode control 1 (unused) */
88
89/*
90 * COR register bits
91 */
92#define RAY_COR_CFG_NUM 0x01 /* currently ignored and set */
93#define RAY_COR_CFG_MASK 0x3f /* mask for function */
94#define RAY_COR_LEVEL_IRQ 0x40 /* currently ignored and set */
95#define RAY_COR_RESET 0x80 /* soft-reset the card */
96#define RAY_COR_DEFAULT (RAY_COR_CFG_NUM | RAY_COR_LEVEL_IRQ)
97
98/*
99 * CCS register bits
100 */
101#define RAY_CCS_NORMAL 0x00 /* normal operation */
102#define RAY_CCS_IRQ 0x02 /* interrupt pending */
103#define RAY_CCS_POWER_DOWN 0x04 /* when written powers down card */
104
105/*
106 * HCSIR bits
107 *
108 * the host can only clear this bit.
109 */
110#define RAY_HCSIR_IRQ 0x01 /* indicates an interrupt */
111
112/*
113 * ECFIR values
114 */
115#define RAY_ECFIR_IRQ 0x01 /* interrupt the card */
116
117/*
118 * AR0 values
119 * used for testing/programming the card (unused)
120 */
121#define RAY_AR0_ON 0x57
122
123/*
124 * AR1 values
125 * used for testing/programming the card (unused)
126 */
127#define RAY_AR1_ON 0x82
128
129/*
130 * PMR bits
131 * these are used to program the card (unused)
132 */
133#define RAY_PMR_NORMAL 0x00 /* normal operation */
134#define RAY_PMR_PC2PM 0x02 /* grant access to firmware flash */
135#define RAY_PMR_PC2CAL 0x10 /* read access to the A/D modem inp */
136#define RAY_PMR_MLSE 0x20 /* read access to the MSLE prom */
137
138/*
139 * TMR bits
140 * get access to test modes (unused)
141 */
142#define RAY_TMR_NORMAL 0x00 /* normal operation */
143#define RAY_TMR_TEST 0x08 /* test mode */
144
145/*
146 * FCWR -- frequency control word, values from [0x02,0xA6] map to
147 * RF frequency values.
148 */
149
150/*
151 * 48k of memory
152 */
153#define RAY_SRAM_MEM_BASE 0
154#define RAY_SRAM_MEM_SIZE 0xc000
155
156/*
157 * offsets into shared ram
158 */
159#define RAY_SCB_BASE 0x0000 /* cfg/status/ctl area */
160#define RAY_STATUS_BASE 0x0100
161#define RAY_HOST_TO_ECF_BASE 0x0200
162#define RAY_ECF_TO_HOST_BASE 0x0300
163#define RAY_CCS_BASE 0x0400
164#define RAY_RCS_BASE 0x0800
165#define RAY_APOINT_TIM_BASE 0x0c00
166#define RAY_SSID_LIST_BASE 0x0d00
167#define RAY_TX_BASE 0x1000
168#define RAY_TX_SIZE 0x7000
169#define RAY_TX_END 0x8000
170#define RAY_RX_BASE 0x8000
171#define RAY_RX_END 0xc000
172#define RAY_RX_MASK 0x3fff
173
174/*
175 * Startup reporting stucture
176 */
177struct ray_ecf_startup_v4 {
178 u_int8_t e_status;
179 u_int8_t e_station_addr[ETHER_ADDR_LEN];
180 u_int8_t e_prg_cksum;
181 u_int8_t e_cis_cksum;
182 u_int8_t e_resv0[7];
183 u_int8_t e_japan_callsign[12];
184};
185struct ray_ecf_startup_v5 {
186 u_int8_t e_status;
187 u_int8_t e_station_addr[ETHER_ADDR_LEN];
188 u_int8_t e_resv0;
189 u_int8_t e_rates[8];
190 u_int8_t e_japan_callsign[12];
191 u_int8_t e_prg_cksum;
192 u_int8_t e_cis_cksum;
193 u_int8_t e_fw_build_string;
194 u_int8_t e_fw_build;
195 u_int8_t e_fw_resv;
196 u_int8_t e_asic_version;
197 u_int8_t e_tibsize;
198 u_int8_t e_resv1[29];
199};
200
201/*
202 * Startup status word result codes
203 */
204#define RAY_ECFS_RESERVED0 0x01
205#define RAY_ECFS_PROC_SELF_TEST 0x02
206#define RAY_ECFS_PROG_MEM_CHECKSUM 0x04
207#define RAY_ECFS_DATA_MEM_TEST 0x08
208#define RAY_ECFS_RX_CALIBRATION 0x10
209#define RAY_ECFS_FW_VERSION_COMPAT 0x20
210#define RAY_ECFS_RERSERVED1 0x40
211#define RAY_ECFS_TEST_COMPLETE 0x80
212#define RAY_ECFS_CARD_OK RAY_ECFS_TEST_COMPLETE
213#define RAY_ECFS_PRINTFB \
214 "\020" \
215 "\001RESERVED0" \
216 "\002PROC_SELF_TEST" \
217 "\003PROG_MEM_CHECKSUM" \
218 "\004DATA_MEM_TEST" \
219 "\005RX_CALIBRATION" \
220 "\006FW_VERSION_COMPAT" \
221 "\007RERSERVED1" \
222 "\010TEST_COMPLETE"
223
224/*
225 * Firmware build codes
226 */
227#define RAY_ECFS_BUILD_4 0x55
228#define RAY_ECFS_BUILD_5 0x5
229
230/*
231 * System Control Block
232 */
233#define RAY_SCB_CCSI 0x00 /* host CCS index */
234#define RAY_SCB_RCSI 0x01 /* ecf RCS index */
235
236/*
237 * command control structures (for CCSR commands)
238 */
239
240/*
241 * commands for CCSR
242 */
243#define RAY_CMD_DOWNLOAD_PARAMS 0x01 /* download start params */
244#define RAY_CMD_UPDATE_PARAMS 0x02 /* update params */
245#define RAY_CMD_REPORT_PARAMS 0x03 /* report params */
246#define RAY_CMD_UPDATE_MCAST 0x04 /* update mcast list */
247#define RAY_CMD_UPDATE_APM 0x05 /* update power saving mode */
248#define RAY_CMD_START_NET 0x06
249#define RAY_CMD_JOIN_NET 0x07
250#define RAY_CMD_START_ASSOC 0x08
251#define RAY_CMD_TX_REQ 0x09
252#define RAY_CMD_TEST_MEM 0x0a
253#define RAY_CMD_SHUTDOWN 0x0b
254#define RAY_CMD_DUMP_MEM 0x0c
255#define RAY_CMD_START_TIMER 0x0d
256#define RAY_CMD_MAX 0x0e
257
258/*
259 * unsolicted commands from the ECF
260 */
261#define RAY_ECMD_RX_DONE 0x80 /* process rx packet */
262#define RAY_ECMD_REJOIN_DONE 0x81 /* rejoined the network */
263#define RAY_ECMD_ROAM_START 0x82 /* romaining started */
264#define RAY_ECMD_JAPAN_CALL_SIGNAL 0x83 /* japan test thing */
265
266
267/*
268 * Configure/status/control memory
269 */
270struct ray_csc {
271 u_int8_t csc_mrxo_own; /* 0 ECF writes, 1 host write */
272 u_int8_t csc_mrxc_own; /* 0 ECF writes, 1 host write */
273 u_int8_t csc_rxhc_own; /* 0 ECF writes, 1 host write */
274 u_int8_t csc_resv;
275 u_int16_t csc_mrx_overflow; /* ECF incs on rx overflow */
276 u_int16_t csc_mrx_cksum; /* ECF incs on cksum error */
277 u_int16_t csc_rx_hcksum; /* ECF incs on header cksum error */
278 u_int8_t csc_rx_noise; /* average RSL measuremant */
279};
280
281/*
282 * CCS area
283 */
284#define RAY_CCS_LINK_NULL 0xff
285#define RAY_CCS_SIZE 16
286
287#define RAY_CCS_TX_FIRST 0
288#define RAY_CCS_TX_LAST 13
289#define RAY_CCS_NTX (RAY_CCS_TX_LAST - RAY_CCS_TX_FIRST + 1)
290#define RAY_TX_BUF_SIZE 2048
291#define RAY_CCS_CMD_FIRST 14
292#define RAY_CCS_CMD_LAST 63
293#define RAY_CCS_NCMD (RAY_CCS_CMD_LAST - RAY_CCS_CMD_FIRST + 1)
294#define RAY_CCS_LAST 63
295
296#define RAY_CCS_INDEX(ccs) (((ccs) - RAY_CCS_BASE) / RAY_CCS_SIZE)
297#define RAY_CCS_ADDRESS(i) (RAY_CCS_BASE + (i) * RAY_CCS_SIZE)
298
299/*
300 * RCS area
301 */
302#define RAY_RCS_FIRST 64
303#define RAY_RCS_LAST 127
304
305/*
306 * CCS commands
307 */
308struct ray_cmd {
309 u_int8_t c_status; /* ccs generic header */
310 u_int8_t c_cmd; /* " */
311 u_int8_t c_link; /* " */
312};
313
314#define RAY_CCS_STATUS_FREE 0x0
315#define RAY_CCS_STATUS_BUSY 0x1
316#define RAY_CCS_STATUS_COMPLETE 0x2
317#define RAY_CCS_STATUS_FAIL 0x3
318#define RAY_CCS_STATUS_STRINGS { \
319 "free", \
320 "busy", \
321 "complete", \
322 "fail" \
323}
324
325/* RAY_CMD_UPDATE_PARAMS */
326struct ray_cmd_update {
327 u_int8_t c_status; /* ccs generic header */
328 u_int8_t c_cmd; /* " */
329 u_int8_t c_link; /* " */
330 u_int8_t c_paramid;
331 u_int8_t c_nparam;
332 u_int8_t c_failcause;
333};
334
335/* RAY_CMD_REPORT_PARAMS */
336struct ray_cmd_report {
337 u_int8_t c_status; /* ccs generic header */
338 u_int8_t c_cmd; /* " */
339 u_int8_t c_link; /* " */
340 u_int8_t c_paramid;
341 u_int8_t c_nparam;
342 u_int8_t c_failcause;
343 u_int8_t c_len;
344};
345
346/* RAY_CMD_UPDATE_MCAST */
347struct ray_cmd_update_mcast {
348 u_int8_t c_status; /* ccs generic header */
349 u_int8_t c_cmd; /* " */
350 u_int8_t c_link; /* " */
351 u_int8_t c_nmcast;
352};
353
354/* RAY_CMD_UPDATE_APM */
355struct ray_cmd_udpate_apm {
356 u_int8_t c_status; /* ccs generic header */
357 u_int8_t c_cmd; /* " */
358 u_int8_t c_link; /* " */
359 u_int8_t c_mode;
360};
361
362/* RAY_CMD_START_NET and RAY_CMD_JOIN_NET */
363struct ray_cmd_net {
364 u_int8_t c_status; /* ccs generic header */
365 u_int8_t c_cmd; /* " */
366 u_int8_t c_link; /* " */
367 u_int8_t c_upd_param;
368 u_int8_t c_bss_id[ETHER_ADDR_LEN];
369 u_int8_t c_inited;
370 u_int8_t c_def_txrate;
371 u_int8_t c_encrypt;
372};
373/* Parameters passed in HOST_TO_ECF section when c_upd_param is set in
374 * ray_cmd_net. */
375struct ray_net_params {
376 u_int8_t p_net_type;
377 u_int8_t p_ssid[32];
378 u_int8_t p_privacy_must_start;
379 u_int8_t p_privacy_can_join;
380};
381
382/* RAY_CMD_START_ASSOC */
383struct ray_cmd_update_assoc {
384 u_int8_t c_status; /* ccs generic header */
385 u_int8_t c_cmd; /* " */
386 u_int8_t c_link; /* " */
387 u_int8_t c_astatus;
388 u_int8_t c_aid[2];
389};
390
391/* RAY_CMD_TX_REQ */
392struct ray_cmd_tx {
393 u_int8_t c_status; /* ccs generic header */
394 u_int8_t c_cmd; /* " */
395 u_int8_t c_link; /* " */
396 u_int8_t c_bufp[2];
397 u_int8_t c_len[2];
398 u_int8_t c_resv[5];
399 u_int8_t c_tx_rate;
400 u_int8_t c_apm_mode;
401 u_int8_t c_nretry;
402 u_int8_t c_antenna;
403};
404struct ray_cmd_tx_4 {
405 u_int8_t c_status; /* ccs generic header */
406 u_int8_t c_cmd; /* " */
407 u_int8_t c_link; /* " */
408 u_int8_t c_bufp[2];
409 u_int8_t c_len[2];
410 u_int8_t c_addr[ETHER_ADDR_LEN];
411 u_int8_t c_apm_mode;
412 u_int8_t c_nretry;
413 u_int8_t c_antenna;
414};
415
416/* RAY_CMD_DUMP_MEM */
417struct ray_cmd_dump_mem {
418 u_int8_t c_status; /* ccs generic header */
419 u_int8_t c_cmd; /* " */
420 u_int8_t c_link; /* " */
421 u_int8_t c_memtype;
422 u_int8_t c_memp[2];
423 u_int8_t c_len;
424};
425
426/* RAY_CMD_START_TIMER */
427struct ray_cmd_start_timer {
428 u_int8_t c_status; /* ccs generic header */
429 u_int8_t c_cmd; /* " */
430 u_int8_t c_link; /* " */
431 u_int8_t c_duration[2];
432};
433
434/* RAY_ECMD_RX_DONE */
435struct ray_cmd_rx {
436 u_int8_t c_status; /* ccs generic header */
437 u_int8_t c_cmd; /* " */
438 u_int8_t c_link; /* " */
439 u_int8_t c_bufp[2]; /* buffer pointer */
440 u_int8_t c_len[2]; /* length */
441 u_int8_t c_siglev; /* signal level */
442 u_int8_t c_nextfrag; /* next fragment in packet */
443 u_int8_t c_pktlen[2]; /* total packet length */
444 u_int8_t c_antenna; /* ant. with best reception */
445 u_int8_t c_updbss; /* only 1 for beacon messages */
446};
447
448/*
449 * Transmit scratch space and phy header structures
450 */
451struct ray_tx_tib {
452 u_int8_t t_ccs_index;
453 u_int8_t t_psm;
454 u_int8_t t_pass_fail;
455 u_int8_t t_retry_count;
456 u_int8_t t_max_retries;
457 u_int8_t t_frags_remaining;
458 u_int8_t t_no_rb;
459 u_int8_t t_rts_reqd;
460 u_int8_t t_csma_tx_cntrl_2;
461 u_int8_t t_sifs_tx_cntrl_2;
462 u_int8_t t_tx_dma_addr_1[2];
463 u_int8_t t_tx_dma_addr_2[2];
464 u_int8_t t_var_dur_2mhz[2];
465 u_int8_t t_var_dur_1mhz[2];
466 u_int8_t t_max_dur_2mhz[2];
467 u_int8_t t_max_dur_1mhz[2];
468 u_int8_t t_hdr_len;
469 u_int8_t t_max_frag_len[2];
470 u_int8_t t_var_len[2];
471 u_int8_t t_phy_hdr_4;
472 u_int8_t t_mac_hdr_1;
473 u_int8_t t_mac_hdr_2;
474 u_int8_t t_sid[2];
475};
476
477struct ray_tx_phy_header {
478 u_int8_t t_sfd[2];
479 u_int8_t t_hdr_3;
480 u_int8_t t_hdr_4;
481};