pci intr config: 'j' is the pin index we want to skip.
[dragonfly.git] / sys / bus / pci / i386 / pci_cfgreg.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $
d7510ae6 29 * $DragonFly: src/sys/bus/pci/i386/pci_cfgreg.c,v 1.15 2008/08/02 05:22:20 dillon Exp $
984263bc
MD
30 *
31 */
32
33#include <sys/param.h> /* XXX trim includes */
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/module.h>
38#include <sys/malloc.h>
bbb83b93 39#include <sys/sysctl.h>
984263bc
MD
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <machine/md_var.h>
2e05c219 43#include <machine/clock.h>
1f2de5d4
MD
44#include <bus/pci/pcivar.h>
45#include <bus/pci/pcireg.h>
46#include <bus/isa/isavar.h>
21ce0dfa 47#include "pci_cfgreg.h"
984263bc
MD
48#include <machine/segments.h>
49#include <machine/pc/bios.h>
984263bc 50#include <machine/smp.h>
984263bc 51
bbca97bc
JS
52#define PRVERB(a) do { \
53 if (bootverbose) \
85f8e2ea 54 kprintf a ; \
bbca97bc
JS
55} while(0)
56
bbb83b93
JS
57static int pci_disable_bios_route = 0;
58SYSCTL_INT(_hw, OID_AUTO, pci_disable_bios_route, CTLFLAG_RD,
59 &pci_disable_bios_route, 0, "disable interrupt routing via PCI-BIOS");
60TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route);
61
984263bc
MD
62static int cfgmech;
63static int devmax;
64
bbca97bc 65static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
984263bc
MD
66static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
67static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
68static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
69static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
70
bbca97bc
JS
71static void pci_print_irqmask(u_int16_t irqs);
72static void pci_print_route_table(struct PIR_table *prt, int size);
984263bc
MD
73static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
74static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
75static int pcireg_cfgopen(void);
76
77static struct PIR_table *pci_route_table;
78static int pci_route_count;
79
bbca97bc
JS
80/*
81 * Some BIOS writers seem to want to ignore the spec and put
82 * 0 in the intline rather than 255 to indicate none. Some use
83 * numbers in the range 128-254 to indicate something strange and
84 * apparently undocumented anywhere. Assume these are completely bogus
85 * and map them to 255, which means "none".
86 */
87static int
d7510ae6 88pci_map_intline(int line)
bbca97bc
JS
89{
90 if (line == 0 || line >= 128)
91 return (PCI_INVALID_IRQ);
92 return (line);
93}
94
984263bc
MD
95static u_int16_t
96pcibios_get_version(void)
97{
bb4722f4 98 struct bios_regs args;
984263bc 99
bbca97bc 100 if (PCIbios.ventry == 0) {
bb4722f4
JS
101 PRVERB(("pcibios: No call entry point\n"));
102 return (0);
103 }
104 args.eax = PCIBIOS_BIOS_PRESENT;
105 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
106 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
107 return (0);
108 }
109 if (args.edx != 0x20494350) {
110 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
111 return (0);
112 }
113 return (args.ebx & 0xffff);
984263bc
MD
114}
115
116/*
117 * Initialise access to PCI configuration space
118 */
119int
120pci_cfgregopen(void)
121{
bb4722f4
JS
122 static int opened = 0;
123 u_long sigaddr;
124 static struct PIR_table *pt;
bbca97bc 125 u_int16_t v;
bb4722f4
JS
126 u_int8_t ck, *cv;
127 int i;
128
129 if (opened)
130 return (1);
131
132 if (pcireg_cfgopen() == 0)
133 return (0);
134
bbca97bc
JS
135 v = pcibios_get_version();
136 if (v > 0)
85f8e2ea 137 kprintf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
bbca97bc
JS
138 v & 0xff);
139
bb4722f4
JS
140 /*
141 * Look for the interrupt routing table.
bbca97bc
JS
142 *
143 * We use PCI BIOS's PIR table if it's available $PIR is the
144 * standard way to do this. Sadly some machines are not
145 * standards conforming and have _PIR instead. We shrug and cope
146 * by looking for both.
bb4722f4 147 */
bbca97bc
JS
148 if (pcibios_get_version() >= 0x0210 && pt == NULL) {
149 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
150 if (sigaddr == 0)
151 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
152 if (sigaddr != 0) {
153 pt = (struct PIR_table *)(uintptr_t)
154 BIOS_PADDRTOVADDR(sigaddr);
155 for (cv = (u_int8_t *)pt, ck = 0, i = 0;
156 i < (pt->pt_header.ph_length); i++)
157 ck += cv[i];
158 if (ck == 0 && pt->pt_header.ph_length >
159 sizeof(struct PIR_header)) {
160 pci_route_table = pt;
161 pci_route_count = (pt->pt_header.ph_length -
162 sizeof(struct PIR_header)) /
163 sizeof(struct PIR_entry);
85f8e2ea 164 kprintf("Using $PIR table, %d entries at %p\n",
bbca97bc
JS
165 pci_route_count, pci_route_table);
166 if (bootverbose)
167 pci_print_route_table(pci_route_table,
168 pci_route_count);
169 }
bb4722f4 170 }
bbca97bc 171 }
bb4722f4 172 opened = 1;
bbca97bc 173 return (1);
984263bc
MD
174}
175
176/*
177 * Read configuration space register
178 */
984263bc
MD
179u_int32_t
180pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
181{
bbca97bc 182 uint32_t line;
984263bc 183#ifdef APIC_IO
bbca97bc
JS
184 uint32_t pin;
185
bb4722f4 186 /*
bbca97bc
JS
187 * If we are using the APIC, the contents of the intline
188 * register will probably be wrong (since they are set up for
189 * use with the PIC. Rather than rewrite these registers
190 * (maybe that would be smarter) we trap attempts to read them
191 * and translate to our private vector numbers.
bb4722f4
JS
192 */
193 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
bb4722f4 194
bbca97bc
JS
195 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
196 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
bb4722f4
JS
197
198 if (pin != 0) {
199 int airq;
200
201 airq = pci_apic_irq(bus, slot, pin);
202 if (airq >= 0) {
203 /* PCI specific entry found in MP table */
204 if (airq != line)
205 undirect_pci_irq(line);
206 return (airq);
207 } else {
208 /*
209 * PCI interrupts might be redirected to the
210 * ISA bus according to some MP tables. Use the
211 * same methods as used by the ISA devices
212 * devices to find the proper IOAPIC int pin.
213 */
214 airq = isa_apic_irq(line);
215 if ((airq >= 0) && (airq != line)) {
216 /* XXX: undirect_pci_irq() ? */
217 undirect_isa_irq(line);
218 return (airq);
219 }
220 }
984263bc 221 }
bb4722f4
JS
222 return (line);
223 }
bbca97bc
JS
224#else
225 /*
226 * Some BIOS writers seem to want to ignore the spec and put
227 * 0 in the intline rather than 255 to indicate none. The rest of
228 * the code uses 255 as an invalid IRQ.
229 */
230 if (reg == PCIR_INTLINE && bytes == 1) {
231 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
d7510ae6 232 return pci_map_intline(line);
bbca97bc 233 }
984263bc 234#endif /* APIC_IO */
bbca97bc 235 return (pcireg_cfgread(bus, slot, func, reg, bytes));
984263bc
MD
236}
237
238/*
239 * Write configuration space register
240 */
241void
242pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
243{
bbca97bc 244 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
984263bc
MD
245}
246
247int
248pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
249{
bb4722f4 250 return (pci_cfgregread(cfg->bus, cfg->slot, cfg->func, reg, bytes));
984263bc
MD
251}
252
253void
254pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
255{
256 pci_cfgregwrite(cfg->bus, cfg->slot, cfg->func, reg, data, bytes);
257}
258
259
260/*
261 * Route a PCI interrupt
984263bc
MD
262 */
263int
bbca97bc 264pci_cfgintr(int bus, int device, int pin, int oldirq)
984263bc 265{
bb4722f4
JS
266 struct PIR_entry *pe;
267 int i, irq;
268 struct bios_regs args;
269 u_int16_t v;
bbca97bc 270
bb4722f4 271 int already = 0;
bbca97bc 272 int errok = 0;
061051cd 273
bb4722f4
JS
274 v = pcibios_get_version();
275 if (v < 0x0210) {
276 PRVERB((
277 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
278 (v & 0xff00) >> 8, v & 0xff));
bbca97bc 279 return (PCI_INVALID_IRQ);
bb4722f4
JS
280 }
281 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
282 (pin < 1) || (pin > 4))
bbca97bc 283 return (PCI_INVALID_IRQ);
984263bc
MD
284
285 /*
bb4722f4 286 * Scan the entry table for a contender
984263bc 287 */
bbca97bc
JS
288 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
289 i++, pe++) {
bb4722f4
JS
290 if ((bus != pe->pe_bus) || (device != pe->pe_device))
291 continue;
984263bc 292
bbca97bc
JS
293 /*
294 * A link of 0 means that this intpin is not connected to
295 * any other device's interrupt pins and is not connected to
296 * any of the Interrupt Router's interrupt pins, so we can't
297 * route it.
298 */
299 if (pe->pe_intpin[pin - 1].link == 0)
300 continue;
301
302 if (pci_cfgintr_valid(pe, pin, oldirq)) {
85f8e2ea 303 kprintf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
bbca97bc
JS
304 device, 'A' + pin - 1, oldirq);
305 return (oldirq);
306 }
307
308 /*
309 * We try to find a linked interrupt, then we look to see
310 * if the interrupt is uniquely routed, then we look for
311 * a virgin interrupt. The virgin interrupt should return
312 * an interrupt we can route, but if that fails, maybe we
313 * should try harder to route a different interrupt.
314 * However, experience has shown that that's rarely the
315 * failure mode we see.
316 */
bb4722f4 317 irq = pci_cfgintr_linked(pe, pin);
bbca97bc 318 if (irq != PCI_INVALID_IRQ)
bb4722f4 319 already = 1;
bbca97bc 320 if (irq == PCI_INVALID_IRQ) {
bb4722f4 321 irq = pci_cfgintr_unique(pe, pin);
bbca97bc
JS
322 if (irq != PCI_INVALID_IRQ)
323 errok = 1;
324 }
325 if (irq == PCI_INVALID_IRQ)
bb4722f4
JS
326 irq = pci_cfgintr_virgin(pe, pin);
327
bbca97bc 328 if (irq == PCI_INVALID_IRQ)
bb4722f4
JS
329 break;
330
bbb83b93
JS
331 if (pci_disable_bios_route != 0)
332 break;
bb4722f4 333 /*
bbca97bc
JS
334 * Ask the BIOS to route the interrupt. If we picked an
335 * interrupt that failed, we should really try other
336 * choices that the BIOS offers us.
337 *
338 * For uniquely routed interrupts, we need to try
339 * to route them on some machines. Yet other machines
340 * fail to route, so we have to pretend that in that
341 * case it worked. Isn't PC hardware fun?
342 *
343 * NOTE: if we want to whack hardware to do this, then
344 * I think the right way to do that would be to have
345 * bridge drivers that do this. I'm not sure that the
346 * $PIR table would be valid for those interrupt
347 * routers.
bb4722f4
JS
348 */
349 args.eax = PCIBIOS_ROUTE_INTERRUPT;
350 args.ebx = (bus << 8) | (device << 3);
bbca97bc
JS
351 /* pin value is 0xa - 0xd */
352 args.ecx = (irq << 8) | (0xa + pin -1);
353 if (!already &&
354 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
355 !errok) {
bb4722f4 356 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
bbca97bc 357 return (PCI_INVALID_IRQ);
bb4722f4 358 }
85f8e2ea 359 kprintf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
bbca97bc 360 device, 'A' + pin - 1, irq);
bb4722f4 361 return(irq);
bbca97bc
JS
362 }
363
ed1bd994
MD
364 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c oldirq=%d\n", bus,
365 device, 'A' + pin - 1, oldirq));
bbca97bc
JS
366 return (PCI_INVALID_IRQ);
367}
368
369/*
370 * Check to see if an existing IRQ setting is valid.
371 */
372static int
373pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
374{
375 uint32_t irqmask;
bb4722f4 376
bbca97bc
JS
377 if (!PCI_INTERRUPT_VALID(irq))
378 return (0);
379 irqmask = pe->pe_intpin[pin - 1].irqs;
380 if (irqmask & (1 << irq)) {
381 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
382 return (1);
383 }
384 return (0);
984263bc
MD
385}
386
387/*
388 * Look to see if the routing table claims this pin is uniquely routed.
389 */
390static int
391pci_cfgintr_unique(struct PIR_entry *pe, int pin)
392{
bbca97bc
JS
393 int irq;
394 uint32_t irqmask;
395
396 irqmask = pe->pe_intpin[pin - 1].irqs;
397 if(irqmask != 0 && powerof2(irqmask)) {
398 irq = ffs(irqmask) - 1;
bb4722f4
JS
399 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
400 return (irq);
401 }
bbca97bc 402 return (PCI_INVALID_IRQ);
984263bc
MD
403}
404
405/*
406 * Look for another device which shares the same link byte and
407 * already has a unique IRQ, or which has had one routed already.
408 */
409static int
410pci_cfgintr_linked(struct PIR_entry *pe, int pin)
411{
bb4722f4
JS
412 struct PIR_entry *oe;
413 struct PIR_intpin *pi;
414 int i, j, irq;
984263bc 415
bb4722f4
JS
416 /*
417 * Scan table slots.
bbca97bc
JS
418 */
419 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
420 i++, oe++) {
bb4722f4
JS
421 /* scan interrupt pins */
422 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
984263bc 423
bbca97bc 424 /* don't look at the entry we're trying to match */
54c778f3 425 if ((pe == oe) && (j == (pin - 1)))
bb4722f4 426 continue;
bb4722f4
JS
427 /* compare link bytes */
428 if (pi->link != pe->pe_intpin[pin - 1].link)
429 continue;
bb4722f4 430 /* link destination mapped to a unique interrupt? */
bbca97bc 431 if (pi->irqs != 0 && powerof2(pi->irqs)) {
bb4722f4
JS
432 irq = ffs(pi->irqs) - 1;
433 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
434 pi->link, irq));
435 return(irq);
bbca97bc
JS
436 }
437
438 /*
439 * look for the real PCI device that matches this
440 * table entry
441 */
442 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
16c751ca 443 j + 1, pin);
bbca97bc
JS
444 if (irq != PCI_INVALID_IRQ)
445 return (irq);
bb4722f4 446 }
984263bc 447 }
bbca97bc 448 return (PCI_INVALID_IRQ);
984263bc
MD
449}
450
451/*
452 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
453 * see if it has already been assigned an interrupt.
454 */
455static int
456pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
457{
bb4722f4
JS
458 devclass_t pci_devclass;
459 device_t *pci_devices;
460 int pci_count;
461 device_t *pci_children;
462 int pci_childcount;
463 device_t *busp, *childp;
464 int i, j, irq;
465
466 /*
467 * Find all the PCI busses.
468 */
469 pci_count = 0;
470 if ((pci_devclass = devclass_find("pci")) != NULL)
471 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
472
473 /*
474 * Scan all the PCI busses/devices looking for this one.
475 */
bbca97bc
JS
476 irq = PCI_INVALID_IRQ;
477 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
478 i++, busp++) {
bb4722f4
JS
479 pci_childcount = 0;
480 device_get_children(*busp, &pci_children, &pci_childcount);
984263bc 481
bbca97bc
JS
482 for (j = 0, childp = pci_children; j < pci_childcount; j++,
483 childp++) {
bb4722f4
JS
484 if ((pci_get_bus(*childp) == bus) &&
485 (pci_get_slot(*childp) == device) &&
486 (pci_get_intpin(*childp) == matchpin)) {
d7510ae6 487 irq = pci_map_intline(pci_get_irq(*childp));
bbca97bc 488 if (irq != PCI_INVALID_IRQ)
bb4722f4 489 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
bbca97bc
JS
490 pe->pe_intpin[pin - 1].link, irq,
491 pci_get_bus(*childp),
492 pci_get_slot(*childp),
493 pci_get_function(*childp)));
bb4722f4
JS
494 break;
495 }
496 }
497 if (pci_children != NULL)
efda3bd0 498 kfree(pci_children, M_TEMP);
984263bc 499 }
bb4722f4 500 if (pci_devices != NULL)
efda3bd0 501 kfree(pci_devices, M_TEMP);
bb4722f4 502 return (irq);
984263bc
MD
503}
504
505/*
506 * Pick a suitable IRQ from those listed as routable to this device.
507 */
508static int
509pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
510{
bb4722f4 511 int irq, ibit;
984263bc 512
bbca97bc
JS
513 /*
514 * first scan the set of PCI-only interrupts and see if any of these
515 * are routable
516 */
bb4722f4
JS
517 for (irq = 0; irq < 16; irq++) {
518 ibit = (1 << irq);
519
520 /* can we use this interrupt? */
521 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
522 (pe->pe_intpin[pin - 1].irqs & ibit)) {
523 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
524 return (irq);
525 }
984263bc 526 }
984263bc 527
bb4722f4
JS
528 /* life is tough, so just pick an interrupt */
529 for (irq = 0; irq < 16; irq++) {
530 ibit = (1 << irq);
984263bc 531
bb4722f4
JS
532 if (pe->pe_intpin[pin - 1].irqs & ibit) {
533 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
534 return (irq);
535 }
984263bc 536 }
bbca97bc
JS
537 return (PCI_INVALID_IRQ);
538}
539
540static void
541pci_print_irqmask(u_int16_t irqs)
542{
543 int i, first;
544
545 if (irqs == 0) {
85f8e2ea 546 kprintf("none");
bbca97bc
JS
547 return;
548 }
549 first = 1;
550 for (i = 0; i < 16; i++, irqs >>= 1)
551 if (irqs & 1) {
552 if (!first)
85f8e2ea 553 kprintf(" ");
bbca97bc
JS
554 else
555 first = 0;
85f8e2ea 556 kprintf("%d", i);
bbca97bc
JS
557 }
558}
559
560/*
561 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
562 */
563static void
564pci_print_route_table(struct PIR_table *ptr, int size)
565{
566 struct PIR_entry *entry;
567 struct PIR_intpin *intpin;
568 int i, pin;
569
85f8e2ea 570 kprintf("PCI-Only Interrupts: ");
bbca97bc 571 pci_print_irqmask(ptr->pt_header.ph_pci_irqs);
85f8e2ea 572 kprintf("\nLocation Bus Device Pin Link IRQs\n");
bbca97bc
JS
573 entry = &ptr->pt_entry[0];
574 for (i = 0; i < size; i++, entry++) {
575 intpin = &entry->pe_intpin[0];
576 for (pin = 0; pin < 4; pin++, intpin++)
577 if (intpin->link != 0) {
578 if (entry->pe_slot == 0)
85f8e2ea 579 kprintf("embedded ");
bbca97bc 580 else
85f8e2ea
SW
581 kprintf("slot %-3d ", entry->pe_slot);
582 kprintf(" %3d %3d %c 0x%02x ",
bbca97bc
JS
583 entry->pe_bus, entry->pe_device,
584 'A' + pin, intpin->link);
585 pci_print_irqmask(intpin->irqs);
85f8e2ea 586 kprintf("\n");
bbca97bc
JS
587 }
588 }
589}
590
591/*
592 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
593 * even bother looking if the BIOS doesn't support routing anyways.
594 */
595int
596pci_probe_route_table(int bus)
597{
598 int i;
599 u_int16_t v;
600
601 v = pcibios_get_version();
602 if (v < 0x0210)
603 return (0);
604 for (i = 0; i < pci_route_count; i++)
605 if (pci_route_table->pt_entry[i].pe_bus == bus)
606 return (1);
607 return (0);
984263bc
MD
608}
609
610/*
611 * Configuration space access using direct register operations
612 */
613
614/* enable configuration space accesses and return data port address */
615static int
616pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
617{
bb4722f4
JS
618 int dataport = 0;
619
620 if (bus <= PCI_BUSMAX
621 && slot < devmax
622 && func <= PCI_FUNCMAX
623 && reg <= PCI_REGMAX
624 && bytes != 3
625 && (unsigned) bytes <= 4
bbca97bc 626 && (reg & (bytes - 1)) == 0) {
bb4722f4
JS
627 switch (cfgmech) {
628 case 1:
629 outl(CONF1_ADDR_PORT, (1 << 31)
630 | (bus << 16) | (slot << 11)
631 | (func << 8) | (reg & ~0x03));
632 dataport = CONF1_DATA_PORT + (reg & 0x03);
633 break;
634 case 2:
635 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
636 outb(CONF2_FORWARD_PORT, bus);
637 dataport = 0xc000 | (slot << 8) | reg;
638 break;
639 }
984263bc 640 }
bb4722f4 641 return (dataport);
984263bc
MD
642}
643
644/* disable configuration space accesses */
645static void
646pci_cfgdisable(void)
647{
bb4722f4
JS
648 switch (cfgmech) {
649 case 1:
650 outl(CONF1_ADDR_PORT, 0);
651 break;
652 case 2:
653 outb(CONF2_ENABLE_PORT, 0);
654 outb(CONF2_FORWARD_PORT, 0);
655 break;
656 }
984263bc
MD
657}
658
659static int
660pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
661{
bb4722f4
JS
662 int data = -1;
663 int port;
664
665 port = pci_cfgenable(bus, slot, func, reg, bytes);
bb4722f4
JS
666 if (port != 0) {
667 switch (bytes) {
668 case 1:
669 data = inb(port);
670 break;
671 case 2:
672 data = inw(port);
673 break;
674 case 4:
675 data = inl(port);
676 break;
677 }
678 pci_cfgdisable();
984263bc 679 }
bb4722f4 680 return (data);
984263bc
MD
681}
682
683static void
684pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
685{
bb4722f4
JS
686 int port;
687
688 port = pci_cfgenable(bus, slot, func, reg, bytes);
689 if (port != 0) {
690 switch (bytes) {
691 case 1:
692 outb(port, data);
693 break;
694 case 2:
695 outw(port, data);
696 break;
697 case 4:
698 outl(port, data);
699 break;
700 }
701 pci_cfgdisable();
984263bc 702 }
984263bc
MD
703}
704
705/* check whether the configuration mechanism has been correctly identified */
706static int
707pci_cfgcheck(int maxdev)
708{
bbca97bc
JS
709 uint32_t id, class;
710 uint8_t header;
711 uint8_t device;
712 int port;
984263bc 713
984263bc 714 if (bootverbose)
85f8e2ea 715 kprintf("pci_cfgcheck:\tdevice ");
bb4722f4
JS
716
717 for (device = 0; device < maxdev; device++) {
bb4722f4 718 if (bootverbose)
85f8e2ea 719 kprintf("%d ", device);
bb4722f4 720
bbca97bc
JS
721 port = pci_cfgenable(0, device, 0, 0, 4);
722 id = inl(port);
723 if (id == 0 || id == 0xffffffff)
bb4722f4
JS
724 continue;
725
bbca97bc
JS
726 port = pci_cfgenable(0, device, 0, 8, 4);
727 class = inl(port) >> 8;
bb4722f4 728 if (bootverbose)
85f8e2ea 729 kprintf("[class=%06x] ", class);
bb4722f4
JS
730 if (class == 0 || (class & 0xf870ff) != 0)
731 continue;
732
bbca97bc
JS
733 port = pci_cfgenable(0, device, 0, 14, 1);
734 header = inb(port);
735 if (bootverbose)
85f8e2ea 736 kprintf("[hdr=%02x] ", header);
bb4722f4
JS
737 if ((header & 0x7e) != 0)
738 continue;
739
740 if (bootverbose)
85f8e2ea 741 kprintf("is there (id=%08x)\n", id);
bb4722f4
JS
742
743 pci_cfgdisable();
744 return (1);
745 }
984263bc 746 if (bootverbose)
85f8e2ea 747 kprintf("-- nothing found\n");
984263bc
MD
748
749 pci_cfgdisable();
bb4722f4 750 return (0);
984263bc
MD
751}
752
753static int
754pcireg_cfgopen(void)
755{
bbca97bc
JS
756 uint32_t mode1res,oldval1;
757 uint8_t mode2res,oldval2;
984263bc 758
bb4722f4 759 oldval1 = inl(CONF1_ADDR_PORT);
984263bc 760
bb4722f4 761 if (bootverbose) {
85f8e2ea 762 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
bb4722f4
JS
763 oldval1);
764 }
984263bc 765
bb4722f4 766 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
984263bc 767
bb4722f4
JS
768 cfgmech = 1;
769 devmax = 32;
984263bc 770
bb4722f4 771 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
2e05c219 772 DELAY(1);
bb4722f4
JS
773 mode1res = inl(CONF1_ADDR_PORT);
774 outl(CONF1_ADDR_PORT, oldval1);
984263bc 775
bb4722f4 776 if (bootverbose)
85f8e2ea 777 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
bbca97bc 778 mode1res, CONF1_ENABLE_CHK);
984263bc 779
bb4722f4
JS
780 if (mode1res) {
781 if (pci_cfgcheck(32))
782 return (cfgmech);
783 }
984263bc 784
bb4722f4
JS
785 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
786 mode1res = inl(CONF1_ADDR_PORT);
787 outl(CONF1_ADDR_PORT, oldval1);
984263bc 788
bb4722f4 789 if (bootverbose)
85f8e2ea 790 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
bbca97bc 791 mode1res, CONF1_ENABLE_CHK1);
984263bc 792
bb4722f4
JS
793 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
794 if (pci_cfgcheck(32))
795 return (cfgmech);
796 }
984263bc 797 }
984263bc 798
bb4722f4 799 oldval2 = inb(CONF2_ENABLE_PORT);
984263bc 800
bb4722f4 801 if (bootverbose) {
85f8e2ea 802 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
bb4722f4
JS
803 oldval2);
804 }
984263bc 805
bb4722f4 806 if ((oldval2 & 0xf0) == 0) {
984263bc 807
bb4722f4
JS
808 cfgmech = 2;
809 devmax = 16;
984263bc 810
bb4722f4
JS
811 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
812 mode2res = inb(CONF2_ENABLE_PORT);
813 outb(CONF2_ENABLE_PORT, oldval2);
984263bc 814
bb4722f4 815 if (bootverbose)
85f8e2ea 816 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
bb4722f4 817 mode2res, CONF2_ENABLE_CHK);
984263bc 818
bb4722f4
JS
819 if (mode2res == CONF2_ENABLE_RES) {
820 if (bootverbose)
85f8e2ea 821 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
984263bc 822
bb4722f4
JS
823 if (pci_cfgcheck(16))
824 return (cfgmech);
825 }
984263bc 826 }
984263bc 827
bb4722f4
JS
828 cfgmech = 0;
829 devmax = 0;
830 return (cfgmech);
984263bc 831}