Say hello to a sound system update from FreeBSD. This includes the long
[dragonfly.git] / sys / dev / sound / isa / mss.c
CommitLineData
558a398b 1/*-
984263bc 2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
558a398b 3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
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4 * Copyright Luigi Rizzo, 1997,1998
5 * Copyright by Hannu Savolainen 1994, 1995
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
1de703da 28 *
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29 * $FreeBSD: src/sys/dev/sound/isa/mss.c,v 1.95.2.3 2006/04/04 17:30:59 ariff Exp $
30 * $DragonFly: src/sys/dev/sound/isa/mss.c,v 1.10 2007/01/04 21:47:02 corecode Exp $
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31 */
32
33#include <dev/sound/pcm/sound.h>
34
558a398b 35SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/isa/mss.c,v 1.10 2007/01/04 21:47:02 corecode Exp $");
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36
37/* board-specific include files */
38#include <dev/sound/isa/mss.h>
39#include <dev/sound/isa/sb.h>
40#include <dev/sound/chip.h>
41
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42#include <bus/isa/isavar.h>
43
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44#include "mixer_if.h"
45
46#define MSS_DEFAULT_BUFSZ (4096)
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47#define MSS_INDEXED_REGS 0x20
48#define OPL_INDEXED_REGS 0x19
49
50struct mss_info;
51
52struct mss_chinfo {
53 struct mss_info *parent;
54 struct pcm_channel *channel;
55 struct snd_dbuf *buffer;
56 int dir;
57 u_int32_t fmt, blksz;
58};
59
60struct mss_info {
61 struct resource *io_base; /* primary I/O address for the board */
62 int io_rid;
63 struct resource *conf_base; /* and the opti931 also has a config space */
64 int conf_rid;
65 struct resource *irq;
66 int irq_rid;
67 struct resource *drq1; /* play */
68 int drq1_rid;
69 struct resource *drq2; /* rec */
70 int drq2_rid;
71 void *ih;
72 bus_dma_tag_t parent_dmat;
558a398b 73 struct spinlock *lock;
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74
75 char mss_indexed_regs[MSS_INDEXED_REGS];
76 char opl_indexed_regs[OPL_INDEXED_REGS];
77 int bd_id; /* used to hold board-id info, eg. sb version,
78 * mss codec type, etc. etc.
79 */
80 int opti_offset; /* offset from config_base for opti931 */
81 u_long bd_flags; /* board-specific flags */
82 int optibase; /* base address for OPTi9xx config */
83 struct resource *indir; /* Indirect register index address */
84 int indir_rid;
85 int password; /* password for opti9xx cards */
86 int passwdreg; /* password register */
87 unsigned int bufsize;
88 struct mss_chinfo pch, rch;
89};
90
91static int mss_probe(device_t dev);
92static int mss_attach(device_t dev);
93
94static driver_intr_t mss_intr;
95
96/* prototypes for local functions */
97static int mss_detect(device_t dev, struct mss_info *mss);
558a398b 98#ifndef PC98
984263bc 99static int opti_detect(device_t dev, struct mss_info *mss);
558a398b 100#endif
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101static char *ymf_test(device_t dev, struct mss_info *mss);
102static void ad_unmute(struct mss_info *mss);
103
104/* mixer set funcs */
105static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
106static int mss_set_recsrc(struct mss_info *mss, int mask);
107
108/* io funcs */
109static int ad_wait_init(struct mss_info *mss, int x);
110static int ad_read(struct mss_info *mss, int reg);
111static void ad_write(struct mss_info *mss, int reg, u_char data);
112static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
113static void ad_enter_MCE(struct mss_info *mss);
114static void ad_leave_MCE(struct mss_info *mss);
115
116/* OPTi-specific functions */
117static void opti_write(struct mss_info *mss, u_char reg,
118 u_char data);
558a398b 119#ifndef PC98
984263bc 120static u_char opti_read(struct mss_info *mss, u_char reg);
558a398b 121#endif
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122static int opti_init(device_t dev, struct mss_info *mss);
123
124/* io primitives */
125static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
126static u_char conf_rd(struct mss_info *mss, u_char reg);
127
128static int pnpmss_probe(device_t dev);
129static int pnpmss_attach(device_t dev);
130
131static driver_intr_t opti931_intr;
132
133static u_int32_t mss_fmt[] = {
134 AFMT_U8,
135 AFMT_STEREO | AFMT_U8,
136 AFMT_S16_LE,
137 AFMT_STEREO | AFMT_S16_LE,
138 AFMT_MU_LAW,
139 AFMT_STEREO | AFMT_MU_LAW,
140 AFMT_A_LAW,
141 AFMT_STEREO | AFMT_A_LAW,
142 0
143};
144static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
145
146static u_int32_t guspnp_fmt[] = {
147 AFMT_U8,
148 AFMT_STEREO | AFMT_U8,
149 AFMT_S16_LE,
150 AFMT_STEREO | AFMT_S16_LE,
151 AFMT_A_LAW,
152 AFMT_STEREO | AFMT_A_LAW,
153 0
154};
155static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
156
157static u_int32_t opti931_fmt[] = {
158 AFMT_U8,
159 AFMT_STEREO | AFMT_U8,
160 AFMT_S16_LE,
161 AFMT_STEREO | AFMT_S16_LE,
162 0
163};
164static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
165
166#define MD_AD1848 0x91
167#define MD_AD1845 0x92
168#define MD_CS42XX 0xA1
558a398b 169#define MD_CS423X 0xA2
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170#define MD_OPTI930 0xB0
171#define MD_OPTI931 0xB1
172#define MD_OPTI925 0xB2
173#define MD_OPTI924 0xB3
174#define MD_GUSPNP 0xB8
175#define MD_GUSMAX 0xB9
176#define MD_YM0020 0xC1
177#define MD_VIVO 0xD1
178
179#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
180
181#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
182
183static void
184mss_lock(struct mss_info *mss)
185{
186 snd_mtxlock(mss->lock);
187}
188
189static void
190mss_unlock(struct mss_info *mss)
191{
192 snd_mtxunlock(mss->lock);
193}
194
195static int
196port_rd(struct resource *port, int off)
197{
198 if (port)
199 return bus_space_read_1(rman_get_bustag(port),
200 rman_get_bushandle(port),
201 off);
202 else
203 return -1;
204}
205
206static void
207port_wr(struct resource *port, int off, u_int8_t data)
208{
209 if (port)
210 bus_space_write_1(rman_get_bustag(port),
211 rman_get_bushandle(port),
212 off, data);
213}
214
215static int
216io_rd(struct mss_info *mss, int reg)
217{
218 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
219 return port_rd(mss->io_base, reg);
220}
221
222static void
223io_wr(struct mss_info *mss, int reg, u_int8_t data)
224{
225 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
226 port_wr(mss->io_base, reg, data);
227}
228
229static void
230conf_wr(struct mss_info *mss, u_char reg, u_char value)
231{
232 port_wr(mss->conf_base, 0, reg);
233 port_wr(mss->conf_base, 1, value);
234}
235
236static u_char
237conf_rd(struct mss_info *mss, u_char reg)
238{
239 port_wr(mss->conf_base, 0, reg);
240 return port_rd(mss->conf_base, 1);
241}
242
243static void
244opti_wr(struct mss_info *mss, u_char reg, u_char value)
245{
246 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
247 port_wr(mss->conf_base, mss->opti_offset + 1, value);
248}
249
250static u_char
251opti_rd(struct mss_info *mss, u_char reg)
252{
253 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
254 return port_rd(mss->conf_base, mss->opti_offset + 1);
255}
256
257static void
258gus_wr(struct mss_info *mss, u_char reg, u_char value)
259{
260 port_wr(mss->conf_base, 3, reg);
261 port_wr(mss->conf_base, 5, value);
262}
263
264static u_char
265gus_rd(struct mss_info *mss, u_char reg)
266{
267 port_wr(mss->conf_base, 3, reg);
268 return port_rd(mss->conf_base, 5);
269}
270
271static void
272mss_release_resources(struct mss_info *mss, device_t dev)
273{
274 if (mss->irq) {
275 if (mss->ih)
276 bus_teardown_intr(dev, mss->irq, mss->ih);
277 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
278 mss->irq);
279 mss->irq = 0;
280 }
281 if (mss->drq2) {
282 if (mss->drq2 != mss->drq1) {
283 isa_dma_release(rman_get_start(mss->drq2));
284 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
285 mss->drq2);
286 }
287 mss->drq2 = 0;
288 }
289 if (mss->drq1) {
290 isa_dma_release(rman_get_start(mss->drq1));
291 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
292 mss->drq1);
293 mss->drq1 = 0;
294 }
295 if (mss->io_base) {
296 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
297 mss->io_base);
298 mss->io_base = 0;
299 }
300 if (mss->conf_base) {
301 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
302 mss->conf_base);
303 mss->conf_base = 0;
304 }
305 if (mss->indir) {
306 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
307 mss->indir);
308 mss->indir = 0;
309 }
310 if (mss->parent_dmat) {
311 bus_dma_tag_destroy(mss->parent_dmat);
312 mss->parent_dmat = 0;
313 }
314 if (mss->lock) snd_mtxfree(mss->lock);
315
efda3bd0 316 kfree(mss, M_DEVBUF);
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317}
318
319static int
320mss_alloc_resources(struct mss_info *mss, device_t dev)
321{
322 int pdma, rdma, ok = 1;
323 if (!mss->io_base)
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324 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
325 &mss->io_rid, RF_ACTIVE);
984263bc 326 if (!mss->irq)
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327 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
328 &mss->irq_rid, RF_ACTIVE);
984263bc 329 if (!mss->drq1)
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330 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
331 &mss->drq1_rid,
332 RF_ACTIVE);
984263bc 333 if (mss->conf_rid >= 0 && !mss->conf_base)
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334 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
335 &mss->conf_rid,
336 RF_ACTIVE);
984263bc 337 if (mss->drq2_rid >= 0 && !mss->drq2)
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338 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
339 &mss->drq2_rid,
340 RF_ACTIVE);
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341
342 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
343 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
344 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
345
346 if (ok) {
347 pdma = rman_get_start(mss->drq1);
348 isa_dma_acquire(pdma);
349 isa_dmainit(pdma, mss->bufsize);
350 mss->bd_flags &= ~BD_F_DUPLEX;
351 if (mss->drq2) {
352 rdma = rman_get_start(mss->drq2);
353 isa_dma_acquire(rdma);
354 isa_dmainit(rdma, mss->bufsize);
355 mss->bd_flags |= BD_F_DUPLEX;
356 } else mss->drq2 = mss->drq1;
357 }
358 return ok;
359}
360
361/*
362 * The various mixers use a variety of bitmasks etc. The Voxware
363 * driver had a very nice technique to describe a mixer and interface
364 * to it. A table defines, for each channel, which register, bits,
365 * offset, polarity to use. This procedure creates the new value
366 * using the table and the old value.
367 */
368
369static void
370change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
371{
372 u_char mask;
373 int shift;
374
e3869ec7 375 DEB(kprintf("ch_bits dev %d ch %d val %d old 0x%02x "
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376 "r %d p %d bit %d off %d\n",
377 dev, chn, newval, *regval,
378 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
379 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
380
381 if ( (*t)[dev][chn].polarity == 1) /* reverse */
382 newval = 100 - newval ;
383
384 mask = (1 << (*t)[dev][chn].nbits) - 1;
385 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
386 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
387
388 *regval &= ~(mask << shift); /* Filter out the previous value */
389 *regval |= (newval & mask) << shift; /* Set the new value */
390}
391
392/* -------------------------------------------------------------------- */
393/* only one source can be set... */
394static int
395mss_set_recsrc(struct mss_info *mss, int mask)
396{
397 u_char recdev;
398
399 switch (mask) {
400 case SOUND_MASK_LINE:
401 case SOUND_MASK_LINE3:
402 recdev = 0;
403 break;
404
405 case SOUND_MASK_CD:
406 case SOUND_MASK_LINE1:
407 recdev = 0x40;
408 break;
409
410 case SOUND_MASK_IMIX:
411 recdev = 0xc0;
412 break;
413
414 case SOUND_MASK_MIC:
415 default:
416 mask = SOUND_MASK_MIC;
417 recdev = 0x80;
418 }
419 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
420 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
421 return mask;
422}
423
424/* there are differences in the mixer depending on the actual sound card. */
425static int
426mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
427{
428 int regoffs;
429 mixer_tab *mix_d;
430 u_char old, val;
431
432 switch (mss->bd_id) {
433 case MD_OPTI931:
434 mix_d = &opti931_devices;
435 break;
436 case MD_OPTI930:
437 mix_d = &opti930_devices;
438 break;
439 default:
440 mix_d = &mix_devices;
441 }
442
443 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
e3869ec7 444 DEB(kprintf("nbits = 0 for dev %d\n", dev));
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445 return -1;
446 }
447
448 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
449
450 /* Set the left channel */
451
452 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
453 old = val = ad_read(mss, regoffs);
454 /* if volume is 0, mute chan. Otherwise, unmute. */
455 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
456 change_bits(mix_d, &val, dev, LEFT_CHN, left);
457 ad_write(mss, regoffs, val);
458
e3869ec7 459 DEB(kprintf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
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460 dev, regoffs, old, val));
461
462 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
463 /* Set the right channel */
464 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
465 old = val = ad_read(mss, regoffs);
466 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
467 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
468 ad_write(mss, regoffs, val);
469
e3869ec7 470 DEB(kprintf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
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471 dev, regoffs, old, val));
472 }
473 return 0; /* success */
474}
475
476/* -------------------------------------------------------------------- */
477
478static int
479mssmix_init(struct snd_mixer *m)
480{
481 struct mss_info *mss = mix_getdevinfo(m);
482
483 mix_setdevs(m, MODE2_MIXER_DEVICES);
484 mix_setrecdevs(m, MSS_REC_DEVICES);
485 switch(mss->bd_id) {
486 case MD_OPTI930:
487 mix_setdevs(m, OPTI930_MIXER_DEVICES);
488 break;
489
490 case MD_OPTI931:
491 mix_setdevs(m, OPTI931_MIXER_DEVICES);
492 mss_lock(mss);
493 ad_write(mss, 20, 0x88);
494 ad_write(mss, 21, 0x88);
495 mss_unlock(mss);
496 break;
497
498 case MD_AD1848:
499 mix_setdevs(m, MODE1_MIXER_DEVICES);
500 break;
501
502 case MD_GUSPNP:
503 case MD_GUSMAX:
504 /* this is only necessary in mode 3 ... */
505 mss_lock(mss);
506 ad_write(mss, 22, 0x88);
507 ad_write(mss, 23, 0x88);
508 mss_unlock(mss);
509 break;
510 }
511 return 0;
512}
513
514static int
515mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
516{
517 struct mss_info *mss = mix_getdevinfo(m);
518
519 mss_lock(mss);
520 mss_mixer_set(mss, dev, left, right);
521 mss_unlock(mss);
522
523 return left | (right << 8);
524}
525
526static int
527mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
528{
529 struct mss_info *mss = mix_getdevinfo(m);
530
531 mss_lock(mss);
532 src = mss_set_recsrc(mss, src);
533 mss_unlock(mss);
534 return src;
535}
536
537static kobj_method_t mssmix_mixer_methods[] = {
538 KOBJMETHOD(mixer_init, mssmix_init),
539 KOBJMETHOD(mixer_set, mssmix_set),
540 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
541 { 0, 0 }
542};
543MIXER_DECLARE(mssmix_mixer);
544
545/* -------------------------------------------------------------------- */
546
547static int
548ymmix_init(struct snd_mixer *m)
549{
550 struct mss_info *mss = mix_getdevinfo(m);
551
552 mssmix_init(m);
553 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
554 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
555 /* Set master volume */
556 mss_lock(mss);
557 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
558 conf_wr(mss, OPL3SAx_VOLUMER, 7);
559 mss_unlock(mss);
560
561 return 0;
562}
563
564static int
565ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
566{
567 struct mss_info *mss = mix_getdevinfo(m);
568 int t, l, r;
569
570 mss_lock(mss);
571 switch (dev) {
572 case SOUND_MIXER_VOLUME:
573 if (left) t = 15 - (left * 15) / 100;
574 else t = 0x80; /* mute */
575 conf_wr(mss, OPL3SAx_VOLUMEL, t);
576 if (right) t = 15 - (right * 15) / 100;
577 else t = 0x80; /* mute */
578 conf_wr(mss, OPL3SAx_VOLUMER, t);
579 break;
580
581 case SOUND_MIXER_MIC:
582 t = left;
583 if (left) t = 31 - (left * 31) / 100;
584 else t = 0x80; /* mute */
585 conf_wr(mss, OPL3SAx_MIC, t);
586 break;
587
588 case SOUND_MIXER_BASS:
589 l = (left * 7) / 100;
590 r = (right * 7) / 100;
591 t = (r << 4) | l;
592 conf_wr(mss, OPL3SAx_BASS, t);
593 break;
594
595 case SOUND_MIXER_TREBLE:
596 l = (left * 7) / 100;
597 r = (right * 7) / 100;
598 t = (r << 4) | l;
599 conf_wr(mss, OPL3SAx_TREBLE, t);
600 break;
601
602 default:
603 mss_mixer_set(mss, dev, left, right);
604 }
605 mss_unlock(mss);
606
607 return left | (right << 8);
608}
609
610static int
611ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
612{
613 struct mss_info *mss = mix_getdevinfo(m);
614 mss_lock(mss);
615 src = mss_set_recsrc(mss, src);
616 mss_unlock(mss);
617 return src;
618}
619
620static kobj_method_t ymmix_mixer_methods[] = {
621 KOBJMETHOD(mixer_init, ymmix_init),
622 KOBJMETHOD(mixer_set, ymmix_set),
623 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
624 { 0, 0 }
625};
626MIXER_DECLARE(ymmix_mixer);
627
628/* -------------------------------------------------------------------- */
629/*
630 * XXX This might be better off in the gusc driver.
631 */
632static void
633gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
634{
635 static const unsigned char irq_bits[16] = {
636 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
637 };
638 static const unsigned char dma_bits[8] = {
639 0, 1, 0, 2, 0, 3, 4, 5
640 };
641 device_t parent = device_get_parent(dev);
642 unsigned char irqctl, dmactl;
984263bc 643
b6d92ffb 644 crit_enter();
984263bc
MD
645
646 port_wr(alt, 0x0f, 0x05);
647 port_wr(alt, 0x00, 0x0c);
648 port_wr(alt, 0x0b, 0x00);
649
650 port_wr(alt, 0x0f, 0x00);
651
652 irqctl = irq_bits[isa_get_irq(parent)];
653 /* Share the IRQ with the MIDI driver. */
654 irqctl |= 0x40;
655 dmactl = dma_bits[isa_get_drq(parent)];
656 if (device_get_flags(parent) & DV_F_DUAL_DMA)
657 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
658 << 3;
659
660 /*
661 * Set the DMA and IRQ control latches.
662 */
663 port_wr(alt, 0x00, 0x0c);
664 port_wr(alt, 0x0b, dmactl | 0x80);
665 port_wr(alt, 0x00, 0x4c);
666 port_wr(alt, 0x0b, irqctl);
667
668 port_wr(alt, 0x00, 0x0c);
669 port_wr(alt, 0x0b, dmactl);
670 port_wr(alt, 0x00, 0x4c);
671 port_wr(alt, 0x0b, irqctl);
672
673 port_wr(mss->conf_base, 2, 0);
674 port_wr(alt, 0x00, 0x0c);
675 port_wr(mss->conf_base, 2, 0);
676
b6d92ffb 677 crit_exit();
984263bc
MD
678}
679
680static int
681mss_init(struct mss_info *mss, device_t dev)
682{
683 u_char r6, r9;
684 struct resource *alt;
685 int rid, tmp;
686
687 mss->bd_flags |= BD_F_MCE_BIT;
688 switch(mss->bd_id) {
689 case MD_OPTI931:
690 /*
691 * The MED3931 v.1.0 allocates 3 bytes for the config
692 * space, whereas v.2.0 allocates 4 bytes. What I know
693 * for sure is that the upper two ports must be used,
694 * and they should end on a boundary of 4 bytes. So I
695 * need the following trick.
696 */
697 mss->opti_offset =
698 (rman_get_start(mss->conf_base) & ~3) + 2
699 - rman_get_start(mss->conf_base);
e3869ec7 700 BVDDB(kprintf("mss_init: opti_offset=%d\n", mss->opti_offset));
984263bc
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701 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
702 ad_write(mss, 10, 2); /* enable interrupts */
703 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
704 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
705 break;
706
707 case MD_GUSPNP:
708 case MD_GUSMAX:
709 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
710 DELAY(1000 * 30);
711 /* release reset and enable DAC */
712 gus_wr(mss, 0x4c /* _URSTI */, 3);
713 DELAY(1000 * 30);
714 /* end of reset */
715
716 rid = 0;
558a398b
SS
717 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
718 RF_ACTIVE);
984263bc 719 if (alt == NULL) {
e3869ec7 720 kprintf("XXX couldn't init GUS PnP/MAX\n");
984263bc
MD
721 break;
722 }
723 port_wr(alt, 0, 0xC); /* enable int and dma */
724 if (mss->bd_id == MD_GUSMAX)
725 gusmax_setup(mss, dev, alt);
726 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
727
728 /*
729 * unmute left & right line. Need to go in mode3, unmute,
730 * and back to mode 2
731 */
732 tmp = ad_read(mss, 0x0c);
733 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
734 ad_write(mss, 0x19, 0); /* unmute left */
735 ad_write(mss, 0x1b, 0); /* unmute right */
736 ad_write(mss, 0x0c, tmp); /* restore old mode */
737
738 /* send codec interrupts on irq1 and only use that one */
739 gus_wr(mss, 0x5a, 0x4f);
740
741 /* enable access to hidden regs */
742 tmp = gus_rd(mss, 0x5b /* IVERI */);
743 gus_wr(mss, 0x5b, tmp | 1);
e3869ec7 744 BVDDB(kprintf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
984263bc
MD
745 break;
746
747 case MD_YM0020:
748 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
749 r6 = conf_rd(mss, OPL3SAx_DMACONF);
750 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
e3869ec7 751 BVDDB(kprintf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
984263bc
MD
752 /* yamaha - set volume to max */
753 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
754 conf_wr(mss, OPL3SAx_VOLUMER, 0);
755 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
756 break;
757 }
758 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
759 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
760 ad_enter_MCE(mss);
761 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
762 ad_leave_MCE(mss);
763 ad_write(mss, 10, 2); /* int enable */
764 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
765 /* the following seem required on the CS4232 */
766 ad_unmute(mss);
767 return 0;
768}
769
770
771/*
772 * main irq handler for the CS423x. The OPTi931 code is
773 * a separate one.
774 * The correct way to operate for a device with multiple internal
775 * interrupt sources is to loop on the status register and ack
776 * interrupts until all interrupts are served and none are reported. At
777 * this point the IRQ line to the ISA IRQ controller should go low
778 * and be raised at the next interrupt.
779 *
780 * Since the ISA IRQ controller is sent EOI _before_ passing control
781 * to the isr, it might happen that we serve an interrupt early, in
782 * which case the status register at the next interrupt should just
783 * say that there are no more interrupts...
784 */
785
786static void
787mss_intr(void *arg)
788{
789 struct mss_info *mss = arg;
790 u_char c = 0, served = 0;
791 int i;
792
e3869ec7 793 DEB(kprintf("mss_intr\n"));
984263bc
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794 mss_lock(mss);
795 ad_read(mss, 11); /* fake read of status bits */
796
797 /* loop until there are interrupts, but no more than 10 times. */
798 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
799 /* get exact reason for full-duplex boards */
800 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
801 c &= ~served;
802 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
803 served |= 0x10;
558a398b 804 mss_unlock(mss);
984263bc 805 chn_intr(mss->pch.channel);
558a398b 806 mss_lock(mss);
984263bc
MD
807 }
808 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
809 served |= 0x20;
558a398b 810 mss_unlock(mss);
984263bc 811 chn_intr(mss->rch.channel);
558a398b 812 mss_lock(mss);
984263bc
MD
813 }
814 /* now ack the interrupt */
815 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
816 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
817 }
818 if (i == 10) {
e3869ec7 819 BVDDB(kprintf("mss_intr: irq, but not from mss\n"));
984263bc 820 } else if (served == 0) {
e3869ec7 821 BVDDB(kprintf("mss_intr: unexpected irq with reason %x\n", c));
984263bc
MD
822 /*
823 * this should not happen... I have no idea what to do now.
824 * maybe should do a sanity check and restart dmas ?
825 */
826 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
827 }
828 mss_unlock(mss);
829}
830
831/*
832 * AD_WAIT_INIT waits if we are initializing the board and
833 * we cannot modify its settings
834 */
835static int
836ad_wait_init(struct mss_info *mss, int x)
837{
838 int arg = x, n = 0; /* to shut up the compiler... */
839 for (; x > 0; x--)
840 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
841 else return n;
e3869ec7 842 kprintf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
984263bc
MD
843 return n;
844}
845
846static int
847ad_read(struct mss_info *mss, int reg)
848{
849 int x;
850
851 ad_wait_init(mss, 201000);
852 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
853 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
854 x = io_rd(mss, MSS_IDATA);
e3869ec7 855 /* kprintf("ad_read %d, %x\n", reg, x); */
984263bc
MD
856 return x;
857}
858
859static void
860ad_write(struct mss_info *mss, int reg, u_char data)
861{
862 int x;
863
e3869ec7 864 /* kprintf("ad_write %d, %x\n", reg, data); */
984263bc
MD
865 ad_wait_init(mss, 1002000);
866 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
867 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
868 io_wr(mss, MSS_IDATA, data);
869}
870
871static void
872ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
873{
874 ad_write(mss, reg+1, cnt & 0xff);
875 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
876}
877
878static void
879wait_for_calibration(struct mss_info *mss)
880{
881 int t;
882
883 /*
884 * Wait until the auto calibration process has finished.
885 *
886 * 1) Wait until the chip becomes ready (reads don't return 0x80).
887 * 2) Wait until the ACI bit of I11 gets on
888 * 3) Wait until the ACI bit of I11 gets off
889 */
890
891 t = ad_wait_init(mss, 1000000);
e3869ec7 892 if (t & MSS_IDXBUSY) kprintf("mss: Auto calibration timed out(1).\n");
984263bc
MD
893
894 /*
895 * The calibration mode for chips that support it is set so that
896 * we never see ACI go on.
897 */
898 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
899 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
900 } else {
901 /*
902 * XXX This should only be enabled for cards that *really*
903 * need it. Are there any?
904 */
905 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
906 }
907 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
908}
909
910static void
911ad_unmute(struct mss_info *mss)
912{
913 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
914 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
915}
916
917static void
918ad_enter_MCE(struct mss_info *mss)
919{
920 int prev;
921
922 mss->bd_flags |= BD_F_MCE_BIT;
923 ad_wait_init(mss, 203000);
924 prev = io_rd(mss, MSS_INDEX);
925 prev &= ~MSS_TRD;
926 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
927}
928
929static void
930ad_leave_MCE(struct mss_info *mss)
931{
932 u_char prev;
933
934 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
e3869ec7 935 DEB(kprintf("--- hey, leave_MCE: MCE bit was not set!\n"));
984263bc
MD
936 return;
937 }
938
939 ad_wait_init(mss, 1000000);
940
941 mss->bd_flags &= ~BD_F_MCE_BIT;
942
943 prev = io_rd(mss, MSS_INDEX);
944 prev &= ~MSS_TRD;
945 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
946 wait_for_calibration(mss);
947}
948
949static int
950mss_speed(struct mss_chinfo *ch, int speed)
951{
952 struct mss_info *mss = ch->parent;
953 /*
954 * In the CS4231, the low 4 bits of I8 are used to hold the
955 * sample rate. Only a fixed number of values is allowed. This
956 * table lists them. The speed-setting routines scans the table
957 * looking for the closest match. This is the only supported method.
958 *
959 * In the CS4236, there is an alternate metod (which we do not
960 * support yet) which provides almost arbitrary frequency setting.
961 * In the AD1845, it looks like the sample rate can be
962 * almost arbitrary, and written directly to a register.
963 * In the OPTi931, there is a SB command which provides for
964 * almost arbitrary frequency setting.
965 *
966 */
967 ad_enter_MCE(mss);
968 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
969 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
970 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
971 /* XXX must also do something in I27 for the ad1845 */
972 } else {
973 int i, sel = 0; /* assume entry 0 does not contain -1 */
974 static int speeds[] =
975 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
976 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
977
558a398b 978#define abs(i) (i < 0 ? -i : i)
984263bc
MD
979 for (i = 1; i < 16; i++)
980 if (speeds[i] > 0 &&
981 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
558a398b 982#undef abs
984263bc
MD
983 speed = speeds[sel];
984 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
558a398b 985 ad_wait_init(mss, 10000);
984263bc
MD
986 }
987 ad_leave_MCE(mss);
988
989 return speed;
990}
991
992/*
993 * mss_format checks that the format is supported (or defaults to AFMT_U8)
994 * and returns the bit setting for the 1848 register corresponding to
995 * the desired format.
996 *
997 * fixed lr970724
998 */
999
1000static int
1001mss_format(struct mss_chinfo *ch, u_int32_t format)
1002{
1003 struct mss_info *mss = ch->parent;
1004 int i, arg = format & ~AFMT_STEREO;
1005
1006 /*
1007 * The data format uses 3 bits (just 2 on the 1848). For each
1008 * bit setting, the following array returns the corresponding format.
1009 * The code scans the array looking for a suitable format. In
1010 * case it is not found, default to AFMT_U8 (not such a good
1011 * choice, but let's do it for compatibility...).
1012 */
1013
1014 static int fmts[] =
1015 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1016 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1017
1018 ch->fmt = format;
1019 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1020 arg = i << 1;
1021 if (format & AFMT_STEREO) arg |= 1;
1022 arg <<= 4;
1023 ad_enter_MCE(mss);
1024 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
558a398b
SS
1025 ad_wait_init(mss, 10000);
1026 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1027 ad_write(mss, 28, arg); /* capture mode */
1028 ad_wait_init(mss, 10000);
1029 }
984263bc
MD
1030 ad_leave_MCE(mss);
1031 return format;
1032}
1033
1034static int
1035mss_trigger(struct mss_chinfo *ch, int go)
1036{
1037 struct mss_info *mss = ch->parent;
1038 u_char m;
1039 int retry, wr, cnt, ss;
1040
1041 ss = 1;
1042 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1043 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1044
1045 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1046 m = ad_read(mss, 9);
1047 switch (go) {
1048 case PCMTRIG_START:
1049 cnt = (ch->blksz / ss) - 1;
1050
e3869ec7 1051 DEB(if (m & 4) kprintf("OUCH! reg 9 0x%02x\n", m););
984263bc
MD
1052 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1053 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1054 break;
1055
1056 case PCMTRIG_STOP:
1057 case PCMTRIG_ABORT: /* XXX check this... */
1058 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1059#if 0
1060 /*
1061 * try to disable DMA by clearing count registers. Not sure it
1062 * is needed, and it might cause false interrupts when the
1063 * DMA is re-enabled later.
1064 */
1065 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1066#endif
1067 }
1068 /* on the OPTi931 the enable bit seems hard to set... */
1069 for (retry = 10; retry > 0; retry--) {
1070 ad_write(mss, 9, m);
1071 if (ad_read(mss, 9) == m) break;
1072 }
e3869ec7 1073 if (retry == 0) BVDDB(kprintf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
984263bc
MD
1074 m, ad_read(mss, 9)));
1075 return 0;
1076}
1077
1078
1079/*
1080 * the opti931 seems to miss interrupts when working in full
1081 * duplex, so we try some heuristics to catch them.
1082 */
1083static void
1084opti931_intr(void *arg)
1085{
1086 struct mss_info *mss = (struct mss_info *)arg;
1087 u_char masked = 0, i11, mc11, c = 0;
1088 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1089 int loops = 10;
1090
1091#if 0
1092 reason = io_rd(mss, MSS_STATUS);
1093 if (!(reason & 1)) {/* no int, maybe a shared line ? */
e3869ec7 1094 DEB(kprintf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
984263bc
MD
1095 return;
1096 }
1097#endif
1098 mss_lock(mss);
1099 i11 = ad_read(mss, 11); /* XXX what's for ? */
1100 again:
1101
1102 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1103 mc11 &= 0x0c;
1104 if (c & 0x10) {
e3869ec7 1105 DEB(kprintf("Warning: CD interrupt\n");)
984263bc
MD
1106 mc11 |= 0x10;
1107 }
1108 if (c & 0x20) {
e3869ec7 1109 DEB(kprintf("Warning: MPU interrupt\n");)
984263bc
MD
1110 mc11 |= 0x20;
1111 }
e3869ec7 1112 if (mc11 & masked) BVDDB(kprintf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
984263bc
MD
1113 mc11, masked));
1114 masked |= mc11;
1115 /*
1116 * the nice OPTi931 sets the IRQ line before setting the bits in
1117 * mc11. So, on some occasions I have to retry (max 10 times).
1118 */
1119 if (mc11 == 0) { /* perhaps can return ... */
1120 reason = io_rd(mss, MSS_STATUS);
1121 if (reason & 1) {
e3869ec7 1122 DEB(kprintf("one more try...\n");)
984263bc 1123 if (--loops) goto again;
558a398b 1124 else BVDDB(kprintf("intr, but mc11 not set\n");)
984263bc 1125 }
e3869ec7 1126 if (loops == 0) BVDDB(kprintf("intr, nothing in mcir11 0x%02x\n", mc11));
984263bc
MD
1127 mss_unlock(mss);
1128 return;
1129 }
1130
558a398b
SS
1131 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1132 mss_unlock(mss);
1133 chn_intr(mss->rch.channel);
1134 mss_lock(mss);
1135 }
1136 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1137 mss_unlock(mss);
1138 chn_intr(mss->pch.channel);
1139 mss_lock(mss);
1140 }
984263bc
MD
1141 opti_wr(mss, 11, ~mc11); /* ack */
1142 if (--loops) goto again;
1143 mss_unlock(mss);
e3869ec7 1144 DEB(kprintf("xxx too many loops\n");)
984263bc
MD
1145}
1146
1147/* -------------------------------------------------------------------- */
1148/* channel interface */
1149static void *
1150msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1151{
1152 struct mss_info *mss = devinfo;
1153 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1154
1155 ch->parent = mss;
1156 ch->channel = c;
1157 ch->buffer = b;
1158 ch->dir = dir;
558a398b
SS
1159 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) != 0)
1160 return NULL;
1161 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
984263bc
MD
1162 return ch;
1163}
1164
1165static int
1166msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1167{
1168 struct mss_chinfo *ch = data;
1169 struct mss_info *mss = ch->parent;
1170
1171 mss_lock(mss);
1172 mss_format(ch, format);
1173 mss_unlock(mss);
1174 return 0;
1175}
1176
1177static int
1178msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1179{
1180 struct mss_chinfo *ch = data;
1181 struct mss_info *mss = ch->parent;
1182 int r;
1183
1184 mss_lock(mss);
1185 r = mss_speed(ch, speed);
1186 mss_unlock(mss);
1187
1188 return r;
1189}
1190
1191static int
1192msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1193{
1194 struct mss_chinfo *ch = data;
1195
1196 ch->blksz = blocksize;
1197 sndbuf_resize(ch->buffer, 2, ch->blksz);
1198
1199 return ch->blksz;
1200}
1201
1202static int
1203msschan_trigger(kobj_t obj, void *data, int go)
1204{
1205 struct mss_chinfo *ch = data;
1206 struct mss_info *mss = ch->parent;
1207
1208 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
1209 return 0;
1210
558a398b 1211 sndbuf_dma(ch->buffer, go);
984263bc
MD
1212 mss_lock(mss);
1213 mss_trigger(ch, go);
1214 mss_unlock(mss);
1215 return 0;
1216}
1217
1218static int
1219msschan_getptr(kobj_t obj, void *data)
1220{
1221 struct mss_chinfo *ch = data;
558a398b 1222 return sndbuf_dmaptr(ch->buffer);
984263bc
MD
1223}
1224
1225static struct pcmchan_caps *
1226msschan_getcaps(kobj_t obj, void *data)
1227{
1228 struct mss_chinfo *ch = data;
1229
1230 switch(ch->parent->bd_id) {
1231 case MD_OPTI931:
1232 return &opti931_caps;
1233 break;
1234
1235 case MD_GUSPNP:
1236 case MD_GUSMAX:
1237 return &guspnp_caps;
1238 break;
1239
1240 default:
1241 return &mss_caps;
1242 break;
1243 }
1244}
1245
1246static kobj_method_t msschan_methods[] = {
1247 KOBJMETHOD(channel_init, msschan_init),
1248 KOBJMETHOD(channel_setformat, msschan_setformat),
1249 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1250 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1251 KOBJMETHOD(channel_trigger, msschan_trigger),
1252 KOBJMETHOD(channel_getptr, msschan_getptr),
1253 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1254 { 0, 0 }
1255};
1256CHANNEL_DECLARE(msschan);
1257
1258/* -------------------------------------------------------------------- */
1259
1260/*
1261 * mss_probe() is the probe routine. Note, it is not necessary to
1262 * go through this for PnP devices, since they are already
1263 * indentified precisely using their PnP id.
1264 *
1265 * The base address supplied in the device refers to the old MSS
1266 * specs where the four 4 registers in io space contain configuration
1267 * information. Some boards (as an example, early MSS boards)
1268 * has such a block of registers, whereas others (generally CS42xx)
1269 * do not. In order to distinguish between the two and do not have
1270 * to supply two separate probe routines, the flags entry in isa_device
1271 * has a bit to mark this.
1272 *
1273 */
1274
1275static int
1276mss_probe(device_t dev)
1277{
1278 u_char tmp, tmpx;
1279 int flags, irq, drq, result = ENXIO, setres = 0;
1280 struct mss_info *mss;
1281
1282 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1283
efda3bd0 1284 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1285 if (!mss) return ENXIO;
1286
1287 mss->io_rid = 0;
1288 mss->conf_rid = -1;
1289 mss->irq_rid = 0;
1290 mss->drq1_rid = 0;
1291 mss->drq2_rid = -1;
1292 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1293 0, ~0, 8, RF_ACTIVE);
1294 if (!mss->io_base) {
e3869ec7 1295 BVDDB(kprintf("mss_probe: no address given, try 0x%x\n", 0x530));
984263bc
MD
1296 mss->io_rid = 0;
1297 /* XXX verify this */
1298 setres = 1;
1299 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1300 0x530, 8);
1301 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1302 0, ~0, 8, RF_ACTIVE);
1303 }
1304 if (!mss->io_base) goto no;
1305
1306 /* got irq/dma regs? */
1307 flags = device_get_flags(dev);
1308 irq = isa_get_irq(dev);
1309 drq = isa_get_drq(dev);
1310
1311 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1312
1313 /*
1314 * Check if the IO port returns valid signature. The original MS
1315 * Sound system returns 0x04 while some cards
1316 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1317 */
1318
1319 device_set_desc(dev, "MSS");
1320 tmpx = tmp = io_rd(mss, 3);
1321 if (tmp == 0xff) { /* Bus float */
e3869ec7 1322 BVDDB(kprintf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
984263bc
MD
1323 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1324 goto mss_probe_end;
1325 }
1326 tmp &= 0x3f;
1327 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
e3869ec7 1328 BVDDB(kprintf("No MSS signature detected on port 0x%lx (0x%x)\n",
984263bc
MD
1329 rman_get_start(mss->io_base), tmpx));
1330 goto no;
1331 }
984263bc 1332 if (irq > 11) {
e3869ec7 1333 kprintf("MSS: Bad IRQ %d\n", irq);
984263bc
MD
1334 goto no;
1335 }
1336 if (!(drq == 0 || drq == 1 || drq == 3)) {
e3869ec7 1337 kprintf("MSS: Bad DMA %d\n", drq);
984263bc
MD
1338 goto no;
1339 }
1340 if (tmpx & 0x80) {
1341 /* 8-bit board: only drq1/3 and irq7/9 */
1342 if (drq == 0) {
e3869ec7 1343 kprintf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
984263bc
MD
1344 goto no;
1345 }
1346 if (!(irq == 7 || irq == 9)) {
e3869ec7 1347 kprintf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
984263bc
MD
1348 irq);
1349 goto no;
1350 }
1351 }
1352 mss_probe_end:
1353 result = mss_detect(dev, mss);
1354 no:
1355 mss_release_resources(mss, dev);
1356#if 0
1357 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1358 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1359#endif
1360 return result;
1361}
1362
1363static int
1364mss_detect(device_t dev, struct mss_info *mss)
1365{
1366 int i;
1367 u_char tmp = 0, tmp1, tmp2;
1368 char *name, *yamaha;
1369
1370 if (mss->bd_id != 0) {
1371 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1372 device_get_desc(dev));
1373 return 0;
1374 }
1375
1376 name = "AD1848";
1377 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1378
558a398b 1379#ifndef PC98
984263bc
MD
1380 if (opti_detect(dev, mss)) {
1381 switch (mss->bd_id) {
1382 case MD_OPTI924:
1383 name = "OPTi924";
1384 break;
1385 case MD_OPTI930:
1386 name = "OPTi930";
1387 break;
1388 }
e3869ec7 1389 kprintf("Found OPTi device %s\n", name);
984263bc
MD
1390 if (opti_init(dev, mss) == 0) goto gotit;
1391 }
558a398b 1392#endif
984263bc
MD
1393
1394 /*
1395 * Check that the I/O address is in use.
1396 *
1397 * bit 7 of the base I/O port is known to be 0 after the chip has
1398 * performed its power on initialization. Just assume this has
1399 * happened before the OS is starting.
1400 *
1401 * If the I/O address is unused, it typically returns 0xff.
1402 */
1403
1404 for (i = 0; i < 10; i++)
1405 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1406 else break;
1407
558a398b 1408 if (i >= 10) { /* Not an AD1848 */
e3869ec7 1409 BVDDB(kprintf("mss_detect, busy still set (0x%02x)\n", tmp));
984263bc
MD
1410 goto no;
1411 }
1412 /*
1413 * Test if it's possible to change contents of the indirect
1414 * registers. Registers 0 and 1 are ADC volume registers. The bit
1415 * 0x10 is read only so try to avoid using it.
1416 */
1417
1418 ad_write(mss, 0, 0xaa);
1419 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1420 tmp1 = ad_read(mss, 0);
1421 tmp2 = ad_read(mss, 1);
1422 if (tmp1 != 0xaa || tmp2 != 0x45) {
e3869ec7 1423 BVDDB(kprintf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
984263bc
MD
1424 goto no;
1425 }
1426
1427 ad_write(mss, 0, 0x45);
1428 ad_write(mss, 1, 0xaa);
1429 tmp1 = ad_read(mss, 0);
1430 tmp2 = ad_read(mss, 1);
1431 if (tmp1 != 0x45 || tmp2 != 0xaa) {
e3869ec7 1432 BVDDB(kprintf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
984263bc
MD
1433 goto no;
1434 }
1435
1436 /*
1437 * The indirect register I12 has some read only bits. Lets try to
1438 * change them.
1439 */
1440
1441 tmp = ad_read(mss, 12);
1442 ad_write(mss, 12, (~tmp) & 0x0f);
1443 tmp1 = ad_read(mss, 12);
1444
1445 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
e3869ec7 1446 BVDDB(kprintf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
984263bc
MD
1447 goto no;
1448 }
1449
1450 /*
1451 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1452 * 0x01=RevB
1453 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1454 */
1455
e3869ec7 1456 BVDDB(kprintf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
984263bc
MD
1457
1458 /*
1459 * The original AD1848/CS4248 has just 16 indirect registers. This
1460 * means that I0 and I16 should return the same value (etc.). Ensure
1461 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1462 * with new parts.
1463 */
1464
1465 ad_write(mss, 12, 0); /* Mode2=disabled */
1466#if 0
1467 for (i = 0; i < 16; i++) {
1468 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
e3869ec7 1469 BVDDB(kprintf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
984263bc
MD
1470 i, tmp1, tmp2));
1471 /*
1472 * note - this seems to fail on the 4232 on I11. So we just break
1473 * rather than fail. (which makes this test pointless - cg)
1474 */
1475 break; /* return 0; */
1476 }
1477 }
1478#endif
1479 /*
1480 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1481 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1482 *
1483 * On the OPTi931, however, I12 is readonly and only contains the
1484 * chip revision ID (as in the CS4231A). The upper bits return 0.
1485 */
1486
1487 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1488
1489 tmp1 = ad_read(mss, 12);
1490 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1491 if ((tmp1 & 0xf0) == 0x00) {
e3869ec7 1492 BVDDB(kprintf("this should be an OPTi931\n");)
984263bc
MD
1493 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1494 /*
1495 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1496 * We want to check that this is really a CS4231
1497 * Verify that setting I0 doesn't change I16.
1498 */
1499 ad_write(mss, 16, 0); /* Set I16 to known value */
1500 ad_write(mss, 0, 0x45);
1501 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1502
1503 ad_write(mss, 0, 0xaa);
1504 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
e3869ec7 1505 BVDDB(kprintf("mss_detect error - step H(%x)\n", tmp1));
984263bc
MD
1506 goto no;
1507 }
1508 /* Verify that some bits of I25 are read only. */
1509 tmp1 = ad_read(mss, 25); /* Original bits */
1510 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1511 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1512 int id;
1513
1514 /* It's at least CS4231 */
1515 name = "CS4231";
1516 mss->bd_id = MD_CS42XX;
1517
1518 /*
1519 * It could be an AD1845 or CS4231A as well.
1520 * CS4231 and AD1845 report the same revision info in I25
1521 * while the CS4231A reports different.
1522 */
1523
1524 id = ad_read(mss, 25) & 0xe7;
1525 /*
1526 * b7-b5 = version number;
1527 * 100 : all CS4231
1528 * 101 : CS4231A
1529 *
1530 * b2-b0 = chip id;
1531 */
1532 switch (id) {
1533
1534 case 0xa0:
1535 name = "CS4231A";
1536 mss->bd_id = MD_CS42XX;
1537 break;
1538
1539 case 0xa2:
1540 name = "CS4232";
1541 mss->bd_id = MD_CS42XX;
1542 break;
1543
1544 case 0xb2:
1545 /* strange: the 4231 data sheet says b4-b3 are XX
1546 * so this should be the same as 0xa2
1547 */
1548 name = "CS4232A";
1549 mss->bd_id = MD_CS42XX;
1550 break;
1551
1552 case 0x80:
1553 /*
1554 * It must be a CS4231 or AD1845. The register I23
1555 * of CS4231 is undefined and it appears to be read
1556 * only. AD1845 uses I23 for setting sample rate.
1557 * Assume the chip is AD1845 if I23 is changeable.
1558 */
1559
1560 tmp = ad_read(mss, 23);
1561
1562 ad_write(mss, 23, ~tmp);
1563 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1564 name = "AD1845";
1565 mss->bd_id = MD_AD1845;
1566 }
1567 ad_write(mss, 23, tmp); /* Restore */
1568
1569 yamaha = ymf_test(dev, mss);
1570 if (yamaha) {
1571 mss->bd_id = MD_YM0020;
1572 name = yamaha;
1573 }
1574 break;
1575
1576 case 0x83: /* CS4236 */
1577 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1578 name = "CS4236";
1579 mss->bd_id = MD_CS42XX;
1580 break;
1581
1582 default: /* Assume CS4231 */
e3869ec7 1583 BVDDB(kprintf("unknown id 0x%02x, assuming CS4231\n", id);)
984263bc
MD
1584 mss->bd_id = MD_CS42XX;
1585 }
1586 }
1587 ad_write(mss, 25, tmp1); /* Restore bits */
1588gotit:
e3869ec7 1589 BVDDB(kprintf("mss_detect() - Detected %s\n", name));
984263bc
MD
1590 device_set_desc(dev, name);
1591 device_set_flags(dev,
1592 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1593 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1594 return 0;
1595no:
1596 return ENXIO;
1597}
1598
558a398b 1599#ifndef PC98
984263bc
MD
1600static int
1601opti_detect(device_t dev, struct mss_info *mss)
1602{
1603 int c;
1604 static const struct opticard {
1605 int boardid;
1606 int passwdreg;
1607 int password;
1608 int base;
1609 int indir_reg;
1610 } cards[] = {
1611 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1612 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1613 { 0 },
1614 };
1615 mss->conf_rid = 3;
1616 mss->indir_rid = 4;
1617 for (c = 0; cards[c].base; c++) {
1618 mss->optibase = cards[c].base;
1619 mss->password = cards[c].password;
1620 mss->passwdreg = cards[c].passwdreg;
1621 mss->bd_id = cards[c].boardid;
1622
1623 if (cards[c].indir_reg)
1624 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1625 &mss->indir_rid, cards[c].indir_reg,
1626 cards[c].indir_reg+1, 1, RF_ACTIVE);
1627
1628 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1629 &mss->conf_rid, mss->optibase, mss->optibase+9,
1630 9, RF_ACTIVE);
1631
1632 if (opti_read(mss, 1) != 0xff) {
1633 return 1;
1634 } else {
1635 if (mss->indir)
1636 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1637 mss->indir = NULL;
1638 if (mss->conf_base)
1639 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1640 mss->conf_base = NULL;
1641 }
1642 }
1643 return 0;
1644}
558a398b 1645#endif
984263bc
MD
1646
1647static char *
1648ymf_test(device_t dev, struct mss_info *mss)
1649{
1650 static int ports[] = {0x370, 0x310, 0x538};
1651 int p, i, j, version;
1652 static char *chipset[] = {
1653 NULL, /* 0 */
1654 "OPL3-SA2 (YMF711)", /* 1 */
1655 "OPL3-SA3 (YMF715)", /* 2 */
1656 "OPL3-SA3 (YMF715)", /* 3 */
1657 "OPL3-SAx (YMF719)", /* 4 */
1658 "OPL3-SAx (YMF719)", /* 5 */
1659 "OPL3-SAx (YMF719)", /* 6 */
1660 "OPL3-SAx (YMF719)", /* 7 */
1661 };
1662
1663 for (p = 0; p < 3; p++) {
1664 mss->conf_rid = 1;
1665 mss->conf_base = bus_alloc_resource(dev,
1666 SYS_RES_IOPORT,
1667 &mss->conf_rid,
1668 ports[p], ports[p] + 1, 2,
1669 RF_ACTIVE);
1670 if (!mss->conf_base) return 0;
1671
1672 /* Test the index port of the config registers */
1673 i = port_rd(mss->conf_base, 0);
1674 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1675 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1676 port_wr(mss->conf_base, 0, i);
1677 if (!j) {
1678 bus_release_resource(dev, SYS_RES_IOPORT,
1679 mss->conf_rid, mss->conf_base);
558a398b
SS
1680#ifdef PC98
1681 /* PC98 need this. I don't know reason why. */
1682 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1683#endif
984263bc
MD
1684 mss->conf_base = 0;
1685 continue;
1686 }
1687 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1688 return chipset[version];
1689 }
1690 return NULL;
1691}
1692
1693static int
1694mss_doattach(device_t dev, struct mss_info *mss)
1695{
1696 int pdma, rdma, flags = device_get_flags(dev);
1697 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1698
1699 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1700 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1701 if (!mss_alloc_resources(mss, dev)) goto no;
1702 mss_init(mss, dev);
1703 pdma = rman_get_start(mss->drq1);
1704 rdma = rman_get_start(mss->drq2);
1705 if (flags & DV_F_TRUE_MSS) {
1706 /* has IRQ/DMA registers, set IRQ and DMA addr */
558a398b
SS
1707#ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
1708 static char interrupt_bits[13] =
1709 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
1710#else
984263bc
MD
1711 static char interrupt_bits[12] =
1712 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
558a398b 1713#endif
984263bc
MD
1714 static char pdma_bits[4] = {1, 2, -1, 3};
1715 static char valid_rdma[4] = {1, 0, -1, 0};
1716 char bits;
1717
1718 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1719 goto no;
558a398b 1720#ifndef PC98 /* CS423[12] in PC98 don't support this. */
984263bc
MD
1721 io_wr(mss, 0, bits | 0x40); /* config port */
1722 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
558a398b 1723#endif
984263bc
MD
1724 /* Write IRQ+DMA setup */
1725 if (pdma_bits[pdma] == -1) goto no;
1726 bits |= pdma_bits[pdma];
1727 if (pdma != rdma) {
1728 if (rdma == valid_rdma[pdma]) bits |= 4;
1729 else {
e3869ec7 1730 kprintf("invalid dual dma config %d:%d\n", pdma, rdma);
984263bc
MD
1731 goto no;
1732 }
1733 }
1734 io_wr(mss, 0, bits);
e3869ec7 1735 kprintf("drq/irq conf %x\n", io_rd(mss, 0));
984263bc
MD
1736 }
1737 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1738 switch (mss->bd_id) {
1739 case MD_OPTI931:
558a398b 1740 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
984263bc
MD
1741 break;
1742 default:
558a398b 1743 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
984263bc
MD
1744 }
1745 if (pdma == rdma)
1746 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1747 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1748 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1749 /*highaddr*/BUS_SPACE_MAXADDR,
1750 /*filter*/NULL, /*filterarg*/NULL,
1751 /*maxsize*/mss->bufsize, /*nsegments*/1,
558a398b
SS
1752 /*maxsegz*/0x3ffff, /*flags*/0,
1753 &mss->parent_dmat) != 0) {
984263bc
MD
1754 device_printf(dev, "unable to create dma tag\n");
1755 goto no;
1756 }
1757
1758 if (pdma != rdma)
f8c7a42d 1759 ksnprintf(status2, SND_STATUSLEN, ":%d", rdma);
984263bc
MD
1760 else
1761 status2[0] = '\0';
1762
f8c7a42d 1763 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
984263bc
MD
1764 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1765
1766 if (pcm_register(dev, mss, 1, 1)) goto no;
1767 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1768 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1769 pcm_setstatus(dev, status);
1770
1771 return 0;
1772no:
1773 mss_release_resources(mss, dev);
1774 return ENXIO;
1775}
1776
1777static int
1778mss_detach(device_t dev)
1779{
1780 int r;
1781 struct mss_info *mss;
1782
1783 r = pcm_unregister(dev);
1784 if (r)
1785 return r;
1786
1787 mss = pcm_getdevinfo(dev);
1788 mss_release_resources(mss, dev);
1789
1790 return 0;
1791}
1792
1793static int
1794mss_attach(device_t dev)
1795{
1796 struct mss_info *mss;
1797 int flags = device_get_flags(dev);
1798
efda3bd0 1799 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1800 if (!mss) return ENXIO;
1801
1802 mss->io_rid = 0;
1803 mss->conf_rid = -1;
1804 mss->irq_rid = 0;
1805 mss->drq1_rid = 0;
1806 mss->drq2_rid = -1;
1807 if (flags & DV_F_DUAL_DMA) {
1808 bus_set_resource(dev, SYS_RES_DRQ, 1,
1809 flags & DV_F_DRQ_MASK, 1);
1810 mss->drq2_rid = 1;
1811 }
1812 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1813 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1814 return mss_doattach(dev, mss);
1815}
1816
1817/*
1818 * mss_resume() is the code to allow a laptop to resume using the sound
1819 * card.
1820 *
1821 * This routine re-sets the state of the board to the state before going
1822 * to sleep. According to the yamaha docs this is the right thing to do,
1823 * but getting DMA restarted appears to be a bit of a trick, so the device
1824 * has to be closed and re-opened to be re-used, but there is no skipping
1825 * problem, and volume, bass/treble and most other things are restored
1826 * properly.
1827 *
1828 */
1829
1830static int
1831mss_resume(device_t dev)
1832{
1833 /*
1834 * Restore the state taken below.
1835 */
1836 struct mss_info *mss;
1837 int i;
1838
1839 mss = pcm_getdevinfo(dev);
1840
558a398b 1841 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
984263bc
MD
1842 /* This works on a Toshiba Libretto 100CT. */
1843 for (i = 0; i < MSS_INDEXED_REGS; i++)
1844 ad_write(mss, i, mss->mss_indexed_regs[i]);
1845 for (i = 0; i < OPL_INDEXED_REGS; i++)
1846 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1847 mss_intr(mss);
1848 }
558a398b
SS
1849
1850 if (mss->bd_id == MD_CS423X) {
1851 /* Needed on IBM Thinkpad 600E */
1852 mss_lock(mss);
1853 mss_format(&mss->pch, mss->pch.channel->format);
1854 mss_speed(&mss->pch, mss->pch.channel->speed);
1855 mss_unlock(mss);
1856 }
1857
984263bc
MD
1858 return 0;
1859
1860}
1861
1862/*
1863 * mss_suspend() is the code that gets called right before a laptop
1864 * suspends.
1865 *
1866 * This code saves the state of the sound card right before shutdown
1867 * so it can be restored above.
1868 *
1869 */
1870
1871static int
1872mss_suspend(device_t dev)
1873{
1874 int i;
1875 struct mss_info *mss;
1876
1877 mss = pcm_getdevinfo(dev);
1878
558a398b 1879 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
984263bc
MD
1880 {
1881 /* this stops playback. */
1882 conf_wr(mss, 0x12, 0x0c);
1883 for(i = 0; i < MSS_INDEXED_REGS; i++)
1884 mss->mss_indexed_regs[i] = ad_read(mss, i);
1885 for(i = 0; i < OPL_INDEXED_REGS; i++)
1886 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1887 mss->opl_indexed_regs[0x12] = 0x0;
1888 }
1889 return 0;
1890}
1891
1892static device_method_t mss_methods[] = {
1893 /* Device interface */
1894 DEVMETHOD(device_probe, mss_probe),
1895 DEVMETHOD(device_attach, mss_attach),
1896 DEVMETHOD(device_detach, mss_detach),
1897 DEVMETHOD(device_suspend, mss_suspend),
1898 DEVMETHOD(device_resume, mss_resume),
1899
1900 { 0, 0 }
1901};
1902
1903static driver_t mss_driver = {
1904 "pcm",
1905 mss_methods,
1906 PCM_SOFTC_SIZE,
1907};
1908
1909DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
558a398b 1910MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
1911MODULE_VERSION(snd_mss, 1);
1912
1913static int
1914azt2320_mss_mode(struct mss_info *mss, device_t dev)
1915{
1916 struct resource *sbport;
1917 int i, ret, rid;
1918
1919 rid = 0;
1920 ret = -1;
558a398b 1921 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
984263bc
MD
1922 if (sbport) {
1923 for (i = 0; i < 1000; i++) {
1924 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1925 DELAY((i > 100) ? 1000 : 10);
1926 else {
1927 port_wr(sbport, SBDSP_CMD, 0x09);
1928 break;
1929 }
1930 }
1931 for (i = 0; i < 1000; i++) {
1932 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1933 DELAY((i > 100) ? 1000 : 10);
1934 else {
1935 port_wr(sbport, SBDSP_CMD, 0x00);
1936 ret = 0;
1937 break;
1938 }
1939 }
1940 DELAY(1000);
1941 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1942 }
1943 return ret;
1944}
1945
1946static struct isa_pnp_id pnpmss_ids[] = {
1947 {0x0000630e, "CS423x"}, /* CSC0000 */
1948 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1949 {0x01000000, "CMI8330"}, /* @@@0001 */
1950 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1951 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1952 {0x1093143e, "OPTi931"}, /* OPT9310 */
1953 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1954 {0x0000143e, "OPTi924"}, /* OPT0924 */
1955 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1956 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1957#if 0
1958 {0x0000561e, "GusPnP"}, /* GRV0000 */
1959#endif
1960 {0},
1961};
1962
1963static int
1964pnpmss_probe(device_t dev)
1965{
1966 u_int32_t lid, vid;
1967
1968 lid = isa_get_logicalid(dev);
1969 vid = isa_get_vendorid(dev);
1970 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1971 return ENXIO;
1972 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1973}
1974
1975static int
1976pnpmss_attach(device_t dev)
1977{
1978 struct mss_info *mss;
1979
efda3bd0 1980 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1981 if (!mss)
1982 return ENXIO;
1983
1984 mss->io_rid = 0;
1985 mss->conf_rid = -1;
1986 mss->irq_rid = 0;
1987 mss->drq1_rid = 0;
1988 mss->drq2_rid = 1;
1989 mss->bd_id = MD_CS42XX;
1990
1991 switch (isa_get_logicalid(dev)) {
1992 case 0x0000630e: /* CSC0000 */
1993 case 0x0001630e: /* CSC0100 */
1994 mss->bd_flags |= BD_F_MSS_OFFSET;
558a398b 1995 mss->bd_id = MD_CS423X;
984263bc
MD
1996 break;
1997
1998 case 0x2100a865: /* YHM0021 */
1999 mss->io_rid = 1;
2000 mss->conf_rid = 4;
2001 mss->bd_id = MD_YM0020;
2002 break;
2003
2004 case 0x1110d315: /* ENS1011 */
2005 mss->io_rid = 1;
2006 mss->bd_id = MD_VIVO;
2007 break;
2008
2009 case 0x1093143e: /* OPT9310 */
2010 mss->bd_flags |= BD_F_MSS_OFFSET;
2011 mss->conf_rid = 3;
2012 mss->bd_id = MD_OPTI931;
2013 break;
2014
2015 case 0x5092143e: /* OPT9250 XXX guess */
2016 mss->io_rid = 1;
2017 mss->conf_rid = 3;
2018 mss->bd_id = MD_OPTI925;
2019 break;
2020
2021 case 0x0000143e: /* OPT0924 */
2022 mss->password = 0xe5;
2023 mss->passwdreg = 3;
2024 mss->optibase = 0xf0c;
2025 mss->io_rid = 2;
2026 mss->conf_rid = 3;
2027 mss->bd_id = MD_OPTI924;
2028 mss->bd_flags |= BD_F_924PNP;
558a398b
SS
2029 if(opti_init(dev, mss) != 0) {
2030 kfree(mss, M_DEVBUF);
984263bc 2031 return ENXIO;
558a398b 2032 }
984263bc
MD
2033 break;
2034
2035 case 0x1022b839: /* NMX2210 */
2036 mss->io_rid = 1;
2037 break;
2038
2039 case 0x01005407: /* AZT0001 */
2040 /* put into MSS mode first (snatched from NetBSD) */
558a398b
SS
2041 if (azt2320_mss_mode(mss, dev) == -1) {
2042 kfree(mss, M_DEVBUF);
984263bc 2043 return ENXIO;
558a398b 2044 }
984263bc
MD
2045
2046 mss->bd_flags |= BD_F_MSS_OFFSET;
2047 mss->io_rid = 2;
2048 break;
2049
2050#if 0
2051 case 0x0000561e: /* GRV0000 */
2052 mss->bd_flags |= BD_F_MSS_OFFSET;
2053 mss->io_rid = 2;
2054 mss->conf_rid = 1;
2055 mss->drq1_rid = 1;
2056 mss->drq2_rid = 0;
2057 mss->bd_id = MD_GUSPNP;
2058 break;
2059#endif
2060 case 0x01000000: /* @@@0001 */
2061 mss->drq2_rid = -1;
2062 break;
2063
2064 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2065 default:
2066 mss->bd_flags |= BD_F_MSS_OFFSET;
2067 break;
2068 }
2069 return mss_doattach(dev, mss);
2070}
2071
2072static int
2073opti_init(device_t dev, struct mss_info *mss)
2074{
2075 int flags = device_get_flags(dev);
2076 int basebits = 0;
2077
2078 if (!mss->conf_base) {
2079 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2080 mss->optibase, 0x9);
2081
2082 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2083 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2084 0x9, RF_ACTIVE);
2085 }
2086
2087 if (!mss->conf_base)
2088 return ENXIO;
2089
2090 if (!mss->io_base)
2091 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2092 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2093
2094 if (!mss->io_base) /* No hint specified, use 0x530 */
2095 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2096 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2097
2098 if (!mss->io_base)
2099 return ENXIO;
2100
2101 switch (rman_get_start(mss->io_base)) {
2102 case 0x530:
2103 basebits = 0x0;
2104 break;
2105 case 0xe80:
2106 basebits = 0x10;
2107 break;
2108 case 0xf40:
2109 basebits = 0x20;
2110 break;
2111 case 0x604:
2112 basebits = 0x30;
2113 break;
2114 default:
e3869ec7 2115 kprintf("opti_init: invalid MSS base address!\n");
984263bc
MD
2116 return ENXIO;
2117 }
2118
2119
2120 switch (mss->bd_id) {
2121 case MD_OPTI924:
2122 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2123 opti_write(mss, 2, 0x00); /* Disable CD */
2124 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2125 opti_write(mss, 4, 0xf0);
2126 opti_write(mss, 5, 0x00);
2127 opti_write(mss, 6, 0x02); /* MPU stuff */
2128 break;
2129
2130 case MD_OPTI930:
2131 opti_write(mss, 1, 0x00 | basebits);
2132 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2133 opti_write(mss, 4, 0x52); /* Empty FIFO */
2134 opti_write(mss, 5, 0x3c); /* Mode 2 */
2135 opti_write(mss, 6, 0x02); /* Enable MSS */
2136 break;
2137 }
2138
2139 if (mss->bd_flags & BD_F_924PNP) {
2140 u_int32_t irq = isa_get_irq(dev);
2141 u_int32_t drq = isa_get_drq(dev);
2142 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2143 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2144 if (flags & DV_F_DUAL_DMA) {
2145 bus_set_resource(dev, SYS_RES_DRQ, 1,
2146 flags & DV_F_DRQ_MASK, 1);
2147 mss->drq2_rid = 1;
2148 }
2149 }
2150
2151 /* OPTixxx has I/DRQ registers */
2152
2153 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2154
2155 return 0;
2156}
2157
2158static void
2159opti_write(struct mss_info *mss, u_char reg, u_char val)
2160{
2161 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2162
2163 switch(mss->bd_id) {
2164 case MD_OPTI924:
2165 if (reg > 7) { /* Indirect register */
2166 port_wr(mss->conf_base, mss->passwdreg, reg);
2167 port_wr(mss->conf_base, mss->passwdreg,
2168 mss->password);
2169 port_wr(mss->conf_base, 9, val);
2170 return;
2171 }
2172 port_wr(mss->conf_base, reg, val);
2173 break;
2174
2175 case MD_OPTI930:
2176 port_wr(mss->indir, 0, reg);
2177 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2178 port_wr(mss->indir, 1, val);
2179 break;
2180 }
2181}
2182
558a398b 2183#ifndef PC98
984263bc
MD
2184u_char
2185opti_read(struct mss_info *mss, u_char reg)
2186{
2187 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2188
2189 switch(mss->bd_id) {
2190 case MD_OPTI924:
2191 if (reg > 7) { /* Indirect register */
2192 port_wr(mss->conf_base, mss->passwdreg, reg);
2193 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2194 return(port_rd(mss->conf_base, 9));
2195 }
2196 return(port_rd(mss->conf_base, reg));
2197 break;
2198
2199 case MD_OPTI930:
2200 port_wr(mss->indir, 0, reg);
2201 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2202 return port_rd(mss->indir, 1);
2203 break;
2204 }
2205 return -1;
2206}
558a398b 2207#endif
984263bc
MD
2208
2209static device_method_t pnpmss_methods[] = {
2210 /* Device interface */
2211 DEVMETHOD(device_probe, pnpmss_probe),
2212 DEVMETHOD(device_attach, pnpmss_attach),
2213 DEVMETHOD(device_detach, mss_detach),
2214 DEVMETHOD(device_suspend, mss_suspend),
2215 DEVMETHOD(device_resume, mss_resume),
2216
2217 { 0, 0 }
2218};
2219
2220static driver_t pnpmss_driver = {
2221 "pcm",
2222 pnpmss_methods,
2223 PCM_SOFTC_SIZE,
2224};
2225
2226DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
558a398b
SS
2227DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
2228MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
2229MODULE_VERSION(snd_pnpmss, 1);
2230
2231static int
2232guspcm_probe(device_t dev)
2233{
2234 struct sndcard_func *func;
2235
2236 func = device_get_ivars(dev);
2237 if (func == NULL || func->func != SCF_PCM)
2238 return ENXIO;
2239
2240 device_set_desc(dev, "GUS CS4231");
2241 return 0;
2242}
2243
2244static int
2245guspcm_attach(device_t dev)
2246{
2247 device_t parent = device_get_parent(dev);
2248 struct mss_info *mss;
2249 int base, flags;
2250 unsigned char ctl;
2251
efda3bd0 2252 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
2253 if (mss == NULL)
2254 return ENOMEM;
2255
2256 mss->bd_flags = BD_F_MSS_OFFSET;
2257 mss->io_rid = 2;
2258 mss->conf_rid = 1;
2259 mss->irq_rid = 0;
2260 mss->drq1_rid = 1;
2261 mss->drq2_rid = -1;
2262
2263 if (isa_get_logicalid(parent) == 0)
2264 mss->bd_id = MD_GUSMAX;
2265 else {
2266 mss->bd_id = MD_GUSPNP;
2267 mss->drq2_rid = 0;
2268 goto skip_setup;
2269 }
2270
2271 flags = device_get_flags(parent);
2272 if (flags & DV_F_DUAL_DMA)
2273 mss->drq2_rid = 0;
2274
2275 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2276 0, ~0, 8, RF_ACTIVE);
2277
2278 if (mss->conf_base == NULL) {
2279 mss_release_resources(mss, dev);
2280 return ENXIO;
2281 }
2282
2283 base = isa_get_port(parent);
2284
2285 ctl = 0x40; /* CS4231 enable */
2286 if (isa_get_drq(dev) > 3)
2287 ctl |= 0x10; /* 16-bit dma channel 1 */
2288 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2289 ctl |= 0x20; /* 16-bit dma channel 2 */
2290 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2291 port_wr(mss->conf_base, 6, ctl);
2292
2293skip_setup:
2294 return mss_doattach(dev, mss);
2295}
2296
2297static device_method_t guspcm_methods[] = {
2298 DEVMETHOD(device_probe, guspcm_probe),
2299 DEVMETHOD(device_attach, guspcm_attach),
2300 DEVMETHOD(device_detach, mss_detach),
2301
2302 { 0, 0 }
2303};
2304
2305static driver_t guspcm_driver = {
2306 "pcm",
2307 guspcm_methods,
2308 PCM_SOFTC_SIZE,
2309};
2310
2311DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
558a398b 2312MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
2313MODULE_VERSION(snd_guspcm, 1);
2314
2315