Say hello to a sound system update from FreeBSD. This includes the long
[dragonfly.git] / sys / dev / sound / pci / cmi.c
CommitLineData
558a398b 1/*-
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2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
558a398b 30 * registers and the 8738 mixer devices. His Linux driver was also a
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31 * useful reference point.
32 *
33 * TODO: MIDI
34 *
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
36 *
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
40 * those that don't.
1de703da 41 *
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42 * $FreeBSD: src/sys/dev/sound/pci/cmi.c,v 1.32.2.2 2006/01/24 18:54:22 joel Exp $
43 * $DragonFly: src/sys/dev/sound/pci/cmi.c,v 1.9 2007/01/04 21:47:02 corecode Exp $
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44 */
45
46#include <dev/sound/pcm/sound.h>
47#include <dev/sound/pci/cmireg.h>
48#include <dev/sound/isa/sb.h>
49
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50#include <bus/pci/pcireg.h>
51#include <bus/pci/pcivar.h>
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52
53#include <sys/sysctl.h>
54
55#include "mixer_if.h"
56
558a398b 57SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/cmi.c,v 1.9 2007/01/04 21:47:02 corecode Exp $");
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58
59/* Supported chip ID's */
60#define CMI8338A_PCI_ID 0x010013f6
61#define CMI8338B_PCI_ID 0x010113f6
62#define CMI8738_PCI_ID 0x011113f6
63#define CMI8738B_PCI_ID 0x011213f6
64
65/* Buffer size max is 64k for permitted DMA boundaries */
66#define CMI_DEFAULT_BUFSZ 16384
67
68/* Interrupts per length of buffer */
69#define CMI_INTR_PER_BUFFER 2
70
71/* Clarify meaning of named defines in cmireg.h */
72#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
73#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
74#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
75#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
76
77/* Our indication of custom mixer control */
78#define CMPCI_NON_SB16_CONTROL 0xff
79
80/* Debugging macro's */
81#undef DEB
82#ifndef DEB
83#define DEB(x) /* x */
84#endif /* DEB */
85
86#ifndef DEBMIX
87#define DEBMIX(x) /* x */
88#endif /* DEBMIX */
89
90/* ------------------------------------------------------------------------- */
91/* Structures */
92
93struct sc_info;
94
95struct sc_chinfo {
96 struct sc_info *parent;
97 struct pcm_channel *channel;
98 struct snd_dbuf *buffer;
99 u_int32_t fmt, spd, phys_buf, bps;
100 u_int32_t dma_active:1, dma_was_active:1;
101 int dir;
102};
103
104struct sc_info {
105 device_t dev;
106
107 bus_space_tag_t st;
108 bus_space_handle_t sh;
109 bus_dma_tag_t parent_dmat;
110 struct resource *reg, *irq;
111 int regid, irqid;
112 void *ih;
558a398b 113 struct spinlock *lock;
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114
115 int spdif_enabled;
116 unsigned int bufsz;
117 struct sc_chinfo pch, rch;
118};
119
120/* Channel caps */
121
122static u_int32_t cmi_fmt[] = {
123 AFMT_U8,
124 AFMT_STEREO | AFMT_U8,
125 AFMT_S16_LE,
126 AFMT_STEREO | AFMT_S16_LE,
127 0
128};
129
130static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
131
132/* ------------------------------------------------------------------------- */
133/* Register Utilities */
134
135static u_int32_t
136cmi_rd(struct sc_info *sc, int regno, int size)
137{
138 switch (size) {
139 case 1:
140 return bus_space_read_1(sc->st, sc->sh, regno);
141 case 2:
142 return bus_space_read_2(sc->st, sc->sh, regno);
143 case 4:
144 return bus_space_read_4(sc->st, sc->sh, regno);
145 default:
e3869ec7 146 DEB(kprintf("cmi_rd: failed 0x%04x %d\n", regno, size));
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147 return 0xFFFFFFFF;
148 }
149}
150
151static void
152cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
153{
154 switch (size) {
155 case 1:
156 bus_space_write_1(sc->st, sc->sh, regno, data);
157 break;
158 case 2:
159 bus_space_write_2(sc->st, sc->sh, regno, data);
160 break;
161 case 4:
162 bus_space_write_4(sc->st, sc->sh, regno, data);
163 break;
164 }
165}
166
167static void
168cmi_partial_wr4(struct sc_info *sc,
169 int reg, int shift, u_int32_t mask, u_int32_t val)
170{
171 u_int32_t r;
172
173 r = cmi_rd(sc, reg, 4);
174 r &= ~(mask << shift);
175 r |= val << shift;
176 cmi_wr(sc, reg, r, 4);
177}
178
179static void
180cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
181{
182 u_int32_t r;
183
184 r = cmi_rd(sc, reg, 4);
185 r &= ~mask;
186 cmi_wr(sc, reg, r, 4);
187}
188
189static void
190cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
191{
192 u_int32_t r;
193
194 r = cmi_rd(sc, reg, 4);
195 r |= mask;
196 cmi_wr(sc, reg, r, 4);
197}
198
199/* ------------------------------------------------------------------------- */
200/* Rate Mapping */
201
202static int cmi_rates[] = {5512, 8000, 11025, 16000,
203 22050, 32000, 44100, 48000};
204#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
205
206/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
207 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
208
209static u_int32_t
210cmpci_rate_to_regvalue(int rate)
211{
212 int i, r;
213
214 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
215 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
216 break;
217 }
218 }
219
e3869ec7 220 DEB(kprintf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
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221
222 r = ((i >> 1) | (i << 2)) & 0x07;
223 return r;
224}
225
226static int
227cmpci_regvalue_to_rate(u_int32_t r)
228{
229 int i;
230
231 i = ((r << 1) | (r >> 2)) & 0x07;
e3869ec7 232 DEB(kprintf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
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233 return cmi_rates[i];
234}
235
236/* ------------------------------------------------------------------------- */
237/* ADC/DAC control - there are 2 dma channels on 8738, either can be
238 * playback or capture. We use ch0 for playback and ch1 for capture. */
239
240static void
241cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
242{
243 u_int32_t s, i, sz;
244
558a398b 245 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
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246
247 cmi_wr(sc, base, ch->phys_buf, 4);
248 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
249
250 s = sz / ch->bps - 1;
251 cmi_wr(sc, base + 4, s, 2);
252
253 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
254 cmi_wr(sc, base + 6, i, 2);
255}
256
257
258static void
259cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
260{
261 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
262
263 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
264 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
265 CMPCI_REG_CH0_INTR_ENABLE);
266
267 ch->dma_active = 1;
268}
269
270static u_int32_t
271cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
272{
273 u_int32_t r = ch->dma_active;
274
275 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
276 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
277 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
278 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
279 ch->dma_active = 0;
280 return r;
281}
282
283static void
284cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
285{
286 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
287 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
288 /* Enable Interrupts */
289 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
290 CMPCI_REG_CH1_INTR_ENABLE);
e3869ec7 291 DEB(kprintf("cmi_ch1_start: dma prog\n"));
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292 ch->dma_active = 1;
293}
294
295static u_int32_t
296cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
297{
298 u_int32_t r = ch->dma_active;
299
300 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
301 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
302 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
303 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
304 ch->dma_active = 0;
305 return r;
306}
307
308static void
309cmi_spdif_speed(struct sc_info *sc, int speed) {
310 u_int32_t fcr1, lcr, mcr;
311
312 if (speed >= 44100) {
313 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
314 lcr = CMPCI_REG_XSPDIF_ENABLE;
315 mcr = (speed == 48000) ?
316 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
317 } else {
318 fcr1 = mcr = lcr = 0;
319 }
320
321 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
322 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
323 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
324 CMPCI_REG_SPDIF0_ENABLE, fcr1);
325 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
326 CMPCI_REG_XSPDIF_ENABLE, lcr);
327}
328
329/* ------------------------------------------------------------------------- */
330/* Channel Interface implementation */
331
332static void *
333cmichan_init(kobj_t obj, void *devinfo,
334 struct snd_dbuf *b, struct pcm_channel *c, int dir)
335{
336 struct sc_info *sc = devinfo;
337 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
338
339 ch->parent = sc;
340 ch->channel = c;
341 ch->bps = 1;
342 ch->fmt = AFMT_U8;
343 ch->spd = DSP_DEFAULT_SPEED;
344 ch->buffer = b;
345 ch->dma_active = 0;
346 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
e3869ec7 347 DEB(kprintf("cmichan_init failed\n"));
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348 return NULL;
349 }
350
351 ch->dir = dir;
352 snd_mtxlock(sc->lock);
353 if (ch->dir == PCMDIR_PLAY) {
354 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
355 } else {
356 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
357 }
358 snd_mtxunlock(sc->lock);
359
360 return ch;
361}
362
363static int
364cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
365{
366 struct sc_chinfo *ch = data;
367 struct sc_info *sc = ch->parent;
368 u_int32_t f;
369
370 if (format & AFMT_S16_LE) {
371 f = CMPCI_REG_FORMAT_16BIT;
372 ch->bps = 2;
373 } else {
374 f = CMPCI_REG_FORMAT_8BIT;
375 ch->bps = 1;
376 }
377
378 if (format & AFMT_STEREO) {
379 f |= CMPCI_REG_FORMAT_STEREO;
380 ch->bps *= 2;
381 } else {
382 f |= CMPCI_REG_FORMAT_MONO;
383 }
384
385 snd_mtxlock(sc->lock);
386 if (ch->dir == PCMDIR_PLAY) {
387 cmi_partial_wr4(ch->parent,
388 CMPCI_REG_CHANNEL_FORMAT,
389 CMPCI_REG_CH0_FORMAT_SHIFT,
390 CMPCI_REG_CH0_FORMAT_MASK,
391 f);
392 } else {
393 cmi_partial_wr4(ch->parent,
394 CMPCI_REG_CHANNEL_FORMAT,
395 CMPCI_REG_CH1_FORMAT_SHIFT,
396 CMPCI_REG_CH1_FORMAT_MASK,
397 f);
398 }
399 snd_mtxunlock(sc->lock);
400 ch->fmt = format;
401
402 return 0;
403}
404
405static int
406cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
407{
408 struct sc_chinfo *ch = data;
409 struct sc_info *sc = ch->parent;
410 u_int32_t r, rsp;
411
412 r = cmpci_rate_to_regvalue(speed);
413 snd_mtxlock(sc->lock);
414 if (ch->dir == PCMDIR_PLAY) {
415 if (speed < 44100) {
416 /* disable if req before rate change */
417 cmi_spdif_speed(ch->parent, speed);
418 }
419 cmi_partial_wr4(ch->parent,
420 CMPCI_REG_FUNC_1,
421 CMPCI_REG_DAC_FS_SHIFT,
422 CMPCI_REG_DAC_FS_MASK,
423 r);
424 if (speed >= 44100 && ch->parent->spdif_enabled) {
425 /* enable if req after rate change */
426 cmi_spdif_speed(ch->parent, speed);
427 }
428 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
429 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
430 rsp &= CMPCI_REG_DAC_FS_MASK;
431 } else {
432 cmi_partial_wr4(ch->parent,
433 CMPCI_REG_FUNC_1,
434 CMPCI_REG_ADC_FS_SHIFT,
435 CMPCI_REG_ADC_FS_MASK,
436 r);
437 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
438 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
439 rsp &= CMPCI_REG_ADC_FS_MASK;
440 }
441 snd_mtxunlock(sc->lock);
442 ch->spd = cmpci_regvalue_to_rate(r);
443
e3869ec7 444 DEB(kprintf("cmichan_setspeed (%s) %d -> %d (%d)\n",
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445 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
446 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
447
448 return ch->spd;
449}
450
451static int
452cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
453{
454 struct sc_chinfo *ch = data;
455 struct sc_info *sc = ch->parent;
456
457 /* user has requested interrupts every blocksize bytes */
458 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
459 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
460 }
461 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
462
463 return blocksize;
464}
465
466static int
467cmichan_trigger(kobj_t obj, void *data, int go)
468{
469 struct sc_chinfo *ch = data;
470 struct sc_info *sc = ch->parent;
471
472 snd_mtxlock(sc->lock);
473 if (ch->dir == PCMDIR_PLAY) {
474 switch(go) {
475 case PCMTRIG_START:
476 cmi_ch0_start(sc, ch);
477 break;
478 case PCMTRIG_ABORT:
479 cmi_ch0_stop(sc, ch);
480 break;
481 }
482 } else {
483 switch(go) {
484 case PCMTRIG_START:
485 cmi_ch1_start(sc, ch);
486 break;
487 case PCMTRIG_ABORT:
488 cmi_ch1_stop(sc, ch);
489 break;
490 }
491 }
492 snd_mtxunlock(sc->lock);
493 return 0;
494}
495
496static int
497cmichan_getptr(kobj_t obj, void *data)
498{
499 struct sc_chinfo *ch = data;
500 struct sc_info *sc = ch->parent;
501 u_int32_t physptr, bufptr, sz;
502
503 snd_mtxlock(sc->lock);
504 if (ch->dir == PCMDIR_PLAY) {
505 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
506 } else {
507 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
508 }
509 snd_mtxunlock(sc->lock);
510
511 sz = sndbuf_getsize(ch->buffer);
512 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
513
514 return bufptr;
515}
516
517static void
518cmi_intr(void *data)
519{
520 struct sc_info *sc = data;
521 u_int32_t intrstat;
558a398b 522 u_int32_t toclear;
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523
524 snd_mtxlock(sc->lock);
525 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
558a398b 526 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
984263bc 527
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528 toclear = 0;
529 if (intrstat & CMPCI_REG_CH0_INTR) {
530 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
531 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); */
532 }
984263bc 533
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534 if (intrstat & CMPCI_REG_CH1_INTR) {
535 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
536 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); */
537 }
984263bc 538
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539 if (toclear) {
540 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
541 snd_mtxunlock(sc->lock);
984263bc 542
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543 /* Signal interrupts to channel */
544 if (intrstat & CMPCI_REG_CH0_INTR) {
545 chn_intr(sc->pch.channel);
546 }
984263bc 547
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548 if (intrstat & CMPCI_REG_CH1_INTR) {
549 chn_intr(sc->rch.channel);
550 }
984263bc 551
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552 snd_mtxlock(sc->lock);
553 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
984263bc 554
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555 }
556 }
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557 snd_mtxunlock(sc->lock);
558 return;
559}
560
561static struct pcmchan_caps *
562cmichan_getcaps(kobj_t obj, void *data)
563{
564 return &cmi_caps;
565}
566
567static kobj_method_t cmichan_methods[] = {
568 KOBJMETHOD(channel_init, cmichan_init),
569 KOBJMETHOD(channel_setformat, cmichan_setformat),
570 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
571 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
572 KOBJMETHOD(channel_trigger, cmichan_trigger),
573 KOBJMETHOD(channel_getptr, cmichan_getptr),
574 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
575 { 0, 0 }
576};
577CHANNEL_DECLARE(cmichan);
578
579/* ------------------------------------------------------------------------- */
580/* Mixer - sb16 with kinks */
581
582static void
583cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
584{
585 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
586 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
587}
588
589static u_int8_t
590cmimix_rd(struct sc_info *sc, u_int8_t port)
591{
592 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
593 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
594}
595
596struct sb16props {
597 u_int8_t rreg; /* right reg chan register */
598 u_int8_t stereo:1; /* (no explanation needed, honest) */
599 u_int8_t rec:1; /* recording source */
600 u_int8_t bits:3; /* num bits to represent maximum gain rep */
601 u_int8_t oselect; /* output select mask */
602 u_int8_t iselect; /* right input select mask */
603} static const cmt[SOUND_MIXER_NRDEVICES] = {
604 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
605 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
606 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
607 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
608 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
609 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
610 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
611 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
612 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
613 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
614 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
615 /* These controls are not implemented in CMI8738, but maybe at a
616 future date. They are not documented in C-Media documentation,
617 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
618 */
619 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
620 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
621 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
622 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
623 /* The mic pre-amp is implemented with non-SB16 compatible
624 registers. */
625 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
626};
627
628#define MIXER_GAIN_REG_RTOL(r) (r - 1)
629
630static int
631cmimix_init(struct snd_mixer *m)
632{
633 struct sc_info *sc = mix_getdevinfo(m);
634 u_int32_t i,v;
635
636 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
637 if (cmt[i].bits) v |= 1 << i;
638 }
639 mix_setdevs(m, v);
640
641 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
642 if (cmt[i].rec) v |= 1 << i;
643 }
644 mix_setrecdevs(m, v);
645
646 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
647 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
648 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
649 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
650 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
651 return 0;
652}
653
654static int
655cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
656{
657 struct sc_info *sc = mix_getdevinfo(m);
658 u_int32_t r, l, max;
659 u_int8_t v;
660
661 max = (1 << cmt[dev].bits) - 1;
662
663 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
664 /* For time being this can only be one thing (mic in
665 * mic/aux reg) */
666 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
667 l = left * max / 100;
668 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
669 v |= ((l << 1) | (~l >> 3)) & 0x0f;
670 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
671 return 0;
672 }
673
674 l = (left * max / 100) << (8 - cmt[dev].bits);
675 if (cmt[dev].stereo) {
676 r = (right * max / 100) << (8 - cmt[dev].bits);
677 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
678 cmimix_wr(sc, cmt[dev].rreg, r);
e3869ec7 679 DEBMIX(kprintf("Mixer stereo write dev %d reg 0x%02x "\
984263bc
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680 "value 0x%02x:0x%02x\n",
681 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
682 } else {
683 r = l;
684 cmimix_wr(sc, cmt[dev].rreg, l);
e3869ec7 685 DEBMIX(kprintf("Mixer mono write dev %d reg 0x%02x " \
984263bc
MD
686 "value 0x%02x:0x%02x\n",
687 dev, cmt[dev].rreg, l, l));
688 }
689
690 /* Zero gain does not mute channel from output, but this does... */
691 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
692 if (l == 0 && r == 0) {
693 v &= ~cmt[dev].oselect;
694 } else {
695 v |= cmt[dev].oselect;
696 }
697 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
698
699 return 0;
700}
701
702static int
703cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
704{
705 struct sc_info *sc = mix_getdevinfo(m);
706 u_int32_t i, ml, sl;
707
708 ml = sl = 0;
709 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
710 if ((1<<i) & src) {
711 if (cmt[i].stereo) {
712 sl |= cmt[i].iselect;
713 } else {
714 ml |= cmt[i].iselect;
715 }
716 }
717 }
718 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
e3869ec7 719 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
984263bc
MD
720 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
721 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
722 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
e3869ec7 723 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
984263bc
MD
724 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
725
726 return src;
727}
728
729/* Optional SPDIF support. */
730
731static int
732cmi_initsys(struct sc_info* sc)
733{
734#ifdef SND_DYNSYSCTL
735 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
736 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
737 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
738 &sc->spdif_enabled, 0,
739 "enable SPDIF output at 44.1 kHz and above");
740#endif /* SND_DYNSYSCTL */
741 return 0;
742}
743
744/* ------------------------------------------------------------------------- */
745static kobj_method_t cmi_mixer_methods[] = {
746 KOBJMETHOD(mixer_init, cmimix_init),
747 KOBJMETHOD(mixer_set, cmimix_set),
748 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
749 { 0, 0 }
750};
751MIXER_DECLARE(cmi_mixer);
752
753/* ------------------------------------------------------------------------- */
754/* Power and reset */
755
756static void
757cmi_power(struct sc_info *sc, int state)
758{
759 switch (state) {
760 case 0: /* full power */
761 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
762 break;
763 default:
764 /* power off */
765 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
766 break;
767 }
768}
769
770static int
771cmi_init(struct sc_info *sc)
772{
773 /* Effect reset */
774 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
775 DELAY(100);
776 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
777
778 /* Disable interrupts and channels */
779 cmi_clr4(sc, CMPCI_REG_FUNC_0,
780 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
781 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
782 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
783
784 /* Configure DMA channels, ch0 = play, ch1 = capture */
785 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
786 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
787
788 /* Attempt to enable 4 Channel output */
789 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
790
791 /* Disable SPDIF1 - not compatible with config */
792 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
793 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
794
795 return 0;
796}
797
798static void
799cmi_uninit(struct sc_info *sc)
800{
801 /* Disable interrupts and channels */
802 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
803 CMPCI_REG_CH0_INTR_ENABLE |
804 CMPCI_REG_CH1_INTR_ENABLE |
805 CMPCI_REG_TDMA_INTR_ENABLE);
806 cmi_clr4(sc, CMPCI_REG_FUNC_0,
807 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
808}
809
810/* ------------------------------------------------------------------------- */
811/* Bus and device registration */
812static int
813cmi_probe(device_t dev)
814{
815 switch(pci_get_devid(dev)) {
816 case CMI8338A_PCI_ID:
817 device_set_desc(dev, "CMedia CMI8338A");
558a398b 818 return BUS_PROBE_DEFAULT;
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819 case CMI8338B_PCI_ID:
820 device_set_desc(dev, "CMedia CMI8338B");
558a398b 821 return BUS_PROBE_DEFAULT;
984263bc
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822 case CMI8738_PCI_ID:
823 device_set_desc(dev, "CMedia CMI8738");
558a398b 824 return BUS_PROBE_DEFAULT;
984263bc
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825 case CMI8738B_PCI_ID:
826 device_set_desc(dev, "CMedia CMI8738B");
558a398b 827 return BUS_PROBE_DEFAULT;
984263bc
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828 default:
829 return ENXIO;
830 }
831}
832
833static int
834cmi_attach(device_t dev)
835{
984263bc
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836 struct sc_info *sc;
837 u_int32_t data;
838 char status[SND_STATUSLEN];
839
efda3bd0 840 sc = kmalloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
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841 if (sc == NULL) {
842 device_printf(dev, "cannot allocate softc\n");
843 return ENXIO;
844 }
845
846 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
847 data = pci_read_config(dev, PCIR_COMMAND, 2);
848 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
849 pci_write_config(dev, PCIR_COMMAND, data, 2);
850 data = pci_read_config(dev, PCIR_COMMAND, 2);
851
852 sc->dev = dev;
558a398b
SS
853 sc->regid = PCIR_BAR(0);
854 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
855 RF_ACTIVE);
984263bc
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856 if (!sc->reg) {
857 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
858 goto bad;
859 }
860 sc->st = rman_get_bustag(sc->reg);
861 sc->sh = rman_get_bushandle(sc->reg);
862
863 sc->irqid = 0;
558a398b
SS
864 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
865 RF_ACTIVE | RF_SHAREABLE);
984263bc 866 if (!sc->irq ||
558a398b 867 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
984263bc
MD
868 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
869 goto bad;
870 }
871
872 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
873
874 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
875 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
876 /*highaddr*/BUS_SPACE_MAXADDR,
877 /*filter*/NULL, /*filterarg*/NULL,
878 /*maxsize*/sc->bufsz, /*nsegments*/1,
879 /*maxsegz*/0x3ffff, /*flags*/0,
880 &sc->parent_dmat) != 0) {
881 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
882 goto bad;
883 }
884
885 cmi_power(sc, 0);
886 if (cmi_init(sc))
887 goto bad;
888
889 if (mixer_init(dev, &cmi_mixer_class, sc))
890 goto bad;
891
892 if (pcm_register(dev, sc, 1, 1))
893 goto bad;
894
895 cmi_initsys(sc);
896
897 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
898 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
899
558a398b
SS
900 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
901 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
984263bc
MD
902 pcm_setstatus(dev, status);
903
e3869ec7 904 DEB(kprintf("cmi_attach: succeeded\n"));
984263bc
MD
905 return 0;
906
907 bad:
908 if (sc->parent_dmat)
909 bus_dma_tag_destroy(sc->parent_dmat);
910 if (sc->ih)
911 bus_teardown_intr(dev, sc->irq, sc->ih);
912 if (sc->irq)
913 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
914 if (sc->reg)
915 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
916 if (sc->lock)
917 snd_mtxfree(sc->lock);
918 if (sc)
efda3bd0 919 kfree(sc, M_DEVBUF);
984263bc
MD
920
921 return ENXIO;
922}
923
924static int
925cmi_detach(device_t dev)
926{
927 struct sc_info *sc;
928 int r;
929
930 r = pcm_unregister(dev);
931 if (r) return r;
932
933 sc = pcm_getdevinfo(dev);
934 cmi_uninit(sc);
935 cmi_power(sc, 3);
936
937 bus_dma_tag_destroy(sc->parent_dmat);
938 bus_teardown_intr(dev, sc->irq, sc->ih);
939 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
940 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
941 snd_mtxfree(sc->lock);
efda3bd0 942 kfree(sc, M_DEVBUF);
984263bc
MD
943
944 return 0;
945}
946
947static int
948cmi_suspend(device_t dev)
949{
950 struct sc_info *sc = pcm_getdevinfo(dev);
951
952 snd_mtxlock(sc->lock);
953 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
954 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
955 cmi_power(sc, 3);
956 snd_mtxunlock(sc->lock);
957 return 0;
958}
959
960static int
961cmi_resume(device_t dev)
962{
963 struct sc_info *sc = pcm_getdevinfo(dev);
964
965 snd_mtxlock(sc->lock);
966 cmi_power(sc, 0);
967 if (cmi_init(sc) != 0) {
968 device_printf(dev, "unable to reinitialize the card\n");
969 snd_mtxunlock(sc->lock);
970 return ENXIO;
971 }
972
973 if (mixer_reinit(dev) == -1) {
974 device_printf(dev, "unable to reinitialize the mixer\n");
975 snd_mtxunlock(sc->lock);
976 return ENXIO;
977 }
978
979 if (sc->pch.dma_was_active) {
980 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
981 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
982 cmi_ch0_start(sc, &sc->pch);
983 }
984
985 if (sc->rch.dma_was_active) {
986 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
987 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
988 cmi_ch1_start(sc, &sc->rch);
989 }
990 snd_mtxunlock(sc->lock);
991 return 0;
992}
993
994static device_method_t cmi_methods[] = {
995 DEVMETHOD(device_probe, cmi_probe),
996 DEVMETHOD(device_attach, cmi_attach),
997 DEVMETHOD(device_detach, cmi_detach),
998 DEVMETHOD(device_resume, cmi_resume),
999 DEVMETHOD(device_suspend, cmi_suspend),
1000 { 0, 0 }
1001};
1002
1003static driver_t cmi_driver = {
1004 "pcm",
1005 cmi_methods,
1006 PCM_SOFTC_SIZE
1007};
1008
1009DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
558a398b 1010MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc 1011MODULE_VERSION(snd_cmi, 1);