Say hello to a sound system update from FreeBSD. This includes the long
[dragonfly.git] / sys / dev / sound / pci / gnu / maestro3_reg.h
CommitLineData
558a398b
SS
1/* $FreeBSD: src/sys/gnu/dev/sound/pci/maestro3_reg.h,v 1.5 2005/01/06 18:27:30 imp Exp $ */
2/* $DragonFly: src/sys/dev/sound/pci/gnu/maestro3_reg.h,v 1.3 2007/01/04 21:47:03 corecode Exp $ */
3/*-
984263bc
MD
4 * ESS Technology allegro audio driver.
5 *
6 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Hacked for the maestro3 driver by zab
23 */
24
25/* Allegro PCI configuration registers */
26#define PCI_LEGACY_AUDIO_CTRL 0x40
27#define SOUND_BLASTER_ENABLE 0x00000001
28#define FM_SYNTHESIS_ENABLE 0x00000002
29#define GAME_PORT_ENABLE 0x00000004
30#define MPU401_IO_ENABLE 0x00000008
31#define MPU401_IRQ_ENABLE 0x00000010
32#define ALIAS_10BIT_IO 0x00000020
33#define SB_DMA_MASK 0x000000C0
34#define SB_DMA_0 0x00000040
35#define SB_DMA_1 0x00000040
36#define SB_DMA_R 0x00000080
37#define SB_DMA_3 0x000000C0
38#define SB_IRQ_MASK 0x00000700
39#define SB_IRQ_5 0x00000000
40#define SB_IRQ_7 0x00000100
41#define SB_IRQ_9 0x00000200
42#define SB_IRQ_10 0x00000300
43#define MIDI_IRQ_MASK 0x00003800
44#define SERIAL_IRQ_ENABLE 0x00004000
45#define DISABLE_LEGACY 0x00008000
46
47#define PCI_ALLEGRO_CONFIG 0x50
48#define SB_ADDR_240 0x00000004
49#define MPU_ADDR_MASK 0x00000018
50#define MPU_ADDR_330 0x00000000
51#define MPU_ADDR_300 0x00000008
52#define MPU_ADDR_320 0x00000010
53#define MPU_ADDR_340 0x00000018
54#define USE_PCI_TIMING 0x00000040
55#define POSTED_WRITE_ENABLE 0x00000080
56#define DMA_POLICY_MASK 0x00000700
57#define DMA_DDMA 0x00000000
58#define DMA_TDMA 0x00000100
59#define DMA_PCPCI 0x00000200
60#define DMA_WBDMA16 0x00000400
61#define DMA_WBDMA4 0x00000500
62#define DMA_WBDMA2 0x00000600
63#define DMA_WBDMA1 0x00000700
64#define DMA_SAFE_GUARD 0x00000800
65#define HI_PERF_GP_ENABLE 0x00001000
66#define PIC_SNOOP_MODE_0 0x00002000
67#define PIC_SNOOP_MODE_1 0x00004000
68#define SOUNDBLASTER_IRQ_MASK 0x00008000
69#define RING_IN_ENABLE 0x00010000
70#define SPDIF_TEST_MODE 0x00020000
71#define CLK_MULT_MODE_SELECT_2 0x00040000
72#define EEPROM_WRITE_ENABLE 0x00080000
73#define CODEC_DIR_IN 0x00100000
74#define HV_BUTTON_FROM_GD 0x00200000
75#define REDUCED_DEBOUNCE 0x00400000
76#define HV_CTRL_ENABLE 0x00800000
77#define SPDIF_ENABLE 0x01000000
78#define CLK_DIV_SELECT 0x06000000
79#define CLK_DIV_BY_48 0x00000000
80#define CLK_DIV_BY_49 0x02000000
81#define CLK_DIV_BY_50 0x04000000
82#define CLK_DIV_RESERVED 0x06000000
83#define PM_CTRL_ENABLE 0x08000000
84#define CLK_MULT_MODE_SELECT 0x30000000
85#define CLK_MULT_MODE_SHIFT 28
86#define CLK_MULT_MODE_0 0x00000000
87#define CLK_MULT_MODE_1 0x10000000
88#define CLK_MULT_MODE_2 0x20000000
89#define CLK_MULT_MODE_3 0x30000000
90#define INT_CLK_SELECT 0x40000000
91#define INT_CLK_MULT_RESET 0x80000000
92
93/* M3 */
94#define INT_CLK_SRC_NOT_PCI 0x00100000
95#define INT_CLK_MULT_ENABLE 0x80000000
96
97#define PCI_ACPI_CONTROL 0x54
98#define PCI_ACPI_D0 0x00000000
99#define PCI_ACPI_D1 0xB4F70000
100#define PCI_ACPI_D2 0xB4F7B4F7
101
102#define PCI_USER_CONFIG 0x58
103#define EXT_PCI_MASTER_ENABLE 0x00000001
104#define SPDIF_OUT_SELECT 0x00000002
105#define TEST_PIN_DIR_CTRL 0x00000004
106#define AC97_CODEC_TEST 0x00000020
107#define TRI_STATE_BUFFER 0x00000080
108#define IN_CLK_12MHZ_SELECT 0x00000100
109#define MULTI_FUNC_DISABLE 0x00000200
110#define EXT_MASTER_PAIR_SEL 0x00000400
111#define PCI_MASTER_SUPPORT 0x00000800
112#define STOP_CLOCK_ENABLE 0x00001000
113#define EAPD_DRIVE_ENABLE 0x00002000
114#define REQ_TRI_STATE_ENABLE 0x00004000
115#define REQ_LOW_ENABLE 0x00008000
116#define MIDI_1_ENABLE 0x00010000
117#define MIDI_2_ENABLE 0x00020000
118#define SB_AUDIO_SYNC 0x00040000
119#define HV_CTRL_TEST 0x00100000
120#define SOUNDBLASTER_TEST 0x00400000
121
122#define PCI_USER_CONFIG_C 0x5C
123
124#define PCI_DDMA_CTRL 0x60
125#define DDMA_ENABLE 0x00000001
126
127
128/* Allegro registers */
129#define HOST_INT_CTRL 0x18
130#define SB_INT_ENABLE 0x0001
131#define MPU401_INT_ENABLE 0x0002
132#define ASSP_INT_ENABLE 0x0010
133#define RING_INT_ENABLE 0x0020
134#define HV_INT_ENABLE 0x0040
135#define CLKRUN_GEN_ENABLE 0x0100
136#define HV_CTRL_TO_PME 0x0400
137#define SOFTWARE_RESET_ENABLE 0x8000
138
139/*
140 * should be using the above defines, probably.
141 */
142#define REGB_ENABLE_RESET 0x01
143#define REGB_STOP_CLOCK 0x10
144
145#define HOST_INT_STATUS 0x1A
146#define SB_INT_PENDING 0x01
147#define MPU401_INT_PENDING 0x02
148#define ASSP_INT_PENDING 0x10
149#define RING_INT_PENDING 0x20
150#define HV_INT_PENDING 0x40
151
152#define HARDWARE_VOL_CTRL 0x1B
153#define SHADOW_MIX_REG_VOICE 0x1C
154#define HW_VOL_COUNTER_VOICE 0x1D
155#define SHADOW_MIX_REG_MASTER 0x1E
156#define HW_VOL_COUNTER_MASTER 0x1F
157
158#define CODEC_COMMAND 0x30
159#define CODEC_READ_B 0x80
160
161#define CODEC_STATUS 0x30
162#define CODEC_BUSY_B 0x01
163
164#define CODEC_DATA 0x32
165
166#define RING_BUS_CTRL_A 0x36
167#define RAC_PME_ENABLE 0x0100
168#define RAC_SDFS_ENABLE 0x0200
169#define LAC_PME_ENABLE 0x0400
170#define LAC_SDFS_ENABLE 0x0800
171#define SERIAL_AC_LINK_ENABLE 0x1000
172#define IO_SRAM_ENABLE 0x2000
173#define IIS_INPUT_ENABLE 0x8000
174
175#define RING_BUS_CTRL_B 0x38
176#define SECOND_CODEC_ID_MASK 0x0003
177#define SPDIF_FUNC_ENABLE 0x0010
178#define SECOND_AC_ENABLE 0x0020
179#define SB_MODULE_INTF_ENABLE 0x0040
180#define SSPE_ENABLE 0x0040
181#define M3I_DOCK_ENABLE 0x0080
182
183#define SDO_OUT_DEST_CTRL 0x3A
184#define COMMAND_ADDR_OUT 0x0003
185#define PCM_LR_OUT_LOCAL 0x0000
186#define PCM_LR_OUT_REMOTE 0x0004
187#define PCM_LR_OUT_MUTE 0x0008
188#define PCM_LR_OUT_BOTH 0x000C
189#define LINE1_DAC_OUT_LOCAL 0x0000
190#define LINE1_DAC_OUT_REMOTE 0x0010
191#define LINE1_DAC_OUT_MUTE 0x0020
192#define LINE1_DAC_OUT_BOTH 0x0030
193#define PCM_CLS_OUT_LOCAL 0x0000
194#define PCM_CLS_OUT_REMOTE 0x0040
195#define PCM_CLS_OUT_MUTE 0x0080
196#define PCM_CLS_OUT_BOTH 0x00C0
197#define PCM_RLF_OUT_LOCAL 0x0000
198#define PCM_RLF_OUT_REMOTE 0x0100
199#define PCM_RLF_OUT_MUTE 0x0200
200#define PCM_RLF_OUT_BOTH 0x0300
201#define LINE2_DAC_OUT_LOCAL 0x0000
202#define LINE2_DAC_OUT_REMOTE 0x0400
203#define LINE2_DAC_OUT_MUTE 0x0800
204#define LINE2_DAC_OUT_BOTH 0x0C00
205#define HANDSET_OUT_LOCAL 0x0000
206#define HANDSET_OUT_REMOTE 0x1000
207#define HANDSET_OUT_MUTE 0x2000
208#define HANDSET_OUT_BOTH 0x3000
209#define IO_CTRL_OUT_LOCAL 0x0000
210#define IO_CTRL_OUT_REMOTE 0x4000
211#define IO_CTRL_OUT_MUTE 0x8000
212#define IO_CTRL_OUT_BOTH 0xC000
213
214#define SDO_IN_DEST_CTRL 0x3C
215#define STATUS_ADDR_IN 0x0003
216#define PCM_LR_IN_LOCAL 0x0000
217#define PCM_LR_IN_REMOTE 0x0004
218#define PCM_LR_RESERVED 0x0008
219#define PCM_LR_IN_BOTH 0x000C
220#define LINE1_ADC_IN_LOCAL 0x0000
221#define LINE1_ADC_IN_REMOTE 0x0010
222#define LINE1_ADC_IN_MUTE 0x0020
223#define MIC_ADC_IN_LOCAL 0x0000
224#define MIC_ADC_IN_REMOTE 0x0040
225#define MIC_ADC_IN_MUTE 0x0080
226#define LINE2_DAC_IN_LOCAL 0x0000
227#define LINE2_DAC_IN_REMOTE 0x0400
228#define LINE2_DAC_IN_MUTE 0x0800
229#define HANDSET_IN_LOCAL 0x0000
230#define HANDSET_IN_REMOTE 0x1000
231#define HANDSET_IN_MUTE 0x2000
232#define IO_STATUS_IN_LOCAL 0x0000
233#define IO_STATUS_IN_REMOTE 0x4000
234
235#define SPDIF_IN_CTRL 0x3E
236#define SPDIF_IN_ENABLE 0x0001
237
238#define GPIO_DATA 0x60
239#define GPIO_DATA_MASK 0x0FFF
240#define GPIO_HV_STATUS 0x3000
241#define GPIO_PME_STATUS 0x4000
242
243#define GPIO_MASK 0x64
244#define GPIO_DIRECTION 0x68
245#define GPO_PRIMARY_AC97 0x0001
246#define GPI_LINEOUT_SENSE 0x0004
247#define GPO_SECONDARY_AC97 0x0008
248#define GPI_VOL_DOWN 0x0010
249#define GPI_VOL_UP 0x0020
250#define GPI_IIS_CLK 0x0040
251#define GPI_IIS_LRCLK 0x0080
252#define GPI_IIS_DATA 0x0100
253#define GPI_DOCKING_STATUS 0x0100
254#define GPI_HEADPHONE_SENSE 0x0200
255#define GPO_EXT_AMP_SHUTDOWN 0x1000
256
257/* M3 */
258#define GPO_M3_EXT_AMP_SHUTDN 0x0002
259
260#define ASSP_INDEX_PORT 0x80
261#define ASSP_MEMORY_PORT 0x82
262#define ASSP_DATA_PORT 0x84
263
264#define MPU401_DATA_PORT 0x98
265#define MPU401_STATUS_PORT 0x99
266
267#define CLK_MULT_DATA_PORT 0x9C
268
269#define ASSP_CONTROL_A 0xA2
270#define ASSP_0_WS_ENABLE 0x01
271#define ASSP_CTRL_A_RESERVED1 0x02
272#define ASSP_CTRL_A_RESERVED2 0x04
273#define ASSP_CLK_49MHZ_SELECT 0x08
274#define FAST_PLU_ENABLE 0x10
275#define ASSP_CTRL_A_RESERVED3 0x20
276#define DSP_CLK_36MHZ_SELECT 0x40
277
278#define ASSP_CONTROL_B 0xA4
279#define RESET_ASSP 0x00
280#define RUN_ASSP 0x01
281#define ENABLE_ASSP_CLOCK 0x00
282#define STOP_ASSP_CLOCK 0x10
283#define RESET_TOGGLE 0x40
284
285#define ASSP_CONTROL_C 0xA6
286#define ASSP_HOST_INT_ENABLE 0x01
287#define FM_ADDR_REMAP_DISABLE 0x02
288#define HOST_WRITE_PORT_ENABLE 0x08
289
290#define ASSP_HOST_INT_STATUS 0xAC
291#define DSP2HOST_REQ_PIORECORD 0x01
292#define DSP2HOST_REQ_I2SRATE 0x02
293#define DSP2HOST_REQ_TIMER 0x04
294
295/* AC97 registers */
296/* XXX fix this crap up */
297/*#define AC97_RESET 0x00*/
298
299#define AC97_VOL_MUTE_B 0x8000
300#define AC97_VOL_M 0x1F
301#define AC97_LEFT_VOL_S 8
302
303#define AC97_MASTER_VOL 0x02
304#define AC97_LINE_LEVEL_VOL 0x04
305#define AC97_MASTER_MONO_VOL 0x06
306#define AC97_PC_BEEP_VOL 0x0A
307#define AC97_PC_BEEP_VOL_M 0x0F
308#define AC97_SROUND_MASTER_VOL 0x38
309#define AC97_PC_BEEP_VOL_S 1
310
311/*#define AC97_PHONE_VOL 0x0C
312#define AC97_MIC_VOL 0x0E*/
313#define AC97_MIC_20DB_ENABLE 0x40
314
315/*#define AC97_LINEIN_VOL 0x10
316#define AC97_CD_VOL 0x12
317#define AC97_VIDEO_VOL 0x14
318#define AC97_AUX_VOL 0x16*/
319#define AC97_PCM_OUT_VOL 0x18
320/*#define AC97_RECORD_SELECT 0x1A*/
321#define AC97_RECORD_MIC 0x00
322#define AC97_RECORD_CD 0x01
323#define AC97_RECORD_VIDEO 0x02
324#define AC97_RECORD_AUX 0x03
325#define AC97_RECORD_MONO_MUX 0x02
326#define AC97_RECORD_DIGITAL 0x03
327#define AC97_RECORD_LINE 0x04
328#define AC97_RECORD_STEREO 0x05
329#define AC97_RECORD_MONO 0x06
330#define AC97_RECORD_PHONE 0x07
331
332/*#define AC97_RECORD_GAIN 0x1C*/
333#define AC97_RECORD_VOL_M 0x0F
334
335/*#define AC97_GENERAL_PURPOSE 0x20*/
336#define AC97_POWER_DOWN_CTRL 0x26
337#define AC97_ADC_READY 0x0001
338#define AC97_DAC_READY 0x0002
339#define AC97_ANALOG_READY 0x0004
340#define AC97_VREF_ON 0x0008
341#define AC97_PR0 0x0100
342#define AC97_PR1 0x0200
343#define AC97_PR2 0x0400
344#define AC97_PR3 0x0800
345#define AC97_PR4 0x1000
346
347#define AC97_RESERVED1 0x28
348
349#define AC97_VENDOR_TEST 0x5A
350
351#define AC97_CLOCK_DELAY 0x5C
352#define AC97_LINEOUT_MUX_SEL 0x0001
353#define AC97_MONO_MUX_SEL 0x0002
354#define AC97_CLOCK_DELAY_SEL 0x1F
355#define AC97_DAC_CDS_SHIFT 6
356#define AC97_ADC_CDS_SHIFT 11
357
358#define AC97_MULTI_CHANNEL_SEL 0x74
359
360/*#define AC97_VENDOR_ID1 0x7C
361#define AC97_VENDOR_ID2 0x7E*/
362
363/*
364 * ASSP control regs
365 */
366#define DSP_PORT_TIMER_COUNT 0x06
367
368#define DSP_PORT_MEMORY_INDEX 0x80
369
370#define DSP_PORT_MEMORY_TYPE 0x82
371#define MEMTYPE_INTERNAL_CODE 0x0002
372#define MEMTYPE_INTERNAL_DATA 0x0003
373#define MEMTYPE_MASK 0x0003
374
375#define DSP_PORT_MEMORY_DATA 0x84
376
377#define DSP_PORT_CONTROL_REG_A 0xA2
378#define DSP_PORT_CONTROL_REG_B 0xA4
379#define DSP_PORT_CONTROL_REG_C 0xA6
380
381#define REV_A_CODE_MEMORY_BEGIN 0x0000
382#define REV_A_CODE_MEMORY_END 0x0FFF
383#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
384#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
385
386#define REV_B_CODE_MEMORY_BEGIN 0x0000
387#define REV_B_CODE_MEMORY_END 0x0BFF
388#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
389#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
390
391#define REV_A_DATA_MEMORY_BEGIN 0x1000
392#define REV_A_DATA_MEMORY_END 0x2FFF
393#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
394#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
395
396#define REV_B_DATA_MEMORY_BEGIN 0x1000
397#define REV_B_DATA_MEMORY_END 0x2BFF
398#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
399#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
400
401
402#define NUM_UNITS_KERNEL_CODE 16
403#define NUM_UNITS_KERNEL_DATA 2
404
405#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
406#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
407
408/*
409 * Kernel data layout
410 */
411
412#define DP_SHIFT_COUNT 7
413
414#define KDATA_BASE_ADDR 0x1000
415#define KDATA_BASE_ADDR2 0x1080
416
417#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
418#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
419#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
420#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
421#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
422#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
423#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
424#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
425#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
426
427#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
428#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
429
430#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
431#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
432#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
433#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
434#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
435#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
436#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
437#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
438#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
439#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
440
441#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
442#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
443
444#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
445#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
446
447#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
448#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
449
450#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
451#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
452#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
453
454#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
455#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
456#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
457#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
458#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
459
460#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
461#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
462#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
463
464#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
465#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
466#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
467
468#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
469#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
470#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
471#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
472#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
473#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
474#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
475#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
476#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
477#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
478
479#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
480#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
481#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
482
483#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
484#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
485
486#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
487#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
488#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
489
490#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
491#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
492#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
493#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
494#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
495#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
496
497#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
498#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
499#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
500#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
501#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
502#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
503
504#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
505#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
506#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
507#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
508#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
509#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
510
511#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
512#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
513#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
514#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
515
516#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
517#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
518
519#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
520#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
521
522#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
523#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
524#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
525#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
526#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
527
528#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
529#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
530
531#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
532#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
533#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
534
535#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
536#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
537
538#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
539
540#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
541#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
542#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
543#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
544#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
545#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
546#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
547#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
548#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
549#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
550#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
551#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
552
553#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
554#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
555#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
556#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
557
558#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
559#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
560
561#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
562#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
563#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
564#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
565
566#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
567#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
568#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
569#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
570#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
571
572/*
573 * second 'segment' (?) reserved for mixer
574 * buffers..
575 */
576
577#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
578#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
579#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
580#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
581#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
582#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
583#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
584#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
585#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
586#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
587#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
588#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
589#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
590#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
591#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
592#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
593
594#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
595#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
596#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
597#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
598#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
599#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
600#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
601#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
602#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
603#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
604#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
605
606#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
607#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
608#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
609#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
610#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
611#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
612
613#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
614#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
615#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
616#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
617
618/*
619 * client data area offsets
620 */
621#define CDATA_INSTANCE_READY 0x00
622
623#define CDATA_HOST_SRC_ADDRL 0x01
624#define CDATA_HOST_SRC_ADDRH 0x02
625#define CDATA_HOST_SRC_END_PLUS_1L 0x03
626#define CDATA_HOST_SRC_END_PLUS_1H 0x04
627#define CDATA_HOST_SRC_CURRENTL 0x05
628#define CDATA_HOST_SRC_CURRENTH 0x06
629
630#define CDATA_IN_BUF_CONNECT 0x07
631#define CDATA_OUT_BUF_CONNECT 0x08
632
633#define CDATA_IN_BUF_BEGIN 0x09
634#define CDATA_IN_BUF_END_PLUS_1 0x0A
635#define CDATA_IN_BUF_HEAD 0x0B
636#define CDATA_IN_BUF_TAIL 0x0C
637#define CDATA_OUT_BUF_BEGIN 0x0D
638#define CDATA_OUT_BUF_END_PLUS_1 0x0E
639#define CDATA_OUT_BUF_HEAD 0x0F
640#define CDATA_OUT_BUF_TAIL 0x10
641
642#define CDATA_DMA_CONTROL 0x11
643#define CDATA_RESERVED 0x12
644
645#define CDATA_FREQUENCY 0x13
646#define CDATA_LEFT_VOLUME 0x14
647#define CDATA_RIGHT_VOLUME 0x15
648#define CDATA_LEFT_SUR_VOL 0x16
649#define CDATA_RIGHT_SUR_VOL 0x17
650
651#define CDATA_HEADER_LEN 0x18
652
653#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
654#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
655#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
656#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
657#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
658#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
659#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
660#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
661
662#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
663#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
664#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
665#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
666#define MINISRC_BIQUAD_STAGE 2
667#define MINISRC_COEF_LOC 0X175
668
669#define DMACONTROL_BLOCK_MASK 0x000F
670#define DMAC_BLOCK0_SELECTOR 0x0000
671#define DMAC_BLOCK1_SELECTOR 0x0001
672#define DMAC_BLOCK2_SELECTOR 0x0002
673#define DMAC_BLOCK3_SELECTOR 0x0003
674#define DMAC_BLOCK4_SELECTOR 0x0004
675#define DMAC_BLOCK5_SELECTOR 0x0005
676#define DMAC_BLOCK6_SELECTOR 0x0006
677#define DMAC_BLOCK7_SELECTOR 0x0007
678#define DMAC_BLOCK8_SELECTOR 0x0008
679#define DMAC_BLOCK9_SELECTOR 0x0009
680#define DMAC_BLOCKA_SELECTOR 0x000A
681#define DMAC_BLOCKB_SELECTOR 0x000B
682#define DMAC_BLOCKC_SELECTOR 0x000C
683#define DMAC_BLOCKD_SELECTOR 0x000D
684#define DMAC_BLOCKE_SELECTOR 0x000E
685#define DMAC_BLOCKF_SELECTOR 0x000F
686#define DMACONTROL_PAGE_MASK 0x00F0
687#define DMAC_PAGE0_SELECTOR 0x0030
688#define DMAC_PAGE1_SELECTOR 0x0020
689#define DMAC_PAGE2_SELECTOR 0x0010
690#define DMAC_PAGE3_SELECTOR 0x0000
691#define DMACONTROL_AUTOREPEAT 0x1000
692#define DMACONTROL_STOPPED 0x2000
693#define DMACONTROL_DIRECTION 0x0100