hptmv(4): Reduce si_iosize_max to 64KB.
[dragonfly.git] / sys / dev / raid / hptmv / entry.c
CommitLineData
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1/*
2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/hptmv/entry.c,v 1.23 2010/06/19 13:42:14 mav Exp $
27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/bus.h>
33#include <sys/malloc.h>
34#include <sys/resource.h>
35#include <sys/time.h>
36#include <sys/callout.h>
37#include <sys/signalvar.h>
38#include <sys/eventhandler.h>
39#include <sys/proc.h>
40#include <sys/kthread.h>
41
42#include <sys/lock.h>
43#include <sys/module.h>
44
45#include <bus/pci/pcireg.h>
46#include <bus/pci/pcivar.h>
47
48#ifndef __KERNEL__
49#define __KERNEL__
50#endif
51
52#include <dev/raid/hptmv/global.h>
53#include <dev/raid/hptmv/hptintf.h>
54#include <dev/raid/hptmv/osbsd.h>
55#include <dev/raid/hptmv/access601.h>
56
57
58#ifdef DEBUG
59#ifdef DEBUG_LEVEL
60int hpt_dbg_level = DEBUG_LEVEL;
61#else
62int hpt_dbg_level = 0;
63#endif
64#endif
65
66#define MV_ERROR kprintf
67
68/*
69 * CAM SIM entry points
70 */
71static int hpt_probe (device_t dev);
72static void launch_worker_thread(void);
73static int hpt_attach(device_t dev);
74static int hpt_detach(device_t dev);
75static int hpt_shutdown(device_t dev);
76static void hpt_poll(struct cam_sim *sim);
77static void hpt_intr(void *arg);
78static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
79static void hpt_action(struct cam_sim *sim, union ccb *ccb);
80
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81static struct thread *hptdaemonproc;
82
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83static device_method_t driver_methods[] = {
84 /* Device interface */
85 DEVMETHOD(device_probe, hpt_probe),
86 DEVMETHOD(device_attach, hpt_attach),
87 DEVMETHOD(device_detach, hpt_detach),
88
89 DEVMETHOD(device_shutdown, hpt_shutdown),
90 { 0, 0 }
91};
92
93static driver_t hpt_pci_driver = {
94 __str(PROC_DIR_NAME),
95 driver_methods,
96 sizeof(IAL_ADAPTER_T)
97};
98
99static devclass_t hpt_devclass;
100
101#define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
102__DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
103
104#define ccb_ccb_ptr spriv_ptr0
105#define ccb_adapter ccb_h.spriv_ptr1
106
107static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
108static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
109static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
110static void ccb_done(union ccb *ccb);
111static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
112static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
113static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
114static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
115static void handleEdmaError(_VBUS_ARG PCommand pCmd);
116static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
117static int fResetActiveCommands(PVBus _vbus_p);
118static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
119static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
120static void hptmv_handle_event_disconnect(void *data);
121static void hptmv_handle_event_connect(void *data);
122static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
123static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
124static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
125static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
126 int logical);
127static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
128 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
129 MV_U16 responseFlags, MV_U32 timeStamp,
130 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
131static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
132 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
133
134#define ccb_ccb_ptr spriv_ptr0
135#define ccb_adapter ccb_h.spriv_ptr1
136
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137IAL_ADAPTER_T *gIal_Adapter = NULL;
138IAL_ADAPTER_T *pCurAdapter = NULL;
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139static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
140
141typedef struct st_HPT_DPC {
142 IAL_ADAPTER_T *pAdapter;
143 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
144 void *arg;
145 UCHAR flags;
146} ST_HPT_DPC;
147
148#define MAX_DPC 16
149UCHAR DPC_Request_Nums = 0;
150static ST_HPT_DPC DpcQueue[MAX_DPC];
151static int DpcQueue_First=0;
152static int DpcQueue_Last = 0;
153
154char DRIVER_VERSION[] = "v1.16";
155
156static struct lock driver_lock;
c898d682 157void lock_driver(void)
35878b55 158{
35878b55 159 lockmgr(&driver_lock, LK_EXCLUSIVE);
35878b55 160}
c898d682 161void unlock_driver(void)
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162{
163 lockmgr(&driver_lock, LK_RELEASE);
164}
165
166/*******************************************************************************
167 * Name: hptmv_free_channel
168 *
169 * Description: free allocated queues for the given channel
170 *
171 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this
172 * channel connected to.
173 * channelNum - channel number.
174 *
175 ******************************************************************************/
176static void
177hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
178{
179 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
180 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
181}
182
183static void failDevice(PVDevice pVDev)
184{
185 PVBus _vbus_p = pVDev->pVBus;
186 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
187
188 pVDev->u.disk.df_on_line = 0;
189 pVDev->vf_online = 0;
190 if (pVDev->pfnDeviceFailed)
191 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
192
193 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
194
195#ifndef FOR_DEMO
196 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
197 pAdapter->beeping = 1;
198 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
199 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
200 }
201#endif
202}
203
204int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
205
206static void
207handleEdmaError(_VBUS_ARG PCommand pCmd)
208{
209 PDevice pDevice = &pCmd->pVDevice->u.disk;
210 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
211
212 if (!pDevice->df_on_line) {
213 KdPrint(("Device is offline"));
214 pCmd->Result = RETURN_BAD_DEVICE;
215 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
216 return;
217 }
218
219 if (pCmd->RetryCount++>5) {
220 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
221failed:
222 failDevice(pCmd->pVDevice);
223 pCmd->Result = RETURN_IDE_ERROR;
224 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
225 return;
226 }
227
228 /* reset the channel and retry the command */
229 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
230 goto failed;
231
232 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
233
234 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
235 fDeviceSendCommand(_VBUS_P pCmd);
236}
237
238/****************************************************************
239 * Name: hptmv_init_channel
240 *
241 * Description: allocate request and response queues for the EDMA of the
242 * given channel and sets other fields.
243 *
244 * Parameters:
245 * pAdapter - pointer to the emulated adapter data structure
246 * channelNum - channel number.
247 * Return: 0 on success, otherwise on failure
248 ****************************************************************/
249static int
250hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
251{
252 MV_SATA_CHANNEL *pMvSataChannel;
253 dma_addr_t req_dma_addr;
254 dma_addr_t rsp_dma_addr;
255
256 if (channelNum >= MV_SATA_CHANNELS_NUM)
257 {
258 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
259 pAdapter->mvSataAdapter.adapterId, channelNum);
260 return -1;
261 }
262
263 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
264 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
265 pMvSataChannel->channelNumber = channelNum;
266 pMvSataChannel->lba48Address = MV_FALSE;
267 pMvSataChannel->maxReadTransfer = MV_FALSE;
268
269 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
270 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
271 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
272
273
274 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
275
276 /* check the 1K alignment of the request queue*/
277 if (req_dma_addr & 0x3ff)
278 {
279 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
280 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
281 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
282 return -1;
283 }
284 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
285 pMvSataChannel->requestQueuePciHiAddress = 0;
286 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
287 pAdapter->mvSataAdapter.adapterId, channelNum,
288 pMvSataChannel->requestQueue));
289 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
290 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
291 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
292
293 /* check the 256 alignment of the response queue*/
294 if (rsp_dma_addr & 0xff)
295 {
296 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
297 "aligned, dma_addr=%llx\n",
298 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
299 return -1;
300 }
301 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
302 pMvSataChannel->responseQueuePciHiAddress = 0;
303 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
304 pAdapter->mvSataAdapter.adapterId, channelNum,
305 pMvSataChannel->responseQueue));
306
307 pAdapter->mvChannel[channelNum].online = MV_TRUE;
308 return 0;
309}
310
311/******************************************************************************
312 * Name: hptmv_parse_identify_results
313 *
314 * Description: this functions parses the identify command results, checks
315 * that the connected deives can be accesed by RR18xx EDMA,
316 * and updates the channel stucture accordingly.
317 *
318 * Parameters: pMvSataChannel, pointer to the channel data structure.
319 *
320 * Returns: =0 ->success, < 0 ->failure.
321 *
322 ******************************************************************************/
323static int
324hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
325{
326 MV_U16 *iden = pMvSataChannel->identifyDevice;
327
328 /*LBA addressing*/
329 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
330 {
331 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
332 return -1;
333 }
334 else
335 {
336 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
337 }
338 /*DMA support*/
339 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
340 {
341 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
342 return -1;
343 }
344 else
345 {
346 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
347 }
348 /* PIO */
349 if ((iden[IDEN_VALID] & 2) == 0)
350 {
351 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
352 return -1;
353 }
354 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
355 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
356
357 /*UDMA*/
358 if ((iden[IDEN_VALID] & 4) == 0)
359 {
360 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
361 return -1;
362 }
363
364 /* 48 bit address */
365 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
366 {
367 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
368 pMvSataChannel->lba48Address = MV_TRUE;
369 }
370 else
371 {
372 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
373 pMvSataChannel->lba48Address = MV_FALSE;
374 }
375 return 0;
376}
377
378static void
379init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
380{
381 PVDevice pVDev = &pAdapter->VDevices[channel];
382 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
383 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
384
385 pMvSataChannel->outstandingCommands = 0;
386
387 pVDev->u.disk.mv = pMvSataChannel;
388 pVDev->u.disk.df_on_line = 1;
389 pVDev->u.disk.pVBus = &pAdapter->VBus;
390 pVDev->pVBus = &pAdapter->VBus;
391
392#ifdef SUPPORT_48BIT_LBA
393 if (pMvSataChannel->lba48Address == MV_TRUE)
394 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
395 else
396#endif
397 if(IdentifyData[53] & 1) {
398 pVDev->u.disk.dDeRealCapacity =
399 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
400 (IdentifyData[61]<<16 | IdentifyData[60]) :
401 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
402 } else
403 pVDev->u.disk.dDeRealCapacity =
404 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
405
406 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
407 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
408
409 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
410 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
411 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
412 }
413}
414
415static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
416{
417 PVDevice pVDev;
418 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
419 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
420
421 if (!pMvSataChannel) return;
422
423 if (plugged)
424 {
425 pVDev = &(pAdapter->VDevices[channelIndex]);
426 init_vdev_params(pAdapter, channelIndex);
427
428 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
429 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
430
431 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
432 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
433 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
434 pVDev->vf_online = 1;
435
436#ifdef SUPPORT_ARRAY
437 if(pVDev->pParent)
438 {
439 int iMember;
440 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
441 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
442 pVDev->pParent->u.array.pMember[iMember] = NULL;
443 pVDev->pParent = NULL;
444 }
445#endif
446 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
447 fCheckBootable(pVDev);
448 RegisterVDevice(pVDev);
449
450#ifndef FOR_DEMO
451 if (pAdapter->beeping) {
452 pAdapter->beeping = 0;
453 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
454 }
455#endif
456
457 }
458 else
459 {
460 pVDev = &(pAdapter->VDevices[channelIndex]);
461 failDevice(pVDev);
462 }
463}
464
465static int
466start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
467{
468 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
469 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
470 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
471 MV_U32 udmaMode,pioMode;
472
473 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
474 channelNum));
475
476
477 /* Software reset channel */
478 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
479 {
480 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
481 pMvSataAdapter->adapterId, channelNum);
482 return -1;
483 }
484
485 /* Hardware reset channel */
486 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
487 {
488 /* If failed, try again - this is when trying to hardreset a channel */
489 /* when drive is just spinning up */
490 StallExec(5000000); /* wait 5 sec before trying again */
491 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
492 {
493 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
494 pMvSataAdapter->adapterId, channelNum);
495 return -1;
496 }
497 }
498
499 /* identify device*/
500 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
501 {
502 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
503 , pMvSataAdapter->adapterId, channelNum);
504 return -1;
505 }
506 if (hptmv_parse_identify_results(pMvSataChannel))
507 {
508 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
509 , pMvSataAdapter->adapterId, channelNum);
510 return -1;
511 }
512
513 /* mvStorageDevATASetFeatures */
514 /* Disable 8 bit PIO in case CFA enabled */
515 if (pMvSataChannel->identifyDevice[86] & 4)
516 {
517 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
518 pMvSataAdapter->adapterId));
519 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
520 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
521 0, 0, 0) == MV_FALSE)
522 {
523 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
524 " failed\n", pMvSataAdapter->adapterId, channelNum);
525 return -1;
526 }
527 }
528 /* Write cache */
529#ifdef ENABLE_WRITE_CACHE
530 if (pMvSataChannel->identifyDevice[82] & 0x20)
531 {
532 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
533 {
534 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
535 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
536 0, 0, 0) == MV_FALSE)
537 {
538 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
539 pMvSataAdapter->adapterId, channelNum);
540 return -1;
541 }
542 }
543 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
544 pMvSataAdapter->adapterId, channelNum));
545 }
546 else
547 {
548 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
549 pMvSataAdapter->adapterId, channelNum));
550 }
551#else /* disable write cache */
552 {
553 if (pMvSataChannel->identifyDevice[85] & 0x20)
554 {
555 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
556 pMvSataAdapter->adapterId, channelNum));
557 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
558 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
559 0, 0, 0) == MV_FALSE)
560 {
561 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
562 pMvSataAdapter->adapterId, channelNum);
563 return -1;
564 }
565 }
566 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
567 pMvSataAdapter->adapterId, channelNum));
568 }
569#endif
570
571 /* Set transfer mode */
572 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
573 pMvSataAdapter->adapterId));
574 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
575 MV_ATA_SET_FEATURES_TRANSFER,
576 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
577 MV_FALSE)
578 {
579 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
580 pMvSataAdapter->adapterId, channelNum);
581 return -1;
582 }
583
584 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
585 {
586 pioMode = MV_ATA_TRANSFER_PIO_4;
587 }
588 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
589 {
590 pioMode = MV_ATA_TRANSFER_PIO_3;
591 }
592 else
593 {
594 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
595 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
596 }
597
598 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
599 pMvSataAdapter->adapterId));
600 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
601 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
602 MV_ATA_SET_FEATURES_TRANSFER,
603 pioMode, 0, 0, 0) == MV_FALSE)
604 {
605 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
606 pMvSataAdapter->adapterId, channelNum);
607 return -1;
608 }
609
610 udmaMode = MV_ATA_TRANSFER_UDMA_0;
611 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
612 {
613 udmaMode = MV_ATA_TRANSFER_UDMA_6;
614 }
615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
616 {
617 udmaMode = MV_ATA_TRANSFER_UDMA_5;
618 }
619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
620 {
621 udmaMode = MV_ATA_TRANSFER_UDMA_4;
622 }
623 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
624 {
625 udmaMode = MV_ATA_TRANSFER_UDMA_3;
626 }
627 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
628 {
629 udmaMode = MV_ATA_TRANSFER_UDMA_2;
630 }
631
632 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
633 pMvSataAdapter->adapterId, udmaMode & 0xf));
634 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
635
636 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
637 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
638 0, 0, 0) == MV_FALSE)
639 {
640 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
641 pMvSataAdapter->adapterId, channelNum);
642 return -1;
643 }*/
644 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
645 return TRUE;
646 else
647 do
648 {
649 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
650 MV_ATA_SET_FEATURES_TRANSFER,
651 pChannelInfo->maxUltraDmaModeSupported,
652 0, 0, 0) == MV_FALSE)
653 {
654 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
655 {
656 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
657 {
658 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
659 pMvSataChannel->eDmaRegsOffset +
660 0x11c, /* command reg */
661 MV_ATA_COMMAND_IDLE_IMMEDIATE);
662 mvMicroSecondsDelay(10000);
663 mvSataChannelHardReset(pMvSataAdapter, channelNum);
664 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
665 return FALSE;
666 }
667 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
668 return FALSE;
669 pChannelInfo->maxUltraDmaModeSupported--;
670 continue;
671 }
672 else return FALSE;
673 }
674 break;
675 }while (1);
676
677 /* Read look ahead */
678#ifdef ENABLE_READ_AHEAD
679 if (pMvSataChannel->identifyDevice[82] & 0x40)
680 {
681 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
682 {
683 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
684 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
685 0, 0) == MV_FALSE)
686 {
687 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
688 pMvSataAdapter->adapterId, channelNum);
689 return -1;
690 }
691 }
692 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
693 pMvSataAdapter->adapterId, channelNum));
694 }
695 else
696 {
697 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
698 pMvSataAdapter->adapterId, channelNum));
699 }
700#else
701 {
702 if (pMvSataChannel->identifyDevice[86] & 0x20)
703 {
704 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
705 pMvSataAdapter->adapterId, channelNum));
706 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
707 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
708 0, 0) == MV_FALSE)
709 {
710 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
711 pMvSataAdapter->adapterId, channelNum);
712 return -1;
713 }
714 }
715 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
716 pMvSataAdapter->adapterId, channelNum));
717 }
718#endif
719
720
721 {
722 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
723 pMvSataAdapter->adapterId,
724 channelNum));
725 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
726 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
727 {
728 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
729 pMvSataAdapter->adapterId, channelNum);
730 return -1;
731 }
732 }
733 /* Enable EDMA */
734 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
735 {
736 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
737 pMvSataAdapter->adapterId, channelNum);
738 return -1;
739 }
740 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
741 pMvSataAdapter->adapterId, channelNum);
742
743#ifndef FOR_DEMO
744 set_fail_led(pMvSataAdapter, channelNum, 0);
745#endif
746 return 0;
747}
748
749static void
750hptmv_handle_event(void * data, int flag)
751{
752 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
753 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
754 MV_U8 channelIndex;
755
756/* mvOsSemTake(&pMvSataAdapter->semaphore); */
757 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
758 {
759 switch(pAdapter->sataEvents[channelIndex])
760 {
761 case SATA_EVENT_CHANNEL_CONNECTED:
762 /* Handle only connects */
763 if (flag == 1)
764 break;
765 KdPrint(("RR18xx [%d,%d]: new device connected\n",
766 pMvSataAdapter->adapterId, channelIndex));
767 hptmv_init_channel(pAdapter, channelIndex);
768 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
769 {
770 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
771 pMvSataAdapter->adapterId, channelIndex);
772 hptmv_free_channel(pAdapter, channelIndex);
773 }
774 else
775 {
776 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
777 if (start_channel( pAdapter, channelIndex))
778 {
779 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
780 pMvSataAdapter->adapterId, channelIndex);
781 hptmv_free_channel(pAdapter, channelIndex);
782 }
783 else
784 {
785 device_change(pAdapter, channelIndex, TRUE);
786 }
787 }
788 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
789 break;
790
791 case SATA_EVENT_CHANNEL_DISCONNECTED:
792 /* Handle only disconnects */
793 if (flag == 0)
794 break;
795 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
796 pMvSataAdapter->adapterId, channelIndex));
797 /* Flush pending commands */
798 if(pMvSataAdapter->sataChannel[channelIndex])
799 {
800 _VBUS_INST(&pAdapter->VBus)
801 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
802 MV_FLUSH_TYPE_CALLBACK);
803 CheckPendingCall(_VBUS_P0);
804 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
805 hptmv_free_channel(pAdapter, channelIndex);
806 pMvSataAdapter->sataChannel[channelIndex] = NULL;
807 KdPrint(("RR18xx [%d,%d]: channel removed\n",
808 pMvSataAdapter->adapterId, channelIndex));
809 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
810 Check_Idle_Call(pAdapter);
811 }
812 else
813 {
814 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
815 pMvSataAdapter->adapterId, channelIndex));
816 }
817 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
818 break;
819
820 case SATA_EVENT_NO_CHANGE:
821 break;
822
823 default:
824 break;
825 }
826 }
827/* mvOsSemRelease(&pMvSataAdapter->semaphore); */
828}
829
830#define EVENT_CONNECT 1
831#define EVENT_DISCONNECT 0
832
833static void
834hptmv_handle_event_connect(void *data)
835{
836 hptmv_handle_event (data, 0);
837}
838
839static void
840hptmv_handle_event_disconnect(void *data)
841{
842 hptmv_handle_event (data, 1);
843}
844
845static MV_BOOLEAN
846hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
847 MV_U32 param1, MV_U32 param2)
848{
849 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
850
851 switch (eventType)
852 {
853 case MV_EVENT_TYPE_SATA_CABLE:
854 {
855 MV_U8 channel = param2;
856
857 if (param1 == EVENT_CONNECT)
858 {
859 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
860 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
861 pMvSataAdapter->adapterId, channel));
862 /* Delete previous timers (if multiple drives connected in the same time */
863 callout_reset(&pAdapter->event_timer_connect, 10*hz, hptmv_handle_event_connect, pAdapter);
864 }
865 else if (param1 == EVENT_DISCONNECT)
866 {
867 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
868 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
869 pMvSataAdapter->adapterId, channel));
870 device_change(pAdapter, channel, FALSE);
871 /* Delete previous timers (if multiple drives disconnected in the same time */
872 /* callout_reset(&pAdapter->event_timer_disconnect, 10*hz, hptmv_handle_event_disconnect, pAdapter); */
873 /*It is not necessary to wait, handle it directly*/
874 hptmv_handle_event_disconnect(pAdapter);
875 }
876 else
877 {
878
879 MV_ERROR("RR18xx: illigal value for param1(%d) at "
880 "connect/disconect event, host=%d\n", param1,
881 pMvSataAdapter->adapterId );
882
883 }
884 }
885 break;
886 case MV_EVENT_TYPE_ADAPTER_ERROR:
887 KdPrint(("RR18xx: DEVICE error event received, pci cause "
888 "reg=%x, don't how to handle this\n", param1));
889 return MV_TRUE;
890 default:
891 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
892 pMvSataAdapter->adapterId, eventType);
893 return MV_FALSE;
894 }
895 return MV_TRUE;
896}
897
898static int
899hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
900{
901 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
902 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
903 if (pAdapter->requestsArrayBaseAddr == NULL)
904 {
905 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
906 " queues\n", pAdapter->mvSataAdapter.adapterId);
907 return -1;
908 }
909 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
910 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
911 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
912 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
913 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
914 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
915 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
916 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
917
918 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
919 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
920 {
921 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
922 pAdapter->mvSataAdapter.adapterId);
923 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
924 return -1;
925 }
926 /* response queues */
927 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
928 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
929 if (pAdapter->responsesArrayBaseAddr == NULL)
930 {
931 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
932 " queues\n", pAdapter->mvSataAdapter.adapterId);
933 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
934 return -1;
935 }
936 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
937 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
938 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
939 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
940 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
941 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
942 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
943 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
944
945 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
946 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
947 {
948 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n",
949 pAdapter->mvSataAdapter.adapterId);
950 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
951 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
952 return -1;
953 }
954 return 0;
955}
956
957static void
958hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
959{
960 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
961 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
962}
963
964static PVOID
965AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
966{
967 PVOID ret;
968 if (pAdapter->pFreePRDLink) {
969 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
970 ret = pAdapter->pFreePRDLink;
971 pAdapter->pFreePRDLink = *(void**)ret;
972 return ret;
973 }
974 return NULL;
975}
976
977static void
978FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
979{
980 *(void**)PRDTable = pAdapter->pFreePRDLink;
981 pAdapter->pFreePRDLink = PRDTable;
982}
983
984extern PVDevice fGetFirstChild(PVDevice pLogical);
985extern void fResetBootMark(PVDevice pLogical);
986static void
987fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
988{
989 PVDevice pPhysical, pLogical;
990 PVBus pVBus;
991 int i,j;
992
993 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) {
994 pPhysical = &(pAdapter->VDevices[i]);
995 pLogical = pPhysical;
996 while (pLogical->pParent) pLogical = pLogical->pParent;
997 if (pLogical->vf_online==0) {
998 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
999 continue;
1000 }
1001 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
1002 continue;
1003
1004 pVBus = &pAdapter->VBus;
1005 if(pVBus)
1006 {
1007 j=0;
1008 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1009 if(j<MAX_VDEVICE_PER_VBUS){
1010 pVBus->pVDevice[j] = pLogical;
1011 pLogical->pVBus = pVBus;
1012
1013 if (j>0 && pLogical->vf_bootmark) {
1014 if (pVBus->pVDevice[0]->vf_bootmark) {
1015 fResetBootMark(pLogical);
1016 }
1017 else {
1018 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1019 pVBus->pVDevice[0] = pLogical;
1020 }
1021 }
1022 }
1023 }
1024 }
1025}
1026
1027PVDevice
1028GetSpareDisk(_VBUS_ARG PVDevice pArray)
1029{
1030 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1031 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1032 LBA_T thiscap, maxcap = MAX_LBA_T;
1033 PVDevice pVDevice, pFind = NULL;
1034 int i;
1035
1036 for(i=0;i<MV_SATA_CHANNELS_NUM;i++)
1037 {
1038 pVDevice = &pAdapter->VDevices[i];
1039 if(!pVDevice)
1040 continue;
1041 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1042 /* find the smallest usable spare disk */
1043 if (pVDevice->VDeviceType==VD_SPARE &&
1044 pVDevice->u.disk.df_on_line &&
1045 thiscap < maxcap &&
1046 thiscap >= capacity)
1047 {
1048 maxcap = pVDevice->VDeviceCapacity;
1049 pFind = pVDevice;
1050 }
1051 }
1052 return pFind;
1053}
1054
1055/******************************************************************
1056 * IO ATA Command
1057 *******************************************************************/
1058int HPTLIBAPI
1059fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1060{
1061 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1062}
1063
1064void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1065{
1066 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1067 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1068 MV_U8 channelIndex = pSataChannel->channelNumber;
1069 UCHAR mvMode;
1070 /* 508x don't use MW-DMA? */
1071 if (NewMode>4 && NewMode<8) NewMode = 4;
1072 pDev->bDeModeSetting = NewMode;
1073 if (NewMode<=4)
1074 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1075 else
1076 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1077
1078 /*To fix 88i8030 bug*/
1079 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1080 mvMode = MV_ATA_TRANSFER_UDMA_0;
1081
1082 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1083 /* Flush pending commands */
1084 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1085
1086 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1087 MV_ATA_SET_FEATURES_TRANSFER,
1088 mvMode, 0, 0, 0) == MV_FALSE)
1089 {
1090 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1091 }
1092 /* Enable EDMA */
1093 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1094 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1095}
1096
1097int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1098{
1099 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1100 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1101 MV_U8 channelIndex = pSataChannel->channelNumber;
1102 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1103 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1104 int dmaActive = pSataChannel->queueCommandsEnabled;
1105 int ret = 0;
1106
1107 if (dmaActive) {
1108 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1109 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1110 }
1111
1112 if (enable) {
1113 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1114 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1115 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1116 channelInfo->queueDepth = (depth==32)? 31 : depth;
1117 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1118 ret = 1;
1119 }
1120 }
1121 else
1122 {
1123 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1124 channelInfo->queueDepth = 2;
1125 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1126 ret = 1;
1127 }
1128 }
1129
1130 if (dmaActive)
1131 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1132 return ret;
1133}
1134
1135int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1136{
1137 return 0;
1138}
1139
1140int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1141{
1142 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1143 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1144 MV_U8 channelIndex = pSataChannel->channelNumber;
1145 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1146 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1147 int dmaActive = pSataChannel->queueCommandsEnabled;
1148 int ret = 0;
1149
1150 if (dmaActive) {
1151 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1152 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1153 }
1154
1155 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1156 if (enable) {
1157 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1158 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1159 {
1160 channelInfo->writeCacheEnabled = MV_TRUE;
1161 ret = 1;
1162 }
1163 }
1164 else {
1165 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1166 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1167 {
1168 channelInfo->writeCacheEnabled = MV_FALSE;
1169 ret = 1;
1170 }
1171 }
1172 }
1173
1174 if (dmaActive)
1175 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1176 return ret;
1177}
1178
1179int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1180{
1181 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1182 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1183 MV_U8 channelIndex = pSataChannel->channelNumber;
1184 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1185 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1186 int dmaActive = pSataChannel->queueCommandsEnabled;
1187 int ret = 0;
1188
1189 if (dmaActive) {
1190 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1191 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1192 }
1193
1194 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1195 if (enable) {
1196 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1197 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1198 {
1199 channelInfo->readAheadEnabled = MV_TRUE;
1200 ret = 1;
1201 }
1202 }
1203 else {
1204 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1205 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1206 {
1207 channelInfo->readAheadEnabled = MV_FALSE;
1208 ret = 1;
1209 }
1210 }
1211 }
1212
1213 if (dmaActive)
1214 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1215 return ret;
1216}
1217
1218#ifdef SUPPORT_ARRAY
1219#define IdeRegisterVDevice fCheckArray
1220#else
1221void
1222IdeRegisterVDevice(PDevice pDev)
1223{
1224 PVDevice pVDev = Map2pVDevice(pDev);
1225
1226 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1227 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1228 pVDev->vf_online = 1;
1229 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1230 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1231 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1232}
1233#endif
1234
1235static __inline PBUS_DMAMAP
1236dmamap_get(struct IALAdapter * pAdapter)
1237{
1238 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1239 if (p)
1240 pAdapter->pbus_dmamap_list = p-> next;
1241 return p;
1242}
1243
1244static __inline void
1245dmamap_put(PBUS_DMAMAP p)
1246{
1247 p->next = p->pAdapter->pbus_dmamap_list;
1248 p->pAdapter->pbus_dmamap_list = p;
1249}
1250
1251/*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/
1252#define override_kernel_driver()
1253
1254static void hpt_init(void *dummy)
1255{
1256 override_kernel_driver();
1257 lockinit(&driver_lock, "hptsleeplock", 0, LK_CANRECURSE);
1258}
1259SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL);
1260
1261static int num_adapters = 0;
1262static int
1263init_adapter(IAL_ADAPTER_T *pAdapter)
1264{
1265 PVBus _vbus_p = &pAdapter->VBus;
1266 MV_SATA_ADAPTER *pMvSataAdapter;
1267 int i, channel, rid;
1268
1269 PVDevice pVDev;
1270
c898d682 1271 lock_driver();
35878b55
SW
1272
1273 pAdapter->next = 0;
1274
4090d6ff 1275 if(gIal_Adapter == NULL){
35878b55
SW
1276 gIal_Adapter = pAdapter;
1277 pCurAdapter = gIal_Adapter;
1278 }
1279 else {
1280 pCurAdapter->next = pAdapter;
1281 pCurAdapter = pAdapter;
1282 }
1283
1284 pAdapter->outstandingCommands = 0;
1285
1286 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1287 _vbus_p->OsExt = (void *)pAdapter;
1288 pMvSataAdapter->IALData = pAdapter;
1289
1290 if (bus_dma_tag_create(NULL,/* parent */
1291 4, /* alignment */
1292 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1293 BUS_SPACE_MAXADDR, /* lowaddr */
1294 BUS_SPACE_MAXADDR, /* highaddr */
1295 NULL, NULL, /* filter, filterarg */
1296 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1297 MAX_SG_DESCRIPTORS, /* nsegments */
1298 0x10000, /* maxsegsize */
1299 BUS_DMA_WAITOK, /* flags */
1300 &pAdapter->io_dma_parent /* tag */))
1301 {
1302 return ENXIO;
1303 }
1304
1305
1306 if (hptmv_allocate_edma_queues(pAdapter))
1307 {
1308 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
c898d682 1309 unlock_driver();
35878b55
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1310 return ENOMEM;
1311 }
1312
1313 /* also map EPROM address */
1314 rid = 0x10;
1315 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid,
1316 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE))
1317 ||
1318 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1319 {
1320 MV_ERROR("RR18xx: Failed to remap memory space\n");
1321 hptmv_free_edma_queues(pAdapter);
c898d682 1322 unlock_driver();
35878b55
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1323 return ENXIO;
1324 }
1325 else
1326 {
1327 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1328 }
1329
1330 pMvSataAdapter->adapterId = num_adapters++;
1331 /* get the revision ID */
1332 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1333 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1334
1335 /* init RR18xx */
1336 pMvSataAdapter->intCoalThre[0]= 1;
1337 pMvSataAdapter->intCoalThre[1]= 1;
1338 pMvSataAdapter->intTimeThre[0] = 1;
1339 pMvSataAdapter->intTimeThre[1] = 1;
1340 pMvSataAdapter->pciCommand = 0x0107E371;
1341 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1342 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1343 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1344
1345 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1346 {
1347 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1348 pMvSataAdapter->adapterId);
1349unregister:
1350 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1351 hptmv_free_edma_queues(pAdapter);
c898d682 1352 unlock_driver();
35878b55
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1353 return ENXIO;
1354 }
1355 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1356
1357#ifndef FOR_DEMO
1358 set_fail_leds(pMvSataAdapter, 0);
1359#endif
1360
1361 /* setup command blocks */
1362 KdPrint(("Allocate command blocks\n"));
1363 _vbus_(pFreeCommands) = 0;
1364 pAdapter->pCommandBlocks =
1365 kmalloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1366 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1367 if (!pAdapter->pCommandBlocks) {
1368 MV_ERROR("insufficient memory\n");
1369 goto unregister;
1370 }
1371
1372 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1373 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1374 }
1375
1376 /*Set up the bus_dmamap*/
1377 pAdapter->pbus_dmamap = (PBUS_DMAMAP)kmalloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1378 if(!pAdapter->pbus_dmamap) {
1379 MV_ERROR("insufficient memory\n");
1380 kfree(pAdapter->pCommandBlocks, M_DEVBUF);
1381 goto unregister;
1382 }
1383
1384 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1385 pAdapter->pbus_dmamap_list = 0;
1386 for (i=0; i < MAX_QUEUE_COMM; i++) {
1387 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1388 pmap->pAdapter = pAdapter;
1389 dmamap_put(pmap);
1390
1391 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1392 MV_ERROR("Can not allocate dma map\n");
1393 kfree(pAdapter->pCommandBlocks, M_DEVBUF);
1394 kfree(pAdapter->pbus_dmamap, M_DEVBUF);
1395 goto unregister;
1396 }
1397 }
1398 /* setup PRD Tables */
1399 KdPrint(("Allocate PRD Tables\n"));
1400 pAdapter->pFreePRDLink = 0;
1401
1402 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1403 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1404
1405 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1406 if (!pAdapter->prdTableAddr) {
1407 MV_ERROR("insufficient PRD Tables\n");
1408 goto unregister;
1409 }
1410 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1411 {
1412 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1413 for (i=0; i<PRD_TABLES_FOR_VBUS; i++)
1414 {
1415/* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1416 FreePRDTable(pAdapter, PRDTable);
1417 PRDTable += PRD_ENTRIES_SIZE;
1418 }
1419 }
1420
1421 /* enable the adapter interrupts */
1422
1423 /* configure and start the connected channels*/
1424 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1425 {
1426 pAdapter->mvChannel[channel].online = MV_FALSE;
1427 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1428 == MV_TRUE)
1429 {
1430 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1431 pMvSataAdapter->adapterId, channel));
1432
1433 if (hptmv_init_channel(pAdapter, channel) == 0)
1434 {
1435 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1436 {
1437 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1438 " %d\n",pMvSataAdapter->adapterId, channel);
1439 hptmv_free_channel(pAdapter, channel);
1440 }
1441 else
1442 {
1443 if (start_channel(pAdapter, channel))
1444 {
1445 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1446 " channel=%d\n",pMvSataAdapter->adapterId,
1447 channel);
1448 hptmv_free_channel(pAdapter, channel);
1449 }
1450 pAdapter->mvChannel[channel].online = MV_TRUE;
1451 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1452 channel,
1453 MV_TRUE);*/
1454 }
1455 }
1456 }
1457 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1458 pAdapter->mvChannel[channel].online, channel));
1459 }
1460
1461#ifdef SUPPORT_ARRAY
1462 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1463 pVDev = ArrayTables(i);
1464 mArFreeArrayTable(pVDev);
1465 }
1466#endif
1467
1468 KdPrint(("Initialize Devices\n"));
1469 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1470 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1471 if (pMvSataChannel) {
1472 init_vdev_params(pAdapter, channel);
1473 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1474 }
1475 }
1476#ifdef SUPPORT_ARRAY
1477 CheckArrayCritical(_VBUS_P0);
1478#endif
1479 _vbus_p->nInstances = 1;
1480 fRegisterVdevice(pAdapter);
1481
1482 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) {
1483 pVDev = _vbus_p->pVDevice[channel];
1484 if (pVDev && pVDev->vf_online)
1485 fCheckBootable(pVDev);
1486 }
1487
1488#if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1489 init_raid5_memory(_VBUS_P0);
1490 _vbus_(r5).enable_write_back = 1;
1491 kprintf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1492#endif
1493
1494 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
c898d682 1495 unlock_driver();
35878b55
SW
1496 return 0;
1497}
1498
1499int
1500MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1501{
1502 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1503
1504 mvSataDisableChannelDma(pMvSataAdapter, channel);
1505 /* Flush pending commands */
1506 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1507
1508 /* Software reset channel */
1509 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1510 {
1511 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1512 pMvSataAdapter->adapterId, channel);
1513 hptmv_free_channel(pAdapter, channel);
1514 return -1;
1515 }
1516
1517 /* Hardware reset channel */
1518 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1519 {
1520 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1521 pMvSataAdapter->adapterId, channel);
1522 hptmv_free_channel(pAdapter, channel);
1523 return -1;
1524 }
1525
1526 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1527 {
1528 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1529 pMvSataAdapter->adapterId, channel);
1530 hptmv_free_channel(pAdapter, channel);
1531 return -1;
1532 }else
1533 {
1534 MV_ERROR("channel %d: perform recalibrate command", channel);
1535 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1536 MV_NON_UDMA_PROTOCOL_NON_DATA,
1537 MV_FALSE,
1538 NULL, /* pBuffer*/
1539 0, /* count */
1540 0, /*features*/
1541 /* sectorCount */
1542 0,
1543 0, /* lbaLow */
1544 0, /* lbaMid */
1545 /* lbaHigh */
1546 0,
1547 0, /* device */
1548 /* command */
1549 0x10))
1550 MV_ERROR("channel %d: recalibrate failed", channel);
1551
1552 /* Set transfer mode */
1553 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1554 MV_ATA_SET_FEATURES_TRANSFER,
1555 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1556 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1557 MV_ATA_SET_FEATURES_TRANSFER,
1558 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1559 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1560 MV_ATA_SET_FEATURES_TRANSFER,
1561 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1562 {
1563 MV_ERROR("channel %d: Set Features failed", channel);
1564 hptmv_free_channel(pAdapter, channel);
1565 return -1;
1566 }
1567 /* Enable EDMA */
1568 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1569 {
1570 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1571 hptmv_free_channel(pAdapter, channel);
1572 return -1;
1573 }
1574 }
1575 return 0;
1576}
1577
1578static int
1579fResetActiveCommands(PVBus _vbus_p)
1580{
1581 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1582 MV_U8 channel;
1583 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1584 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1585 MvSataResetChannel(pMvSataAdapter,channel);
1586 }
1587 return 0;
1588}
1589
1590void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1591{
1592 UINT cont;
1593 ULONG ticks = 0;
1594 MV_U8 channel;
1595 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1596 MV_SATA_CHANNEL *pMvSataChannel;
1597
1598 do {
1599check_cmds:
1600 cont = 0;
1601 CheckPendingCall(_VBUS_P0);
1602#ifdef _RAID5N_
1603 dataxfer_poll();
1604 xor_poll();
1605#endif
1606 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1607 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1608 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1609 {
1610 while (pMvSataChannel->outstandingCommands) {
1611 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1612 StallExec(1000);
1613 if (ticks++ > 3000) {
1614 MvSataResetChannel(pMvSataAdapter,channel);
1615 goto check_cmds;
1616 }
1617 }
1618 else
1619 ticks = 0;
1620 }
1621 cont = 1;
1622 }
1623 }
1624 } while (cont);
1625}
1626
1627void
1628fResetVBus(_VBUS_ARG0)
1629{
1630 KdPrint(("fMvResetBus(%p)", _vbus_p));
1631
1632 /* some commands may already finished. */
1633 CheckPendingCall(_VBUS_P0);
1634
1635 fResetActiveCommands(_vbus_p);
1636 /*
1637 * the other pending commands may still be finished successfully.
1638 */
1639 fCompleteAllCommandsSynchronously(_vbus_p);
1640
1641 /* Now there should be no pending commands. No more action needed. */
1642 CheckIdleCall(_VBUS_P0);
1643
1644 KdPrint(("fMvResetBus() done"));
1645}
1646
1647/*No rescan function*/
1648void
1649fRescanAllDevice(_VBUS_ARG0)
1650{
1651}
1652
1653static MV_BOOLEAN
1654CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1655 MV_U8 channelNum,
1656 MV_COMPLETION_TYPE comp_type,
1657 MV_VOID_PTR commandId,
1658 MV_U16 responseFlags,
1659 MV_U32 timeStamp,
1660 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1661{
1662 PCommand pCmd = (PCommand) commandId;
1663 _VBUS_INST(pCmd->pVDevice->pVBus)
1664
1665 if (pCmd->uScratch.sata_param.prdAddr)
1666 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1667
1668 switch (comp_type)
1669 {
1670 case MV_COMPLETION_TYPE_NORMAL:
1671 pCmd->Result = RETURN_SUCCESS;
1672 break;
1673 case MV_COMPLETION_TYPE_ABORT:
1674 pCmd->Result = RETURN_BUS_RESET;
1675 break;
1676 case MV_COMPLETION_TYPE_ERROR:
1677 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1678 pMvSataAdapter->adapterId, channelNum, responseFlags);
1679
1680 if (responseFlags & 4) {
1681 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1682 " LBA high %x, device %x, status %x\n",
1683 registerStruct->errorRegister,
1684 registerStruct->sectorCountRegister,
1685 registerStruct->lbaLowRegister,
1686 registerStruct->lbaMidRegister,
1687 registerStruct->lbaHighRegister,
1688 registerStruct->deviceRegister,
1689 registerStruct->statusRegister);
1690 }
1691 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1692 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1693 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1694 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1695 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1696 pCmd->pVDevice->u.disk.QueueLength--;
1697 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1698 return TRUE;
1699
1700 default:
1701 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1702 return MV_FALSE;
1703 }
1704
1705 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1706 pCmd->uScratch.sata_param.cmd_priv --;
1707 return TRUE;
1708 }
1709 pCmd->pVDevice->u.disk.QueueLength--;
1710 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1711 return TRUE;
1712}
1713
1714void
1715fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1716{
1717 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1718 MV_SATA_ADAPTER *pMvSataAdapter;
1719 MV_SATA_CHANNEL *pMvSataChannel;
1720 PVDevice pVDevice = pCmd->pVDevice;
1721 PDevice pDevice = &pVDevice->u.disk;
1722 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1723 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1724
1725 MV_QUEUE_COMMAND_RESULT result;
1726 MV_QUEUE_COMMAND_INFO commandInfo;
1727 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1728 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1729
1730 MV_BOOLEAN is48bit;
1731 MV_U8 channel;
1732 int i=0;
1733
1734 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1735
1736 if (!pDevice->df_on_line) {
1737 MV_ERROR("Device is offline");
1738 pCmd->Result = RETURN_BAD_DEVICE;
1739 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1740 return;
1741 }
1742
1743 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1744 pMvSataChannel = pDevice->mv;
1745 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1746 channel = pMvSataChannel->channelNumber;
1747
1748 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1749 Lba += pDevice->dDeHiddenLba;
1750 /* check LBA */
1751 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1752 pCmd->Result = RETURN_INVALID_REQUEST;
1753 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1754 return;
1755 }
1756
1757 /*
1758 * always use 48bit LBA if drive supports it.
1759 * Some Seagate drives report error if you use a 28-bit command
1760 * to access sector 0xfffffff.
1761 */
1762 is48bit = pMvSataChannel->lba48Address;
1763
1764 switch (pCmd->uCmd.Ide.Command)
1765 {
1766 case IDE_COMMAND_READ:
1767 case IDE_COMMAND_WRITE:
1768 if (pDevice->bDeModeSetting<8) goto pio;
1769
1770 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1771 pUdmaParams->isEXT = is48bit;
1772 pUdmaParams->numOfSectors = nSector;
1773 pUdmaParams->lowLBAAddress = Lba;
1774 pUdmaParams->highLBAAddress = 0;
1775 pUdmaParams->prdHighAddr = 0;
1776 pUdmaParams->callBack = CommandCompletionCB;
1777 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1778 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1779 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1780 else
1781 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1782
1783 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1784 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1785 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1786 }
1787 else {
1788 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1789pio:
1790 mvSataDisableChannelDma(pMvSataAdapter, channel);
1791 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1792
1793 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1794 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1795 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1796 }
1797 else {
1798 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1799 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1800 goto finish_cmd;
1801 }
1802 }
1803
1804 do {
1805 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1806 ULONG_PTR addr = tmpSg->dSgAddress;
1807 if (size & 0x1ff) {
1808 pCmd->Result = RETURN_INVALID_REQUEST;
1809 goto finish_cmd;
1810 }
1811 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1812 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1813 is48bit,
1814 (MV_U16_PTR)addr,
1815 size >> 1, /* count */
1816 0, /* features N/A */
1817 (MV_U16)(size>>9), /*sector count*/
1818 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1819 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1820 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1821 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1822 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1823 )==MV_FALSE)
1824 {
1825 pCmd->Result = RETURN_IDE_ERROR;
1826 goto finish_cmd;
1827 }
1828 Lba += size>>9;
1829 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1830 }
1831 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1832 pCmd->Result = RETURN_SUCCESS;
1833finish_cmd:
1834 mvSataEnableChannelDma(pMvSataAdapter,channel);
1835 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1836 return;
1837 }
1838 }
1839
1840 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1841 KdPrint(("pPRDTable:%p\n",pPRDTable));
1842 if (!pPRDTable) {
1843 pCmd->Result = RETURN_DEVICE_BUSY;
1844 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1845 HPT_ASSERT(0);
1846 return;
1847 }
1848
1849 do{
1850 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1851 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1852 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1853 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1854 pPRDTable[i].reserved = 0;
1855 i++;
1856 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1857
1858 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1859 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1860 pUdmaParams->numOfSectors = 0;
1861 }
1862
1863 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1864
1865 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1866
1867 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1868 {
1869queue_failed:
1870 switch (result)
1871 {
1872 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1873 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1874 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1875 pCmd->Result = RETURN_IDE_ERROR;
1876 break;
1877 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1878 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1879 " disabled adapter %d channel %d\n",
1880 pMvSataAdapter->adapterId, channel);
1881 mvSataEnableChannelDma(pMvSataAdapter,channel);
1882 pCmd->Result = RETURN_IDE_ERROR;
1883 break;
1884 case MV_QUEUE_COMMAND_RESULT_FULL:
1885 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1886 " Full adapter %d channel %d\n",
1887 pMvSataAdapter->adapterId, channel);
1888 pCmd->Result = RETURN_DEVICE_BUSY;
1889 break;
1890 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1891 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1892 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1893 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1894 pCmd->Result = RETURN_IDE_ERROR;
1895 break;
1896 default:
1897 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1898 " command\n", result);
1899 pCmd->Result = RETURN_IDE_ERROR;
1900 }
1901 if(pPRDTable)
1902 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1903 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1904 }
1905 pDevice->QueueLength++;
1906 return;
1907
1908 case IDE_COMMAND_VERIFY:
1909 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1910 pNoUdmaParams->bufPtr = NULL;
1911 pNoUdmaParams->callBack = CommandCompletionCB;
1912 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1913 pNoUdmaParams->count = 0;
1914 pNoUdmaParams->features = 0;
1915 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1916
1917 pCmd->uScratch.sata_param.cmd_priv = 1;
1918 if (pMvSataChannel->lba48Address == MV_TRUE){
1919 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1920 pNoUdmaParams->isEXT = MV_TRUE;
1921 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1922 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1923 pNoUdmaParams->lbaLow =
1924 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1925 pNoUdmaParams->sectorCount = nSector;
1926 pNoUdmaParams->device = 0x40;
1927 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1928 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1929 goto queue_failed;
1930 }
1931 return;
1932 }
1933 else{
1934 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1935 pNoUdmaParams->isEXT = MV_FALSE;
1936 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1937 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1938 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1939 pNoUdmaParams->sectorCount = 0xff & nSector;
1940 pNoUdmaParams->device = (MV_U8)(0x40 |
1941 ((Lba & 0xf000000) >> 24));
1942 pNoUdmaParams->callBack = CommandCompletionCB;
1943 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1944 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1945 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1946 goto queue_failed;
1947 }
1948 }
1949 break;
1950 default:
1951 pCmd->Result = RETURN_INVALID_REQUEST;
1952 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1953 break;
1954 }
1955}
1956
1957/**********************************************************
1958 *
1959 * Probe the hostadapter.
1960 *
1961 **********************************************************/
1962static int
1963hpt_probe(device_t dev)
1964{
1965 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1966 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1967#ifdef FOR_DEMO
1968 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1969#endif
1970 ))
1971 {
1972 KdPrintI((CONTROLLER_NAME " found\n"));
1973 device_set_desc(dev, CONTROLLER_NAME);
1974 return 0;
1975 }
1976 else
1977 return(ENXIO);
1978}
1979
1980/***********************************************************
1981 *
1982 * Auto configuration: attach and init a host adapter.
1983 *
1984 ***********************************************************/
1985static int
1986hpt_attach(device_t dev)
1987{
1988 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1989 int rid;
1990 union ccb *ccb;
1991 struct cam_devq *devq;
1992 struct cam_sim *hpt_vsim;
1993
1994 kprintf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1995
1996 if (!pAdapter)
1997 {
1998 pAdapter = (IAL_ADAPTER_T *)kmalloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT);
1999 device_set_softc(dev, (void *)pAdapter);
2000 }
2001
2002 if (!pAdapter) return (ENOMEM);
2003 bzero(pAdapter, sizeof(IAL_ADAPTER_T));
2004
2005 pAdapter->hpt_dev = dev;
2006
2007 rid = init_adapter(pAdapter);
2008 if (rid)
2009 return rid;
2010
2011 rid = 0;
2012 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL)
2013 {
2014 hpt_printk(("can't allocate interrupt\n"));
2015 return(ENXIO);
2016 }
2017
2018 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 0,
2019 hpt_intr, pAdapter, &pAdapter->hpt_intr, NULL))
2020 {
2021 hpt_printk(("can't set up interrupt\n"));
2022 kfree(pAdapter, M_DEVBUF);
2023 return(ENXIO);
2024 }
2025
2026
2027 if((ccb = (union ccb *)kmalloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL)
2028 {
2029 bzero(ccb, sizeof(*ccb));
2030 ccb->ccb_h.pinfo.priority = 1;
2031 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2032 }
2033 else
2034 {
2035 return ENOMEM;
2036 }
2037 /*
2038 * Create the device queue for our SIM(s).
2039 */
2040 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2041 {
2042 KdPrint(("ENXIO\n"));
2043 return ENOMEM;
2044 }
2045
2046 /*
2047 * Construct our SIM entry
2048 */
2049 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2050 pAdapter, device_get_unit(pAdapter->hpt_dev), &sim_mplock, 1, 8, devq);
2051 cam_simq_release(devq);
2052 if (hpt_vsim == NULL) {
2053 return ENOMEM;
2054 }
2055
2056 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS)
2057 {
2058 cam_sim_free(hpt_vsim);
2059 hpt_vsim = NULL;
2060 return ENXIO;
2061 }
2062
2063 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2064 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2065 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2066 {
2067 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2068 cam_sim_free(hpt_vsim);
2069 hpt_vsim = NULL;
2070 return ENXIO;
2071 }
2072
2073 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2074 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2075 ccb->csa.event_enable = AC_LOST_DEVICE;
2076 ccb->csa.callback = hpt_async;
2077 ccb->csa.callback_arg = hpt_vsim;
2078 xpt_action((union ccb *)ccb);
2079 kfree(ccb, M_DEVBUF);
2080
2081 callout_init(&pAdapter->event_timer_connect);
2082 callout_init(&pAdapter->event_timer_disconnect);
2083
2084 if (device_get_unit(dev) == 0) {
2085 /* Start the work thread. XXX */
2086 launch_worker_thread();
2050a95d
SW
2087
2088 /*
2089 * hpt_worker_thread needs to be suspended after shutdown
2090 * sync, when fs sync finished.
2091 */
2092 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_post_sync,
2093 shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST);
35878b55
SW
2094 }
2095
2096 return 0;
2097}
2098
2099static int
2100hpt_detach(device_t dev)
2101{
2102 return (EBUSY);
2103}
2104
2105
2106/***************************************************************
2107 * The poll function is used to simulate the interrupt when
2108 * the interrupt subsystem is not functioning.
2109 *
2110 ***************************************************************/
2111static void
2112hpt_poll(struct cam_sim *sim)
2113{
2114 hpt_intr((void *)cam_sim_softc(sim));
2115}
2116
2117/****************************************************************
2118 * Name: hpt_intr
2119 * Description: Interrupt handler.
2120 ****************************************************************/
2121static void
2122hpt_intr(void *arg)
2123{
2124 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg;
35878b55 2125
c898d682 2126 lock_driver();
35878b55
SW
2127 /* KdPrintI(("----- Entering Isr() -----\n")); */
2128 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2129 {
2130 _VBUS_INST(&pAdapter->VBus)
2131 CheckPendingCall(_VBUS_P0);
2132 }
2133
2134 /* KdPrintI(("----- Leaving Isr() -----\n")); */
c898d682 2135 unlock_driver();
35878b55
SW
2136}
2137
2138/**********************************************************
2139 * Asynchronous Events
2140 *********************************************************/
2141#if (!defined(UNREFERENCED_PARAMETER))
2142#define UNREFERENCED_PARAMETER(x) (void)(x)
2143#endif
2144
2145static void
2146hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2147 void * arg)
2148{
2149 /* debug XXXX */
2150 panic("Here");
2151 UNREFERENCED_PARAMETER(callback_arg);
2152 UNREFERENCED_PARAMETER(code);
2153 UNREFERENCED_PARAMETER(path);
2154 UNREFERENCED_PARAMETER(arg);
2155
2156}
2157
2158static void
2159FlushAdapter(IAL_ADAPTER_T *pAdapter)
2160{
2161 int i;
2162
2163 hpt_printk(("flush all devices\n"));
2164
2165 /* flush all devices */
2166 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2167 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2168 if(pVDev) fFlushVDev(pVDev);
2169 }
2170}
2171
2172static int
2173hpt_shutdown(device_t dev)
2174{
2175 IAL_ADAPTER_T *pAdapter;
2176
2177 pAdapter = device_get_softc(dev);
2178 if (pAdapter == NULL)
2179 return (EINVAL);
2180
2050a95d 2181 EVENTHANDLER_DEREGISTER(shutdown_post_sync, pAdapter->eh);
35878b55
SW
2182 FlushAdapter(pAdapter);
2183 /* give the flush some time to happen,
2184 *otherwise "shutdown -p now" will make file system corrupted */
2185 DELAY(1000 * 1000 * 5);
2186 return 0;
2187}
2188
2189void
2190Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2191{
2192 _VBUS_INST(&pAdapter->VBus)
2193
2194 if (mWaitingForIdle(_VBUS_P0)) {
2195 CheckIdleCall(_VBUS_P0);
2196#ifdef SUPPORT_ARRAY
2197 {
2198 int i;
2199 PVDevice pArray;
2200 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2201 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2202 continue;
2203 else if (pArray->u.array.rf_auto_rebuild) {
2204 KdPrint(("auto rebuild.\n"));
2205 pArray->u.array.rf_auto_rebuild = 0;
2206 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2207 }
2208 }
2209 }
2210#endif
2211 }
2212 /* launch the awaiting commands blocked by mWaitingForIdle */
2213 while(pAdapter->pending_Q!= NULL)
2214 {
2215 _VBUS_INST(&pAdapter->VBus)
2216 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2217 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2218 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2219 }
2220}
2221
2222static void
2223ccb_done(union ccb *ccb)
2224{
2225 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2226 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2227 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2228
2229 dmamap_put(pmap);
2230 xpt_done(ccb);
2231
2232 pAdapter->outstandingCommands--;
2233
2234 if (pAdapter->outstandingCommands == 0)
2235 {
2236 if(DPC_Request_Nums == 0)
2237 Check_Idle_Call(pAdapter);
2238 }
2239}
2240
2241/****************************************************************
2242 * Name: hpt_action
2243 * Description: Process a queued command from the CAM layer.
2244 * Parameters: sim - Pointer to SIM object
2245 * ccb - Pointer to SCSI command structure.
2246 ****************************************************************/
2247
2248void
2249hpt_action(struct cam_sim *sim, union ccb *ccb)
2250{
35878b55
SW
2251 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2252 PBUS_DMAMAP pmap;
2253 _VBUS_INST(&pAdapter->VBus)
2254
2255 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2256 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2257
2258 switch (ccb->ccb_h.func_code)
2259 {
2260 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2261 {
2262 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2263
2264 if (ccb->ccb_h.target_lun) {
2265 ccb->ccb_h.status = CAM_LUN_INVALID;
2266 xpt_done(ccb);
2267 return;
2268 }
2269 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2270 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2271 ccb->ccb_h.status = CAM_TID_INVALID;
2272 xpt_done(ccb);
2273 return;
2274 }
2275
c898d682 2276 lock_driver();
35878b55
SW
2277 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2278 Check_Idle_Call(pAdapter);
2279
2280 pmap = dmamap_get(pAdapter);
2281 HPT_ASSERT(pmap);
2282 ccb->ccb_adapter = pmap;
2283 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2284
2285 if (mWaitingForIdle(_VBUS_P0))
2286 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2287 else
2288 OsSendCommand(_VBUS_P ccb);
c898d682 2289 unlock_driver();
35878b55
SW
2290
2291 /* KdPrint(("leave scsiio\n")); */
2292 break;
2293 }
2294
2295 case XPT_RESET_BUS:
2296 KdPrint(("reset bus\n"));
c898d682 2297 lock_driver();
35878b55 2298 fResetVBus(_VBUS_P0);
c898d682 2299 unlock_driver();
35878b55
SW
2300 xpt_done(ccb);
2301 break;
2302
2303 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2304 case XPT_EN_LUN: /* Enable LUN as a target */
2305 case XPT_TARGET_IO: /* Execute target I/O request */
2306 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2307 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2308 case XPT_ABORT: /* Abort the specified CCB */
2309 case XPT_TERM_IO: /* Terminate the I/O process */
2310 /* XXX Implement */
2311 ccb->ccb_h.status = CAM_REQ_INVALID;
2312 xpt_done(ccb);
2313 break;
2314
2315 case XPT_GET_TRAN_SETTINGS:
2316 case XPT_SET_TRAN_SETTINGS:
2317 /* XXX Implement */
2318 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2319 xpt_done(ccb);
2320 break;
2321
2322 case XPT_CALC_GEOMETRY:
2323 {
2324 struct ccb_calc_geometry *ccg;
2325 u_int32_t size_mb;
2326 u_int32_t secs_per_cylinder;
2327
2328 ccg = &ccb->ccg;
2329 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size);
2330
2331 if (size_mb > 1024 ) {
2332 ccg->heads = 255;
2333 ccg->secs_per_track = 63;
2334 } else {
2335 ccg->heads = 64;
2336 ccg->secs_per_track = 32;
2337 }
2338 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
2339 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
2340 ccb->ccb_h.status = CAM_REQ_CMP;
2341 xpt_done(ccb);
2342 break;
2343 }
2344
2345 case XPT_PATH_INQ: /* Path routing inquiry */
2346 {
2347 struct ccb_pathinq *cpi = &ccb->cpi;
2348
2349 cpi->version_num = 1; /* XXX??? */
2350 cpi->hba_inquiry = PI_SDTR_ABLE;
2351 cpi->target_sprt = 0;
2352 /* Not necessary to reset bus */
2353 cpi->hba_misc = PIM_NOBUSRESET;
2354 cpi->hba_eng_cnt = 0;
2355
2356 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2357 cpi->max_lun = 0;
2358 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2359
2360 cpi->bus_id = cam_sim_bus(sim);
2361 cpi->base_transfer_speed = 3300;
2362 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2363 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2364 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2365 cpi->unit_number = cam_sim_unit(sim);
2366 cpi->transport = XPORT_SPI;
2367 cpi->transport_version = 2;
2368 cpi->protocol = PROTO_SCSI;
2369 cpi->protocol_version = SCSI_REV_2;
5597f4e1 2370 cpi->maxio = HPTMV_DFLTPHYS;
35878b55
SW
2371 cpi->ccb_h.status = CAM_REQ_CMP;
2372 xpt_done(ccb);
2373 break;
2374 }
2375
2376 default:
2377 KdPrint(("invalid cmd\n"));
2378 ccb->ccb_h.status = CAM_REQ_INVALID;
2379 xpt_done(ccb);
2380 break;
2381 }
2382 /* KdPrint(("leave hpt_action..............\n")); */
2383}
2384
2385/* shall be called at lock_driver() */
2386static void
2387hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2388{
2389 if(*ccb_Q == NULL)
2390 ccb->ccb_h.ccb_ccb_ptr = ccb;
2391 else {
2392 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2393 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2394 }
2395
2396 *ccb_Q = ccb;
2397}
2398
2399/* shall be called at lock_driver() */
2400static void
2401hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2402{
2403 union ccb *TempCCB;
2404
2405 TempCCB = *ccb_Q;
2406
2407 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2408 *ccb_Q = NULL;
2409 else {
2410 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2411 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2412
2413 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2414
2415 if(*ccb_Q == ccb)
2416 *ccb_Q = TempCCB;
2417 }
2418}
2419
2420#ifdef SUPPORT_ARRAY
2421/***************************************************************************
2422 * Function: hpt_worker_thread
2423 * Description: Do background rebuilding. Execute in kernel thread context.
2424 * Returns: None
2425 ***************************************************************************/
2426static void hpt_worker_thread(void)
2427{
35878b55
SW
2428 for(;;) {
2429 while (DpcQueue_First!=DpcQueue_Last) {
2430 ST_HPT_DPC p;
c898d682 2431 lock_driver();
35878b55
SW
2432 p = DpcQueue[DpcQueue_First];
2433 DpcQueue_First++;
2434 DpcQueue_First %= MAX_DPC;
2435 DPC_Request_Nums++;
c898d682 2436 unlock_driver();
35878b55
SW
2437 p.dpc(p.pAdapter, p.arg, p.flags);
2438
c898d682 2439 lock_driver();
35878b55
SW
2440 DPC_Request_Nums--;
2441 /* since we may have prevented Check_Idle_Call, do it here */
2442 if (DPC_Request_Nums==0) {
2443 if (p.pAdapter->outstandingCommands == 0) {
2444 _VBUS_INST(&p.pAdapter->VBus);
2445 Check_Idle_Call(p.pAdapter);
2446 CheckPendingCall(_VBUS_P0);
2447 }
2448 }
c898d682 2449 unlock_driver();
35878b55
SW
2450
2451 /*Schedule out*/
2452 tsleep((caddr_t)hpt_worker_thread, 0, "sched", 1);
2453 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2454 /* abort rebuilding process. */
2455 IAL_ADAPTER_T *pAdapter;
2456 PVDevice pArray;
2457 PVBus _vbus_p;
2458 int i;
2459 pAdapter = gIal_Adapter;
2460
4090d6ff 2461 while(pAdapter != NULL){
35878b55
SW
2462
2463 _vbus_p = &pAdapter->VBus;
2464
2465 for (i=0;i<MAX_ARRAY_PER_VBUS;i++)
2466 {
2467 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2468 continue;
2469 else if (pArray->u.array.rf_rebuilding ||
2470 pArray->u.array.rf_verifying ||
2471 pArray->u.array.rf_initializing)
2472 {
2473 pArray->u.array.rf_abort_rebuild = 1;
2474 }
2475 }
2476 pAdapter = pAdapter->next;
2477 }
2478 }
2479 }
2480
2481/*Remove this debug option*/
2482/*
2483#ifdef DEBUG
2484 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2485 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz);
2486#endif
2487*/
2488 kproc_suspend_loop();
2489 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); /* wait for something to do */
2490 }
2491}
2492
35878b55
SW
2493static struct kproc_desc hpt_kp = {
2494 "hpt_wt",
2495 hpt_worker_thread,
2496 &hptdaemonproc
2497};
2498
2499/*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2500static void
2501launch_worker_thread(void)
2502{
2503 IAL_ADAPTER_T *pAdapTemp;
2504
2505 kproc_start(&hpt_kp);
2506
2507 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2508
2509 _VBUS_INST(&pAdapTemp->VBus)
2510 int i;
2511 PVDevice pVDev;
2512
2513 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2514 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2515 continue;
2516 else{
2517 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2518 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2519 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2520 }
2521 }
35878b55
SW
2522}
2523/*
2524 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2525*/
2526
2527#endif
2528
2529/********************************************************************************/
2530
2531int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2532{
2533 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2534 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2535 int idx;
2536
2537 if(logical) {
2538 if (ccb->ccb_h.flags & CAM_DATA_PHYS)
2539 panic("physical address unsupported");
2540
2541 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2542 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2543 panic("physical address unsupported");
2544
2545 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2546 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2547 pSg[idx].wSgSize = sgList[idx].ds_len;
2548 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0;
2549 }
2550 }
2551 else {
2552 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2553 pSg->wSgSize = ccb->csio.dxfer_len;
2554 pSg->wSgFlag = SG_FLAG_EOT;
2555 }
2556 return TRUE;
2557 }
2558
2559 /* since we have provided physical sg, nobody will ask us to build physical sg */
2560 HPT_ASSERT(0);
2561 return FALSE;
2562}
2563
2564/*******************************************************************************/
2565ULONG HPTLIBAPI
2566GetStamp(void)
2567{
2568 /*
2569 * the system variable, ticks, can't be used since it hasn't yet been active
2570 * when our driver starts (ticks==0, it's a invalid stamp value)
2571 */
2572 ULONG stamp;
2573 do { stamp = krandom(); } while (stamp==0);
2574 return stamp;
2575}
2576
2577
2578static void
2579SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2580{
2581 int i;
2582 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2583
2584 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2585 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2586#ifndef SERIAL_CMDS
2587 inquiryData->CommandQueue = 1;
2588#endif
2589
2590 switch(pVDev->VDeviceType) {
2591 case VD_SINGLE_DISK:
2592 case VD_ATAPI:
2593 case VD_REMOVABLE:
2594 /* Set the removable bit, if applicable. */
2595 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2596 inquiryData->RemovableMedia = 1;
2597
2598 /* Fill in vendor identification fields. */
2599 for (i = 0; i < 20; i += 2) {
2600 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2601 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2602
2603 }
2604
2605 /* Initialize unused portion of product id. */
2606 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2607
2608 /* firmware revision */
2609 for (i = 0; i < 4; i += 2)
2610 {
2611 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2612 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2613 }
2614 break;
2615 default:
2616 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2617#ifdef SUPPORT_ARRAY
2618 switch(pVDev->VDeviceType){
2619 case VD_RAID_0:
2620 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2621 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2622 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2623 else
2624 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2625 break;
2626 case VD_RAID_1:
2627 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2628 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2629 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2630 else
2631 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2632 break;
2633 case VD_RAID_5:
2634 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2635 break;
2636 case VD_JBOD:
2637 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2638 break;
2639 }
2640#endif
2641 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2642 break;
2643 }
2644}
2645
2646static void
2647hpt_timeout(void *arg)
2648{
2649 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus)
c898d682 2650 lock_driver();
35878b55 2651 fResetVBus(_VBUS_P0);
c898d682 2652 unlock_driver();
35878b55
SW
2653}
2654
2655static void
2656hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2657{
2658 PCommand pCmd = (PCommand)arg;
2659 union ccb *ccb = pCmd->pOrgCommand;
2660 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2661 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2662 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2663 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2664 FPSCAT_GATH psg = pCmd->pSgTable;
2665 int idx;
2666 _VBUS_INST(pVDev->pVBus)
2667
2668 HPT_ASSERT(pCmd->cf_physical_sg);
2669
2670 if (error || nsegs == 0)
2671 panic("busdma error");
2672
2673 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2674
2675 for (idx = 0; idx < nsegs; idx++, psg++) {
2676 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2677 psg->wSgSize = segs[idx].ds_len;
2678 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2679/* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2680 }
2681/* psg[-1].wSgFlag = SG_FLAG_EOT; */
2682
2683 if (pCmd->cf_data_in) {
2684 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD);
2685 }
2686 else if (pCmd->cf_data_out) {
2687 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE);
2688 }
2689
2690 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb);
2691 pVDev->pfnSendCommand(_VBUS_P pCmd);
2692 CheckPendingCall(_VBUS_P0);
2693}
2694
2695
2696
2697static void HPTLIBAPI
2698OsSendCommand(_VBUS_ARG union ccb *ccb)
2699{
2700 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2701 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2702 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2703 struct ccb_scsiio *csio = &ccb->csio;
2704 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2705
2706 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2707 ccb,
2708 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2709 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2710 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2711 ));
2712
2713 pAdapter->outstandingCommands++;
2714
2715 if (pVDev == NULL || pVDev->vf_online == 0) {
2716 ccb->ccb_h.status = CAM_REQ_INVALID;
2717 ccb_done(ccb);
2718 goto Command_Complished;
2719 }
2720
2721 switch(ccb->csio.cdb_io.cdb_bytes[0])
2722 {
2723 case TEST_UNIT_READY:
2724 case START_STOP_UNIT:
2725 case SYNCHRONIZE_CACHE:
2726 /* FALLTHROUGH */
2727 ccb->ccb_h.status = CAM_REQ_CMP;
2728 break;
2729
2730 case INQUIRY:
2731 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2732 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2733 ccb_h->status = CAM_REQ_CMP;
2734 break;
2735
2736 case READ_CAPACITY:
2737 {
2738 UCHAR *rbuf=csio->data_ptr;
2739 unsigned int cap;
2740
2741 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2742 cap = 0xfffffffful;
2743 } else {
2744 cap = pVDev->VDeviceCapacity - 1;
2745 }
2746
2747 rbuf[0] = (UCHAR)(cap>>24);
2748 rbuf[1] = (UCHAR)(cap>>16);
2749 rbuf[2] = (UCHAR)(cap>>8);
2750 rbuf[3] = (UCHAR)cap;
2751 /* Claim 512 byte blocks (big-endian). */
2752 rbuf[4] = 0;
2753 rbuf[5] = 0;
2754 rbuf[6] = 2;
2755 rbuf[7] = 0;
2756
2757 ccb_h->status = CAM_REQ_CMP;
2758 break;
2759 }
2760
2761 case 0x9e: /*SERVICE_ACTION_IN*/
2762 {
2763 UCHAR *rbuf = csio->data_ptr;
2764 LBA_T cap = pVDev->VDeviceCapacity - 1;
2765
2766 rbuf[0] = (UCHAR)(cap>>56);
2767 rbuf[1] = (UCHAR)(cap>>48);
2768 rbuf[2] = (UCHAR)(cap>>40);
2769 rbuf[3] = (UCHAR)(cap>>32);
2770 rbuf[4] = (UCHAR)(cap>>24);
2771 rbuf[5] = (UCHAR)(cap>>16);
2772 rbuf[6] = (UCHAR)(cap>>8);
2773 rbuf[7] = (UCHAR)cap;
2774 rbuf[8] = 0;
2775 rbuf[9] = 0;
2776 rbuf[10] = 2;
2777 rbuf[11] = 0;
2778
2779 ccb_h->status = CAM_REQ_CMP;
2780 break;
2781 }
2782
2783 case READ_6:
2784 case WRITE_6:
2785 case READ_10:
2786 case WRITE_10:
2787 case 0x88: /* READ_16 */
2788 case 0x8a: /* WRITE_16 */
2789 case 0x13:
2790 case 0x2f:
2791 {
2792 UCHAR Cdb[16];
2793 UCHAR CdbLength;
2794 _VBUS_INST(pVDev->pVBus)
2795 PCommand pCmd = AllocateCommand(_VBUS_P0);
2796 HPT_ASSERT(pCmd);
2797
2798 CdbLength = csio->cdb_len;
2799 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2800 {
2801 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2802 {
2803 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2804 }
2805 else
2806 {
2807 KdPrintE(("ERROR!!!\n"));
2808 ccb->ccb_h.status = CAM_REQ_INVALID;
2809 break;
2810 }
2811 }
2812 else
2813 {
2814 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2815 }
2816
2817 pCmd->pOrgCommand = ccb;
2818 pCmd->pVDevice = pVDev;
2819 pCmd->pfnCompletion = fOsCommandDone;
2820 pCmd->pfnBuildSgl = fOsBuildSgl;
2821 pCmd->pSgTable = pmap->psg;
2822
2823 switch (Cdb[0])
2824 {
2825 case READ_6:
2826 case WRITE_6:
2827 case 0x13:
2828 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2829 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2830 break;
2831
2832 case 0x88: /* READ_16 */
2833 case 0x8a: /* WRITE_16 */
2834 pCmd->uCmd.Ide.Lba =
2835 (HPT_U64)Cdb[2] << 56 |
2836 (HPT_U64)Cdb[3] << 48 |
2837 (HPT_U64)Cdb[4] << 40 |
2838 (HPT_U64)Cdb[5] << 32 |
2839 (HPT_U64)Cdb[6] << 24 |
2840 (HPT_U64)Cdb[7] << 16 |
2841 (HPT_U64)Cdb[8] << 8 |
2842 (HPT_U64)Cdb[9];
2843 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2844 break;
2845
2846 default:
2847 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2848 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2849 break;
2850 }
2851
2852 switch (Cdb[0])
2853 {
2854 case READ_6:
2855 case READ_10:
2856 case 0x88: /* READ_16 */
2857 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2858 pCmd->cf_data_in = 1;
2859 break;
2860
2861 case WRITE_6:
2862 case WRITE_10:
2863 case 0x8a: /* WRITE_16 */
2864 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2865 pCmd->cf_data_out = 1;
2866 break;
2867 case 0x13:
2868 case 0x2f:
2869 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2870 break;
2871 }
2872/*///////////////////////// */
2873 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2874 int idx;
2875 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2876
2877 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2878 pCmd->cf_physical_sg = 1;
2879
2880 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2881 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2882 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len;
2883 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0;
2884 }
2885
2886 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb);
2887 pVDev->pfnSendCommand(_VBUS_P pCmd);
2888 }
2889 else {
2890 int error;
2891 pCmd->cf_physical_sg = 1;
2892 error = bus_dmamap_load(pAdapter->io_dma_parent,
2893 pmap->dma_map,
2894 ccb->csio.data_ptr, ccb->csio.dxfer_len,
2895 hpt_io_dmamap_callback, pCmd,
2896 BUS_DMA_WAITOK
2897 );
2898 KdPrint(("bus_dmamap_load return %d\n", error));
2899 if (error && error!=EINPROGRESS) {
2900 hpt_printk(("bus_dmamap_load error %d\n", error));
2901 FreeCommand(_VBUS_P pCmd);
2902 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2903 dmamap_put(pmap);
2904 pAdapter->outstandingCommands--;
2905 xpt_done(ccb);
2906 }
2907 }
2908 goto Command_Complished;
2909 }
2910
2911 default:
2912 ccb->ccb_h.status = CAM_REQ_INVALID;
2913 break;
2914 }
2915 ccb_done(ccb);
2916Command_Complished:
2917 CheckPendingCall(_VBUS_P0);
2918 return;
2919}
2920
2921static void HPTLIBAPI
2922fOsCommandDone(_VBUS_ARG PCommand pCmd)
2923{
2924 union ccb *ccb = pCmd->pOrgCommand;
2925 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2926 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2927
2928 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2929
2930 callout_stop(&ccb->ccb_h.timeout_ch);
2931
2932 switch(pCmd->Result) {
2933 case RETURN_SUCCESS:
2934 ccb->ccb_h.status = CAM_REQ_CMP;
2935 break;
2936 case RETURN_BAD_DEVICE:
2937 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2938 break;
2939 case RETURN_DEVICE_BUSY:
2940 ccb->ccb_h.status = CAM_BUSY;
2941 break;
2942 case RETURN_INVALID_REQUEST:
2943 ccb->ccb_h.status = CAM_REQ_INVALID;
2944 break;
2945 case RETURN_SELECTION_TIMEOUT:
2946 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2947 break;
2948 case RETURN_RETRY:
2949 ccb->ccb_h.status = CAM_BUSY;
2950 break;
2951 default:
2952 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2953 break;
2954 }
2955
2956 if (pCmd->cf_data_in) {
2957 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2958 }
2959 else if (pCmd->cf_data_in) {
2960 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2961 }
2962
2963 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2964
2965 FreeCommand(_VBUS_P pCmd);
2966 ccb_done(ccb);
2967}
2968
2969int
2970hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2971{
2972 int p;
2973
2974 p = (DpcQueue_Last + 1) % MAX_DPC;
2975 if (p==DpcQueue_First) {
2976 KdPrint(("DPC Queue full!\n"));
2977 return -1;
2978 }
2979
2980 DpcQueue[DpcQueue_Last].dpc = dpc;
2981 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2982 DpcQueue[DpcQueue_Last].arg = arg;
2983 DpcQueue[DpcQueue_Last].flags = flags;
2984 DpcQueue_Last = p;
2985
2986 return 0;
2987}
2988
2989#ifdef _RAID5N_
2990/*
2991 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2992 * How about the memory for 5081 request/response array and PRD table?
2993 */
2994void
2995*os_alloc_page(_VBUS_ARG0)
2996{
2997 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2998}
2999
3000void
3001*os_alloc_dma_page(_VBUS_ARG0)
3002{
3003 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
3004}
3005
3006void
3007os_free_page(_VBUS_ARG void *p)
3008{
3009 contigfree(p, 0x1000, M_DEVBUF);
3010}
3011
3012void
3013os_free_dma_page(_VBUS_ARG void *p)
3014{
3015 contigfree(p, 0x1000, M_DEVBUF);
3016}
3017
3018void
3019DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
3020{
3021 UINT i;
3022 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
3023}
3024
3025void
3026DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
3027{
3028 UINT i;
3029 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
3030}
3031#endif