ng_pppoe(4): Fix a typo in the code.
[dragonfly.git] / sys / dev / disk / mpt / mpt_pci.c
CommitLineData
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1/*-
2 * PCI specific probe and attach routines for LSI Fusion Adapters
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3 * FreeBSD Version.
4 *
d751f32e 5 * Copyright (c) 2000, 2001 by Greg Ansley
984263bc 6 * Partially derived from Matt Jacob's ISP driver.
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7 * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob
8 * Feral Software
9 * All rights reserved.
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10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
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32/*-
33 * Copyright (c) 2002, 2006 by Matthew Jacob
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are
38 * met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
42 * substantially similar to the "NO WARRANTY" disclaimer below
43 * ("Disclaimer") and any redistribution must be conditioned upon including
44 * a substantially similar Disclaimer requirement for further binary
45 * redistribution.
46 * 3. Neither the names of the above listed copyright holders nor the names
47 * of any contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
60 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 * Support from Chris Ellsworth in order to make SAS adapters work
63 * is gratefully acknowledged.
64 *
65 * Support from LSI-Logic has also gone a great deal toward making this a
66 * workable subsystem and is gratefully acknowledged.
67 */
984263bc 68/*
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69 * Copyright (c) 2004, Avid Technology, Inc. and its contributors.
70 * Copyright (c) 2005, WHEEL Sp. z o.o.
71 * Copyright (c) 2004, 2005 Justin T. Gibbs
72 * All rights reserved.
73 *
74 * Redistribution and use in source and binary forms, with or without
75 * modification, are permitted provided that the following conditions are
76 * met:
77 * 1. Redistributions of source code must retain the above copyright
78 * notice, this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
80 * substantially similar to the "NO WARRANTY" disclaimer below
81 * ("Disclaimer") and any redistribution must be conditioned upon including
82 * a substantially similar Disclaimer requirement for further binary
83 * redistribution.
84 * 3. Neither the names of the above listed copyright holders nor the names
85 * of any contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
91 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
92 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
98 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af04f7 99 *
2545bca0 100 * $FreeBSD: src/sys/dev/mpt/mpt_pci.c,v 1.54 2009/07/10 08:18:08 scottl Exp $
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101 */
102
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103#include <dev/disk/mpt/mpt.h>
104#include <dev/disk/mpt/mpt_cam.h>
105#include <dev/disk/mpt/mpt_raid.h>
984263bc 106
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107#if __FreeBSD_version < 700000
108#define pci_msix_count(x) 0
109#define pci_msi_count(x) 0
110#define pci_alloc_msi(x, y) 1
111#define pci_alloc_msix(x, y) 1
112#define pci_release_msi(x) do { ; } while (0)
113#endif
114
115#ifndef PCI_VENDOR_LSI
116#define PCI_VENDOR_LSI 0x1000
117#endif
984263bc 118
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119#ifndef PCI_PRODUCT_LSI_FC909
120#define PCI_PRODUCT_LSI_FC909 0x0620
121#endif
122
123#ifndef PCI_PRODUCT_LSI_FC909A
124#define PCI_PRODUCT_LSI_FC909A 0x0621
125#endif
126
127#ifndef PCI_PRODUCT_LSI_FC919
128#define PCI_PRODUCT_LSI_FC919 0x0624
129#endif
130
131#ifndef PCI_PRODUCT_LSI_FC929
132#define PCI_PRODUCT_LSI_FC929 0x0622
133#endif
134
135#ifndef PCI_PRODUCT_LSI_FC929X
136#define PCI_PRODUCT_LSI_FC929X 0x0626
137#endif
138
139#ifndef PCI_PRODUCT_LSI_FC919X
140#define PCI_PRODUCT_LSI_FC919X 0x0628
141#endif
142
143#ifndef PCI_PRODUCT_LSI_FC7X04X
144#define PCI_PRODUCT_LSI_FC7X04X 0x0640
145#endif
146
147#ifndef PCI_PRODUCT_LSI_FC646
148#define PCI_PRODUCT_LSI_FC646 0x0646
149#endif
150
151#ifndef PCI_PRODUCT_LSI_1030
152#define PCI_PRODUCT_LSI_1030 0x0030
153#endif
154
155#ifndef PCI_PRODUCT_LSI_SAS1064
156#define PCI_PRODUCT_LSI_SAS1064 0x0050
157#endif
158
159#ifndef PCI_PRODUCT_LSI_SAS1064A
160#define PCI_PRODUCT_LSI_SAS1064A 0x005C
161#endif
162
163#ifndef PCI_PRODUCT_LSI_SAS1064E
164#define PCI_PRODUCT_LSI_SAS1064E 0x0056
165#endif
166
167#ifndef PCI_PRODUCT_LSI_SAS1066
168#define PCI_PRODUCT_LSI_SAS1066 0x005E
169#endif
170
171#ifndef PCI_PRODUCT_LSI_SAS1066E
172#define PCI_PRODUCT_LSI_SAS1066E 0x005A
173#endif
174
175#ifndef PCI_PRODUCT_LSI_SAS1068
176#define PCI_PRODUCT_LSI_SAS1068 0x0054
177#endif
178
179#ifndef PCI_PRODUCT_LSI_SAS1068E
180#define PCI_PRODUCT_LSI_SAS1068E 0x0058
181#endif
182
183#ifndef PCI_PRODUCT_LSI_SAS1078
184#define PCI_PRODUCT_LSI_SAS1078 0x0062
185#endif
186
187#ifndef PCI_PRODUCT_LSI_SAS1078DE
188#define PCI_PRODUCT_LSI_SAS1078DE 0x007C
189#endif
984263bc 190
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191#ifndef PCIM_CMD_SERRESPEN
192#define PCIM_CMD_SERRESPEN 0x0100
193#endif
194
195
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196#define MPT_IO_BAR 0
197#define MPT_MEM_BAR 1
984263bc 198
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199static int mpt_pci_probe(device_t);
200static int mpt_pci_attach(device_t);
201static void mpt_free_bus_resources(struct mpt_softc *mpt);
202static int mpt_pci_detach(device_t);
203static int mpt_pci_shutdown(device_t);
204static int mpt_dma_mem_alloc(struct mpt_softc *mpt);
205static void mpt_dma_mem_free(struct mpt_softc *mpt);
206static void mpt_read_config_regs(struct mpt_softc *mpt);
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207static void mpt_pci_intr(void *);
208
209static device_method_t mpt_methods[] = {
210 /* Device interface */
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211 DEVMETHOD(device_probe, mpt_pci_probe),
212 DEVMETHOD(device_attach, mpt_pci_attach),
213 DEVMETHOD(device_detach, mpt_pci_detach),
214 DEVMETHOD(device_shutdown, mpt_pci_shutdown),
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215 { 0, 0 }
216};
217
218static driver_t mpt_driver = {
d751f32e 219 "mpt", mpt_methods, sizeof(struct mpt_softc)
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220};
221static devclass_t mpt_devclass;
222DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, 0, 0);
d751f32e 223MODULE_DEPEND(mpt, pci, 1, 1, 1);
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224MODULE_VERSION(mpt, 1);
225
984263bc 226static int
d751f32e 227mpt_pci_probe(device_t dev)
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228{
229 char *desc;
230
d751f32e 231 if (pci_get_vendor(dev) != PCI_VENDOR_LSI) {
984263bc 232 return (ENXIO);
d751f32e 233 }
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234
235 switch ((pci_get_device(dev) & ~1)) {
d751f32e 236 case PCI_PRODUCT_LSI_FC909:
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237 desc = "LSILogic FC909 FC Adapter";
238 break;
d751f32e 239 case PCI_PRODUCT_LSI_FC909A:
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240 desc = "LSILogic FC909A FC Adapter";
241 break;
d751f32e 242 case PCI_PRODUCT_LSI_FC919:
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243 desc = "LSILogic FC919 FC Adapter";
244 break;
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245 case PCI_PRODUCT_LSI_FC929:
246 desc = "Dual LSILogic FC929 FC Adapter";
984263bc 247 break;
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248 case PCI_PRODUCT_LSI_FC919X:
249 desc = "LSILogic FC919 FC PCI-X Adapter";
d30c73c7 250 break;
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251 case PCI_PRODUCT_LSI_FC929X:
252 desc = "Dual LSILogic FC929X 2Gb/s FC PCI-X Adapter";
253 break;
254 case PCI_PRODUCT_LSI_FC646:
255 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-Express Adapter";
256 break;
257 case PCI_PRODUCT_LSI_FC7X04X:
258 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-X Adapter";
259 break;
260 case PCI_PRODUCT_LSI_1030:
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261 desc = "LSILogic 1030 Ultra4 Adapter";
262 break;
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263 case PCI_PRODUCT_LSI_SAS1064:
264 case PCI_PRODUCT_LSI_SAS1064A:
265 case PCI_PRODUCT_LSI_SAS1064E:
266 case PCI_PRODUCT_LSI_SAS1066:
267 case PCI_PRODUCT_LSI_SAS1066E:
268 case PCI_PRODUCT_LSI_SAS1068:
269 case PCI_PRODUCT_LSI_SAS1068E:
270 case PCI_PRODUCT_LSI_SAS1078:
271 case PCI_PRODUCT_LSI_SAS1078DE:
272 desc = "LSILogic SAS/SATA Adapter";
273 break;
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274 default:
275 return (ENXIO);
276 }
277
278 device_set_desc(dev, desc);
279 return (0);
280}
281
d751f32e 282#if __FreeBSD_version < 500000
984263bc 283static void
d751f32e 284mpt_set_options(struct mpt_softc *mpt)
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285{
286 int bitmap;
287
288 bitmap = 0;
2545bca0 289 if (kgetenv_int("mpt_disable", &bitmap)) {
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290 if (bitmap & (1 << mpt->unit)) {
291 mpt->disabled = 1;
292 }
293 }
d751f32e 294 bitmap = 0;
2545bca0 295 if (kgetenv_int("mpt_debug", &bitmap)) {
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296 if (bitmap & (1 << mpt->unit)) {
297 mpt->verbose = MPT_PRT_DEBUG;
298 }
299 }
300 bitmap = 0;
2545bca0 301 if (kgetenv_int("mpt_debug1", &bitmap)) {
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302 if (bitmap & (1 << mpt->unit)) {
303 mpt->verbose = MPT_PRT_DEBUG1;
304 }
305 }
306 bitmap = 0;
2545bca0 307 if (kgetenv_int("mpt_debug2", &bitmap)) {
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308 if (bitmap & (1 << mpt->unit)) {
309 mpt->verbose = MPT_PRT_DEBUG2;
310 }
311 }
312 bitmap = 0;
2545bca0 313 if (kgetenv_int("mpt_debug3", &bitmap)) {
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314 if (bitmap & (1 << mpt->unit)) {
315 mpt->verbose = MPT_PRT_DEBUG3;
316 }
317 }
984263bc 318
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319 mpt->cfg_role = MPT_ROLE_DEFAULT;
320 bitmap = 0;
2545bca0 321 if (kgetenv_int("mpt_nil_role", &bitmap)) {
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322 if (bitmap & (1 << mpt->unit)) {
323 mpt->cfg_role = 0;
324 }
325 mpt->do_cfg_role = 1;
326 }
327 bitmap = 0;
2545bca0 328 if (kgetenv_int("mpt_tgt_role", &bitmap)) {
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329 if (bitmap & (1 << mpt->unit)) {
330 mpt->cfg_role |= MPT_ROLE_TARGET;
331 }
332 mpt->do_cfg_role = 1;
333 }
984263bc 334 bitmap = 0;
2545bca0 335 if (kgetenv_int("mpt_ini_role", &bitmap)) {
984263bc 336 if (bitmap & (1 << mpt->unit)) {
d751f32e 337 mpt->cfg_role |= MPT_ROLE_INITIATOR;
984263bc 338 }
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339 mpt->do_cfg_role = 1;
340 }
341 mpt->msi_enable = 0;
342}
343#else
344static void
345mpt_set_options(struct mpt_softc *mpt)
346{
347 int tval;
348
349 tval = 0;
350 if (resource_int_value(device_get_name(mpt->dev),
351 device_get_unit(mpt->dev), "disable", &tval) == 0 && tval != 0) {
352 mpt->disabled = 1;
353 }
354 tval = 0;
355 if (resource_int_value(device_get_name(mpt->dev),
356 device_get_unit(mpt->dev), "debug", &tval) == 0 && tval != 0) {
357 mpt->verbose = tval;
358 }
359 tval = -1;
360 if (resource_int_value(device_get_name(mpt->dev),
361 device_get_unit(mpt->dev), "role", &tval) == 0 && tval >= 0 &&
362 tval <= 3) {
363 mpt->cfg_role = tval;
364 mpt->do_cfg_role = 1;
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365 }
366
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367 tval = 0;
368 mpt->msi_enable = 0;
369 if (resource_int_value(device_get_name(mpt->dev),
370 device_get_unit(mpt->dev), "msi_enable", &tval) == 0 && tval == 1) {
371 mpt->msi_enable = 1;
372 }
984263bc 373}
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374#endif
375
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376
377static void
d751f32e 378mpt_link_peer(struct mpt_softc *mpt)
984263bc 379{
d751f32e 380 struct mpt_softc *mpt2;
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381
382 if (mpt->unit == 0) {
383 return;
384 }
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385 /*
386 * XXX: depends on probe order
387 */
d751f32e 388 mpt2 = (struct mpt_softc *)devclass_get_softc(mpt_devclass,mpt->unit-1);
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389
390 if (mpt2 == NULL) {
391 return;
392 }
393 if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) {
394 return;
395 }
396 if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) {
397 return;
398 }
399 mpt->mpt2 = mpt2;
400 mpt2->mpt2 = mpt;
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401 if (mpt->verbose >= MPT_PRT_DEBUG) {
402 mpt_prt(mpt, "linking with peer (mpt%d)\n",
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403 device_get_unit(mpt2->dev));
404 }
405}
406
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407static void
408mpt_unlink_peer(struct mpt_softc *mpt)
409{
410 if (mpt->mpt2) {
411 mpt->mpt2->mpt2 = NULL;
412 }
413}
414
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415
416static int
d751f32e 417mpt_pci_attach(device_t dev)
984263bc 418{
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419 struct mpt_softc *mpt;
420 int iqd;
421 uint32_t data, cmd;
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422
423 /* Allocate the softc structure */
d751f32e 424 mpt = (struct mpt_softc*)device_get_softc(dev);
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425 if (mpt == NULL) {
426 device_printf(dev, "cannot allocate softc\n");
427 return (ENOMEM);
428 }
d751f32e 429 memset(mpt, 0, sizeof(struct mpt_softc));
984263bc 430 switch ((pci_get_device(dev) & ~1)) {
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431 case PCI_PRODUCT_LSI_FC909:
432 case PCI_PRODUCT_LSI_FC909A:
433 case PCI_PRODUCT_LSI_FC919:
434 case PCI_PRODUCT_LSI_FC929:
435 case PCI_PRODUCT_LSI_FC919X:
436 case PCI_PRODUCT_LSI_FC646:
437 case PCI_PRODUCT_LSI_FC7X04X:
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438 mpt->is_fc = 1;
439 break;
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440 case PCI_PRODUCT_LSI_SAS1064:
441 case PCI_PRODUCT_LSI_SAS1064A:
442 case PCI_PRODUCT_LSI_SAS1064E:
443 case PCI_PRODUCT_LSI_SAS1066:
444 case PCI_PRODUCT_LSI_SAS1066E:
445 case PCI_PRODUCT_LSI_SAS1068:
446 case PCI_PRODUCT_LSI_SAS1068E:
447 case PCI_PRODUCT_LSI_SAS1078:
448 case PCI_PRODUCT_LSI_SAS1078DE:
449 mpt->is_sas = 1;
450 break;
984263bc 451 default:
d751f32e 452 mpt->is_spi = 1;
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453 break;
454 }
455 mpt->dev = dev;
456 mpt->unit = device_get_unit(dev);
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457 mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT;
458 mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT;
459 mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT;
460 mpt->verbose = MPT_PRT_NONE;
461 mpt->role = MPT_ROLE_NONE;
984263bc 462 mpt_set_options(mpt);
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463 if (mpt->verbose == MPT_PRT_NONE) {
464 mpt->verbose = MPT_PRT_WARN;
465 /* Print INFO level (if any) if bootverbose is set */
466 mpt->verbose += (bootverbose != 0)? 1 : 0;
467 }
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468 /* Make sure memory access decoders are enabled */
469 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
470 if ((cmd & PCIM_CMD_MEMEN) == 0) {
471 device_printf(dev, "Memory accesses disabled");
d751f32e 472 return (ENXIO);
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473 }
474
475 /*
476 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
477 */
478 cmd |=
479 PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
480 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
481 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
482
483 /*
484 * Make sure we've disabled the ROM.
485 */
486 data = pci_read_config(dev, PCIR_BIOS, 4);
487 data &= ~1;
488 pci_write_config(dev, PCIR_BIOS, data, 4);
489
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490 /*
491 * Is this part a dual?
492 * If so, link with our partner (around yet)
493 */
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494 if ((pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC929 ||
495 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC646 ||
496 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC7X04X ||
497 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_1030) {
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498 mpt_link_peer(mpt);
499 }
500
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501 /*
502 * Set up register access. PIO mode is required for
503 * certain reset operations (but must be disabled for
504 * some cards otherwise).
505 */
506 mpt->pci_pio_rid = PCIR_BAR(MPT_IO_BAR);
507 mpt->pci_pio_reg = bus_alloc_resource(dev, SYS_RES_IOPORT,
508 &mpt->pci_pio_rid, 0, ~0, 0, RF_ACTIVE);
509 if (mpt->pci_pio_reg == NULL) {
510 device_printf(dev, "unable to map registers in PIO mode\n");
511 goto bad;
512 }
513 mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg);
514 mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
515
984263bc 516 /* Allocate kernel virtual memory for the 9x9's Mem0 region */
d751f32e 517 mpt->pci_mem_rid = PCIR_BAR(MPT_MEM_BAR);
984263bc 518 mpt->pci_reg = bus_alloc_resource(dev, SYS_RES_MEMORY,
d751f32e 519 &mpt->pci_mem_rid, 0, ~0, 0, RF_ACTIVE);
984263bc 520 if (mpt->pci_reg == NULL) {
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521 device_printf(dev, "Unable to memory map registers.\n");
522 if (mpt->is_sas) {
523 device_printf(dev, "Giving Up.\n");
524 goto bad;
525 }
526 device_printf(dev, "Falling back to PIO mode.\n");
527 mpt->pci_st = mpt->pci_pio_st;
528 mpt->pci_sh = mpt->pci_pio_sh;
529 } else {
530 mpt->pci_st = rman_get_bustag(mpt->pci_reg);
531 mpt->pci_sh = rman_get_bushandle(mpt->pci_reg);
984263bc 532 }
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533
534 /* Get a handle to the interrupt */
535 iqd = 0;
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536 if (mpt->msi_enable) {
537 /*
538 * First try to alloc an MSI-X message. If that
539 * fails, then try to alloc an MSI message instead.
540 */
541 if (pci_msix_count(dev) == 1) {
542 mpt->pci_msi_count = 1;
543 if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) {
544 iqd = 1;
545 } else {
546 mpt->pci_msi_count = 0;
547 }
548 }
549 if (iqd == 0 && pci_msi_count(dev) == 1) {
550 mpt->pci_msi_count = 1;
551 if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) {
552 iqd = 1;
553 } else {
554 mpt->pci_msi_count = 0;
555 }
556 }
557 }
558 mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
559 RF_ACTIVE | RF_SHAREABLE);
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560 if (mpt->pci_irq == NULL) {
561 device_printf(dev, "could not allocate interrupt\n");
562 goto bad;
563 }
564
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565 MPT_LOCK_SETUP(mpt);
566
567 /* Disable interrupts at the part */
568 mpt_disable_ints(mpt);
569
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MD
570 /* Register the interrupt handler */
571 if (mpt_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, NULL, mpt_pci_intr,
572 mpt, &mpt->ih)) {
573 device_printf(dev, "could not setup interrupt\n");
574 goto bad;
575 }
576
984263bc 577 /* Allocate dma memory */
2545bca0 578 /* XXX JGibbs -Should really be done based on IOCFacts. */
984263bc 579 if (mpt_dma_mem_alloc(mpt)) {
d751f32e 580 mpt_prt(mpt, "Could not allocate DMA memory\n");
984263bc
MD
581 goto bad;
582 }
583
584 /*
585 * Save the PCI config register values
586 *
587 * Hard resets are known to screw up the BAR for diagnostic
588 * memory accesses (Mem1).
589 *
590 * Using Mem1 is known to make the chip stop responding to
591 * configuration space transfers, so we need to save it now
592 */
593
594 mpt_read_config_regs(mpt);
595
d751f32e
MD
596 /*
597 * Disable PIO until we need it
598 */
599 if (mpt->is_sas) {
600 pci_disable_io(dev, SYS_RES_IOPORT);
601 }
602
984263bc
MD
603 /* Initialize the hardware */
604 if (mpt->disabled == 0) {
d751f32e 605 if (mpt_attach(mpt) != 0) {
984263bc
MD
606 goto bad;
607 }
d751f32e
MD
608 } else {
609 mpt_prt(mpt, "device disabled at user request\n");
610 goto bad;
984263bc
MD
611 }
612
d751f32e
MD
613 mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown,
614 dev, SHUTDOWN_PRI_DEFAULT);
615
616 if (mpt->eh == NULL) {
617 mpt_prt(mpt, "shutdown event registration failed\n");
618 (void) mpt_detach(mpt);
619 goto bad;
620 }
984263bc
MD
621 return (0);
622
623bad:
624 mpt_dma_mem_free(mpt);
625 mpt_free_bus_resources(mpt);
d751f32e
MD
626 mpt_unlink_peer(mpt);
627
628 MPT_LOCK_DESTROY(mpt);
984263bc
MD
629
630 /*
631 * but return zero to preserve unit numbering
632 */
633 return (0);
634}
635
636/*
637 * Free bus resources
638 */
639static void
d751f32e 640mpt_free_bus_resources(struct mpt_softc *mpt)
984263bc
MD
641{
642 if (mpt->ih) {
643 bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih);
644 mpt->ih = 0;
645 }
646
647 if (mpt->pci_irq) {
d751f32e
MD
648 bus_release_resource(mpt->dev, SYS_RES_IRQ,
649 mpt->pci_msi_count ? 1 : 0, mpt->pci_irq);
984263bc
MD
650 mpt->pci_irq = 0;
651 }
652
d751f32e
MD
653 if (mpt->pci_msi_count) {
654 pci_release_msi(mpt->dev);
655 mpt->pci_msi_count = 0;
656 }
657
658 if (mpt->pci_pio_reg) {
659 bus_release_resource(mpt->dev, SYS_RES_IOPORT, mpt->pci_pio_rid,
660 mpt->pci_pio_reg);
661 mpt->pci_pio_reg = 0;
662 }
984263bc 663 if (mpt->pci_reg) {
d751f32e 664 bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_mem_rid,
984263bc
MD
665 mpt->pci_reg);
666 mpt->pci_reg = 0;
667 }
668 MPT_LOCK_DESTROY(mpt);
669}
670
671
672/*
673 * Disconnect ourselves from the system.
674 */
675static int
d751f32e 676mpt_pci_detach(device_t dev)
984263bc 677{
d751f32e 678 struct mpt_softc *mpt;
984263bc 679
d751f32e 680 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
681
682 if (mpt) {
683 mpt_disable_ints(mpt);
d751f32e
MD
684 mpt_detach(mpt);
685 mpt_reset(mpt, /*reinit*/FALSE);
984263bc
MD
686 mpt_dma_mem_free(mpt);
687 mpt_free_bus_resources(mpt);
d751f32e
MD
688 mpt_raid_free_mem(mpt);
689 if (mpt->eh != NULL) {
690 EVENTHANDLER_DEREGISTER(shutdown_post_sync, mpt->eh);
691 }
984263bc
MD
692 }
693 return(0);
694}
695
696
697/*
698 * Disable the hardware
699 */
700static int
d751f32e 701mpt_pci_shutdown(device_t dev)
984263bc 702{
d751f32e 703 struct mpt_softc *mpt;
984263bc 704
d751f32e 705 mpt = (struct mpt_softc *)device_get_softc(dev);
984263bc 706 if (mpt) {
d751f32e
MD
707 int r;
708 r = mpt_shutdown(mpt);
709 return (r);
984263bc
MD
710 }
711 return(0);
712}
713
984263bc 714static int
d751f32e 715mpt_dma_mem_alloc(struct mpt_softc *mpt)
984263bc 716{
d751f32e
MD
717 int i, error, nsegs;
718 uint8_t *vptr;
719 uint32_t pptr, end;
984263bc 720 size_t len;
d751f32e 721 struct mpt_map_info mi;
984263bc
MD
722
723 /* Check if we alreay have allocated the reply memory */
3641b7ca 724 if (mpt->reply_phys != 0) {
984263bc
MD
725 return 0;
726 }
727
d751f32e
MD
728 len = sizeof (request_t) * MPT_MAX_REQUESTS(mpt);
729#ifdef RELENG_4
2545bca0 730 mpt->request_pool = (request_t *)kmalloc(len, M_DEVBUF, M_WAITOK);
d751f32e
MD
731 if (mpt->request_pool == NULL) {
732 mpt_prt(mpt, "cannot allocate request pool\n");
733 return (1);
734 }
735 memset(mpt->request_pool, 0, len);
736#else
2545bca0 737 mpt->request_pool = (request_t *)kmalloc(len, M_DEVBUF, M_WAITOK|M_ZERO);
d751f32e
MD
738 if (mpt->request_pool == NULL) {
739 mpt_prt(mpt, "cannot allocate request pool\n");
740 return (1);
741 }
742#endif
984263bc
MD
743
744 /*
d751f32e 745 * Create a parent dma tag for this device.
984263bc 746 *
d751f32e
MD
747 * Align at byte boundaries,
748 * Limit to 32-bit addressing for request/reply queues.
984263bc 749 */
d751f32e
MD
750 if (mpt_dma_tag_create(mpt, /*parent*/bus_get_dma_tag(mpt->dev),
751 /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
752 /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL,
753 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
754 /*nsegments*/BUS_SPACE_MAXSIZE_32BIT,
755 /*maxsegsz*/BUS_SPACE_UNRESTRICTED, /*flags*/0,
984263bc 756 &mpt->parent_dmat) != 0) {
d751f32e 757 mpt_prt(mpt, "cannot create parent dma tag\n");
984263bc
MD
758 return (1);
759 }
760
761 /* Create a child tag for reply buffers */
d751f32e
MD
762 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
763 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
764 NULL, NULL, 2 * PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 765 &mpt->reply_dmat) != 0) {
d751f32e 766 mpt_prt(mpt, "cannot create a dma tag for replies\n");
984263bc
MD
767 return (1);
768 }
769
770 /* Allocate some DMA accessable memory for replies */
771 if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply,
772 BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) {
d751f32e
MD
773 mpt_prt(mpt, "cannot allocate %lu bytes of reply memory\n",
774 (u_long) (2 * PAGE_SIZE));
984263bc
MD
775 return (1);
776 }
777
d751f32e
MD
778 mi.mpt = mpt;
779 mi.error = 0;
984263bc
MD
780
781 /* Load and lock it into "bus space" */
782 bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply,
d751f32e 783 2 * PAGE_SIZE, mpt_map_rquest, &mi, 0);
984263bc 784
d751f32e
MD
785 if (mi.error) {
786 mpt_prt(mpt, "error %d loading dma map for DMA reply queue\n",
787 mi.error);
984263bc
MD
788 return (1);
789 }
d751f32e 790 mpt->reply_phys = mi.phys;
984263bc
MD
791
792 /* Create a child tag for data buffers */
d751f32e
MD
793
794 /*
795 * XXX: we should say that nsegs is 'unrestricted, but that
796 * XXX: tickles a horrible bug in the busdma code. Instead,
797 * XXX: we'll derive a reasonable segment limit from MPT_MAXPHYS
798 */
799 nsegs = (MPT_MAXPHYS / PAGE_SIZE) + 1;
800 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, 1,
984263bc 801 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
d751f32e 802 NULL, NULL, MAXBSIZE, nsegs, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 803 &mpt->buffer_dmat) != 0) {
d751f32e 804 mpt_prt(mpt, "cannot create a dma tag for data buffers\n");
984263bc
MD
805 return (1);
806 }
807
808 /* Create a child tag for request buffers */
d751f32e
MD
809 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
810 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
984263bc
MD
811 NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0,
812 &mpt->request_dmat) != 0) {
d751f32e 813 mpt_prt(mpt, "cannot create a dma tag for requests\n");
984263bc
MD
814 return (1);
815 }
816
817 /* Allocate some DMA accessable memory for requests */
818 if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request,
819 BUS_DMA_NOWAIT, &mpt->request_dmap) != 0) {
d751f32e 820 mpt_prt(mpt, "cannot allocate %d bytes of request memory\n",
984263bc
MD
821 MPT_REQ_MEM_SIZE(mpt));
822 return (1);
823 }
824
d751f32e
MD
825 mi.mpt = mpt;
826 mi.error = 0;
984263bc
MD
827
828 /* Load and lock it into "bus space" */
829 bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request,
d751f32e 830 MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &mi, 0);
984263bc 831
d751f32e
MD
832 if (mi.error) {
833 mpt_prt(mpt, "error %d loading dma map for DMA request queue\n",
834 mi.error);
984263bc
MD
835 return (1);
836 }
d751f32e 837 mpt->request_phys = mi.phys;
984263bc 838
d751f32e
MD
839 /*
840 * Now create per-request dma maps
841 */
984263bc
MD
842 i = 0;
843 pptr = mpt->request_phys;
844 vptr = mpt->request;
845 end = pptr + MPT_REQ_MEM_SIZE(mpt);
846 while(pptr < end) {
847 request_t *req = &mpt->request_pool[i];
848 req->index = i++;
849
850 /* Store location of Request Data */
851 req->req_pbuf = pptr;
852 req->req_vbuf = vptr;
853
854 pptr += MPT_REQUEST_AREA;
855 vptr += MPT_REQUEST_AREA;
856
857 req->sense_pbuf = (pptr - MPT_SENSE_SIZE);
858 req->sense_vbuf = (vptr - MPT_SENSE_SIZE);
859
860 error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap);
861 if (error) {
d751f32e
MD
862 mpt_prt(mpt, "error %d creating per-cmd DMA maps\n",
863 error);
984263bc
MD
864 return (1);
865 }
866 }
d751f32e 867
984263bc
MD
868 return (0);
869}
870
871
872
873/* Deallocate memory that was allocated by mpt_dma_mem_alloc
874 */
875static void
d751f32e 876mpt_dma_mem_free(struct mpt_softc *mpt)
984263bc
MD
877{
878 int i;
879
880 /* Make sure we aren't double destroying */
881 if (mpt->reply_dmat == 0) {
d751f32e 882 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n");
984263bc
MD
883 return;
884 }
885
886 for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) {
887 bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap);
888 }
889 bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap);
890 bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap);
891 bus_dma_tag_destroy(mpt->request_dmat);
892 bus_dma_tag_destroy(mpt->buffer_dmat);
893 bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap);
894 bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap);
895 bus_dma_tag_destroy(mpt->reply_dmat);
896 bus_dma_tag_destroy(mpt->parent_dmat);
897 mpt->reply_dmat = 0;
2545bca0 898 kfree(mpt->request_pool, M_DEVBUF);
984263bc
MD
899 mpt->request_pool = 0;
900
901}
902
903
904
905/* Reads modifiable (via PCI transactions) config registers */
906static void
d751f32e 907mpt_read_config_regs(struct mpt_softc *mpt)
984263bc
MD
908{
909 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
910 mpt->pci_cfg.LatencyTimer_LineSize =
911 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
d751f32e
MD
912 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
913 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
914 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
915 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
916 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4);
984263bc
MD
917 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4);
918 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1);
919 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4);
920}
921
922/* Sets modifiable config registers */
923void
d751f32e 924mpt_set_config_regs(struct mpt_softc *mpt)
984263bc 925{
d751f32e 926 uint32_t val;
984263bc
MD
927
928#define MPT_CHECK(reg, offset, size) \
929 val = pci_read_config(mpt->dev, offset, size); \
930 if (mpt->pci_cfg.reg != val) { \
d751f32e 931 mpt_prt(mpt, \
984263bc
MD
932 "Restoring " #reg " to 0x%X from 0x%X\n", \
933 mpt->pci_cfg.reg, val); \
934 }
935
d751f32e 936 if (mpt->verbose >= MPT_PRT_DEBUG) {
984263bc
MD
937 MPT_CHECK(Command, PCIR_COMMAND, 2);
938 MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2);
d751f32e
MD
939 MPT_CHECK(IO_BAR, PCIR_BAR(0), 4);
940 MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4);
941 MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4);
942 MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4);
943 MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4);
984263bc
MD
944 MPT_CHECK(ROM_BAR, PCIR_BIOS, 4);
945 MPT_CHECK(IntLine, PCIR_INTLINE, 1);
946 MPT_CHECK(PMCSR, 0x44, 4);
947 }
948#undef MPT_CHECK
949
950 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
951 pci_write_config(mpt->dev, PCIR_CACHELNSZ,
952 mpt->pci_cfg.LatencyTimer_LineSize, 2);
d751f32e
MD
953 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4);
954 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4);
955 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4);
956 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4);
957 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4);
984263bc
MD
958 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4);
959 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1);
960 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4);
961}
962
963static void
964mpt_pci_intr(void *arg)
965{
d751f32e
MD
966 struct mpt_softc *mpt;
967
968 mpt = (struct mpt_softc *)arg;
984263bc 969 MPT_LOCK(mpt);
d751f32e 970 mpt_intr(mpt);
984263bc
MD
971 MPT_UNLOCK(mpt);
972}