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mfi(4): Update to LSI's version 4.23 of the driver.
[dragonfly.git] / sys / dev / raid / mfi / mfireg.h
CommitLineData
249d29c8
SW		 1/*-
2 * Copyright (c) 2006 IronPort Systems
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26/*-
27 * Copyright (c) 2007 LSI Corp.
28 * Copyright (c) 2007 Rajesh Prabhakaran.
29 * All rights reserved.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 * 1. Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * 2. Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in the
38 * documentation and/or other materials provided with the distribution.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
f26fa772 52 * $FreeBSD: src/sys/dev/mfi/mfireg.h,v 1.16 2011/07/14 20:20:33 jhb Exp $
590ba11d 53 * FreeBSD projects/head_mfi/ r232888
249d29c8
SW		 54 */
55
56#ifndef _MFIREG_H
57#define _MFIREG_H
58
59/*
60 * MegaRAID SAS MFI firmware definitions
61 *
62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely
63 * new firmware interface from the old AMI MegaRAID one, and there is no
64 * reason why this interface should be limited to just SAS. In any case, LSI
65 * seems to also call this interface 'MFI', so that will be used here.
66 */
67
590ba11d
SW		 68#define MEGAMFI_FRAME_SIZE 64
69
249d29c8
SW		 70/*
71 * Start with the register set. All registers are 32 bits wide.
72 * The usual Intel IOP style setup.
73 */
74#define MFI_IMSG0 0x10 /* Inbound message 0 */
75#define MFI_IMSG1 0x14 /* Inbound message 1 */
76#define MFI_OMSG0 0x18 /* Outbound message 0 */
77#define MFI_OMSG1 0x1c /* Outbound message 1 */
78#define MFI_IDB 0x20 /* Inbound doorbell */
79#define MFI_ISTS 0x24 /* Inbound interrupt status */
80#define MFI_IMSK 0x28 /* Inbound interrupt mask */
81#define MFI_ODB 0x2c /* Outbound doorbell */
82#define MFI_OSTS 0x30 /* Outbound interrupt status */
83#define MFI_OMSK 0x34 /* Outbound interrupt mask */
84#define MFI_IQP 0x40 /* Inbound queue port */
85#define MFI_OQP 0x44 /* Outbound queue port */
86
87/*
590ba11d
SW		 88 * ThunderBolt specific Register
89 */
90
91#define MFI_RPI 0x6c /* reply_post_host_index */
92#define MFI_ILQP 0xc0 /* inbound_low_queue_port */
93#define MFI_IHQP 0xc4 /* inbound_high_queue_port */
94
95/*
249d29c8
SW		 96 * 1078 specific related register
97 */
98#define MFI_ODR0 0x9c /* outbound doorbell register0 */
99#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
100#define MFI_OSP0 0xb0 /* outbound scratch pad0 */
101#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
102#define MFI_RMI 0x2 /* reply message interrupt */
103#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
104#define MFI_ODC 0x4 /* outbound doorbell change interrupt */
105
590ba11d
SW		 106/* OCR registers */
107#define MFI_WSR 0x004 /* write sequence register */
108#define MFI_HDR 0x008 /* host diagnostic register */
109#define MFI_RSR 0x3c3 /* Reset Status Register */
110
249d29c8
SW		 111/*
112 * GEN2 specific changes
113 */
114#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */
115#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */
116
17566092 117/*
17566092
SW		 118 * skinny specific changes
119 */
120#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */
121#define MFI_IQPL 0x000000c0
122#define MFI_IQPH 0x000000c4
123#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */
124
249d29c8
SW		 125/* Bits for MFI_OSTS */
126#define MFI_OSTS_INTR_VALID 0x00000002
127
590ba11d
SW		 128/* OCR specific flags */
129#define MFI_FIRMWARE_STATE_CHANGE 0x00000002
130#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */
131
249d29c8
SW		 132/*
133 * Firmware state values. Found in OMSG0 during initialization.
134 */
135#define MFI_FWSTATE_MASK 0xf0000000
136#define MFI_FWSTATE_UNDEFINED 0x00000000
137#define MFI_FWSTATE_BB_INIT 0x10000000
138#define MFI_FWSTATE_FW_INIT 0x40000000
139#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
140#define MFI_FWSTATE_FW_INIT_2 0x70000000
141#define MFI_FWSTATE_DEVICE_SCAN 0x80000000
f26fa772 142#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000
249d29c8
SW		 143#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
144#define MFI_FWSTATE_READY 0xb0000000
145#define MFI_FWSTATE_OPERATIONAL 0xc0000000
146#define MFI_FWSTATE_FAULT 0xf0000000
147#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
148#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
17566092
SW		 149#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000
150#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000
590ba11d
SW		 151#define MFI_RESET_REQUIRED 0x00000001
152
153/* ThunderBolt Support */
154#define MFI_FWSTATE_TB_MASK 0xf0000000
155#define MFI_FWSTATE_TB_RESET 0x00000000
156#define MFI_FWSTATE_TB_READY 0x10000000
157#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000
158#define MFI_FWSTATE_TB_FAULT 0x40000000
249d29c8
SW		 159
160/*
161 * Control bits to drive the card to ready state. These go into the IDB
162 * register.
163 */
164#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */
165#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
166#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
167#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
f26fa772 168#define MFI_FWINIT_HOTPLUG 0x00000010
249d29c8 169
590ba11d
SW		 170/* ADP reset flags */
171#define MFI_STOP_ADP 0x00000020
172#define MFI_ADP_RESET 0x00000040
173#define DIAG_WRITE_ENABLE 0x00000080
174#define DIAG_RESET_ADAPTER 0x00000004
175
249d29c8
SW		 176/* MFI Commands */
177typedef enum {
178 MFI_CMD_INIT = 0x00,
179 MFI_CMD_LD_READ,
180 MFI_CMD_LD_WRITE,
181 MFI_CMD_LD_SCSI_IO,
182 MFI_CMD_PD_SCSI_IO,
183 MFI_CMD_DCMD,
184 MFI_CMD_ABORT,
185 MFI_CMD_SMP,
186 MFI_CMD_STP
187} mfi_cmd_t;
188
189/* Direct commands */
190typedef enum {
17566092 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100,
249d29c8
SW		 192 MFI_DCMD_CTRL_GETINFO = 0x01010000,
193 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
194 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
195 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
196 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
197 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
198 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
199 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
200 MFI_DCMD_PR_GET_STATUS = 0x01070100,
201 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200,
202 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300,
203 MFI_DCMD_PR_START = 0x01070400,
204 MFI_DCMD_PR_STOP = 0x01070500,
205 MFI_DCMD_TIME_SECS_GET = 0x01080201,
206 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100,
207 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200,
208 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300,
209 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400,
210 MFI_DCMD_PD_GET_LIST = 0x02010000,
17566092 211 MFI_DCMD_PD_LIST_QUERY = 0x02010100,
249d29c8
SW		 212 MFI_DCMD_PD_GET_INFO = 0x02020000,
213 MFI_DCMD_PD_STATE_SET = 0x02030100,
214 MFI_DCMD_PD_REBUILD_START = 0x02040100,
215 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200,
216 MFI_DCMD_PD_CLEAR_START = 0x02050100,
217 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200,
218 MFI_DCMD_PD_GET_PROGRESS = 0x02060000,
219 MFI_DCMD_PD_LOCATE_START = 0x02070100,
220 MFI_DCMD_PD_LOCATE_STOP = 0x02070200,
590ba11d
SW		 221 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101,
222 MFI_DCMD_LD_SYNC = 0x0300e102,
249d29c8
SW		 223 MFI_DCMD_LD_GET_LIST = 0x03010000,
224 MFI_DCMD_LD_GET_INFO = 0x03020000,
225 MFI_DCMD_LD_GET_PROP = 0x03030000,
226 MFI_DCMD_LD_SET_PROP = 0x03040000,
227 MFI_DCMD_LD_INIT_START = 0x03060100,
228 MFI_DCMD_LD_DELETE = 0x03090000,
229 MFI_DCMD_CFG_READ = 0x04010000,
230 MFI_DCMD_CFG_ADD = 0x04020000,
231 MFI_DCMD_CFG_CLEAR = 0x04030000,
232 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000,
233 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000,
234 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
235 MFI_DCMD_BBU_GET_STATUS = 0x05010000,
236 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000,
237 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000,
238 MFI_DCMD_CLUSTER = 0x08000000,
239 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
240 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
241} mfi_dcmd_t;
242
243/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
244#define MFI_FLUSHCACHE_CTRL 0x01
245#define MFI_FLUSHCACHE_DISK 0x02
246
247/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
248#define MFI_SHUTDOWN_SPINDOWN 0x01
249
250/*
251 * MFI Frame flags
252 */
253#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
254#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
255#define MFI_FRAME_SGL32 0x0000
256#define MFI_FRAME_SGL64 0x0002
257#define MFI_FRAME_SENSE32 0x0000
258#define MFI_FRAME_SENSE64 0x0004
259#define MFI_FRAME_DIR_NONE 0x0000
260#define MFI_FRAME_DIR_WRITE 0x0008
261#define MFI_FRAME_DIR_READ 0x0010
262#define MFI_FRAME_DIR_BOTH 0x0018
17566092 263#define MFI_FRAME_IEEE_SGL 0x0020
249d29c8 264
590ba11d
SW		 265/* ThunderBolt Specific */
266
267/*
268 * Pre-TB command size and TB command size.
269 * We will be checking it at the load time for the time being
270 */
271#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */
272
273#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256
274/*
275 * We are defining only 128 byte message to reduce memory move over head
276 * and also it will reduce the SRB extension size by 128byte compared with
277 * 256 message size
278 */
279#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256
280#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024
281#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
282#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8
283#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
284#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
285
286#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
287#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
288
289#define MR_INTERNAL_MFI_FRAMES_SMID 1
290#define MR_CTRL_EVENT_WAIT_SMID 2
291#define MR_INTERNAL_DRIVER_RESET_SMID 3
292
293
249d29c8
SW		 294/* MFI Status codes */
295typedef enum {
296 MFI_STAT_OK = 0x00,
297 MFI_STAT_INVALID_CMD,
298 MFI_STAT_INVALID_DCMD,
299 MFI_STAT_INVALID_PARAMETER,
300 MFI_STAT_INVALID_SEQUENCE_NUMBER,
301 MFI_STAT_ABORT_NOT_POSSIBLE,
302 MFI_STAT_APP_HOST_CODE_NOT_FOUND,
303 MFI_STAT_APP_IN_USE,
304 MFI_STAT_APP_NOT_INITIALIZED,
305 MFI_STAT_ARRAY_INDEX_INVALID,
306 MFI_STAT_ARRAY_ROW_NOT_EMPTY,
307 MFI_STAT_CONFIG_RESOURCE_CONFLICT,
308 MFI_STAT_DEVICE_NOT_FOUND,
309 MFI_STAT_DRIVE_TOO_SMALL,
310 MFI_STAT_FLASH_ALLOC_FAIL,
311 MFI_STAT_FLASH_BUSY,
312 MFI_STAT_FLASH_ERROR = 0x10,
313 MFI_STAT_FLASH_IMAGE_BAD,
314 MFI_STAT_FLASH_IMAGE_INCOMPLETE,
315 MFI_STAT_FLASH_NOT_OPEN,
316 MFI_STAT_FLASH_NOT_STARTED,
317 MFI_STAT_FLUSH_FAILED,
318 MFI_STAT_HOST_CODE_NOT_FOUNT,
319 MFI_STAT_LD_CC_IN_PROGRESS,
320 MFI_STAT_LD_INIT_IN_PROGRESS,
321 MFI_STAT_LD_LBA_OUT_OF_RANGE,
322 MFI_STAT_LD_MAX_CONFIGURED,
323 MFI_STAT_LD_NOT_OPTIMAL,
324 MFI_STAT_LD_RBLD_IN_PROGRESS,
325 MFI_STAT_LD_RECON_IN_PROGRESS,
326 MFI_STAT_LD_WRONG_RAID_LEVEL,
327 MFI_STAT_MAX_SPARES_EXCEEDED,
328 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
329 MFI_STAT_MFC_HW_ERROR,
330 MFI_STAT_NO_HW_PRESENT,
331 MFI_STAT_NOT_FOUND,
332 MFI_STAT_NOT_IN_ENCL,
333 MFI_STAT_PD_CLEAR_IN_PROGRESS,
334 MFI_STAT_PD_TYPE_WRONG,
335 MFI_STAT_PR_DISABLED,
336 MFI_STAT_ROW_INDEX_INVALID,
337 MFI_STAT_SAS_CONFIG_INVALID_ACTION,
338 MFI_STAT_SAS_CONFIG_INVALID_DATA,
339 MFI_STAT_SAS_CONFIG_INVALID_PAGE,
340 MFI_STAT_SAS_CONFIG_INVALID_TYPE,
341 MFI_STAT_SCSI_DONE_WITH_ERROR,
342 MFI_STAT_SCSI_IO_FAILED,
343 MFI_STAT_SCSI_RESERVATION_CONFLICT,
344 MFI_STAT_SHUTDOWN_FAILED = 0x30,
345 MFI_STAT_TIME_NOT_SET,
346 MFI_STAT_WRONG_STATE,
347 MFI_STAT_LD_OFFLINE,
348 MFI_STAT_PEER_NOTIFICATION_REJECTED,
349 MFI_STAT_PEER_NOTIFICATION_FAILED,
350 MFI_STAT_RESERVATION_IN_PROGRESS,
351 MFI_STAT_I2C_ERRORS_DETECTED,
352 MFI_STAT_PCI_ERRORS_DETECTED,
353 MFI_STAT_DIAG_FAILED,
354 MFI_STAT_BOOT_MSG_PENDING,
355 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE,
356 MFI_STAT_INVALID_STATUS = 0xFF
357} mfi_status_t;
358
359typedef enum {
360 MFI_EVT_CLASS_DEBUG = -2,
361 MFI_EVT_CLASS_PROGRESS = -1,
362 MFI_EVT_CLASS_INFO = 0,
363 MFI_EVT_CLASS_WARNING = 1,
364 MFI_EVT_CLASS_CRITICAL = 2,
365 MFI_EVT_CLASS_FATAL = 3,
366 MFI_EVT_CLASS_DEAD = 4
367} mfi_evt_class_t;
368
369typedef enum {
370 MFI_EVT_LOCALE_LD = 0x0001,
371 MFI_EVT_LOCALE_PD = 0x0002,
372 MFI_EVT_LOCALE_ENCL = 0x0004,
373 MFI_EVT_LOCALE_BBU = 0x0008,
374 MFI_EVT_LOCALE_SAS = 0x0010,
375 MFI_EVT_LOCALE_CTRL = 0x0020,
376 MFI_EVT_LOCALE_CONFIG = 0x0040,
377 MFI_EVT_LOCALE_CLUSTER = 0x0080,
378 MFI_EVT_LOCALE_ALL = 0xffff
379} mfi_evt_locale_t;
380
381typedef enum {
382 MR_EVT_ARGS_NONE = 0x00,
383 MR_EVT_ARGS_CDB_SENSE,
384 MR_EVT_ARGS_LD,
385 MR_EVT_ARGS_LD_COUNT,
386 MR_EVT_ARGS_LD_LBA,
387 MR_EVT_ARGS_LD_OWNER,
388 MR_EVT_ARGS_LD_LBA_PD_LBA,
389 MR_EVT_ARGS_LD_PROG,
390 MR_EVT_ARGS_LD_STATE,
391 MR_EVT_ARGS_LD_STRIP,
392 MR_EVT_ARGS_PD,
393 MR_EVT_ARGS_PD_ERR,
394 MR_EVT_ARGS_PD_LBA,
395 MR_EVT_ARGS_PD_LBA_LD,
396 MR_EVT_ARGS_PD_PROG,
397 MR_EVT_ARGS_PD_STATE,
398 MR_EVT_ARGS_PCI,
399 MR_EVT_ARGS_RATE,
400 MR_EVT_ARGS_STR,
401 MR_EVT_ARGS_TIME,
402 MR_EVT_ARGS_ECC
403} mfi_evt_args;
404
590ba11d
SW		 405#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
406#define MR_EVT_PD_REMOVED 0x0070
407#define MR_EVT_PD_INSERTED 0x005b
408
249d29c8
SW		 409typedef enum {
410 MR_LD_CACHE_WRITE_BACK = 0x01,
411 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
412 MR_LD_CACHE_READ_AHEAD = 0x04,
413 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
414 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
415 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
416 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
417} mfi_ld_cache;
418#define MR_LD_CACHE_MASK 0x7f
419
420#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0
421#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD
422#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \
423 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE)
424#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0
425#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK
426#define MR_LD_CACHE_POLICY_IO_CACHED \
427 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE)
428#define MR_LD_CACHE_POLICY_IO_DIRECT 0
429
430typedef enum {
431 MR_PD_CACHE_UNCHANGED = 0,
432 MR_PD_CACHE_ENABLE = 1,
433 MR_PD_CACHE_DISABLE = 2
434} mfi_pd_cache;
435
17566092
SW		 436typedef enum {
437 MR_PD_QUERY_TYPE_ALL = 0,
438 MR_PD_QUERY_TYPE_STATE = 1,
439 MR_PD_QUERY_TYPE_POWER_STATE = 2,
440 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
441 MR_PD_QUERY_TYPE_SPEED = 4,
590ba11d 442 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */
17566092
SW		 443} mfi_pd_query_type;
444
249d29c8
SW		 445/*
446 * Other propertities and definitions
447 */
448#define MFI_MAX_PD_CHANNELS 2
449#define MFI_MAX_LD_CHANNELS 2
450#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
451#define MFI_MAX_CHANNEL_DEVS 128
452#define MFI_DEFAULT_ID -1
453#define MFI_MAX_LUN 8
454#define MFI_MAX_LD 64
455#define MFI_MAX_PD 256
456
457#define MFI_FRAME_SIZE 64
458#define MFI_MBOX_SIZE 12
459
460/* Firmware flashing can take 40s */
461#define MFI_POLL_TIMEOUT_SECS 50
462
463/* Allow for speedier math calculations */
464#define MFI_SECTOR_LEN 512
465
466/* Scatter Gather elements */
467struct mfi_sg32 {
468 uint32_t addr;
469 uint32_t len;
470} __packed;
471
472struct mfi_sg64 {
473 uint64_t addr;
474 uint32_t len;
475} __packed;
476
17566092
SW		 477struct mfi_sg_skinny {
478 uint64_t addr;
479 uint32_t len;
480 uint32_t flag;
481} __packed;
482
249d29c8 483union mfi_sgl {
590ba11d
SW		 484 struct mfi_sg32 sg32[1];
485 struct mfi_sg64 sg64[1];
486 struct mfi_sg_skinny sg_skinny[1];
249d29c8
SW		 487} __packed;
488
489/* Message frames. All messages have a common header */
490struct mfi_frame_header {
491 uint8_t cmd;
492 uint8_t sense_len;
493 uint8_t cmd_status;
494 uint8_t scsi_status;
495 uint8_t target_id;
496 uint8_t lun_id;
497 uint8_t cdb_len;
498 uint8_t sg_count;
499 uint32_t context;
17566092
SW		 500 /*
501 * pad0 is MSI Specific. Not used by Driver. Zero the value before
590ba11d 502 * sending the command to f/w.
17566092 503 */
249d29c8
SW		 504 uint32_t pad0;
505 uint16_t flags;
506#define MFI_FRAME_DATAOUT 0x08
507#define MFI_FRAME_DATAIN 0x10
508 uint16_t timeout;
509 uint32_t data_len;
510} __packed;
511
512struct mfi_init_frame {
513 struct mfi_frame_header header;
514 uint32_t qinfo_new_addr_lo;
515 uint32_t qinfo_new_addr_hi;
516 uint32_t qinfo_old_addr_lo;
517 uint32_t qinfo_old_addr_hi;
590ba11d
SW		 518 // Start LSIP200113393
519 uint32_t driver_ver_lo; /*28h */
520 uint32_t driver_ver_hi; /*2Ch */
521
522 uint32_t reserved[4];
523 // End LSIP200113393
249d29c8
SW		 524} __packed;
525
590ba11d
SW		 526/*
527 * Define MFI Address Context union.
528 */
529#ifdef MFI_ADDRESS_IS_uint64_t
530 typedef uint64_t MFI_ADDRESS;
531#else
532 typedef union _MFI_ADDRESS {
533 struct {
534 uint32_t addressLow;
535 uint32_t addressHigh;
536 } u;
537 uint64_t address;
538 } MFI_ADDRESS, *PMFI_ADDRESS;
539#endif
540
249d29c8
SW		 541#define MFI_IO_FRAME_SIZE 40
542struct mfi_io_frame {
543 struct mfi_frame_header header;
544 uint32_t sense_addr_lo;
545 uint32_t sense_addr_hi;
546 uint32_t lba_lo;
547 uint32_t lba_hi;
548 union mfi_sgl sgl;
549} __packed;
550
551#define MFI_PASS_FRAME_SIZE 48
552struct mfi_pass_frame {
553 struct mfi_frame_header header;
554 uint32_t sense_addr_lo;
555 uint32_t sense_addr_hi;
556 uint8_t cdb[16];
557 union mfi_sgl sgl;
558} __packed;
559
560#define MFI_DCMD_FRAME_SIZE 40
561struct mfi_dcmd_frame {
562 struct mfi_frame_header header;
563 uint32_t opcode;
564 uint8_t mbox[MFI_MBOX_SIZE];
565 union mfi_sgl sgl;
566} __packed;
567
568struct mfi_abort_frame {
569 struct mfi_frame_header header;
570 uint32_t abort_context;
590ba11d 571 /* pad is changed to reserved.*/
17566092 572 uint32_t reserved0;
249d29c8
SW		 573 uint32_t abort_mfi_addr_lo;
574 uint32_t abort_mfi_addr_hi;
17566092 575 uint32_t reserved1[6];
249d29c8
SW		 576} __packed;
577
578struct mfi_smp_frame {
579 struct mfi_frame_header header;
580 uint64_t sas_addr;
581 union {
582 struct mfi_sg32 sg32[2];
583 struct mfi_sg64 sg64[2];
584 } sgl;
585} __packed;
586
587struct mfi_stp_frame {
588 struct mfi_frame_header header;
589 uint16_t fis[10];
590 uint32_t stp_flags;
591 union {
592 struct mfi_sg32 sg32[2];
593 struct mfi_sg64 sg64[2];
594 } sgl;
595} __packed;
596
597union mfi_frame {
598 struct mfi_frame_header header;
599 struct mfi_init_frame init;
590ba11d 600 /* ThunderBolt Initialization */
249d29c8
SW		 601 struct mfi_io_frame io;
602 struct mfi_pass_frame pass;
603 struct mfi_dcmd_frame dcmd;
604 struct mfi_abort_frame abort;
605 struct mfi_smp_frame smp;
606 struct mfi_stp_frame stp;
607 uint8_t bytes[MFI_FRAME_SIZE];
608};
609
610#define MFI_SENSE_LEN 128
611struct mfi_sense {
612 uint8_t data[MFI_SENSE_LEN];
613};
614
615/* The queue init structure that is passed with the init message */
616struct mfi_init_qinfo {
617 uint32_t flags;
618 uint32_t rq_entries;
619 uint32_t rq_addr_lo;
620 uint32_t rq_addr_hi;
621 uint32_t pi_addr_lo;
622 uint32_t pi_addr_hi;
623 uint32_t ci_addr_lo;
624 uint32_t ci_addr_hi;
625} __packed;
626
627/* SAS (?) controller properties, part of mfi_ctrl_info */
628struct mfi_ctrl_props {
629 uint16_t seq_num;
630 uint16_t pred_fail_poll_interval;
631 uint16_t intr_throttle_cnt;
632 uint16_t intr_throttle_timeout;
633 uint8_t rebuild_rate;
634 uint8_t patrol_read_rate;
635 uint8_t bgi_rate;
636 uint8_t cc_rate;
637 uint8_t recon_rate;
638 uint8_t cache_flush_interval;
639 uint8_t spinup_drv_cnt;
640 uint8_t spinup_delay;
641 uint8_t cluster_enable;
642 uint8_t coercion_mode;
643 uint8_t alarm_enable;
644 uint8_t disable_auto_rebuild;
645 uint8_t disable_battery_warn;
646 uint8_t ecc_bucket_size;
647 uint16_t ecc_bucket_leak_rate;
648 uint8_t restore_hotspare_on_insertion;
649 uint8_t expose_encl_devices;
590ba11d
SW		 650 uint8_t maintainPdFailHistory;
651 uint8_t disallowHostRequestReordering;
652 /* set TRUE to abort CC on detecting an inconsistency */
653 uint8_t abortCCOnError;
654 /* load balance mode (MR_LOAD_BALANCE_MODE) */
655 uint8_t loadBalanceMode;
656 /*
657 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using
658 * h/w mechansim like GPIO pins
659 * 1 - disable auto detect SGPIO,
660 * 2 - disable i2c SEP auto detect
661 * 3 - disable both auto detect
662 */
663 uint8_t disableAutoDetectBackplane;
664 /*
665 * % of source LD to be reserved for a VDs snapshot in snapshot
666 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on
667 */
668 uint8_t snapVDSpace;
669
670 /*
671 * Add properties that can be controlled by a bit in the following
672 * structure.
673 */
674 struct {
675 /* set TRUE to disable copyBack (0=copback enabled) */
676 uint32_t copyBackDisabled :1;
677 uint32_t SMARTerEnabled :1;
678 uint32_t prCorrectUnconfiguredAreas :1;
679 uint32_t useFdeOnly :1;
680 uint32_t disableNCQ :1;
681 uint32_t SSDSMARTerEnabled :1;
682 uint32_t SSDPatrolReadEnabled :1;
683 uint32_t enableSpinDownUnconfigured :1;
684 uint32_t autoEnhancedImport :1;
685 uint32_t enableSecretKeyControl :1;
686 uint32_t disableOnlineCtrlReset :1;
687 uint32_t allowBootWithPinnedCache :1;
688 uint32_t disableSpinDownHS :1;
689 uint32_t enableJBOD :1;
690 uint32_t reserved :18;
691 } OnOffProperties;
692 /*
693 * % of source LD to be reserved for auto snapshot in snapshot
694 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on.
695 */
696 uint8_t autoSnapVDSpace;
697 /*
698 * Snapshot writeable VIEWs capacity as a % of source LD capacity:
699 * 0=READ only, 1=5%, 2=10%, 3=15% and so on.
700 */
701 uint8_t viewSpace;
702 /* # of idle minutes before device is spun down (0=use FW defaults) */
703 uint16_t spinDownTime;
704 uint8_t reserved[24];
249d29c8
SW		 705} __packed;
706
707/* PCI information about the card. */
708struct mfi_info_pci {
709 uint16_t vendor;
710 uint16_t device;
711 uint16_t subvendor;
712 uint16_t subdevice;
713 uint8_t reserved[24];
714} __packed;
715
716/* Host (front end) interface information */
717struct mfi_info_host {
718 uint8_t type;
719#define MFI_INFO_HOST_PCIX 0x01
720#define MFI_INFO_HOST_PCIE 0x02
721#define MFI_INFO_HOST_ISCSI 0x04
722#define MFI_INFO_HOST_SAS3G 0x08
723 uint8_t reserved[6];
724 uint8_t port_count;
725 uint64_t port_addr[8];
726} __packed;
727
728/* Device (back end) interface information */
729struct mfi_info_device {
730 uint8_t type;
731#define MFI_INFO_DEV_SPI 0x01
732#define MFI_INFO_DEV_SAS3G 0x02
733#define MFI_INFO_DEV_SATA1 0x04
734#define MFI_INFO_DEV_SATA3G 0x08
735 uint8_t reserved[6];
736 uint8_t port_count;
737 uint64_t port_addr[8];
738} __packed;
739
740/* Firmware component information */
741struct mfi_info_component {
742 char name[8];
743 char version[32];
744 char build_date[16];
745 char build_time[16];
746} __packed;
747
748/* Controller default settings */
749struct mfi_defaults {
750 uint64_t sas_addr;
751 uint8_t phy_polarity;
752 uint8_t background_rate;
753 uint8_t stripe_size;
754 uint8_t flush_time;
755 uint8_t write_back;
756 uint8_t read_ahead;
757 uint8_t cache_when_bbu_bad;
758 uint8_t cached_io;
759 uint8_t smart_mode;
760 uint8_t alarm_disable;
761 uint8_t coercion;
762 uint8_t zrc_config;
763 uint8_t dirty_led_shows_drive_activity;
764 uint8_t bios_continue_on_error;
765 uint8_t spindown_mode;
766 uint8_t allowed_device_types;
767 uint8_t allow_mix_in_enclosure;
768 uint8_t allow_mix_in_ld;
769 uint8_t allow_sata_in_cluster;
770 uint8_t max_chained_enclosures;
771 uint8_t disable_ctrl_r;
772 uint8_t enabel_web_bios;
773 uint8_t phy_polarity_split;
774 uint8_t direct_pd_mapping;
775 uint8_t bios_enumerate_lds;
776 uint8_t restored_hot_spare_on_insertion;
777 uint8_t expose_enclosure_devices;
778 uint8_t maintain_pd_fail_history;
779 uint8_t resv[28];
780} __packed;
781
782/* Controller default settings */
783struct mfi_bios_data {
784 uint16_t boot_target_id;
785 uint8_t do_not_int_13;
786 uint8_t continue_on_error;
787 uint8_t verbose;
788 uint8_t geometry;
789 uint8_t expose_all_drives;
790 uint8_t reserved[56];
791 uint8_t check_sum;
792} __packed;
793
794/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
795struct mfi_ctrl_info {
796 struct mfi_info_pci pci;
797 struct mfi_info_host host;
798 struct mfi_info_device device;
799
800 /* Firmware components that are present and active. */
801 uint32_t image_check_word;
802 uint32_t image_component_count;
803 struct mfi_info_component image_component[8];
804
805 /* Firmware components that have been flashed but are inactive */
806 uint32_t pending_image_component_count;
807 struct mfi_info_component pending_image_component[8];
808
809 uint8_t max_arms;
810 uint8_t max_spans;
811 uint8_t max_arrays;
812 uint8_t max_lds;
813 char product_name[80];
814 char serial_number[32];
815 uint32_t hw_present;
816#define MFI_INFO_HW_BBU 0x01
817#define MFI_INFO_HW_ALARM 0x02
818#define MFI_INFO_HW_NVRAM 0x04
819#define MFI_INFO_HW_UART 0x08
820 uint32_t current_fw_time;
821 uint16_t max_cmds;
822 uint16_t max_sg_elements;
823 uint32_t max_request_size;
824 uint16_t lds_present;
825 uint16_t lds_degraded;
826 uint16_t lds_offline;
827 uint16_t pd_present;
828 uint16_t pd_disks_present;
829 uint16_t pd_disks_pred_failure;
830 uint16_t pd_disks_failed;
831 uint16_t nvram_size;
832 uint16_t memory_size;
833 uint16_t flash_size;
834 uint16_t ram_correctable_errors;
835 uint16_t ram_uncorrectable_errors;
836 uint8_t cluster_allowed;
837 uint8_t cluster_active;
838 uint16_t max_strips_per_io;
839
840 uint32_t raid_levels;
841#define MFI_INFO_RAID_0 0x01
842#define MFI_INFO_RAID_1 0x02
843#define MFI_INFO_RAID_5 0x04
844#define MFI_INFO_RAID_1E 0x08
845#define MFI_INFO_RAID_6 0x10
846
847 uint32_t adapter_ops;
848#define MFI_INFO_AOPS_RBLD_RATE 0x0001
849#define MFI_INFO_AOPS_CC_RATE 0x0002
850#define MFI_INFO_AOPS_BGI_RATE 0x0004
851#define MFI_INFO_AOPS_RECON_RATE 0x0008
852#define MFI_INFO_AOPS_PATROL_RATE 0x0010
853#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
854#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
855#define MFI_INFO_AOPS_BBU 0x0080
856#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
857#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
858#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
859#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
860#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
861#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
862#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
863
864 uint32_t ld_ops;
865#define MFI_INFO_LDOPS_READ_POLICY 0x01
866#define MFI_INFO_LDOPS_WRITE_POLICY 0x02
867#define MFI_INFO_LDOPS_IO_POLICY 0x04
868#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
869#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
870
871 struct {
872 uint8_t min;
873 uint8_t max;
874 uint8_t reserved[2];
875 } __packed stripe_sz_ops;
876
877 uint32_t pd_ops;
878#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
879#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
880#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
881
882 uint32_t pd_mix_support;
883#define MFI_INFO_PDMIX_SAS 0x01
884#define MFI_INFO_PDMIX_SATA 0x02
885#define MFI_INFO_PDMIX_ENCL 0x04
886#define MFI_INFO_PDMIX_LD 0x08
887#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
888
889 uint8_t ecc_bucket_count;
890 uint8_t reserved2[11];
891 struct mfi_ctrl_props properties;
892 char package_version[0x60];
893 uint8_t pad[0x800 - 0x6a0];
894} __packed;
895
896/* keep track of an event. */
897union mfi_evt {
898 struct {
899 uint16_t locale;
900 uint8_t reserved;
f26fa772 901 int8_t evt_class;
249d29c8
SW		 902 } members;
903 uint32_t word;
904} __packed;
905
906/* event log state. */
907struct mfi_evt_log_state {
908 uint32_t newest_seq_num;
909 uint32_t oldest_seq_num;
910 uint32_t clear_seq_num;
911 uint32_t shutdown_seq_num;
912 uint32_t boot_seq_num;
913} __packed;
914
915struct mfi_progress {
916 uint16_t progress;
917 uint16_t elapsed_seconds;
918} __packed;
919
920struct mfi_evt_ld {
921 uint16_t target_id;
922 uint8_t ld_index;
923 uint8_t reserved;
924} __packed;
925
926struct mfi_evt_pd {
927 uint16_t device_id;
928 uint8_t enclosure_index;
929 uint8_t slot_number;
930} __packed;
931
932/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
933struct mfi_evt_detail {
934 uint32_t seq;
935 uint32_t time;
936 uint32_t code;
f26fa772 937 union mfi_evt evt_class;
249d29c8
SW		 938 uint8_t arg_type;
939 uint8_t reserved1[15];
940
941 union {
942 struct {
943 struct mfi_evt_pd pd;
944 uint8_t cdb_len;
945 uint8_t sense_len;
946 uint8_t reserved[2];
947 uint8_t cdb[16];
948 uint8_t sense[64];
949 } cdb_sense;
950
951 struct mfi_evt_ld ld;
952
953 struct {
954 struct mfi_evt_ld ld;
955 uint64_t count;
956 } ld_count;
957
958 struct {
959 uint64_t lba;
960 struct mfi_evt_ld ld;
961 } ld_lba;
962
963 struct {
964 struct mfi_evt_ld ld;
965 uint32_t pre_owner;
966 uint32_t new_owner;
967 } ld_owner;
968
969 struct {
970 uint64_t ld_lba;
971 uint64_t pd_lba;
972 struct mfi_evt_ld ld;
973 struct mfi_evt_pd pd;
974 } ld_lba_pd_lba;
975
976 struct {
977 struct mfi_evt_ld ld;
978 struct mfi_progress prog;
979 } ld_prog;
980
981 struct {
982 struct mfi_evt_ld ld;
983 uint32_t prev_state;
984 uint32_t new_state;
985 } ld_state;
986
987 struct {
988 uint64_t strip;
989 struct mfi_evt_ld ld;
990 } ld_strip;
991
992 struct mfi_evt_pd pd;
993
994 struct {
995 struct mfi_evt_pd pd;
996 uint32_t err;
997 } pd_err;
998
999 struct {
1000 uint64_t lba;
1001 struct mfi_evt_pd pd;
1002 } pd_lba;
1003
1004 struct {
1005 uint64_t lba;
1006 struct mfi_evt_pd pd;
1007 struct mfi_evt_ld ld;
1008 } pd_lba_ld;
1009
1010 struct {
1011 struct mfi_evt_pd pd;
1012 struct mfi_progress prog;
1013 } pd_prog;
1014
1015 struct {
1016 struct mfi_evt_pd ld;
1017 uint32_t prev_state;
1018 uint32_t new_state;
1019 } pd_state;
1020
1021 struct {
1022 uint16_t venderId;
1023 uint16_t deviceId;
1024 uint16_t subVenderId;
1025 uint16_t subDeviceId;
1026 } pci;
1027
1028 uint32_t rate;
1029
1030 char str[96];
1031
1032 struct {
1033 uint32_t rtc;
1034 uint16_t elapsedSeconds;
1035 } time;
1036
1037 struct {
1038 uint32_t ecar;
1039 uint32_t elog;
1040 char str[64];
1041 } ecc;
1042
1043 uint8_t b[96];
1044 uint16_t s[48];
1045 uint32_t w[24];
1046 uint64_t d[12];
1047 } args;
1048
1049 char description[128];
1050} __packed;
1051
1052struct mfi_evt_list {
1053 uint32_t count;
1054 uint32_t reserved;
1055 struct mfi_evt_detail event[1];
1056} __packed;
1057
1058union mfi_pd_ref {
1059 struct {
1060 uint16_t device_id;
1061 uint16_t seq_num;
1062 } v;
1063 uint32_t ref;
1064} __packed;
1065
1066union mfi_pd_ddf_type {
1067 struct {
1068 union {
1069 struct {
1070 uint16_t forced_pd_guid : 1;
1071 uint16_t in_vd : 1;
1072 uint16_t is_global_spare : 1;
1073 uint16_t is_spare : 1;
1074 uint16_t is_foreign : 1;
1075 uint16_t reserved : 7;
1076 uint16_t intf : 4;
1077 } pd_type;
1078 uint16_t type;
1079 } v;
1080 uint16_t reserved;
1081 } ddf;
1082 struct {
1083 uint32_t reserved;
1084 } non_disk;
1085 uint32_t type;
1086} __packed;
1087
1088struct mfi_pd_progress {
1089 uint32_t active;
1090#define MFI_PD_PROGRESS_REBUILD (1<<0)
1091#define MFI_PD_PROGRESS_PATROL (1<<1)
1092#define MFI_PD_PROGRESS_CLEAR (1<<2)
1093 struct mfi_progress rbld;
1094 struct mfi_progress patrol;
1095 struct mfi_progress clear;
1096 struct mfi_progress reserved[4];
1097} __packed;
1098
1099struct mfi_pd_info {
1100 union mfi_pd_ref ref;
1101 uint8_t inquiry_data[96];
1102 uint8_t vpd_page83[64];
1103 uint8_t not_supported;
1104 uint8_t scsi_dev_type;
1105 uint8_t connected_port_bitmap;
1106 uint8_t device_speed;
1107 uint32_t media_err_count;
1108 uint32_t other_err_count;
1109 uint32_t pred_fail_count;
1110 uint32_t last_pred_fail_event_seq_num;
1111 uint16_t fw_state; /* MFI_PD_STATE_* */
1112 uint8_t disabled_for_removal;
1113 uint8_t link_speed;
1114 union mfi_pd_ddf_type state;
1115 struct {
1116 uint8_t count;
1117 uint8_t is_path_broken;
1118 uint8_t reserved[6];
1119 uint64_t sas_addr[4];
1120 } path_info;
1121 uint64_t raw_size;
1122 uint64_t non_coerced_size;
1123 uint64_t coerced_size;
1124 uint16_t encl_device_id;
1125 uint8_t encl_index;
1126 uint8_t slot_number;
1127 struct mfi_pd_progress prog_info;
1128 uint8_t bad_block_table_full;
1129 uint8_t unusable_in_current_config;
1130 uint8_t vpd_page83_ext[64];
1131 uint8_t reserved[512-358];
1132} __packed;
1133
1134struct mfi_pd_address {
1135 uint16_t device_id;
1136 uint16_t encl_device_id;
1137 uint8_t encl_index;
1138 uint8_t slot_number;
1139 uint8_t scsi_dev_type; /* 0 = disk */
1140 uint8_t connect_port_bitmap;
1141 uint64_t sas_addr[2];
1142} __packed;
1143
17566092 1144#define MAX_SYS_PDS 240
249d29c8
SW		 1145struct mfi_pd_list {
1146 uint32_t size;
1147 uint32_t count;
17566092 1148 struct mfi_pd_address addr[MAX_SYS_PDS];
249d29c8
SW		 1149} __packed;
1150
1151enum mfi_pd_state {
1152 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1153 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
1154 MFI_PD_STATE_HOT_SPARE = 0x02,
1155 MFI_PD_STATE_OFFLINE = 0x10,
1156 MFI_PD_STATE_FAILED = 0x11,
1157 MFI_PD_STATE_REBUILD = 0x14,
1158 MFI_PD_STATE_ONLINE = 0x18,
1159 MFI_PD_STATE_COPYBACK = 0x20,
1160 MFI_PD_STATE_SYSTEM = 0x40
1161};
1162
1163union mfi_ld_ref {
1164 struct {
1165 uint8_t target_id;
1166 uint8_t reserved;
1167 uint16_t seq;
1168 } v;
1169 uint32_t ref;
1170} __packed;
1171
1172struct mfi_ld_list {
1173 uint32_t ld_count;
1174 uint32_t reserved1;
1175 struct {
1176 union mfi_ld_ref ld;
1177 uint8_t state;
1178 uint8_t reserved2[3];
1179 uint64_t size;
1180 } ld_list[MFI_MAX_LD];
1181} __packed;
1182
1183enum mfi_ld_access {
1184 MFI_LD_ACCESS_RW = 0,
1185 MFI_LD_ACCSSS_RO = 2,
1186 MFI_LD_ACCESS_BLOCKED = 3,
1187};
1188#define MFI_LD_ACCESS_MASK 3
1189
1190enum mfi_ld_state {
1191 MFI_LD_STATE_OFFLINE = 0,
1192 MFI_LD_STATE_PARTIALLY_DEGRADED = 1,
1193 MFI_LD_STATE_DEGRADED = 2,
1194 MFI_LD_STATE_OPTIMAL = 3
1195};
1196
1197struct mfi_ld_props {
1198 union mfi_ld_ref ld;
1199 char name[16];
1200 uint8_t default_cache_policy;
1201 uint8_t access_policy;
1202 uint8_t disk_cache_policy;
1203 uint8_t current_cache_policy;
1204 uint8_t no_bgi;
1205 uint8_t reserved[7];
1206} __packed;
1207
1208struct mfi_ld_params {
1209 uint8_t primary_raid_level;
1210 uint8_t raid_level_qualifier;
1211 uint8_t secondary_raid_level;
1212 uint8_t stripe_size;
1213 uint8_t num_drives;
1214 uint8_t span_depth;
1215 uint8_t state;
1216 uint8_t init_state;
1217#define MFI_LD_PARAMS_INIT_NO 0
1218#define MFI_LD_PARAMS_INIT_QUICK 1
1219#define MFI_LD_PARAMS_INIT_FULL 2
1220 uint8_t is_consistent;
17566092
SW		 1221 uint8_t reserved1[6];
1222 uint8_t isSSCD;
1223 uint8_t reserved2[16];
249d29c8
SW		 1224} __packed;
1225
1226struct mfi_ld_progress {
1227 uint32_t active;
1228#define MFI_LD_PROGRESS_CC (1<<0)
1229#define MFI_LD_PROGRESS_BGI (1<<1)
1230#define MFI_LD_PROGRESS_FGI (1<<2)
1231#define MFI_LD_PROGRESS_RECON (1<<3)
1232 struct mfi_progress cc;
1233 struct mfi_progress bgi;
1234 struct mfi_progress fgi;
1235 struct mfi_progress recon;
1236 struct mfi_progress reserved[4];
1237} __packed;
1238
1239struct mfi_span {
1240 uint64_t start_block;
1241 uint64_t num_blocks;
1242 uint16_t array_ref;
1243 uint8_t reserved[6];
1244} __packed;
1245
1246#define MFI_MAX_SPAN_DEPTH 8
1247struct mfi_ld_config {
1248 struct mfi_ld_props properties;
1249 struct mfi_ld_params params;
1250 struct mfi_span span[MFI_MAX_SPAN_DEPTH];
1251} __packed;
1252
1253struct mfi_ld_info {
1254 struct mfi_ld_config ld_config;
1255 uint64_t size;
1256 struct mfi_ld_progress progress;
1257 uint16_t cluster_owner;
1258 uint8_t reconstruct_active;
1259 uint8_t reserved1[1];
1260 uint8_t vpd_page83[64];
1261 uint8_t reserved2[16];
1262} __packed;
1263
590ba11d 1264#define MAX_ARRAYS 128
249d29c8
SW		 1265struct mfi_spare {
1266 union mfi_pd_ref ref;
1267 uint8_t spare_type;
1268#define MFI_SPARE_DEDICATED (1 << 0)
1269#define MFI_SPARE_REVERTIBLE (1 << 1)
1270#define MFI_SPARE_ENCL_AFFINITY (1 << 2)
1271 uint8_t reserved[2];
1272 uint8_t array_count;
1273 uint16_t array_ref[MAX_ARRAYS];
1274} __packed;
1275
1276struct mfi_array {
1277 uint64_t size;
1278 uint8_t num_drives;
1279 uint8_t reserved;
1280 uint16_t array_ref;
1281 uint8_t pad[20];
1282 struct {
1283 union mfi_pd_ref ref; /* 0xffff == missing drive */
1284 uint16_t fw_state; /* MFI_PD_STATE_* */
1285 struct {
1286 uint8_t pd;
1287 uint8_t slot;
1288 } encl;
1289 } pd[0];
1290} __packed;
1291
1292struct mfi_config_data {
1293 uint32_t size;
1294 uint16_t array_count;
1295 uint16_t array_size;
1296 uint16_t log_drv_count;
1297 uint16_t log_drv_size;
1298 uint16_t spares_count;
1299 uint16_t spares_size;
1300 uint8_t reserved[16];
ab14081f
SW		 1301 struct mfi_array array[0];
1302 struct mfi_ld_config ld[0];
1303 struct mfi_spare spare[0];
249d29c8
SW		 1304} __packed;
1305
1306struct mfi_bbu_capacity_info {
1307 uint16_t relative_charge;
1308 uint16_t absolute_charge;
1309 uint16_t remaining_capacity;
1310 uint16_t full_charge_capacity;
1311 uint16_t run_time_to_empty;
1312 uint16_t average_time_to_empty;
1313 uint16_t average_time_to_full;
1314 uint16_t cycle_count;
1315 uint16_t max_error;
1316 uint16_t remaining_capacity_alarm;
1317 uint16_t remaining_time_alarm;
1318 uint8_t reserved[26];
1319} __packed;
1320
1321struct mfi_bbu_design_info {
1322 uint32_t mfg_date;
1323 uint16_t design_capacity;
1324 uint16_t design_voltage;
1325 uint16_t spec_info;
1326 uint16_t serial_number;
1327 uint16_t pack_stat_config;
1328 uint8_t mfg_name[12];
1329 uint8_t device_name[8];
1330 uint8_t device_chemistry[8];
1331 uint8_t mfg_data[8];
1332 uint8_t reserved[17];
1333} __packed;
1334
1335struct mfi_ibbu_state {
1336 uint16_t gas_guage_status;
1337 uint16_t relative_charge;
1338 uint16_t charger_system_state;
1339 uint16_t charger_system_ctrl;
1340 uint16_t charging_current;
1341 uint16_t absolute_charge;
1342 uint16_t max_error;
1343 uint8_t reserved[18];
1344} __packed;
1345
1346struct mfi_bbu_state {
1347 uint16_t gas_guage_status;
1348 uint16_t relative_charge;
1349 uint16_t charger_status;
1350 uint16_t remaining_capacity;
1351 uint16_t full_charge_capacity;
1352 uint8_t is_SOH_good;
1353 uint8_t reserved[21];
1354} __packed;
1355
1356union mfi_bbu_status_detail {
1357 struct mfi_ibbu_state ibbu;
1358 struct mfi_bbu_state bbu;
1359};
1360
1361struct mfi_bbu_status {
1362 uint8_t battery_type;
1363#define MFI_BBU_TYPE_NONE 0
1364#define MFI_BBU_TYPE_IBBU 1
1365#define MFI_BBU_TYPE_BBU 2
1366 uint8_t reserved;
1367 uint16_t voltage;
1368 int16_t current;
1369 uint16_t temperature;
1370 uint32_t fw_status;
1371#define MFI_BBU_STATE_PACK_MISSING (1 << 0)
1372#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1)
1373#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2)
1374#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0)
1375#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0)
1376 uint8_t pad[20];
1377 union mfi_bbu_status_detail detail;
1378} __packed;
1379
1380enum mfi_pr_state {
1381 MFI_PR_STATE_STOPPED = 0,
1382 MFI_PR_STATE_READY = 1,
1383 MFI_PR_STATE_ACTIVE = 2,
1384 MFI_PR_STATE_ABORTED = 0xff
1385};
1386
1387struct mfi_pr_status {
1388 uint32_t num_iteration;
1389 uint8_t state;
1390 uint8_t num_pd_done;
1391 uint8_t reserved[10];
1392};
1393
1394enum mfi_pr_opmode {
1395 MFI_PR_OPMODE_AUTO = 0,
1396 MFI_PR_OPMODE_MANUAL = 1,
1397 MFI_PR_OPMODE_DISABLED = 2
1398};
1399
1400struct mfi_pr_properties {
1401 uint8_t op_mode;
1402 uint8_t max_pd;
1403 uint8_t reserved;
1404 uint8_t exclude_ld_count;
1405 uint16_t excluded_ld[MFI_MAX_LD];
1406 uint8_t cur_pd_map[MFI_MAX_PD / 8];
1407 uint8_t last_pd_map[MFI_MAX_PD / 8];
1408 uint32_t next_exec;
1409 uint32_t exec_freq;
1410 uint32_t clear_freq;
1411};
1412
590ba11d
SW		 1413/* ThunderBolt support */
1414
1415/*
1416 * Raid Context structure which describes MegaRAID specific IO Paramenters
1417 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
1418 */
1419typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE {
1420 uint16_t resvd0; /* 0x00 - 0x01 */
1421 uint16_t timeoutValue; /* 0x02 - 0x03 */
1422 uint8_t regLockFlags;
1423 uint8_t armId;
1424 uint16_t TargetID; /* 0x06 - 0x07 */
1425
1426 uint64_t RegLockLBA; /* 0x08 - 0x0F */
1427
1428 uint32_t RegLockLength; /* 0x10 - 0x13 */
1429
1430 uint16_t SMID; /* 0x14 - 0x15 nextLMId */
1431 uint8_t exStatus; /* 0x16 */
1432 uint8_t Status; /* 0x17 status */
1433
1434 uint8_t RAIDFlags; /* 0x18 */
1435 uint8_t numSGE; /* 0x19 numSge */
1436 uint16_t configSeqNum; /* 0x1A - 0x1B */
1437 uint8_t spanArm; /* 0x1C */
1438 uint8_t resvd2[3]; /* 0x1D - 0x1F */
1439} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE;
1440
1441/*** DJA *****/
1442
1443/*****************************************************************************
1444*
1445* Message Functions
1446*
1447*****************************************************************************/
1448
1449#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
1450#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
1451#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
1452#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
1453#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
1454#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
1455#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
1456#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
1457#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
1458#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
1459#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
1460#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
1461#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
1462#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
1463#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
1464#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
1465#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
1466#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
1467#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
1468#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
1469#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
1470#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
1471#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
1472#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
1473#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
1474#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
1475#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
1476#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
1477#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
1478#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
1479
1480/* Doorbell functions */
1481#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
1482#define MPI2_FUNCTION_HANDSHAKE (0x42)
1483
1484/*****************************************************************************
1485*
1486* MPI Version Definitions
1487*
1488*****************************************************************************/
1489
1490#define MPI2_VERSION_MAJOR (0x02)
1491#define MPI2_VERSION_MINOR (0x00)
1492#define MPI2_VERSION_MAJOR_MASK (0xFF00)
1493#define MPI2_VERSION_MAJOR_SHIFT (8)
1494#define MPI2_VERSION_MINOR_MASK (0x00FF)
1495#define MPI2_VERSION_MINOR_SHIFT (0)
1496#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
1497 MPI2_VERSION_MINOR)
1498
1499#define MPI2_VERSION_02_00 (0x0200)
1500
1501/* versioning for this MPI header set */
1502#define MPI2_HEADER_VERSION_UNIT (0x10)
1503#define MPI2_HEADER_VERSION_DEV (0x00)
1504#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
1505#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
1506#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
1507#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
1508#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
1509 MPI2_HEADER_VERSION_DEV)
1510
1511
1512/* IOCInit Request message */
1513struct MPI2_IOC_INIT_REQUEST {
1514 uint8_t WhoInit; /* 0x00 */
1515 uint8_t Reserved1; /* 0x01 */
1516 uint8_t ChainOffset; /* 0x02 */
1517 uint8_t Function; /* 0x03 */
1518 uint16_t Reserved2; /* 0x04 */
1519 uint8_t Reserved3; /* 0x06 */
1520 uint8_t MsgFlags; /* 0x07 */
1521 uint8_t VP_ID; /* 0x08 */
1522 uint8_t VF_ID; /* 0x09 */
1523 uint16_t Reserved4; /* 0x0A */
1524 uint16_t MsgVersion; /* 0x0C */
1525 uint16_t HeaderVersion; /* 0x0E */
1526 uint32_t Reserved5; /* 0x10 */
1527 uint16_t Reserved6; /* 0x14 */
1528 uint8_t Reserved7; /* 0x16 */
1529 uint8_t HostMSIxVectors; /* 0x17 */
1530 uint16_t Reserved8; /* 0x18 */
1531 uint16_t SystemRequestFrameSize; /* 0x1A */
1532 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
1533 uint16_t ReplyFreeQueueDepth; /* 0x1E */
1534 uint32_t SenseBufferAddressHigh; /* 0x20 */
1535 uint32_t SystemReplyAddressHigh; /* 0x24 */
1536 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */
1537 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */
1538 uint64_t ReplyFreeQueueAddress; /* 0x38 */
1539 uint64_t TimeStamp; /* 0x40 */
1540};
1541
1542/* WhoInit values */
1543#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
1544#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
1545#define MPI2_WHOINIT_ROM_BIOS (0x02)
1546#define MPI2_WHOINIT_PCI_PEER (0x03)
1547#define MPI2_WHOINIT_HOST_DRIVER (0x04)
1548#define MPI2_WHOINIT_MANUFACTURER (0x05)
1549
1550struct MPI2_SGE_CHAIN_UNION {
1551 uint16_t Length;
1552 uint8_t NextChainOffset;
1553 uint8_t Flags;
1554 union {
1555 uint32_t Address32;
1556 uint64_t Address64;
1557 } u;
1558};
1559
1560struct MPI2_IEEE_SGE_SIMPLE32 {
1561 uint32_t Address;
1562 uint32_t FlagsLength;
1563};
1564
1565struct MPI2_IEEE_SGE_SIMPLE64 {
1566 uint64_t Address;
1567 uint32_t Length;
1568 uint16_t Reserved1;
1569 uint8_t Reserved2;
1570 uint8_t Flags;
1571};
1572
1573typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1574 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
1575 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
1576} MPI2_IEEE_SGE_SIMPLE_UNION;
1577
1578typedef struct _MPI2_SGE_SIMPLE_UNION {
1579 uint32_t FlagsLength;
1580 union {
1581 uint32_t Address32;
1582 uint64_t Address64;
1583 } u;
1584} MPI2_SGE_SIMPLE_UNION;
1585
1586/****************************************************************************
1587* IEEE SGE field definitions and masks
1588****************************************************************************/
1589
1590/* Flags field bit definitions */
1591
1592#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1593
1594#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1595
1596#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1597
1598/* Element Type */
1599
1600#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1601#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1602
1603/* Data Location Address Space */
1604
1605#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1606#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1607#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1608#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1609#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1610
1611/* Address Size */
1612
1613#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1614#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1615
1616/*******************/
1617/* SCSI IO Control bits */
1618#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000)
1619#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26)
1620
1621#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
1622#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
1623#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
1624#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
1625#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000)
1626
1627#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800)
1628#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11)
1629
1630#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
1631#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
1632#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100)
1633#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
1634#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400)
1635
1636#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0)
1637#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000)
1638#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040)
1639#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080)
1640
1641/*******************/
1642
1643typedef struct {
1644 uint8_t CDB[20]; /* 0x00 */
1645 uint32_t PrimaryReferenceTag; /* 0x14 */
1646 uint16_t PrimaryApplicationTag; /* 0x18 */
1647 uint16_t PrimaryApplicationTagMask; /* 0x1A */
1648 uint32_t TransferLength; /* 0x1C */
1649} MPI2_SCSI_IO_CDB_EEDP32;
1650
1651
1652typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1653 struct MPI2_IEEE_SGE_SIMPLE32 Chain32;
1654 struct MPI2_IEEE_SGE_SIMPLE64 Chain64;
1655} MPI2_IEEE_SGE_CHAIN_UNION;
1656
1657typedef union _MPI2_SIMPLE_SGE_UNION {
1658 MPI2_SGE_SIMPLE_UNION MpiSimple;
1659 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1660} MPI2_SIMPLE_SGE_UNION;
1661
1662typedef union _MPI2_SGE_IO_UNION {
1663 MPI2_SGE_SIMPLE_UNION MpiSimple;
1664 struct MPI2_SGE_CHAIN_UNION MpiChain;
1665 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1666 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1667} MPI2_SGE_IO_UNION;
1668
1669typedef union {
1670 uint8_t CDB32[32];
1671 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
1672 MPI2_SGE_SIMPLE_UNION SGE;
1673} MPI2_SCSI_IO_CDB_UNION;
1674
1675
1676/* MPI 2.5 SGLs */
1677
1678#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1679
1680typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1681 uint64_t Address;
1682 uint32_t Length;
1683 uint16_t Reserved1;
1684 uint8_t NextChainOffset;
1685 uint8_t Flags;
1686} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t;
1687
1688/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */
1689
1690
1691/********/
1692
1693/*
1694 * RAID SCSI IO Request Message
1695 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
1696 */
1697struct mfi_mpi2_request_raid_scsi_io {
1698 uint16_t DevHandle; /* 0x00 */
1699 uint8_t ChainOffset; /* 0x02 */
1700 uint8_t Function; /* 0x03 */
1701 uint16_t Reserved1; /* 0x04 */
1702 uint8_t Reserved2; /* 0x06 */
1703 uint8_t MsgFlags; /* 0x07 */
1704 uint8_t VP_ID; /* 0x08 */
1705 uint8_t VF_ID; /* 0x09 */
1706 uint16_t Reserved3; /* 0x0A */
1707 uint32_t SenseBufferLowAddress; /* 0x0C */
1708 uint16_t SGLFlags; /* 0x10 */
1709 uint8_t SenseBufferLength; /* 0x12 */
1710 uint8_t Reserved4; /* 0x13 */
1711 uint8_t SGLOffset0; /* 0x14 */
1712 uint8_t SGLOffset1; /* 0x15 */
1713 uint8_t SGLOffset2; /* 0x16 */
1714 uint8_t SGLOffset3; /* 0x17 */
1715 uint32_t SkipCount; /* 0x18 */
1716 uint32_t DataLength; /* 0x1C */
1717 uint32_t BidirectionalDataLength; /* 0x20 */
1718 uint16_t IoFlags; /* 0x24 */
1719 uint16_t EEDPFlags; /* 0x26 */
1720 uint32_t EEDPBlockSize; /* 0x28 */
1721 uint32_t SecondaryReferenceTag; /* 0x2C */
1722 uint16_t SecondaryApplicationTag; /* 0x30 */
1723 uint16_t ApplicationTagTranslationMask; /* 0x32 */
1724 uint8_t LUN[8]; /* 0x34 */
1725 uint32_t Control; /* 0x3C */
1726 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
1727 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */
1728 MPI2_SGE_IO_UNION SGL; /* 0x80 */
1729} __packed;
1730
1731/*
1732 * MPT RAID MFA IO Descriptor.
1733 */
1734typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR {
1735 uint32_t RequestFlags : 8;
1736 uint32_t MessageAddress1 : 24; /* bits 31:8*/
1737 uint32_t MessageAddress2; /* bits 61:32 */
1738} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR;
1739
1740struct mfi_mpi2_request_header {
1741 uint8_t RequestFlags; /* 0x00 */
1742 uint8_t MSIxIndex; /* 0x01 */
1743 uint16_t SMID; /* 0x02 */
1744 uint16_t LMID; /* 0x04 */
1745};
1746
1747/* defines for the RequestFlags field */
1748#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
1749#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
1750#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
1751#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
1752#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
1753#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
1754
1755#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
1756
1757struct mfi_mpi2_request_high_priority {
1758 struct mfi_mpi2_request_header header;
1759 uint16_t reserved;
1760};
1761
1762struct mfi_mpi2_request_scsi_io {
1763 struct mfi_mpi2_request_header header;
1764 uint16_t scsi_io_dev_handle;
1765};
1766
1767struct mfi_mpi2_request_scsi_target {
1768 struct mfi_mpi2_request_header header;
1769 uint16_t scsi_target_io_index;
1770};
1771
1772/* Request Descriptors */
1773union mfi_mpi2_request_descriptor {
1774 struct mfi_mpi2_request_header header;
1775 struct mfi_mpi2_request_high_priority high_priority;
1776 struct mfi_mpi2_request_scsi_io scsi_io;
1777 struct mfi_mpi2_request_scsi_target scsi_target;
1778 uint64_t words;
1779};
1780
1781
1782struct mfi_mpi2_reply_header {
1783 uint8_t ReplyFlags; /* 0x00 */
1784 uint8_t MSIxIndex; /* 0x01 */
1785 uint16_t SMID; /* 0x02 */
1786};
1787
1788/* defines for the ReplyFlags field */
1789#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
1790#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
1791#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
1792#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
1793#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
1794#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
1795#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
1796
1797/* values for marking a reply descriptor as unused */
1798#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
1799#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
1800
1801struct mfi_mpi2_reply_default {
1802 struct mfi_mpi2_reply_header header;
1803 uint32_t DescriptorTypeDependent2;
1804};
1805
1806struct mfi_mpi2_reply_address {
1807 struct mfi_mpi2_reply_header header;
1808 uint32_t ReplyFrameAddress;
1809};
1810
1811struct mfi_mpi2_reply_scsi_io {
1812 struct mfi_mpi2_reply_header header;
1813 uint16_t TaskTag; /* 0x04 */
1814 uint16_t Reserved1; /* 0x06 */
1815};
1816
1817struct mfi_mpi2_reply_target_assist {
1818 struct mfi_mpi2_reply_header header;
1819 uint8_t SequenceNumber; /* 0x04 */
1820 uint8_t Reserved1; /* 0x04 */
1821 uint16_t IoIndex; /* 0x06 */
1822};
1823
1824struct mfi_mpi2_reply_target_cmd_buffer {
1825 struct mfi_mpi2_reply_header header;
1826 uint8_t SequenceNumber; /* 0x04 */
1827 uint8_t Flags; /* 0x04 */
1828 uint16_t InitiatorDevHandle; /* 0x06 */
1829 uint16_t IoIndex; /* 0x06 */
1830};
1831
1832struct mfi_mpi2_reply_raid_accel {
1833 struct mfi_mpi2_reply_header header;
1834 uint8_t SequenceNumber; /* 0x04 */
1835 uint32_t Reserved; /* 0x04 */
1836};
1837
1838/* union of Reply Descriptors */
1839union mfi_mpi2_reply_descriptor {
1840 struct mfi_mpi2_reply_header header;
1841 struct mfi_mpi2_reply_scsi_io scsi_io;
1842 struct mfi_mpi2_reply_target_assist target_assist;
1843 struct mfi_mpi2_reply_target_cmd_buffer target_cmd;
1844 struct mfi_mpi2_reply_raid_accel raid_accel;
1845 struct mfi_mpi2_reply_default reply_default;
1846 uint64_t words;
1847};
1848
1849struct IO_REQUEST_INFO {
1850 uint64_t ldStartBlock;
1851 uint32_t numBlocks;
1852 uint16_t ldTgtId;
1853 uint8_t isRead;
1854 uint16_t devHandle;
1855 uint64_t pdBlock;
1856 uint8_t fpOkForIo;
1857};
1858
249d29c8
SW		 1859#define MFI_SCSI_MAX_TARGETS 128
1860#define MFI_SCSI_MAX_LUNS 8
1861#define MFI_SCSI_INITIATOR_ID 255
1862#define MFI_SCSI_MAX_CMDS 8
1863#define MFI_SCSI_MAX_CDB_LEN 16
1864
1865#endif /* _MFIREG_H */
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