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jme: Cache align RX/TX data structure
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
CommitLineData
76fbb0b9
SZ		 1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
76fbb0b9
SZ		 28 */
29
9de40864 30#include "opt_polling.h"
93bfe1b8 31#include "opt_jme.h"
9de40864 32
76fbb0b9
SZ		 33#include <sys/param.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/interrupt.h>
38#include <sys/malloc.h>
39#include <sys/proc.h>
40#include <sys/rman.h>
41#include <sys/serialize.h>
31f0d5a2 42#include <sys/serialize2.h>
76fbb0b9
SZ		 43#include <sys/socket.h>
44#include <sys/sockio.h>
45#include <sys/sysctl.h>
46
47#include <net/ethernet.h>
48#include <net/if.h>
49#include <net/bpf.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/ifq_var.h>
24dd1705 54#include <net/toeplitz.h>
a6acc6e2 55#include <net/toeplitz2.h>
76fbb0b9
SZ		 56#include <net/vlan/if_vlan_var.h>
57#include <net/vlan/if_vlan_ether.h>
58
a6acc6e2
SZ		 59#include <netinet/in.h>
60
76fbb0b9 61#include <dev/netif/mii_layer/miivar.h>
dbe37f03 62#include <dev/netif/mii_layer/jmphyreg.h>
76fbb0b9
SZ		 63
64#include <bus/pci/pcireg.h>
65#include <bus/pci/pcivar.h>
66#include <bus/pci/pcidevs.h>
67
08c76ecf
SZ		 68#include <dev/netif/jme/if_jmereg.h>
69#include <dev/netif/jme/if_jmevar.h>
76fbb0b9
SZ		 70
71#include "miibus_if.h"
72
29890f78
SZ		 73#define JME_TX_SERIALIZE 1
74#define JME_RX_SERIALIZE 2
75
76fbb0b9
SZ		 76#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
77
760c056c
SZ		 78#ifdef JME_RSS_DEBUG
79#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
80do { \
66f75939 81 if ((sc)->jme_rss_debug >= (lvl)) \
760c056c
SZ		 82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
83} while (0)
84#else /* !JME_RSS_DEBUG */
85#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86#endif /* JME_RSS_DEBUG */
87
76fbb0b9
SZ		 88static int jme_probe(device_t);
89static int jme_attach(device_t);
90static int jme_detach(device_t);
91static int jme_shutdown(device_t);
92static int jme_suspend(device_t);
93static int jme_resume(device_t);
94
95static int jme_miibus_readreg(device_t, int, int);
96static int jme_miibus_writereg(device_t, int, int, int);
97static void jme_miibus_statchg(device_t);
98
99static void jme_init(void *);
100static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101static void jme_start(struct ifnet *);
102static void jme_watchdog(struct ifnet *);
103static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104static int jme_mediachange(struct ifnet *);
9de40864
SZ		 105#ifdef DEVICE_POLLING
106static void jme_poll(struct ifnet *, enum poll_cmd, int);
107#endif
31f0d5a2
SZ		 108static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
111#ifdef INVARIANTS
112static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
113 boolean_t);
114#endif
76fbb0b9
SZ		 115
116static void jme_intr(void *);
58880b0d
SZ		 117static void jme_msix_tx(void *);
118static void jme_msix_rx(void *);
76fbb0b9 119static void jme_txeof(struct jme_softc *);
dea2452a 120static void jme_rxeof(struct jme_rxdata *, int);
4447c752 121static void jme_rx_intr(struct jme_softc *, uint32_t);
76fbb0b9 122
58880b0d
SZ		 123static int jme_msix_setup(device_t);
124static void jme_msix_teardown(device_t, int);
125static int jme_intr_setup(device_t);
126static void jme_intr_teardown(device_t);
127static void jme_msix_try_alloc(device_t);
128static void jme_msix_free(device_t);
129static int jme_intr_alloc(device_t);
130static void jme_intr_free(device_t);
76fbb0b9 131static int jme_dma_alloc(struct jme_softc *);
0b3414d9 132static void jme_dma_free(struct jme_softc *);
dea2452a 133static int jme_init_rx_ring(struct jme_rxdata *);
76fbb0b9
SZ		 134static void jme_init_tx_ring(struct jme_softc *);
135static void jme_init_ssb(struct jme_softc *);
dea2452a 136static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
76fbb0b9 137static int jme_encap(struct jme_softc *, struct mbuf **);
dea2452a
SZ		 138static void jme_rxpkt(struct jme_rxdata *);
139static int jme_rxring_dma_alloc(struct jme_rxdata *);
140static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
064b75ed 141static int jme_rxbuf_dma_filter(void *, bus_addr_t);
76fbb0b9
SZ		 142
143static void jme_tick(void *);
144static void jme_stop(struct jme_softc *);
145static void jme_reset(struct jme_softc *);
58880b0d 146static void jme_set_msinum(struct jme_softc *);
76fbb0b9
SZ		 147static void jme_set_vlan(struct jme_softc *);
148static void jme_set_filter(struct jme_softc *);
149static void jme_stop_tx(struct jme_softc *);
150static void jme_stop_rx(struct jme_softc *);
151static void jme_mac_config(struct jme_softc *);
152static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
155#ifdef notyet
156static void jme_setwol(struct jme_softc *);
157static void jme_setlinkspeed(struct jme_softc *);
158#endif
2870abc4
SZ		 159static void jme_set_tx_coal(struct jme_softc *);
160static void jme_set_rx_coal(struct jme_softc *);
760c056c
SZ		 161static void jme_enable_rss(struct jme_softc *);
162static void jme_disable_rss(struct jme_softc *);
cccc3955
SZ		 163static void jme_serialize_skipmain(struct jme_softc *);
164static void jme_deserialize_skipmain(struct jme_softc *);
76fbb0b9
SZ		 165
166static void jme_sysctl_node(struct jme_softc *);
2870abc4
SZ		 167static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
168static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
169static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
170static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
76fbb0b9
SZ		 171
172/*
173 * Devices supported by this driver.
174 */
175static const struct jme_dev {
176 uint16_t jme_vendorid;
177 uint16_t jme_deviceid;
3a5f3f36 178 uint32_t jme_caps;
76fbb0b9
SZ		 179 const char *jme_name;
180} jme_devs[] = {
44e8c66c 181 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
3a5f3f36 182 JME_CAP_JUMBO,
76fbb0b9 183 "JMicron Inc, JMC250 Gigabit Ethernet" },
44e8c66c 184 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
3a5f3f36 185 JME_CAP_FASTETH,
76fbb0b9 186 "JMicron Inc, JMC260 Fast Ethernet" },
3a5f3f36 187 { 0, 0, 0, NULL }
76fbb0b9
SZ		 188};
189
190static device_method_t jme_methods[] = {
191 /* Device interface. */
192 DEVMETHOD(device_probe, jme_probe),
193 DEVMETHOD(device_attach, jme_attach),
194 DEVMETHOD(device_detach, jme_detach),
195 DEVMETHOD(device_shutdown, jme_shutdown),
196 DEVMETHOD(device_suspend, jme_suspend),
197 DEVMETHOD(device_resume, jme_resume),
198
199 /* Bus interface. */
200 DEVMETHOD(bus_print_child, bus_generic_print_child),
201 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
202
203 /* MII interface. */
204 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
205 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
206 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
207
208 { NULL, NULL }
209};
210
211static driver_t jme_driver = {
212 "jme",
213 jme_methods,
214 sizeof(struct jme_softc)
215};
216
217static devclass_t jme_devclass;
218
219DECLARE_DUMMY_MODULE(if_jme);
220MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
aa2b9d05
SW		 221DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
222DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
76fbb0b9 223
4447c752
SZ		 224static const struct {
225 uint32_t jme_coal;
226 uint32_t jme_comp;
58880b0d 227 uint32_t jme_empty;
4447c752 228} jme_rx_status[JME_NRXRING_MAX] = {
58880b0d
SZ		 229 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
230 INTR_RXQ0_DESC_EMPTY },
231 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
232 INTR_RXQ1_DESC_EMPTY },
233 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
234 INTR_RXQ2_DESC_EMPTY },
235 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
236 INTR_RXQ3_DESC_EMPTY }
4447c752
SZ		 237};
238
69325526
SZ		 239static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
240static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
6afef6ab 241static int jme_rx_ring_count = 0;
3eba890a 242static int jme_msi_enable = 1;
58880b0d 243static int jme_msix_enable = 1;
83b03786
SZ		 244
245TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
246TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
413d06bb 247TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
3eba890a 248TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
58880b0d 249TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
83b03786 250
fd2a6d2c
SZ		 251static __inline void
252jme_setup_rxdesc(struct jme_rxdesc *rxd)
253{
254 struct jme_desc *desc;
255
256 desc = rxd->rx_desc;
257 desc->buflen = htole32(MCLBYTES);
258 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
259 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
260 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
261}
262
76fbb0b9
SZ		 263/*
264 * Read a PHY register on the MII of the JMC250.
265 */
266static int
267jme_miibus_readreg(device_t dev, int phy, int reg)
268{
269 struct jme_softc *sc = device_get_softc(dev);
270 uint32_t val;
271 int i;
272
273 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 274 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 275 if (phy == 0)
276 return (0);
277 } else {
278 if (sc->jme_phyaddr != phy)
279 return (0);
280 }
281
282 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
283 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
284
285 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
286 DELAY(1);
287 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
288 break;
289 }
290 if (i == 0) {
291 device_printf(sc->jme_dev, "phy read timeout: "
292 "phy %d, reg %d\n", phy, reg);
293 return (0);
294 }
295
296 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
297}
298
299/*
300 * Write a PHY register on the MII of the JMC250.
301 */
302static int
303jme_miibus_writereg(device_t dev, int phy, int reg, int val)
304{
305 struct jme_softc *sc = device_get_softc(dev);
306 int i;
307
308 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 309 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 310 if (phy == 0)
311 return (0);
312 } else {
313 if (sc->jme_phyaddr != phy)
314 return (0);
315 }
316
317 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
318 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
319 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
320
321 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
322 DELAY(1);
323 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
324 break;
325 }
326 if (i == 0) {
327 device_printf(sc->jme_dev, "phy write timeout: "
328 "phy %d, reg %d\n", phy, reg);
329 }
330
331 return (0);
332}
333
334/*
335 * Callback from MII layer when media changes.
336 */
337static void
338jme_miibus_statchg(device_t dev)
339{
340 struct jme_softc *sc = device_get_softc(dev);
341 struct ifnet *ifp = &sc->arpcom.ac_if;
342 struct mii_data *mii;
343 struct jme_txdesc *txd;
344 bus_addr_t paddr;
4447c752 345 int i, r;
76fbb0b9 346
cccc3955
SZ		 347 if (sc->jme_in_tick)
348 jme_serialize_skipmain(sc);
31f0d5a2 349 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 350
351 if ((ifp->if_flags & IFF_RUNNING) == 0)
cccc3955 352 goto done;
76fbb0b9
SZ		 353
354 mii = device_get_softc(sc->jme_miibus);
355
cccc3955 356 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 357 if ((mii->mii_media_status & IFM_AVALID) != 0) {
358 switch (IFM_SUBTYPE(mii->mii_media_active)) {
359 case IFM_10_T:
360 case IFM_100_TX:
cccc3955 361 sc->jme_has_link = TRUE;
76fbb0b9
SZ		 362 break;
363 case IFM_1000_T:
ec7e787b 364 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 365 break;
cccc3955 366 sc->jme_has_link = TRUE;
76fbb0b9
SZ		 367 break;
368 default:
369 break;
370 }
371 }
372
373 /*
374 * Disabling Rx/Tx MACs have a side-effect of resetting
375 * JME_TXNDA/JME_RXNDA register to the first address of
376 * Tx/Rx descriptor address. So driver should reset its
377 * internal procucer/consumer pointer and reclaim any
378 * allocated resources. Note, just saving the value of
379 * JME_TXNDA and JME_RXNDA registers before stopping MAC
380 * and restoring JME_TXNDA/JME_RXNDA register is not
381 * sufficient to make sure correct MAC state because
382 * stopping MAC operation can take a while and hardware
383 * might have updated JME_TXNDA/JME_RXNDA registers
384 * during the stop operation.
385 */
386
387 /* Disable interrupts */
388 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
389
390 /* Stop driver */
391 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
392 ifp->if_timer = 0;
393 callout_stop(&sc->jme_tick_ch);
394
395 /* Stop receiver/transmitter. */
396 jme_stop_rx(sc);
397 jme_stop_tx(sc);
398
7b040092 399 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 400 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
401
dea2452a 402 jme_rxeof(rdata, -1);
4447c752
SZ		 403 if (rdata->jme_rxhead != NULL)
404 m_freem(rdata->jme_rxhead);
dea2452a 405 JME_RXCHAIN_RESET(rdata);
4447c752
SZ		 406
407 /*
408 * Reuse configured Rx descriptors and reset
409 * procuder/consumer index.
410 */
411 rdata->jme_rx_cons = 0;
412 }
6afef6ab 413 if (JME_ENABLE_HWRSS(sc))
deaeb5a5
SZ		 414 jme_enable_rss(sc);
415 else
416 jme_disable_rss(sc);
76fbb0b9
SZ		 417
418 jme_txeof(sc);
419 if (sc->jme_cdata.jme_tx_cnt != 0) {
420 /* Remove queued packets for transmit. */
b020bb10 421 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ		 422 txd = &sc->jme_cdata.jme_txdesc[i];
423 if (txd->tx_m != NULL) {
424 bus_dmamap_unload(
425 sc->jme_cdata.jme_tx_tag,
426 txd->tx_dmamap);
427 m_freem(txd->tx_m);
428 txd->tx_m = NULL;
429 txd->tx_ndesc = 0;
430 ifp->if_oerrors++;
431 }
432 }
433 }
76fbb0b9
SZ		 434 jme_init_tx_ring(sc);
435
436 /* Initialize shadow status block. */
437 jme_init_ssb(sc);
438
439 /* Program MAC with resolved speed/duplex/flow-control. */
cccc3955 440 if (sc->jme_has_link) {
76fbb0b9
SZ		 441 jme_mac_config(sc);
442
76fbb0b9
SZ		 443 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
444
445 /* Set Tx ring address to the hardware. */
7405bec3 446 paddr = sc->jme_cdata.jme_tx_ring_paddr;
76fbb0b9
SZ		 447 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
448 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
449
7b040092 450 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 451 CSR_WRITE_4(sc, JME_RXCSR,
452 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
453
454 /* Set Rx ring address to the hardware. */
455 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
456 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
457 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
458 }
76fbb0b9
SZ		 459
460 /* Restart receiver/transmitter. */
461 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
462 RXCSR_RXQ_START);
463 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
464 }
465
466 ifp->if_flags |= IFF_RUNNING;
467 ifp->if_flags &= ~IFF_OACTIVE;
468 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
469
9de40864
SZ		 470#ifdef DEVICE_POLLING
471 if (!(ifp->if_flags & IFF_POLLING))
472#endif
76fbb0b9
SZ		 473 /* Reenable interrupts. */
474 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
cccc3955
SZ		 475
476done:
477 if (sc->jme_in_tick)
478 jme_deserialize_skipmain(sc);
76fbb0b9
SZ		 479}
480
481/*
482 * Get the current interface media status.
483 */
484static void
485jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
486{
487 struct jme_softc *sc = ifp->if_softc;
488 struct mii_data *mii = device_get_softc(sc->jme_miibus);
489
31f0d5a2 490 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 491
492 mii_pollstat(mii);
493 ifmr->ifm_status = mii->mii_media_status;
494 ifmr->ifm_active = mii->mii_media_active;
495}
496
497/*
498 * Set hardware to newly-selected media.
499 */
500static int
501jme_mediachange(struct ifnet *ifp)
502{
503 struct jme_softc *sc = ifp->if_softc;
504 struct mii_data *mii = device_get_softc(sc->jme_miibus);
505 int error;
506
31f0d5a2 507 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 508
509 if (mii->mii_instance != 0) {
510 struct mii_softc *miisc;
511
512 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
513 mii_phy_reset(miisc);
514 }
515 error = mii_mediachg(mii);
516
517 return (error);
518}
519
520static int
521jme_probe(device_t dev)
522{
523 const struct jme_dev *sp;
524 uint16_t vid, did;
525
526 vid = pci_get_vendor(dev);
527 did = pci_get_device(dev);
528 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
529 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
3a5f3f36
SZ		 530 struct jme_softc *sc = device_get_softc(dev);
531
532 sc->jme_caps = sp->jme_caps;
76fbb0b9 533 device_set_desc(dev, sp->jme_name);
76fbb0b9
SZ		 534 return (0);
535 }
536 }
537 return (ENXIO);
538}
539
540static int
541jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
542{
543 uint32_t reg;
544 int i;
545
546 *val = 0;
547 for (i = JME_TIMEOUT; i > 0; i--) {
548 reg = CSR_READ_4(sc, JME_SMBCSR);
549 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
550 break;
551 DELAY(1);
552 }
553
554 if (i == 0) {
555 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
556 return (ETIMEDOUT);
557 }
558
559 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
560 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
561 for (i = JME_TIMEOUT; i > 0; i--) {
562 DELAY(1);
563 reg = CSR_READ_4(sc, JME_SMBINTF);
564 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
565 break;
566 }
567
568 if (i == 0) {
569 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
570 return (ETIMEDOUT);
571 }
572
573 reg = CSR_READ_4(sc, JME_SMBINTF);
574 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
575
576 return (0);
577}
578
579static int
580jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
581{
582 uint8_t fup, reg, val;
583 uint32_t offset;
584 int match;
585
586 offset = 0;
587 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
588 fup != JME_EEPROM_SIG0)
589 return (ENOENT);
590 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
591 fup != JME_EEPROM_SIG1)
592 return (ENOENT);
593 match = 0;
594 do {
595 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
596 break;
09927fe6
SZ		 597 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
598 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
76fbb0b9
SZ		 599 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
600 break;
601 if (reg >= JME_PAR0 &&
602 reg < JME_PAR0 + ETHER_ADDR_LEN) {
603 if (jme_eeprom_read_byte(sc, offset + 2,
604 &val) != 0)
605 break;
606 eaddr[reg - JME_PAR0] = val;
607 match++;
608 }
609 }
09927fe6
SZ		 610 /* Check for the end of EEPROM descriptor. */
611 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
612 break;
76fbb0b9
SZ		 613 /* Try next eeprom descriptor. */
614 offset += JME_EEPROM_DESC_BYTES;
615 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
616
617 if (match == ETHER_ADDR_LEN)
618 return (0);
619
620 return (ENOENT);
621}
622
623static void
624jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
625{
626 uint32_t par0, par1;
627
628 /* Read station address. */
629 par0 = CSR_READ_4(sc, JME_PAR0);
630 par1 = CSR_READ_4(sc, JME_PAR1);
631 par1 &= 0xFFFF;
632 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
633 device_printf(sc->jme_dev,
634 "generating fake ethernet address.\n");
635 par0 = karc4random();
636 /* Set OUI to JMicron. */
637 eaddr[0] = 0x00;
638 eaddr[1] = 0x1B;
639 eaddr[2] = 0x8C;
640 eaddr[3] = (par0 >> 16) & 0xff;
641 eaddr[4] = (par0 >> 8) & 0xff;
642 eaddr[5] = par0 & 0xff;
643 } else {
644 eaddr[0] = (par0 >> 0) & 0xFF;
645 eaddr[1] = (par0 >> 8) & 0xFF;
646 eaddr[2] = (par0 >> 16) & 0xFF;
647 eaddr[3] = (par0 >> 24) & 0xFF;
648 eaddr[4] = (par1 >> 0) & 0xFF;
649 eaddr[5] = (par1 >> 8) & 0xFF;
650 }
651}
652
653static int
654jme_attach(device_t dev)
655{
656 struct jme_softc *sc = device_get_softc(dev);
657 struct ifnet *ifp = &sc->arpcom.ac_if;
658 uint32_t reg;
b249905b
SZ		 659 uint16_t did;
660 uint8_t pcie_ptr, rev;
7b040092 661 int error = 0, i, j, rx_desc_cnt;
76fbb0b9
SZ		 662 uint8_t eaddr[ETHER_ADDR_LEN];
663
594bec47
SZ		 664 device_printf(dev, "rxdata %zu, chain_data %zu\n",
665 sizeof(struct jme_rxdata), sizeof(struct jme_chain_data));
666
31f0d5a2
SZ		 667 lwkt_serialize_init(&sc->jme_serialize);
668 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
669 for (i = 0; i < JME_NRXRING_MAX; ++i) {
670 lwkt_serialize_init(
671 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
672 }
673
7b040092 674 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
1cc217a9 675 jme_rx_desc_count);
7b040092
SZ		 676 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
677 if (rx_desc_cnt > JME_NDESC_MAX)
678 rx_desc_cnt = JME_NDESC_MAX;
69325526 679
b020bb10 680 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
1cc217a9 681 jme_tx_desc_count);
b020bb10
SZ		 682 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
683 JME_NDESC_ALIGN);
684 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
685 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
83b03786 686
9389fe19 687 /*
a317449e 688 * Calculate rx rings
9389fe19 689 */
7b040092 690 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
1cc217a9 691 jme_rx_ring_count);
7b040092
SZ		 692 sc->jme_cdata.jme_rx_ring_cnt =
693 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
4447c752 694
31f0d5a2
SZ		 695 i = 0;
696 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
29890f78
SZ		 697
698 KKASSERT(i == JME_TX_SERIALIZE);
31f0d5a2 699 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
29890f78
SZ		 700
701 KKASSERT(i == JME_RX_SERIALIZE);
7b040092 702 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
31f0d5a2
SZ		 703 sc->jme_serialize_arr[i++] =
704 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
705 }
706 KKASSERT(i <= JME_NSERIALIZE);
707 sc->jme_serialize_cnt = i;
708
58880b0d 709 sc->jme_cdata.jme_sc = sc;
7b040092 710 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
58880b0d
SZ		 711 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
712
713 rdata->jme_sc = sc;
714 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
715 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
716 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
717 rdata->jme_rx_idx = i;
7b040092 718 rdata->jme_rx_desc_cnt = rx_desc_cnt;
58880b0d
SZ		 719 }
720
76fbb0b9 721 sc->jme_dev = dev;
b249905b
SZ		 722 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
723
76fbb0b9
SZ		 724 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
725
726 callout_init(&sc->jme_tick_ch);
727
728#ifndef BURN_BRIDGES
729 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
730 uint32_t irq, mem;
731
732 irq = pci_read_config(dev, PCIR_INTLINE, 4);
733 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
734
735 device_printf(dev, "chip is in D%d power mode "
736 "-- setting to D0\n", pci_get_powerstate(dev));
737
738 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
739
740 pci_write_config(dev, PCIR_INTLINE, irq, 4);
741 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
742 }
743#endif /* !BURN_BRIDGE */
744
745 /* Enable bus mastering */
746 pci_enable_busmaster(dev);
747
748 /*
749 * Allocate IO memory
750 *
751 * JMC250 supports both memory mapped and I/O register space
752 * access. Because I/O register access should use different
753 * BARs to access registers it's waste of time to use I/O
754 * register spce access. JMC250 uses 16K to map entire memory
755 * space.
756 */
757 sc->jme_mem_rid = JME_PCIR_BAR;
758 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
759 &sc->jme_mem_rid, RF_ACTIVE);
760 if (sc->jme_mem_res == NULL) {
761 device_printf(dev, "can't allocate IO memory\n");
762 return ENXIO;
763 }
764 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
765 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
766
767 /*
768 * Allocate IRQ
769 */
58880b0d
SZ		 770 error = jme_intr_alloc(dev);
771 if (error)
76fbb0b9 772 goto fail;
76fbb0b9
SZ		 773
774 /*
b249905b 775 * Extract revisions
76fbb0b9
SZ		 776 */
777 reg = CSR_READ_4(sc, JME_CHIPMODE);
778 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
779 CHIPMODE_NOT_FPGA) {
ec7e787b 780 sc->jme_caps |= JME_CAP_FPGA;
76fbb0b9 781 if (bootverbose) {
b249905b 782 device_printf(dev, "FPGA revision: 0x%04x\n",
76fbb0b9
SZ		 783 (reg & CHIPMODE_FPGA_REV_MASK) >>
784 CHIPMODE_FPGA_REV_SHIFT);
785 }
786 }
787
b249905b
SZ		 788 /* NOTE: FM revision is put in the upper 4 bits */
789 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
790 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
791 if (bootverbose)
792 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
793
794 did = pci_get_device(dev);
795 switch (did) {
796 case PCI_PRODUCT_JMICRON_JMC250:
797 if (rev == JME_REV1_A2)
798 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
799 break;
800
801 case PCI_PRODUCT_JMICRON_JMC260:
802 if (rev == JME_REV2)
803 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
804 break;
805
806 default:
ed20d0e3 807 panic("unknown device id 0x%04x", did);
b249905b
SZ		 808 }
809 if (rev >= JME_REV2) {
810 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
811 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
812 GHC_TXMAC_CLKSRC_1000;
813 }
814
76fbb0b9
SZ		 815 /* Reset the ethernet controller. */
816 jme_reset(sc);
817
58880b0d
SZ		 818 /* Map MSI/MSI-X vectors */
819 jme_set_msinum(sc);
820
76fbb0b9
SZ		 821 /* Get station address. */
822 reg = CSR_READ_4(sc, JME_SMBCSR);
823 if (reg & SMBCSR_EEPROM_PRESENT)
824 error = jme_eeprom_macaddr(sc, eaddr);
825 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
826 if (error != 0 && (bootverbose)) {
827 device_printf(dev, "ethernet hardware address "
828 "not found in EEPROM.\n");
829 }
830 jme_reg_macaddr(sc, eaddr);
831 }
832
833 /*
834 * Save PHY address.
835 * Integrated JR0211 has fixed PHY address whereas FPGA version
836 * requires PHY probing to get correct PHY address.
837 */
ec7e787b 838 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
76fbb0b9
SZ		 839 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
840 GPREG0_PHY_ADDR_MASK;
841 if (bootverbose) {
842 device_printf(dev, "PHY is at address %d.\n",
843 sc->jme_phyaddr);
844 }
845 } else {
846 sc->jme_phyaddr = 0;
847 }
848
849 /* Set max allowable DMA size. */
850 pcie_ptr = pci_get_pciecap_ptr(dev);
851 if (pcie_ptr != 0) {
852 uint16_t ctrl;
853
ec7e787b 854 sc->jme_caps |= JME_CAP_PCIE;
76fbb0b9
SZ		 855 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
856 if (bootverbose) {
857 device_printf(dev, "Read request size : %d bytes.\n",
858 128 << ((ctrl >> 12) & 0x07));
859 device_printf(dev, "TLP payload size : %d bytes.\n",
860 128 << ((ctrl >> 5) & 0x07));
861 }
862 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
863 case PCIEM_DEVCTL_MAX_READRQ_128:
864 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
865 break;
866 case PCIEM_DEVCTL_MAX_READRQ_256:
867 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
868 break;
869 default:
870 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
871 break;
872 }
873 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
874 } else {
875 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
876 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
877 }
878
879#ifdef notyet
880 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
ec7e787b 881 sc->jme_caps |= JME_CAP_PMCAP;
76fbb0b9
SZ		 882#endif
883
884 /*
885 * Create sysctl tree
886 */
887 jme_sysctl_node(sc);
888
889 /* Allocate DMA stuffs */
890 error = jme_dma_alloc(sc);
891 if (error)
892 goto fail;
893
894 ifp->if_softc = sc;
895 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
896 ifp->if_init = jme_init;
897 ifp->if_ioctl = jme_ioctl;
898 ifp->if_start = jme_start;
9de40864
SZ		 899#ifdef DEVICE_POLLING
900 ifp->if_poll = jme_poll;
901#endif
76fbb0b9 902 ifp->if_watchdog = jme_watchdog;
31f0d5a2
SZ		 903 ifp->if_serialize = jme_serialize;
904 ifp->if_deserialize = jme_deserialize;
905 ifp->if_tryserialize = jme_tryserialize;
906#ifdef INVARIANTS
907 ifp->if_serialize_assert = jme_serialize_assert;
908#endif
b020bb10
SZ		 909 ifq_set_maxlen(&ifp->if_snd,
910 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
76fbb0b9
SZ		 911 ifq_set_ready(&ifp->if_snd);
912
913 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
914 ifp->if_capabilities = IFCAP_HWCSUM |
915 IFCAP_VLAN_MTU |
916 IFCAP_VLAN_HWTAGGING;
7b040092 917 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
d585233c 918 ifp->if_capabilities |= IFCAP_RSS;
76fbb0b9
SZ		 919 ifp->if_capenable = ifp->if_capabilities;
920
3d2aeb15
SZ		 921 /*
922 * Disable TXCSUM by default to improve bulk data
923 * transmit performance (+20Mbps improvement).
924 */
925 ifp->if_capenable &= ~IFCAP_TXCSUM;
926
927 if (ifp->if_capenable & IFCAP_TXCSUM)
928 ifp->if_hwassist = JME_CSUM_FEATURES;
929
76fbb0b9
SZ		 930 /* Set up MII bus. */
931 error = mii_phy_probe(dev, &sc->jme_miibus,
932 jme_mediachange, jme_mediastatus);
933 if (error) {
934 device_printf(dev, "no PHY found!\n");
935 goto fail;
936 }
937
938 /*
939 * Save PHYADDR for FPGA mode PHY.
940 */
ec7e787b 941 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 942 struct mii_data *mii = device_get_softc(sc->jme_miibus);
943
944 if (mii->mii_instance != 0) {
945 struct mii_softc *miisc;
946
947 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948 if (miisc->mii_phy != 0) {
949 sc->jme_phyaddr = miisc->mii_phy;
950 break;
951 }
952 }
953 if (sc->jme_phyaddr != 0) {
954 device_printf(sc->jme_dev,
955 "FPGA PHY is at %d\n", sc->jme_phyaddr);
956 /* vendor magic. */
dbe37f03
SZ		 957 jme_miibus_writereg(dev, sc->jme_phyaddr,
958 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
959
ad22907f 960 /* XXX should we clear JME_WA_EXTFIFO */
76fbb0b9
SZ		 961 }
962 }
963 }
964
965 ether_ifattach(ifp, eaddr, NULL);
966
967 /* Tell the upper layer(s) we support long frames. */
968 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
969
58880b0d 970 error = jme_intr_setup(dev);
76fbb0b9 971 if (error) {
76fbb0b9
SZ		 972 ether_ifdetach(ifp);
973 goto fail;
974 }
975
76fbb0b9
SZ		 976 return 0;
977fail:
978 jme_detach(dev);
979 return (error);
980}
981
982static int
983jme_detach(device_t dev)
984{
985 struct jme_softc *sc = device_get_softc(dev);
986
987 if (device_is_attached(dev)) {
988 struct ifnet *ifp = &sc->arpcom.ac_if;
989
31f0d5a2 990 ifnet_serialize_all(ifp);
76fbb0b9 991 jme_stop(sc);
58880b0d 992 jme_intr_teardown(dev);
31f0d5a2 993 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 994
995 ether_ifdetach(ifp);
996 }
997
998 if (sc->jme_sysctl_tree != NULL)
999 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1000
1001 if (sc->jme_miibus != NULL)
1002 device_delete_child(dev, sc->jme_miibus);
1003 bus_generic_detach(dev);
1004
58880b0d 1005 jme_intr_free(dev);
76fbb0b9
SZ		 1006
1007 if (sc->jme_mem_res != NULL) {
1008 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1009 sc->jme_mem_res);
1010 }
1011
0b3414d9 1012 jme_dma_free(sc);
76fbb0b9
SZ		 1013
1014 return (0);
1015}
1016
1017static void
1018jme_sysctl_node(struct jme_softc *sc)
1019{
83b03786 1020 int coal_max;
760c056c 1021#ifdef JME_RSS_DEBUG
760c056c
SZ		 1022 int r;
1023#endif
83b03786 1024
76fbb0b9
SZ		 1025 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028 device_get_nameunit(sc->jme_dev),
1029 CTLFLAG_RD, 0, "");
1030 if (sc->jme_sysctl_tree == NULL) {
1031 device_printf(sc->jme_dev, "can't add sysctl node\n");
1032 return;
1033 }
1034
1035 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1037 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
76fbb0b9
SZ		 1039
1040 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1042 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
76fbb0b9
SZ		 1044
1045 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1047 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
76fbb0b9
SZ		 1049
1050 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1052 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
76fbb0b9 1054
83b03786
SZ		 1055 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ		 1057 "rx_desc_count", CTLFLAG_RD,
1058 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
83b03786
SZ		 1059 0, "RX desc count");
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
b020bb10
SZ		 1062 "tx_desc_count", CTLFLAG_RD,
1063 &sc->jme_cdata.jme_tx_desc_cnt,
83b03786 1064 0, "TX desc count");
760c056c
SZ		 1065 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ		 1067 "rx_ring_count", CTLFLAG_RD,
1068 &sc->jme_cdata.jme_rx_ring_cnt,
760c056c 1069 0, "RX ring count");
760c056c
SZ		 1070#ifdef JME_RSS_DEBUG
1071 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
24dd1705 1073 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
760c056c 1074 0, "RSS debug level");
7b040092
SZ		 1075 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076 char rx_ring_pkt[32];
1077
760c056c 1078 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
7b040092
SZ		 1079 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1080 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1081 rx_ring_pkt, CTLFLAG_RW,
1082 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
760c056c
SZ		 1083 }
1084#endif
83b03786
SZ		 1085
1086 /*
1087 * Set default coalesce valves
1088 */
76fbb0b9 1089 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
76fbb0b9 1090 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
76fbb0b9 1091 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
76fbb0b9 1092 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
83b03786
SZ		 1093
1094 /*
1095 * Adjust coalesce valves, in case that the number of TX/RX
1096 * descs are set to small values by users.
1097 *
1098 * NOTE: coal_max will not be zero, since number of descs
1099 * must aligned by JME_NDESC_ALIGN (16 currently)
1100 */
b020bb10 1101 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
83b03786
SZ		 1102 if (coal_max < sc->jme_tx_coal_pkt)
1103 sc->jme_tx_coal_pkt = coal_max;
1104
7b040092 1105 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
83b03786
SZ		 1106 if (coal_max < sc->jme_rx_coal_pkt)
1107 sc->jme_rx_coal_pkt = coal_max;
76fbb0b9
SZ		 1108}
1109
76fbb0b9
SZ		 1110static int
1111jme_dma_alloc(struct jme_softc *sc)
1112{
1113 struct jme_txdesc *txd;
1128a202 1114 bus_dmamem_t dmem;
ff7f3632 1115 int error, i, asize;
76fbb0b9 1116
83b03786 1117 sc->jme_cdata.jme_txdesc =
b020bb10 1118 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
83b03786 1119 M_DEVBUF, M_WAITOK | M_ZERO);
7b040092
SZ		 1120 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1121 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1122
1123 rdata->jme_rxdesc =
1124 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
4447c752
SZ		 1125 M_DEVBUF, M_WAITOK | M_ZERO);
1126 }
83b03786 1127
76fbb0b9
SZ		 1128 /* Create parent ring tag. */
1129 error = bus_dma_tag_create(NULL,/* parent */
a7547dad
SZ		 1130 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1131 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ		 1132 BUS_SPACE_MAXADDR, /* highaddr */
1133 NULL, NULL, /* filter, filterarg */
1134 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1135 0, /* nsegments */
1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1137 0, /* flags */
1138 &sc->jme_cdata.jme_ring_tag);
1139 if (error) {
1140 device_printf(sc->jme_dev,
1141 "could not create parent ring DMA tag.\n");
1142 return error;
1143 }
1144
1145 /*
1146 * Create DMA stuffs for TX ring
1147 */
ff7f3632 1148 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1128a202
SZ		 1149 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1150 JME_TX_RING_ALIGN, 0,
0eb220ec 1151 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1152 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9 1153 if (error) {
1128a202 1154 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
76fbb0b9
SZ		 1155 return error;
1156 }
1128a202
SZ		 1157 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1158 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1159 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1160 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ		 1161
1162 /*
1128a202 1163 * Create DMA stuffs for RX rings
76fbb0b9 1164 */
7b040092 1165 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1166 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752
SZ		 1167 if (error)
1168 return error;
76fbb0b9 1169 }
76fbb0b9 1170
76fbb0b9
SZ		 1171 /* Create parent buffer tag. */
1172 error = bus_dma_tag_create(NULL,/* parent */
1173 1, 0, /* algnmnt, boundary */
b249905b 1174 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ		 1175 BUS_SPACE_MAXADDR, /* highaddr */
1176 NULL, NULL, /* filter, filterarg */
1177 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1178 0, /* nsegments */
1179 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1180 0, /* flags */
1181 &sc->jme_cdata.jme_buffer_tag);
1182 if (error) {
1183 device_printf(sc->jme_dev,
1184 "could not create parent buffer DMA tag.\n");
1185 return error;
1186 }
1187
1188 /*
1189 * Create DMA stuffs for shadow status block
1190 */
ff7f3632 1191 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1128a202 1192 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
0eb220ec 1193 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1194 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9
SZ		 1195 if (error) {
1196 device_printf(sc->jme_dev,
1128a202 1197 "could not create shadow status block.\n");
76fbb0b9
SZ		 1198 return error;
1199 }
1128a202
SZ		 1200 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1201 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1202 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1203 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ		 1204
1205 /*
1206 * Create DMA stuffs for TX buffers
1207 */
1208
1209 /* Create tag for Tx buffers. */
1210 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211 1, 0, /* algnmnt, boundary */
0eb220ec 1212 BUS_SPACE_MAXADDR, /* lowaddr */
76fbb0b9
SZ		 1213 BUS_SPACE_MAXADDR, /* highaddr */
1214 NULL, NULL, /* filter, filterarg */
9d424cee 1215 JME_JUMBO_FRAMELEN, /* maxsize */
76fbb0b9 1216 JME_MAXTXSEGS, /* nsegments */
9d424cee
SZ		 1217 JME_MAXSEGSIZE, /* maxsegsize */
1218 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
76fbb0b9
SZ		 1219 &sc->jme_cdata.jme_tx_tag);
1220 if (error != 0) {
1221 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1222 return error;
1223 }
1224
1225 /* Create DMA maps for Tx buffers. */
b020bb10 1226 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9 1227 txd = &sc->jme_cdata.jme_txdesc[i];
9d424cee
SZ		 1228 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1229 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1230 &txd->tx_dmamap);
76fbb0b9
SZ		 1231 if (error) {
1232 int j;
1233
1234 device_printf(sc->jme_dev,
1235 "could not create %dth Tx dmamap.\n", i);
1236
1237 for (j = 0; j < i; ++j) {
1238 txd = &sc->jme_cdata.jme_txdesc[j];
1239 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1240 txd->tx_dmamap);
1241 }
1242 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1243 sc->jme_cdata.jme_tx_tag = NULL;
1244 return error;
1245 }
1246 }
1247
1248 /*
1249 * Create DMA stuffs for RX buffers
1250 */
7b040092 1251 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1252 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752 1253 if (error)
76fbb0b9 1254 return error;
76fbb0b9
SZ		 1255 }
1256 return 0;
1257}
1258
1259static void
0b3414d9 1260jme_dma_free(struct jme_softc *sc)
76fbb0b9
SZ		 1261{
1262 struct jme_txdesc *txd;
1263 struct jme_rxdesc *rxd;
4447c752
SZ		 1264 struct jme_rxdata *rdata;
1265 int i, r;
76fbb0b9
SZ		 1266
1267 /* Tx ring */
1268 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1269 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1270 sc->jme_cdata.jme_tx_ring_map);
1271 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
560616bf 1272 sc->jme_cdata.jme_tx_ring,
76fbb0b9
SZ		 1273 sc->jme_cdata.jme_tx_ring_map);
1274 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1275 sc->jme_cdata.jme_tx_ring_tag = NULL;
1276 }
1277
1278 /* Rx ring */
7b040092 1279 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 1280 rdata = &sc->jme_cdata.jme_rx_data[r];
1281 if (rdata->jme_rx_ring_tag != NULL) {
1282 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1283 rdata->jme_rx_ring_map);
1284 bus_dmamem_free(rdata->jme_rx_ring_tag,
1285 rdata->jme_rx_ring,
1286 rdata->jme_rx_ring_map);
1287 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1288 rdata->jme_rx_ring_tag = NULL;
1289 }
76fbb0b9
SZ		 1290 }
1291
1292 /* Tx buffers */
1293 if (sc->jme_cdata.jme_tx_tag != NULL) {
b020bb10 1294 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ		 1295 txd = &sc->jme_cdata.jme_txdesc[i];
1296 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1297 txd->tx_dmamap);
1298 }
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1300 sc->jme_cdata.jme_tx_tag = NULL;
1301 }
1302
1303 /* Rx buffers */
7b040092 1304 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 1305 rdata = &sc->jme_cdata.jme_rx_data[r];
1306 if (rdata->jme_rx_tag != NULL) {
7b040092 1307 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 1308 rxd = &rdata->jme_rxdesc[i];
1309 bus_dmamap_destroy(rdata->jme_rx_tag,
1310 rxd->rx_dmamap);
1311 }
1312 bus_dmamap_destroy(rdata->jme_rx_tag,
1313 rdata->jme_rx_sparemap);
1314 bus_dma_tag_destroy(rdata->jme_rx_tag);
1315 rdata->jme_rx_tag = NULL;
76fbb0b9 1316 }
76fbb0b9
SZ		 1317 }
1318
1319 /* Shadow status block. */
1320 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1321 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1322 sc->jme_cdata.jme_ssb_map);
1323 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
560616bf 1324 sc->jme_cdata.jme_ssb_block,
76fbb0b9
SZ		 1325 sc->jme_cdata.jme_ssb_map);
1326 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1327 sc->jme_cdata.jme_ssb_tag = NULL;
1328 }
1329
1330 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1331 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1332 sc->jme_cdata.jme_buffer_tag = NULL;
1333 }
1334 if (sc->jme_cdata.jme_ring_tag != NULL) {
1335 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1336 sc->jme_cdata.jme_ring_tag = NULL;
1337 }
83b03786 1338
0b3414d9
SZ		 1339 if (sc->jme_cdata.jme_txdesc != NULL) {
1340 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1341 sc->jme_cdata.jme_txdesc = NULL;
1342 }
7b040092 1343 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
0b3414d9
SZ		 1344 rdata = &sc->jme_cdata.jme_rx_data[r];
1345 if (rdata->jme_rxdesc != NULL) {
1346 kfree(rdata->jme_rxdesc, M_DEVBUF);
1347 rdata->jme_rxdesc = NULL;
83b03786
SZ		 1348 }
1349 }
76fbb0b9
SZ		 1350}
1351
1352/*
1353 * Make sure the interface is stopped at reboot time.
1354 */
1355static int
1356jme_shutdown(device_t dev)
1357{
1358 return jme_suspend(dev);
1359}
1360
1361#ifdef notyet
1362/*
1363 * Unlike other ethernet controllers, JMC250 requires
1364 * explicit resetting link speed to 10/100Mbps as gigabit
1365 * link will cunsume more power than 375mA.
1366 * Note, we reset the link speed to 10/100Mbps with
1367 * auto-negotiation but we don't know whether that operation
1368 * would succeed or not as we have no control after powering
1369 * off. If the renegotiation fail WOL may not work. Running
1370 * at 1Gbps draws more power than 375mA at 3.3V which is
1371 * specified in PCI specification and that would result in
1372 * complete shutdowning power to ethernet controller.
1373 *
1374 * TODO
1375 * Save current negotiated media speed/duplex/flow-control
1376 * to softc and restore the same link again after resuming.
1377 * PHY handling such as power down/resetting to 100Mbps
1378 * may be better handled in suspend method in phy driver.
1379 */
1380static void
1381jme_setlinkspeed(struct jme_softc *sc)
1382{
1383 struct mii_data *mii;
1384 int aneg, i;
1385
1386 JME_LOCK_ASSERT(sc);
1387
1388 mii = device_get_softc(sc->jme_miibus);
1389 mii_pollstat(mii);
1390 aneg = 0;
1391 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1392 switch IFM_SUBTYPE(mii->mii_media_active) {
1393 case IFM_10_T:
1394 case IFM_100_TX:
1395 return;
1396 case IFM_1000_T:
1397 aneg++;
1398 default:
1399 break;
1400 }
1401 }
1402 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1403 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1404 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1405 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1406 BMCR_AUTOEN | BMCR_STARTNEG);
1407 DELAY(1000);
1408 if (aneg != 0) {
1409 /* Poll link state until jme(4) get a 10/100 link. */
1410 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1411 mii_pollstat(mii);
1412 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1413 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1414 case IFM_10_T:
1415 case IFM_100_TX:
1416 jme_mac_config(sc);
1417 return;
1418 default:
1419 break;
1420 }
1421 }
1422 JME_UNLOCK(sc);
1423 pause("jmelnk", hz);
1424 JME_LOCK(sc);
1425 }
1426 if (i == MII_ANEGTICKS_GIGE)
1427 device_printf(sc->jme_dev, "establishing link failed, "
1428 "WOL may not work!");
1429 }
1430 /*
1431 * No link, force MAC to have 100Mbps, full-duplex link.
1432 * This is the last resort and may/may not work.
1433 */
1434 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1435 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1436 jme_mac_config(sc);
1437}
1438
1439static void
1440jme_setwol(struct jme_softc *sc)
1441{
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1443 uint32_t gpr, pmcs;
1444 uint16_t pmstat;
1445 int pmc;
1446
1447 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1448 /* No PME capability, PHY power down. */
1449 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1450 MII_BMCR, BMCR_PDOWN);
1451 return;
1452 }
1453
1454 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1455 pmcs = CSR_READ_4(sc, JME_PMCS);
1456 pmcs &= ~PMCS_WOL_ENB_MASK;
1457 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1458 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1459 /* Enable PME message. */
1460 gpr |= GPREG0_PME_ENB;
1461 /* For gigabit controllers, reset link speed to 10/100. */
ec7e787b 1462 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
76fbb0b9
SZ		 1463 jme_setlinkspeed(sc);
1464 }
1465
1466 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1467 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1468
1469 /* Request PME. */
1470 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1471 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1472 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1473 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1474 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1475 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1476 /* No WOL, PHY power down. */
1477 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1478 MII_BMCR, BMCR_PDOWN);
1479 }
1480}
1481#endif
1482
1483static int
1484jme_suspend(device_t dev)
1485{
1486 struct jme_softc *sc = device_get_softc(dev);
1487 struct ifnet *ifp = &sc->arpcom.ac_if;
1488
31f0d5a2 1489 ifnet_serialize_all(ifp);
76fbb0b9
SZ		 1490 jme_stop(sc);
1491#ifdef notyet
1492 jme_setwol(sc);
1493#endif
31f0d5a2 1494 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 1495
1496 return (0);
1497}
1498
1499static int
1500jme_resume(device_t dev)
1501{
1502 struct jme_softc *sc = device_get_softc(dev);
1503 struct ifnet *ifp = &sc->arpcom.ac_if;
1504#ifdef notyet
1505 int pmc;
1506#endif
1507
31f0d5a2 1508 ifnet_serialize_all(ifp);
76fbb0b9
SZ		 1509
1510#ifdef notyet
1511 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1512 uint16_t pmstat;
1513
1514 pmstat = pci_read_config(sc->jme_dev,
1515 pmc + PCIR_POWER_STATUS, 2);
1516 /* Disable PME clear PME status. */
1517 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1518 pci_write_config(sc->jme_dev,
1519 pmc + PCIR_POWER_STATUS, pmstat, 2);
1520 }
1521#endif
1522
1523 if (ifp->if_flags & IFF_UP)
1524 jme_init(sc);
1525
31f0d5a2 1526 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 1527
1528 return (0);
1529}
1530
1531static int
1532jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1533{
1534 struct jme_txdesc *txd;
1535 struct jme_desc *desc;
1536 struct mbuf *m;
76fbb0b9 1537 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
b0ba1747 1538 int maxsegs, nsegs;
9b3ee148 1539 int error, i, prod, symbol_desc;
7228f061 1540 uint32_t cflags, flag64;
76fbb0b9
SZ		 1541
1542 M_ASSERTPKTHDR((*m_head));
1543
1544 prod = sc->jme_cdata.jme_tx_prod;
1545 txd = &sc->jme_cdata.jme_txdesc[prod];
1546
9b3ee148
SZ		 1547 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1548 symbol_desc = 1;
1549 else
1550 symbol_desc = 0;
1551
b020bb10 1552 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
9b3ee148 1553 (JME_TXD_RSVD + symbol_desc);
76fbb0b9
SZ		 1554 if (maxsegs > JME_MAXTXSEGS)
1555 maxsegs = JME_MAXTXSEGS;
9b3ee148 1556 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
ed20d0e3 1557 ("not enough segments %d", maxsegs));
76fbb0b9 1558
b0ba1747
SZ		 1559 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1560 txd->tx_dmamap, m_head,
1561 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1562 if (error)
ecc6de9e 1563 goto fail;
76fbb0b9 1564
4458ee95
SZ		 1565 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1566 BUS_DMASYNC_PREWRITE);
1567
76fbb0b9
SZ		 1568 m = *m_head;
1569 cflags = 0;
1570
1571 /* Configure checksum offload. */
1572 if (m->m_pkthdr.csum_flags & CSUM_IP)
1573 cflags |= JME_TD_IPCSUM;
1574 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1575 cflags |= JME_TD_TCPCSUM;
1576 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1577 cflags |= JME_TD_UDPCSUM;
1578
1579 /* Configure VLAN. */
1580 if (m->m_flags & M_VLANTAG) {
1581 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1582 cflags |= JME_TD_VLAN_TAG;
1583 }
1584
560616bf 1585 desc = &sc->jme_cdata.jme_tx_ring[prod];
76fbb0b9 1586 desc->flags = htole32(cflags);
76fbb0b9 1587 desc->addr_hi = htole32(m->m_pkthdr.len);
7228f061
SZ		 1588 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1589 /*
1590 * Use 64bits TX desc chain format.
1591 *
1592 * The first TX desc of the chain, which is setup here,
1593 * is just a symbol TX desc carrying no payload.
1594 */
1595 flag64 = JME_TD_64BIT;
1596 desc->buflen = 0;
1597 desc->addr_lo = 0;
1598
1599 /* No effective TX desc is consumed */
1600 i = 0;
1601 } else {
1602 /*
1603 * Use 32bits TX desc chain format.
1604 *
1605 * The first TX desc of the chain, which is setup here,
1606 * is an effective TX desc carrying the first segment of
1607 * the mbuf chain.
1608 */
1609 flag64 = 0;
1610 desc->buflen = htole32(txsegs[0].ds_len);
1611 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1612
1613 /* One effective TX desc is consumed */
1614 i = 1;
1615 }
76fbb0b9 1616 sc->jme_cdata.jme_tx_cnt++;
9de40864 1617 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
022f915e 1618 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
b020bb10 1619 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
7228f061
SZ		 1620
1621 txd->tx_ndesc = 1 - i;
b0ba1747 1622 for (; i < nsegs; i++) {
560616bf 1623 desc = &sc->jme_cdata.jme_tx_ring[prod];
76fbb0b9
SZ		 1624 desc->buflen = htole32(txsegs[i].ds_len);
1625 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1626 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
a54bd021 1627 desc->flags = htole32(JME_TD_OWN | flag64);
76fbb0b9
SZ		 1628
1629 sc->jme_cdata.jme_tx_cnt++;
1630 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
022f915e 1631 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
b020bb10 1632 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ		 1633 }
1634
1635 /* Update producer index. */
1636 sc->jme_cdata.jme_tx_prod = prod;
1637 /*
1638 * Finally request interrupt and give the first descriptor
1639 * owenership to hardware.
1640 */
1641 desc = txd->tx_desc;
1642 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1643
1644 txd->tx_m = m;
b0ba1747 1645 txd->tx_ndesc += nsegs;
76fbb0b9 1646
ecc6de9e
SZ		 1647 return 0;
1648fail:
1649 m_freem(*m_head);
1650 *m_head = NULL;
1651 return error;
76fbb0b9
SZ		 1652}
1653
1654static void
1655jme_start(struct ifnet *ifp)
1656{
1657 struct jme_softc *sc = ifp->if_softc;
1658 struct mbuf *m_head;
1659 int enq = 0;
1660
31f0d5a2 1661 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9 1662
cccc3955 1663 if (!sc->jme_has_link) {
76fbb0b9
SZ		 1664 ifq_purge(&ifp->if_snd);
1665 return;
1666 }
1667
1668 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1669 return;
1670
83b03786 1671 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
76fbb0b9
SZ		 1672 jme_txeof(sc);
1673
1674 while (!ifq_is_empty(&ifp->if_snd)) {
1675 /*
1676 * Check number of available TX descs, always
1677 * leave JME_TXD_RSVD free TX descs.
1678 */
1679 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
b020bb10 1680 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
76fbb0b9
SZ		 1681 ifp->if_flags |= IFF_OACTIVE;
1682 break;
1683 }
1684
1685 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1686 if (m_head == NULL)
1687 break;
1688
1689 /*
1690 * Pack the data into the transmit ring. If we
1691 * don't have room, set the OACTIVE flag and wait
1692 * for the NIC to drain the ring.
1693 */
1694 if (jme_encap(sc, &m_head)) {
ecc6de9e
SZ		 1695 KKASSERT(m_head == NULL);
1696 ifp->if_oerrors++;
76fbb0b9
SZ		 1697 ifp->if_flags |= IFF_OACTIVE;
1698 break;
1699 }
1700 enq++;
1701
1702 /*
1703 * If there's a BPF listener, bounce a copy of this frame
1704 * to him.
1705 */
1706 ETHER_BPF_MTAP(ifp, m_head);
1707 }
1708
1709 if (enq > 0) {
1710 /*
1711 * Reading TXCSR takes very long time under heavy load
1712 * so cache TXCSR value and writes the ORed value with
1713 * the kick command to the TXCSR. This saves one register
1714 * access cycle.
1715 */
1716 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1717 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1718 /* Set a timeout in case the chip goes out to lunch. */
1719 ifp->if_timer = JME_TX_TIMEOUT;
1720 }
1721}
1722
1723static void
1724jme_watchdog(struct ifnet *ifp)
1725{
1726 struct jme_softc *sc = ifp->if_softc;
1727
31f0d5a2 1728 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9 1729
cccc3955 1730 if (!sc->jme_has_link) {
76fbb0b9
SZ		 1731 if_printf(ifp, "watchdog timeout (missed link)\n");
1732 ifp->if_oerrors++;
1733 jme_init(sc);
1734 return;
1735 }
1736
1737 jme_txeof(sc);
1738 if (sc->jme_cdata.jme_tx_cnt == 0) {
1739 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1740 "-- recovering\n");
1741 if (!ifq_is_empty(&ifp->if_snd))
1742 if_devstart(ifp);
1743 return;
1744 }
1745
1746 if_printf(ifp, "watchdog timeout\n");
1747 ifp->if_oerrors++;
1748 jme_init(sc);
1749 if (!ifq_is_empty(&ifp->if_snd))
1750 if_devstart(ifp);
1751}
1752
1753static int
1754jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1755{
1756 struct jme_softc *sc = ifp->if_softc;
1757 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1758 struct ifreq *ifr = (struct ifreq *)data;
1759 int error = 0, mask;
1760
31f0d5a2 1761 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 1762
1763 switch (cmd) {
1764 case SIOCSIFMTU:
1765 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
3a5f3f36 1766 (!(sc->jme_caps & JME_CAP_JUMBO) &&
76fbb0b9
SZ		 1767 ifr->ifr_mtu > JME_MAX_MTU)) {
1768 error = EINVAL;
1769 break;
1770 }
1771
1772 if (ifp->if_mtu != ifr->ifr_mtu) {
1773 /*
1774 * No special configuration is required when interface
1775 * MTU is changed but availability of Tx checksum
1776 * offload should be chcked against new MTU size as
1777 * FIFO size is just 2K.
1778 */
1779 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1780 ifp->if_capenable &= ~IFCAP_TXCSUM;
1781 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1782 }
1783 ifp->if_mtu = ifr->ifr_mtu;
1784 if (ifp->if_flags & IFF_RUNNING)
1785 jme_init(sc);
1786 }
1787 break;
1788
1789 case SIOCSIFFLAGS:
1790 if (ifp->if_flags & IFF_UP) {
1791 if (ifp->if_flags & IFF_RUNNING) {
1792 if ((ifp->if_flags ^ sc->jme_if_flags) &
1793 (IFF_PROMISC | IFF_ALLMULTI))
1794 jme_set_filter(sc);
1795 } else {
1796 jme_init(sc);
1797 }
1798 } else {
1799 if (ifp->if_flags & IFF_RUNNING)
1800 jme_stop(sc);
1801 }
1802 sc->jme_if_flags = ifp->if_flags;
1803 break;
1804
1805 case SIOCADDMULTI:
1806 case SIOCDELMULTI:
1807 if (ifp->if_flags & IFF_RUNNING)
1808 jme_set_filter(sc);
1809 break;
1810
1811 case SIOCSIFMEDIA:
1812 case SIOCGIFMEDIA:
1813 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1814 break;
1815
1816 case SIOCSIFCAP:
1817 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1818
1819 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
e4616e94
SZ		 1820 ifp->if_capenable ^= IFCAP_TXCSUM;
1821 if (IFCAP_TXCSUM & ifp->if_capenable)
1822 ifp->if_hwassist |= JME_CSUM_FEATURES;
1823 else
1824 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
76fbb0b9 1825 }
e4616e94 1826 if (mask & IFCAP_RXCSUM) {
76fbb0b9
SZ		 1827 uint32_t reg;
1828
1829 ifp->if_capenable ^= IFCAP_RXCSUM;
1830 reg = CSR_READ_4(sc, JME_RXMAC);
1831 reg &= ~RXMAC_CSUM_ENB;
1832 if (ifp->if_capenable & IFCAP_RXCSUM)
1833 reg |= RXMAC_CSUM_ENB;
1834 CSR_WRITE_4(sc, JME_RXMAC, reg);
1835 }
1836
e4616e94 1837 if (mask & IFCAP_VLAN_HWTAGGING) {
76fbb0b9
SZ		 1838 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1839 jme_set_vlan(sc);
1840 }
e4616e94 1841
9f20b7b3 1842 if (mask & IFCAP_RSS)
d585233c 1843 ifp->if_capenable ^= IFCAP_RSS;
76fbb0b9
SZ		 1844 break;
1845
1846 default:
1847 error = ether_ioctl(ifp, cmd, data);
1848 break;
1849 }
1850 return (error);
1851}
1852
1853static void
1854jme_mac_config(struct jme_softc *sc)
1855{
1856 struct mii_data *mii;
3b3da110
SZ		 1857 uint32_t ghc, rxmac, txmac, txpause, gp1;
1858 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
76fbb0b9
SZ		 1859
1860 mii = device_get_softc(sc->jme_miibus);
1861
1862 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1863 DELAY(10);
1864 CSR_WRITE_4(sc, JME_GHC, 0);
1865 ghc = 0;
1866 rxmac = CSR_READ_4(sc, JME_RXMAC);
1867 rxmac &= ~RXMAC_FC_ENB;
1868 txmac = CSR_READ_4(sc, JME_TXMAC);
1869 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1870 txpause = CSR_READ_4(sc, JME_TXPFC);
1871 txpause &= ~TXPFC_PAUSE_ENB;
1872 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1873 ghc |= GHC_FULL_DUPLEX;
1874 rxmac &= ~RXMAC_COLL_DET_ENB;
1875 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1876 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1877 TXMAC_FRAME_BURST);
1878#ifdef notyet
1879 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1880 txpause |= TXPFC_PAUSE_ENB;
1881 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1882 rxmac |= RXMAC_FC_ENB;
1883#endif
1884 /* Disable retry transmit timer/retry limit. */
1885 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1886 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1887 } else {
1888 rxmac |= RXMAC_COLL_DET_ENB;
1889 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1890 /* Enable retry transmit timer/retry limit. */
1891 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1892 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1893 }
1894
3b3da110
SZ		 1895 /*
1896 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1897 */
1898 gp1 = CSR_READ_4(sc, JME_GPREG1);
1899 gp1 &= ~GPREG1_WA_HDX;
1900
1901 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1902 hdx = 1;
1903
76fbb0b9
SZ		 1904 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1905 case IFM_10_T:
b249905b 1906 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
3b3da110
SZ		 1907 if (hdx)
1908 gp1 |= GPREG1_WA_HDX;
76fbb0b9 1909 break;
dbe37f03 1910
76fbb0b9 1911 case IFM_100_TX:
b249905b 1912 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
3b3da110
SZ		 1913 if (hdx)
1914 gp1 |= GPREG1_WA_HDX;
dbe37f03
SZ		 1915
1916 /*
1917 * Use extended FIFO depth to workaround CRC errors
1918 * emitted by chips before JMC250B
1919 */
1920 phyconf = JMPHY_CONF_EXTFIFO;
76fbb0b9 1921 break;
dbe37f03 1922
76fbb0b9 1923 case IFM_1000_T:
ec7e787b 1924 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 1925 break;
dbe37f03 1926
b249905b 1927 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
3b3da110 1928 if (hdx)
76fbb0b9
SZ		 1929 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1930 break;
dbe37f03 1931
76fbb0b9
SZ		 1932 default:
1933 break;
1934 }
1935 CSR_WRITE_4(sc, JME_GHC, ghc);
1936 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1937 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1938 CSR_WRITE_4(sc, JME_TXPFC, txpause);
dbe37f03 1939
ad22907f 1940 if (sc->jme_workaround & JME_WA_EXTFIFO) {
dbe37f03
SZ		 1941 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1942 JMPHY_CONF, phyconf);
1943 }
3b3da110
SZ		 1944 if (sc->jme_workaround & JME_WA_HDX)
1945 CSR_WRITE_4(sc, JME_GPREG1, gp1);
76fbb0b9
SZ		 1946}
1947
1948static void
1949jme_intr(void *xsc)
1950{
1951 struct jme_softc *sc = xsc;
1952 struct ifnet *ifp = &sc->arpcom.ac_if;
1953 uint32_t status;
4447c752 1954 int r;
76fbb0b9 1955
31f0d5a2 1956 ASSERT_SERIALIZED(&sc->jme_serialize);
76fbb0b9
SZ		 1957
1958 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1959 if (status == 0 || status == 0xFFFFFFFF)
1960 return;
1961
1962 /* Disable interrupts. */
1963 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1964
1965 status = CSR_READ_4(sc, JME_INTR_STATUS);
1966 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1967 goto back;
1968
1969 /* Reset PCC counter/timer and Ack interrupts. */
1970 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
4447c752 1971
76fbb0b9
SZ		 1972 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1973 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
4447c752 1974
7b040092 1975 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 1976 if (status & jme_rx_status[r].jme_coal) {
1977 status |= jme_rx_status[r].jme_coal |
1978 jme_rx_status[r].jme_comp;
1979 }
1980 }
1981
76fbb0b9
SZ		 1982 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1983
1984 if (ifp->if_flags & IFF_RUNNING) {
1985 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
4447c752 1986 jme_rx_intr(sc, status);
76fbb0b9
SZ		 1987
1988 if (status & INTR_RXQ_DESC_EMPTY) {
1989 /*
1990 * Notify hardware availability of new Rx buffers.
1991 * Reading RXCSR takes very long time under heavy
1992 * load so cache RXCSR value and writes the ORed
1993 * value with the kick command to the RXCSR. This
1994 * saves one register access cycle.
1995 */
1996 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1997 RXCSR_RX_ENB | RXCSR_RXQ_START);
1998 }
1999
2000 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
31f0d5a2 2001 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ		 2002 jme_txeof(sc);
2003 if (!ifq_is_empty(&ifp->if_snd))
2004 if_devstart(ifp);
31f0d5a2 2005 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ		 2006 }
2007 }
2008back:
2009 /* Reenable interrupts. */
2010 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2011}
2012
2013static void
2014jme_txeof(struct jme_softc *sc)
2015{
2016 struct ifnet *ifp = &sc->arpcom.ac_if;
6960d7d2 2017 int cons;
76fbb0b9
SZ		 2018
2019 cons = sc->jme_cdata.jme_tx_cons;
2020 if (cons == sc->jme_cdata.jme_tx_prod)
2021 return;
2022
76fbb0b9
SZ		 2023 /*
2024 * Go through our Tx list and free mbufs for those
2025 * frames which have been transmitted.
2026 */
2027 while (cons != sc->jme_cdata.jme_tx_prod) {
6960d7d2
SZ		 2028 struct jme_txdesc *txd, *next_txd;
2029 uint32_t status, next_status;
2030 int next_cons, nsegs;
2031
76fbb0b9
SZ		 2032 txd = &sc->jme_cdata.jme_txdesc[cons];
2033 KASSERT(txd->tx_m != NULL,
ed20d0e3 2034 ("%s: freeing NULL mbuf!", __func__));
76fbb0b9
SZ		 2035
2036 status = le32toh(txd->tx_desc->flags);
2037 if ((status & JME_TD_OWN) == JME_TD_OWN)
2038 break;
2039
6960d7d2
SZ		 2040 /*
2041 * NOTE:
2042 * This chip will always update the TX descriptor's
2043 * buflen field and this updating always happens
2044 * after clearing the OWN bit, so even if the OWN
2045 * bit is cleared by the chip, we still don't sure
2046 * about whether the buflen field has been updated
2047 * by the chip or not. To avoid this race, we wait
2048 * for the next TX descriptor's OWN bit to be cleared
2049 * by the chip before reusing this TX descriptor.
2050 */
2051 next_cons = cons;
2052 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2053 sc->jme_cdata.jme_tx_desc_cnt);
2054 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2055 if (next_txd->tx_m == NULL)
2056 break;
2057 next_status = le32toh(next_txd->tx_desc->flags);
2058 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2059 break;
2060
76fbb0b9
SZ		 2061 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2062 ifp->if_oerrors++;
2063 } else {
2064 ifp->if_opackets++;
2065 if (status & JME_TD_COLLISION) {
2066 ifp->if_collisions +=
2067 le32toh(txd->tx_desc->buflen) &
2068 JME_TD_BUF_LEN_MASK;
2069 }
2070 }
2071
2072 /*
2073 * Only the first descriptor of multi-descriptor
2074 * transmission is updated so driver have to skip entire
2075 * chained buffers for the transmiited frame. In other
2076 * words, JME_TD_OWN bit is valid only at the first
2077 * descriptor of a multi-descriptor transmission.
2078 */
2079 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
560616bf 2080 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
b020bb10 2081 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ		 2082 }
2083
2084 /* Reclaim transferred mbufs. */
2085 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2086 m_freem(txd->tx_m);
2087 txd->tx_m = NULL;
2088 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2089 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
ed20d0e3 2090 ("%s: Active Tx desc counter was garbled", __func__));
76fbb0b9
SZ		 2091 txd->tx_ndesc = 0;
2092 }
2093 sc->jme_cdata.jme_tx_cons = cons;
2094
6960d7d2 2095 if (sc->jme_cdata.jme_tx_cnt < JME_MAXTXSEGS + 1)
76fbb0b9
SZ		 2096 ifp->if_timer = 0;
2097
2098 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
b020bb10 2099 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
76fbb0b9 2100 ifp->if_flags &= ~IFF_OACTIVE;
76fbb0b9
SZ		 2101}
2102
2103static __inline void
dea2452a 2104jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
76fbb0b9
SZ		 2105{
2106 int i;
2107
2108 for (i = 0; i < count; ++i) {
fd2a6d2c 2109 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
7b040092 2110 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
76fbb0b9
SZ		 2111 }
2112}
2113
a6acc6e2
SZ		 2114static __inline struct pktinfo *
2115jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2116{
2117 if (flags & JME_RD_IPV4)
2118 pi->pi_netisr = NETISR_IP;
2119 else if (flags & JME_RD_IPV6)
2120 pi->pi_netisr = NETISR_IPV6;
2121 else
2122 return NULL;
2123
2124 pi->pi_flags = 0;
2125 pi->pi_l3proto = IPPROTO_UNKNOWN;
2126
2127 if (flags & JME_RD_MORE_FRAG)
2128 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2129 else if (flags & JME_RD_TCP)
2130 pi->pi_l3proto = IPPROTO_TCP;
2131 else if (flags & JME_RD_UDP)
2132 pi->pi_l3proto = IPPROTO_UDP;
7345eb80
SZ		 2133 else
2134 pi = NULL;
a6acc6e2
SZ		 2135 return pi;
2136}
2137
76fbb0b9
SZ		 2138/* Receive a frame. */
2139static void
dea2452a 2140jme_rxpkt(struct jme_rxdata *rdata)
76fbb0b9 2141{
dea2452a 2142 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
76fbb0b9
SZ		 2143 struct jme_desc *desc;
2144 struct jme_rxdesc *rxd;
2145 struct mbuf *mp, *m;
a6acc6e2 2146 uint32_t flags, status, hash, hashinfo;
76fbb0b9
SZ		 2147 int cons, count, nsegs;
2148
4447c752
SZ		 2149 cons = rdata->jme_rx_cons;
2150 desc = &rdata->jme_rx_ring[cons];
9d4f763d 2151
76fbb0b9
SZ		 2152 flags = le32toh(desc->flags);
2153 status = le32toh(desc->buflen);
a6acc6e2
SZ		 2154 hash = le32toh(desc->addr_hi);
2155 hashinfo = le32toh(desc->addr_lo);
76fbb0b9
SZ		 2156 nsegs = JME_RX_NSEGS(status);
2157
9d4f763d
SZ		 2158 if (nsegs > 1) {
2159 /* Skip the first descriptor. */
2160 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2161
2162 /*
2163 * Clear the OWN bit of the following RX descriptors;
2164 * hardware will not clear the OWN bit except the first
2165 * RX descriptor.
2166 *
2167 * Since the first RX descriptor is setup, i.e. OWN bit
2168 * on, before its followins RX descriptors, leaving the
2169 * OWN bit on the following RX descriptors will trick
2170 * the hardware into thinking that the following RX
2171 * descriptors are ready to be used too.
2172 */
2173 for (count = 1; count < nsegs; count++,
2174 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2175 rdata->jme_rx_ring[cons].flags = 0;
2176
2177 cons = rdata->jme_rx_cons;
2178 }
2179
7b040092 2180 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
a6acc6e2 2181 "hash 0x%08x, hash info 0x%08x\n",
7b040092 2182 rdata->jme_rx_idx, flags, hash, hashinfo);
760c056c 2183
76fbb0b9
SZ		 2184 if (status & JME_RX_ERR_STAT) {
2185 ifp->if_ierrors++;
dea2452a 2186 jme_discard_rxbufs(rdata, cons, nsegs);
76fbb0b9 2187#ifdef JME_SHOW_ERRORS
7b040092 2188 if_printf(ifp, "%s : receive error = 0x%b\n",
76fbb0b9
SZ		 2189 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2190#endif
4447c752 2191 rdata->jme_rx_cons += nsegs;
7b040092 2192 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ		 2193 return;
2194 }
2195
4447c752 2196 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
76fbb0b9 2197 for (count = 0; count < nsegs; count++,
7b040092 2198 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
4447c752 2199 rxd = &rdata->jme_rxdesc[cons];
76fbb0b9
SZ		 2200 mp = rxd->rx_m;
2201
2202 /* Add a new receive buffer to the ring. */
dea2452a 2203 if (jme_newbuf(rdata, rxd, 0) != 0) {
76fbb0b9
SZ		 2204 ifp->if_iqdrops++;
2205 /* Reuse buffer. */
dea2452a 2206 jme_discard_rxbufs(rdata, cons, nsegs - count);
4447c752
SZ		 2207 if (rdata->jme_rxhead != NULL) {
2208 m_freem(rdata->jme_rxhead);
dea2452a 2209 JME_RXCHAIN_RESET(rdata);
76fbb0b9
SZ		 2210 }
2211 break;
2212 }
2213
2214 /*
2215 * Assume we've received a full sized frame.
2216 * Actual size is fixed when we encounter the end of
2217 * multi-segmented frame.
2218 */
2219 mp->m_len = MCLBYTES;
2220
2221 /* Chain received mbufs. */
4447c752
SZ		 2222 if (rdata->jme_rxhead == NULL) {
2223 rdata->jme_rxhead = mp;
2224 rdata->jme_rxtail = mp;
76fbb0b9
SZ		 2225 } else {
2226 /*
2227 * Receive processor can receive a maximum frame
2228 * size of 65535 bytes.
2229 */
4447c752
SZ		 2230 rdata->jme_rxtail->m_next = mp;
2231 rdata->jme_rxtail = mp;
76fbb0b9
SZ		 2232 }
2233
2234 if (count == nsegs - 1) {
a6acc6e2
SZ		 2235 struct pktinfo pi0, *pi;
2236
76fbb0b9 2237 /* Last desc. for this frame. */
4447c752 2238 m = rdata->jme_rxhead;
4447c752 2239 m->m_pkthdr.len = rdata->jme_rxlen;
76fbb0b9
SZ		 2240 if (nsegs > 1) {
2241 /* Set first mbuf size. */
2242 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2243 /* Set last mbuf size. */
4447c752 2244 mp->m_len = rdata->jme_rxlen -
76fbb0b9
SZ		 2245 ((MCLBYTES - JME_RX_PAD_BYTES) +
2246 (MCLBYTES * (nsegs - 2)));
2247 } else {
4447c752 2248 m->m_len = rdata->jme_rxlen;
76fbb0b9
SZ		 2249 }
2250 m->m_pkthdr.rcvif = ifp;
2251
2252 /*
2253 * Account for 10bytes auto padding which is used
2254 * to align IP header on 32bit boundary. Also note,
2255 * CRC bytes is automatically removed by the
2256 * hardware.
2257 */
2258 m->m_data += JME_RX_PAD_BYTES;
2259
2260 /* Set checksum information. */
2261 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2262 (flags & JME_RD_IPV4)) {
2263 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2264 if (flags & JME_RD_IPCSUM)
2265 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2266 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2267 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2268 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2269 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2270 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2271 m->m_pkthdr.csum_flags |=
2272 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2273 m->m_pkthdr.csum_data = 0xffff;
2274 }
2275 }
2276
2277 /* Check for VLAN tagged packets. */
2278 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2279 (flags & JME_RD_VLAN_TAG)) {
2280 m->m_pkthdr.ether_vlantag =
2281 flags & JME_RD_VLAN_MASK;
2282 m->m_flags |= M_VLANTAG;
2283 }
2284
2285 ifp->if_ipackets++;
a6acc6e2
SZ		 2286
2287 if (ifp->if_capenable & IFCAP_RSS)
2288 pi = jme_pktinfo(&pi0, flags);
2289 else
2290 pi = NULL;
2291
2292 if (pi != NULL &&
2293 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2294 m->m_flags |= M_HASH;
2295 m->m_pkthdr.hash = toeplitz_hash(hash);
2296 }
2297
2298#ifdef JME_RSS_DEBUG
2299 if (pi != NULL) {
7b040092 2300 JME_RSS_DPRINTF(rdata->jme_sc, 10,
a6acc6e2
SZ		 2301 "isr %d flags %08x, l3 %d %s\n",
2302 pi->pi_netisr, pi->pi_flags,
2303 pi->pi_l3proto,
2304 (m->m_flags & M_HASH) ? "hash" : "");
2305 }
2306#endif
2307
76fbb0b9 2308 /* Pass it on. */
eda7db08 2309 ether_input_pkt(ifp, m, pi);
76fbb0b9
SZ		 2310
2311 /* Reset mbuf chains. */
dea2452a 2312 JME_RXCHAIN_RESET(rdata);
760c056c 2313#ifdef JME_RSS_DEBUG
7b040092 2314 rdata->jme_rx_pkt++;
760c056c 2315#endif
76fbb0b9
SZ		 2316 }
2317 }
2318
4447c752 2319 rdata->jme_rx_cons += nsegs;
7b040092 2320 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ		 2321}
2322
eda7db08 2323static void
dea2452a 2324jme_rxeof(struct jme_rxdata *rdata, int count)
76fbb0b9
SZ		 2325{
2326 struct jme_desc *desc;
eda7db08 2327 int nsegs, pktlen;
76fbb0b9 2328
76fbb0b9 2329 for (;;) {
3fa06afc
SZ		 2330#ifdef DEVICE_POLLING
2331 if (count >= 0 && count-- == 0)
2332 break;
2333#endif
4447c752 2334 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
76fbb0b9
SZ		 2335 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2336 break;
2337 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2338 break;
2339
2340 /*
2341 * Check number of segments against received bytes.
2342 * Non-matching value would indicate that hardware
2343 * is still trying to update Rx descriptors. I'm not
2344 * sure whether this check is needed.
2345 */
2346 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2347 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2348 if (nsegs != howmany(pktlen, MCLBYTES)) {
dea2452a
SZ		 2349 if_printf(&rdata->jme_sc->arpcom.ac_if,
2350 "RX fragment count(%d) and "
2351 "packet size(%d) mismach\n", nsegs, pktlen);
76fbb0b9
SZ		 2352 break;
2353 }
2354
6afef6ab
SZ		 2355 /*
2356 * NOTE:
2357 * RSS hash and hash information may _not_ be set by the
2358 * hardware even if the OWN bit is cleared and VALID bit
2359 * is set.
2360 *
2361 * If the RSS information is not delivered by the hardware
2362 * yet, we MUST NOT accept this packet, let alone reusing
2363 * its RX descriptor. If this packet was accepted and its
2364 * RX descriptor was reused before hardware delivering the
2365 * RSS information, the RX buffer's address would be trashed
2366 * by the RSS information delivered by the hardware.
2367 */
2368 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2369 struct jme_rxdesc *rxd;
2370 uint32_t hashinfo;
2371
2372 hashinfo = le32toh(desc->addr_lo);
2373 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2374
2375 /*
2376 * This test should be enough to detect the pending
2377 * RSS information delivery, given:
2378 * - If RSS hash is not calculated, the hashinfo
064b75ed
SZ		 2379 * will be 0. Howvever, the lower 32bits of RX
2380 * buffers' physical address will never be 0.
2381 * (see jme_rxbuf_dma_filter)
6afef6ab
SZ		 2382 * - If RSS hash is calculated, the lowest 4 bits
2383 * of hashinfo will be set, while the RX buffers
2384 * are at least 2K aligned.
2385 */
2386 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2387#ifdef JME_SHOW_RSSWB
2388 if_printf(&rdata->jme_sc->arpcom.ac_if,
2389 "RSS is not written back yet\n");
2390#endif
2391 break;
2392 }
2393 }
2394
76fbb0b9 2395 /* Received a frame. */
dea2452a 2396 jme_rxpkt(rdata);
76fbb0b9 2397 }
76fbb0b9
SZ		 2398}
2399
2400static void
2401jme_tick(void *xsc)
2402{
2403 struct jme_softc *sc = xsc;
76fbb0b9
SZ		 2404 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2405
cccc3955 2406 lwkt_serialize_enter(&sc->jme_serialize);
76fbb0b9 2407
cccc3955 2408 sc->jme_in_tick = TRUE;
76fbb0b9 2409 mii_tick(mii);
cccc3955
SZ		 2410 sc->jme_in_tick = FALSE;
2411
76fbb0b9
SZ		 2412 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2413
cccc3955 2414 lwkt_serialize_exit(&sc->jme_serialize);
76fbb0b9
SZ		 2415}
2416
2417static void
2418jme_reset(struct jme_softc *sc)
2419{
409fe405
SZ		 2420 uint32_t val;
2421
2422 /* Make sure that TX and RX are stopped */
76fbb0b9 2423 jme_stop_tx(sc);
409fe405
SZ		 2424 jme_stop_rx(sc);
2425
2426 /* Start reset */
76fbb0b9 2427 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
409fe405
SZ		 2428 DELAY(20);
2429
2430 /*
2431 * Hold reset bit before stop reset
2432 */
2433
2434 /* Disable TXMAC and TXOFL clock sources */
2435 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2436 /* Disable RXMAC clock source */
2437 val = CSR_READ_4(sc, JME_GPREG1);
2438 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2439 /* Flush */
2440 CSR_READ_4(sc, JME_GHC);
2441
2442 /* Stop reset */
2443 CSR_WRITE_4(sc, JME_GHC, 0);
2444 /* Flush */
2445 CSR_READ_4(sc, JME_GHC);
2446
2447 /*
2448 * Clear reset bit after stop reset
2449 */
2450
2451 /* Enable TXMAC and TXOFL clock sources */
2452 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2453 /* Enable RXMAC clock source */
2454 val = CSR_READ_4(sc, JME_GPREG1);
2455 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2456 /* Flush */
2457 CSR_READ_4(sc, JME_GHC);
2458
2459 /* Disable TXMAC and TXOFL clock sources */
76fbb0b9 2460 CSR_WRITE_4(sc, JME_GHC, 0);
409fe405
SZ		 2461 /* Disable RXMAC clock source */
2462 val = CSR_READ_4(sc, JME_GPREG1);
2463 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2464 /* Flush */
2465 CSR_READ_4(sc, JME_GHC);
2466
2467 /* Enable TX and RX */
2468 val = CSR_READ_4(sc, JME_TXCSR);
2469 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2470 val = CSR_READ_4(sc, JME_RXCSR);
2471 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2472 /* Flush */
2473 CSR_READ_4(sc, JME_TXCSR);
2474 CSR_READ_4(sc, JME_RXCSR);
2475
2476 /* Enable TXMAC and TXOFL clock sources */
2477 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2478 /* Eisable RXMAC clock source */
2479 val = CSR_READ_4(sc, JME_GPREG1);
2480 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2481 /* Flush */
2482 CSR_READ_4(sc, JME_GHC);
2483
2484 /* Stop TX and RX */
2485 jme_stop_tx(sc);
2486 jme_stop_rx(sc);
76fbb0b9
SZ		 2487}
2488
2489static void
2490jme_init(void *xsc)
2491{
2492 struct jme_softc *sc = xsc;
2493 struct ifnet *ifp = &sc->arpcom.ac_if;
2494 struct mii_data *mii;
2495 uint8_t eaddr[ETHER_ADDR_LEN];
2496 bus_addr_t paddr;
2497 uint32_t reg;
4447c752 2498 int error, r;
76fbb0b9 2499
31f0d5a2 2500 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2501
2502 /*
2503 * Cancel any pending I/O.
2504 */
2505 jme_stop(sc);
2506
2507 /*
2508 * Reset the chip to a known state.
2509 */
2510 jme_reset(sc);
2511
58880b0d
SZ		 2512 /*
2513 * Setup MSI/MSI-X vectors to interrupts mapping
2514 */
2515 jme_set_msinum(sc);
2516
9b3ee148
SZ		 2517 sc->jme_txd_spare =
2518 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2519 KKASSERT(sc->jme_txd_spare >= 1);
2520
76fbb0b9 2521 /*
9b3ee148
SZ		 2522 * If we use 64bit address mode for transmitting, each Tx request
2523 * needs one more symbol descriptor.
76fbb0b9 2524 */
9b3ee148
SZ		 2525 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2526 sc->jme_txd_spare += 1;
76fbb0b9 2527
6afef6ab 2528 if (JME_ENABLE_HWRSS(sc))
760c056c
SZ		 2529 jme_enable_rss(sc);
2530 else
2531 jme_disable_rss(sc);
4447c752
SZ		 2532
2533 /* Init RX descriptors */
7b040092 2534 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
dea2452a 2535 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
4447c752
SZ		 2536 if (error) {
2537 if_printf(ifp, "initialization failed: "
2538 "no memory for %dth RX ring.\n", r);
2539 jme_stop(sc);
2540 return;
2541 }
2542 }
2543
2544 /* Init TX descriptors */
76fbb0b9
SZ		 2545 jme_init_tx_ring(sc);
2546
2547 /* Initialize shadow status block. */
2548 jme_init_ssb(sc);
2549
2550 /* Reprogram the station address. */
2551 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2552 CSR_WRITE_4(sc, JME_PAR0,
2553 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2554 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2555
2556 /*
2557 * Configure Tx queue.
2558 * Tx priority queue weight value : 0
2559 * Tx FIFO threshold for processing next packet : 16QW
2560 * Maximum Tx DMA length : 512
2561 * Allow Tx DMA burst.
2562 */
2563 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2564 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2565 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2566 sc->jme_txcsr |= sc->jme_tx_dma_size;
2567 sc->jme_txcsr |= TXCSR_DMA_BURST;
2568 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2569
2570 /* Set Tx descriptor counter. */
b020bb10 2571 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ		 2572
2573 /* Set Tx ring address to the hardware. */
7405bec3 2574 paddr = sc->jme_cdata.jme_tx_ring_paddr;
76fbb0b9
SZ		 2575 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2576 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2577
2578 /* Configure TxMAC parameters. */
2579 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2580 reg |= TXMAC_THRESH_1_PKT;
2581 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2582 CSR_WRITE_4(sc, JME_TXMAC, reg);
2583
2584 /*
2585 * Configure Rx queue.
2586 * FIFO full threshold for transmitting Tx pause packet : 128T
2587 * FIFO threshold for processing next packet : 128QW
2588 * Rx queue 0 select
2589 * Max Rx DMA length : 128
2590 * Rx descriptor retry : 32
2591 * Rx descriptor retry time gap : 256ns
2592 * Don't receive runt/bad frame.
2593 */
2594 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
223cfc2f 2595#if 0
76fbb0b9
SZ		 2596 /*
2597 * Since Rx FIFO size is 4K bytes, receiving frames larger
2598 * than 4K bytes will suffer from Rx FIFO overruns. So
2599 * decrease FIFO threshold to reduce the FIFO overruns for
2600 * frames larger than 4000 bytes.
2601 * For best performance of standard MTU sized frames use
2602 * maximum allowable FIFO threshold, 128QW.
2603 */
2604 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2605 JME_RX_FIFO_SIZE)
2606 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2607 else
2608 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
223cfc2f
SZ		 2609#else
2610 /* Improve PCI Express compatibility */
2611 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2612#endif
2613 sc->jme_rxcsr |= sc->jme_rx_dma_size;
76fbb0b9
SZ		 2614 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2615 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2616 /* XXX TODO DROP_BAD */
76fbb0b9 2617
7b040092
SZ		 2618 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2619 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2620
4447c752
SZ		 2621 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2622
2623 /* Set Rx descriptor counter. */
7b040092 2624 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
76fbb0b9 2625
4447c752 2626 /* Set Rx ring address to the hardware. */
7b040092 2627 paddr = rdata->jme_rx_ring_paddr;
4447c752
SZ		 2628 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2629 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2630 }
76fbb0b9
SZ		 2631
2632 /* Clear receive filter. */
2633 CSR_WRITE_4(sc, JME_RXMAC, 0);
2634
2635 /* Set up the receive filter. */
2636 jme_set_filter(sc);
2637 jme_set_vlan(sc);
2638
2639 /*
2640 * Disable all WOL bits as WOL can interfere normal Rx
2641 * operation. Also clear WOL detection status bits.
2642 */
2643 reg = CSR_READ_4(sc, JME_PMCS);
2644 reg &= ~PMCS_WOL_ENB_MASK;
2645 CSR_WRITE_4(sc, JME_PMCS, reg);
2646
2647 /*
2648 * Pad 10bytes right before received frame. This will greatly
2649 * help Rx performance on strict-alignment architectures as
2650 * it does not need to copy the frame to align the payload.
2651 */
2652 reg = CSR_READ_4(sc, JME_RXMAC);
2653 reg |= RXMAC_PAD_10BYTES;
2654
2655 if (ifp->if_capenable & IFCAP_RXCSUM)
2656 reg |= RXMAC_CSUM_ENB;
2657 CSR_WRITE_4(sc, JME_RXMAC, reg);
2658
2659 /* Configure general purpose reg0 */
2660 reg = CSR_READ_4(sc, JME_GPREG0);
2661 reg &= ~GPREG0_PCC_UNIT_MASK;
2662 /* Set PCC timer resolution to micro-seconds unit. */
2663 reg |= GPREG0_PCC_UNIT_US;
2664 /*
2665 * Disable all shadow register posting as we have to read
2666 * JME_INTR_STATUS register in jme_intr. Also it seems
2667 * that it's hard to synchronize interrupt status between
2668 * hardware and software with shadow posting due to
2669 * requirements of bus_dmamap_sync(9).
2670 */
2671 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2672 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2673 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2674 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2675 /* Disable posting of DW0. */
2676 reg &= ~GPREG0_POST_DW0_ENB;
2677 /* Clear PME message. */
2678 reg &= ~GPREG0_PME_ENB;
2679 /* Set PHY address. */
2680 reg &= ~GPREG0_PHY_ADDR_MASK;
2681 reg |= sc->jme_phyaddr;
2682 CSR_WRITE_4(sc, JME_GPREG0, reg);
2683
2684 /* Configure Tx queue 0 packet completion coalescing. */
2870abc4 2685 jme_set_tx_coal(sc);
76fbb0b9 2686
dea2452a 2687 /* Configure Rx queues packet completion coalescing. */
2870abc4 2688 jme_set_rx_coal(sc);
76fbb0b9
SZ		 2689
2690 /* Configure shadow status block but don't enable posting. */
560616bf 2691 paddr = sc->jme_cdata.jme_ssb_block_paddr;
76fbb0b9
SZ		 2692 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2693 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2694
2695 /* Disable Timer 1 and Timer 2. */
2696 CSR_WRITE_4(sc, JME_TIMER1, 0);
2697 CSR_WRITE_4(sc, JME_TIMER2, 0);
2698
2699 /* Configure retry transmit period, retry limit value. */
2700 CSR_WRITE_4(sc, JME_TXTRHD,
2701 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2702 TXTRHD_RT_PERIOD_MASK) |
2703 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2704 TXTRHD_RT_LIMIT_SHIFT));
2705
9de40864
SZ		 2706#ifdef DEVICE_POLLING
2707 if (!(ifp->if_flags & IFF_POLLING))
2708#endif
76fbb0b9
SZ		 2709 /* Initialize the interrupt mask. */
2710 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2711 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2712
2713 /*
2714 * Enabling Tx/Rx DMA engines and Rx queue processing is
2715 * done after detection of valid link in jme_miibus_statchg.
2716 */
cccc3955 2717 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 2718
2719 /* Set the current media. */
2720 mii = device_get_softc(sc->jme_miibus);
2721 mii_mediachg(mii);
2722
2723 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2724
2725 ifp->if_flags |= IFF_RUNNING;
2726 ifp->if_flags &= ~IFF_OACTIVE;
2727}
2728
2729static void
2730jme_stop(struct jme_softc *sc)
2731{
2732 struct ifnet *ifp = &sc->arpcom.ac_if;
2733 struct jme_txdesc *txd;
2734 struct jme_rxdesc *rxd;
4447c752
SZ		 2735 struct jme_rxdata *rdata;
2736 int i, r;
76fbb0b9 2737
31f0d5a2 2738 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2739
2740 /*
2741 * Mark the interface down and cancel the watchdog timer.
2742 */
2743 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2744 ifp->if_timer = 0;
2745
2746 callout_stop(&sc->jme_tick_ch);
cccc3955 2747 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 2748
2749 /*
2750 * Disable interrupts.
2751 */
2752 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2753 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2754
2755 /* Disable updating shadow status block. */
2756 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2757 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2758
2759 /* Stop receiver, transmitter. */
2760 jme_stop_rx(sc);
2761 jme_stop_tx(sc);
2762
76fbb0b9
SZ		 2763 /*
2764 * Free partial finished RX segments
2765 */
7b040092 2766 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 2767 rdata = &sc->jme_cdata.jme_rx_data[r];
2768 if (rdata->jme_rxhead != NULL)
2769 m_freem(rdata->jme_rxhead);
dea2452a 2770 JME_RXCHAIN_RESET(rdata);
4447c752 2771 }
76fbb0b9
SZ		 2772
2773 /*
2774 * Free RX and TX mbufs still in the queues.
2775 */
7b040092 2776 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752 2777 rdata = &sc->jme_cdata.jme_rx_data[r];
7b040092 2778 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 2779 rxd = &rdata->jme_rxdesc[i];
2780 if (rxd->rx_m != NULL) {
2781 bus_dmamap_unload(rdata->jme_rx_tag,
2782 rxd->rx_dmamap);
2783 m_freem(rxd->rx_m);
2784 rxd->rx_m = NULL;
2785 }
76fbb0b9 2786 }
4447c752 2787 }
b020bb10 2788 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ		 2789 txd = &sc->jme_cdata.jme_txdesc[i];
2790 if (txd->tx_m != NULL) {
2791 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2792 txd->tx_dmamap);
2793 m_freem(txd->tx_m);
2794 txd->tx_m = NULL;
2795 txd->tx_ndesc = 0;
2796 }
2797 }
2798}
2799
2800static void
2801jme_stop_tx(struct jme_softc *sc)
2802{
2803 uint32_t reg;
2804 int i;
2805
2806 reg = CSR_READ_4(sc, JME_TXCSR);
2807 if ((reg & TXCSR_TX_ENB) == 0)
2808 return;
2809 reg &= ~TXCSR_TX_ENB;
2810 CSR_WRITE_4(sc, JME_TXCSR, reg);
2811 for (i = JME_TIMEOUT; i > 0; i--) {
2812 DELAY(1);
2813 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2814 break;
2815 }
2816 if (i == 0)
2817 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2818}
2819
2820static void
2821jme_stop_rx(struct jme_softc *sc)
2822{
2823 uint32_t reg;
2824 int i;
2825
2826 reg = CSR_READ_4(sc, JME_RXCSR);
2827 if ((reg & RXCSR_RX_ENB) == 0)
2828 return;
2829 reg &= ~RXCSR_RX_ENB;
2830 CSR_WRITE_4(sc, JME_RXCSR, reg);
2831 for (i = JME_TIMEOUT; i > 0; i--) {
2832 DELAY(1);
2833 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2834 break;
2835 }
2836 if (i == 0)
2837 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2838}
2839
2840static void
2841jme_init_tx_ring(struct jme_softc *sc)
2842{
560616bf 2843 struct jme_chain_data *cd;
76fbb0b9
SZ		 2844 struct jme_txdesc *txd;
2845 int i;
2846
2847 sc->jme_cdata.jme_tx_prod = 0;
2848 sc->jme_cdata.jme_tx_cons = 0;
2849 sc->jme_cdata.jme_tx_cnt = 0;
2850
560616bf
SZ		 2851 cd = &sc->jme_cdata;
2852 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
b020bb10 2853 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ		 2854 txd = &sc->jme_cdata.jme_txdesc[i];
2855 txd->tx_m = NULL;
560616bf 2856 txd->tx_desc = &cd->jme_tx_ring[i];
76fbb0b9
SZ		 2857 txd->tx_ndesc = 0;
2858 }
76fbb0b9
SZ		 2859}
2860
2861static void
2862jme_init_ssb(struct jme_softc *sc)
2863{
560616bf 2864 struct jme_chain_data *cd;
76fbb0b9 2865
560616bf
SZ		 2866 cd = &sc->jme_cdata;
2867 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
76fbb0b9
SZ		 2868}
2869
2870static int
dea2452a 2871jme_init_rx_ring(struct jme_rxdata *rdata)
76fbb0b9 2872{
76fbb0b9
SZ		 2873 struct jme_rxdesc *rxd;
2874 int i;
2875
4447c752
SZ		 2876 KKASSERT(rdata->jme_rxhead == NULL &&
2877 rdata->jme_rxtail == NULL &&
2878 rdata->jme_rxlen == 0);
2879 rdata->jme_rx_cons = 0;
76fbb0b9 2880
7b040092
SZ		 2881 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2882 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
76fbb0b9
SZ		 2883 int error;
2884
4447c752 2885 rxd = &rdata->jme_rxdesc[i];
76fbb0b9 2886 rxd->rx_m = NULL;
4447c752 2887 rxd->rx_desc = &rdata->jme_rx_ring[i];
dea2452a 2888 error = jme_newbuf(rdata, rxd, 1);
76fbb0b9 2889 if (error)
4447c752 2890 return error;
76fbb0b9 2891 }
4447c752 2892 return 0;
76fbb0b9
SZ		 2893}
2894
2895static int
dea2452a 2896jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
76fbb0b9 2897{
76fbb0b9 2898 struct mbuf *m;
76fbb0b9
SZ		 2899 bus_dma_segment_t segs;
2900 bus_dmamap_t map;
b0ba1747 2901 int error, nsegs;
76fbb0b9
SZ		 2902
2903 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2904 if (m == NULL)
4447c752 2905 return ENOBUFS;
76fbb0b9
SZ		 2906 /*
2907 * JMC250 has 64bit boundary alignment limitation so jme(4)
2908 * takes advantage of 10 bytes padding feature of hardware
2909 * in order not to copy entire frame to align IP header on
2910 * 32bit boundary.
2911 */
2912 m->m_len = m->m_pkthdr.len = MCLBYTES;
2913
b0ba1747
SZ		 2914 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2915 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2916 BUS_DMA_NOWAIT);
2917 if (error) {
76fbb0b9 2918 m_freem(m);
dea2452a
SZ		 2919 if (init) {
2920 if_printf(&rdata->jme_sc->arpcom.ac_if,
2921 "can't load RX mbuf\n");
2922 }
4447c752 2923 return error;
76fbb0b9
SZ		 2924 }
2925
2926 if (rxd->rx_m != NULL) {
4447c752 2927 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
76fbb0b9 2928 BUS_DMASYNC_POSTREAD);
4447c752 2929 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
76fbb0b9
SZ		 2930 }
2931 map = rxd->rx_dmamap;
4447c752
SZ		 2932 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2933 rdata->jme_rx_sparemap = map;
76fbb0b9 2934 rxd->rx_m = m;
fd2a6d2c 2935 rxd->rx_paddr = segs.ds_addr;
76fbb0b9 2936
fd2a6d2c 2937 jme_setup_rxdesc(rxd);
4447c752 2938 return 0;
76fbb0b9
SZ		 2939}
2940
2941static void
2942jme_set_vlan(struct jme_softc *sc)
2943{
2944 struct ifnet *ifp = &sc->arpcom.ac_if;
2945 uint32_t reg;
2946
31f0d5a2 2947 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2948
2949 reg = CSR_READ_4(sc, JME_RXMAC);
2950 reg &= ~RXMAC_VLAN_ENB;
2951 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2952 reg |= RXMAC_VLAN_ENB;
2953 CSR_WRITE_4(sc, JME_RXMAC, reg);
2954}
2955
2956static void
2957jme_set_filter(struct jme_softc *sc)
2958{
2959 struct ifnet *ifp = &sc->arpcom.ac_if;
2960 struct ifmultiaddr *ifma;
2961 uint32_t crc;
2962 uint32_t mchash[2];
2963 uint32_t rxcfg;
2964
31f0d5a2 2965 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2966
2967 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2968 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2969 RXMAC_ALLMULTI);
2970
2971 /*
2972 * Always accept frames destined to our station address.
2973 * Always accept broadcast frames.
2974 */
2975 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2976
2977 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2978 if (ifp->if_flags & IFF_PROMISC)
2979 rxcfg |= RXMAC_PROMISC;
2980 if (ifp->if_flags & IFF_ALLMULTI)
2981 rxcfg |= RXMAC_ALLMULTI;
2982 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2983 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2984 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2985 return;
2986 }
2987
2988 /*
2989 * Set up the multicast address filter by passing all multicast
2990 * addresses through a CRC generator, and then using the low-order
2991 * 6 bits as an index into the 64 bit multicast hash table. The
2992 * high order bits select the register, while the rest of the bits
2993 * select the bit within the register.
2994 */
2995 rxcfg |= RXMAC_MULTICAST;
2996 bzero(mchash, sizeof(mchash));
2997
441d34b2 2998 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
76fbb0b9
SZ		 2999 if (ifma->ifma_addr->sa_family != AF_LINK)
3000 continue;
3001 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3002 ifma->ifma_addr), ETHER_ADDR_LEN);
3003
3004 /* Just want the 6 least significant bits. */
3005 crc &= 0x3f;
3006
3007 /* Set the corresponding bit in the hash table. */
3008 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3009 }
3010
3011 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3012 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3013 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3014}
3015
3016static int
2870abc4 3017jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3018{
2870abc4
SZ		 3019 struct jme_softc *sc = arg1;
3020 struct ifnet *ifp = &sc->arpcom.ac_if;
3021 int error, v;
3022
31f0d5a2 3023 ifnet_serialize_all(ifp);
2870abc4
SZ		 3024
3025 v = sc->jme_tx_coal_to;
3026 error = sysctl_handle_int(oidp, &v, 0, req);
3027 if (error || req->newptr == NULL)
3028 goto back;
3029
3030 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3031 error = EINVAL;
3032 goto back;
3033 }
3034
3035 if (v != sc->jme_tx_coal_to) {
3036 sc->jme_tx_coal_to = v;
3037 if (ifp->if_flags & IFF_RUNNING)
3038 jme_set_tx_coal(sc);
3039 }
3040back:
31f0d5a2 3041 ifnet_deserialize_all(ifp);
2870abc4 3042 return error;
76fbb0b9
SZ		 3043}
3044
3045static int
2870abc4 3046jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
76fbb0b9 3047{
2870abc4
SZ		 3048 struct jme_softc *sc = arg1;
3049 struct ifnet *ifp = &sc->arpcom.ac_if;
3050 int error, v;
3051
31f0d5a2 3052 ifnet_serialize_all(ifp);
2870abc4
SZ		 3053
3054 v = sc->jme_tx_coal_pkt;
3055 error = sysctl_handle_int(oidp, &v, 0, req);
3056 if (error || req->newptr == NULL)
3057 goto back;
3058
3059 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3060 error = EINVAL;
3061 goto back;
3062 }
3063
3064 if (v != sc->jme_tx_coal_pkt) {
3065 sc->jme_tx_coal_pkt = v;
3066 if (ifp->if_flags & IFF_RUNNING)
3067 jme_set_tx_coal(sc);
3068 }
3069back:
31f0d5a2 3070 ifnet_deserialize_all(ifp);
2870abc4 3071 return error;
76fbb0b9
SZ		 3072}
3073
3074static int
2870abc4 3075jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3076{
2870abc4
SZ		 3077 struct jme_softc *sc = arg1;
3078 struct ifnet *ifp = &sc->arpcom.ac_if;
3079 int error, v;
3080
31f0d5a2 3081 ifnet_serialize_all(ifp);
2870abc4
SZ		 3082
3083 v = sc->jme_rx_coal_to;
3084 error = sysctl_handle_int(oidp, &v, 0, req);
3085 if (error || req->newptr == NULL)
3086 goto back;
3087
3088 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3089 error = EINVAL;
3090 goto back;
3091 }
3092
3093 if (v != sc->jme_rx_coal_to) {
3094 sc->jme_rx_coal_to = v;
3095 if (ifp->if_flags & IFF_RUNNING)
3096 jme_set_rx_coal(sc);
3097 }
3098back:
31f0d5a2 3099 ifnet_deserialize_all(ifp);
2870abc4 3100 return error;
76fbb0b9
SZ		 3101}
3102
3103static int
2870abc4
SZ		 3104jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3105{
3106 struct jme_softc *sc = arg1;
3107 struct ifnet *ifp = &sc->arpcom.ac_if;
3108 int error, v;
3109
31f0d5a2 3110 ifnet_serialize_all(ifp);
2870abc4
SZ		 3111
3112 v = sc->jme_rx_coal_pkt;
3113 error = sysctl_handle_int(oidp, &v, 0, req);
3114 if (error || req->newptr == NULL)
3115 goto back;
3116
3117 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3118 error = EINVAL;
3119 goto back;
3120 }
3121
3122 if (v != sc->jme_rx_coal_pkt) {
3123 sc->jme_rx_coal_pkt = v;
3124 if (ifp->if_flags & IFF_RUNNING)
3125 jme_set_rx_coal(sc);
3126 }
3127back:
31f0d5a2 3128 ifnet_deserialize_all(ifp);
2870abc4
SZ		 3129 return error;
3130}
3131
3132static void
3133jme_set_tx_coal(struct jme_softc *sc)
3134{
3135 uint32_t reg;
3136
3137 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3138 PCCTX_COAL_TO_MASK;
3139 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3140 PCCTX_COAL_PKT_MASK;
3141 reg |= PCCTX_COAL_TXQ0;
3142 CSR_WRITE_4(sc, JME_PCCTX, reg);
3143}
3144
3145static void
3146jme_set_rx_coal(struct jme_softc *sc)
76fbb0b9 3147{
2870abc4 3148 uint32_t reg;
4447c752 3149 int r;
2870abc4
SZ		 3150
3151 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3152 PCCRX_COAL_TO_MASK;
3153 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3154 PCCRX_COAL_PKT_MASK;
7b040092 3155 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
9f20b7b3 3156 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
76fbb0b9 3157}
9de40864
SZ		 3158
3159#ifdef DEVICE_POLLING
3160
3161static void
3162jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3163{
3164 struct jme_softc *sc = ifp->if_softc;
3165 uint32_t status;
eda7db08 3166 int r;
9de40864 3167
31f0d5a2 3168 ASSERT_SERIALIZED(&sc->jme_serialize);
9de40864
SZ		 3169
3170 switch (cmd) {
3171 case POLL_REGISTER:
3172 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3173 break;
3174
3175 case POLL_DEREGISTER:
3176 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3177 break;
3178
3179 case POLL_AND_CHECK_STATUS:
3180 case POLL_ONLY:
3181 status = CSR_READ_4(sc, JME_INTR_STATUS);
0e7f1e6f 3182
7b040092 3183 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31f0d5a2
SZ		 3184 struct jme_rxdata *rdata =
3185 &sc->jme_cdata.jme_rx_data[r];
3186
3187 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3188 jme_rxeof(rdata, count);
31f0d5a2
SZ		 3189 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3190 }
9de40864
SZ		 3191
3192 if (status & INTR_RXQ_DESC_EMPTY) {
3193 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3194 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3195 RXCSR_RX_ENB | RXCSR_RXQ_START);
3196 }
3197
31f0d5a2 3198 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ		 3199 jme_txeof(sc);
3200 if (!ifq_is_empty(&ifp->if_snd))
3201 if_devstart(ifp);
31f0d5a2 3202 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ		 3203 break;
3204 }
3205}
3206
3207#endif /* DEVICE_POLLING */
4447c752
SZ		 3208
3209static int
dea2452a 3210jme_rxring_dma_alloc(struct jme_rxdata *rdata)
4447c752 3211{
1128a202 3212 bus_dmamem_t dmem;
ff7f3632 3213 int error, asize;
4447c752 3214
ff7f3632 3215 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
dea2452a 3216 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
1128a202 3217 JME_RX_RING_ALIGN, 0,
0eb220ec 3218 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 3219 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4447c752 3220 if (error) {
dea2452a
SZ		 3221 device_printf(rdata->jme_sc->jme_dev,
3222 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
4447c752
SZ		 3223 return error;
3224 }
1128a202
SZ		 3225 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3226 rdata->jme_rx_ring_map = dmem.dmem_map;
3227 rdata->jme_rx_ring = dmem.dmem_addr;
3228 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
4447c752
SZ		 3229
3230 return 0;
3231}
3232
3233static int
064b75ed
SZ		 3234jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3235{
3236 if ((paddr & 0xffffffff) == 0) {
3237 /*
3238 * Don't allow lower 32bits of the RX buffer's
3239 * physical address to be 0, else it will break
3240 * hardware pending RSS information delivery
3241 * detection on RX path.
3242 */
3243 return 1;
3244 }
3245 return 0;
3246}
3247
3248static int
dea2452a 3249jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
4447c752 3250{
064b75ed 3251 bus_addr_t lowaddr;
4447c752
SZ		 3252 int i, error;
3253
064b75ed
SZ		 3254 lowaddr = BUS_SPACE_MAXADDR;
3255 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3256 /* jme_rxbuf_dma_filter will be called */
3257 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3258 }
3259
4447c752 3260 /* Create tag for Rx buffers. */
dea2452a
SZ		 3261 error = bus_dma_tag_create(
3262 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
4447c752 3263 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
064b75ed 3264 lowaddr, /* lowaddr */
4447c752 3265 BUS_SPACE_MAXADDR, /* highaddr */
064b75ed 3266 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
4447c752
SZ		 3267 MCLBYTES, /* maxsize */
3268 1, /* nsegments */
3269 MCLBYTES, /* maxsegsize */
9d424cee 3270 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
4447c752
SZ		 3271 &rdata->jme_rx_tag);
3272 if (error) {
dea2452a
SZ		 3273 device_printf(rdata->jme_sc->jme_dev,
3274 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
4447c752
SZ		 3275 return error;
3276 }
3277
3278 /* Create DMA maps for Rx buffers. */
9d424cee 3279 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ		 3280 &rdata->jme_rx_sparemap);
3281 if (error) {
dea2452a
SZ		 3282 device_printf(rdata->jme_sc->jme_dev,
3283 "could not create %dth spare Rx dmamap.\n",
3284 rdata->jme_rx_idx);
4447c752
SZ		 3285 bus_dma_tag_destroy(rdata->jme_rx_tag);
3286 rdata->jme_rx_tag = NULL;
3287 return error;
3288 }
7b040092 3289 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 3290 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3291
9d424cee 3292 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ		 3293 &rxd->rx_dmamap);
3294 if (error) {
3295 int j;
3296
dea2452a 3297 device_printf(rdata->jme_sc->jme_dev,
4447c752 3298 "could not create %dth Rx dmamap "
dea2452a 3299 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
4447c752
SZ		 3300
3301 for (j = 0; j < i; ++j) {
3302 rxd = &rdata->jme_rxdesc[j];
3303 bus_dmamap_destroy(rdata->jme_rx_tag,
3304 rxd->rx_dmamap);
3305 }
3306 bus_dmamap_destroy(rdata->jme_rx_tag,
3307 rdata->jme_rx_sparemap);
3308 bus_dma_tag_destroy(rdata->jme_rx_tag);
3309 rdata->jme_rx_tag = NULL;
3310 return error;
3311 }
3312 }
3313 return 0;
3314}
3315
3316static void
3317jme_rx_intr(struct jme_softc *sc, uint32_t status)
3318{
eda7db08 3319 int r;
4447c752 3320
7b040092 3321 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31810fb8 3322 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
31f0d5a2 3323
31810fb8 3324 if (status & rdata->jme_rx_coal) {
31f0d5a2 3325 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3326 jme_rxeof(rdata, -1);
31f0d5a2
SZ		 3327 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3328 }
4447c752
SZ		 3329 }
3330}
760c056c
SZ		 3331
3332static void
3333jme_enable_rss(struct jme_softc *sc)
3334{
24dd1705
SZ		 3335 uint32_t rssc, ind;
3336 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
760c056c
SZ		 3337 int i;
3338
022f915e
SZ		 3339 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3340 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
ed20d0e3 3341 ("%s: invalid # of RX rings (%d)",
022f915e 3342 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
66f75939 3343
760c056c
SZ		 3344 rssc = RSSC_HASH_64_ENTRY;
3345 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
7b040092 3346 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
760c056c
SZ		 3347 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3348 CSR_WRITE_4(sc, JME_RSSC, rssc);
3349
24dd1705
SZ		 3350 toeplitz_get_key(key, sizeof(key));
3351 for (i = 0; i < RSSKEY_NREGS; ++i) {
3352 uint32_t keyreg;
3353
3354 keyreg = RSSKEY_REGVAL(key, i);
3355 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3356
3357 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3358 }
760c056c 3359
66f75939
SZ		 3360 /*
3361 * Create redirect table in following fashion:
3362 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3363 */
760c056c 3364 ind = 0;
66f75939
SZ		 3365 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3366 int q;
3367
7b040092 3368 q = i % sc->jme_cdata.jme_rx_ring_cnt;
66f75939 3369 ind |= q << (i * 8);
760c056c
SZ		 3370 }
3371 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
66f75939 3372
760c056c
SZ		 3373 for (i = 0; i < RSSTBL_NREGS; ++i)
3374 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3375}
3376
3377static void
3378jme_disable_rss(struct jme_softc *sc)
3379{
760c056c
SZ		 3380 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3381}
31f0d5a2
SZ		 3382
3383static void
3384jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3385{
3386 struct jme_softc *sc = ifp->if_softc;
3387
29890f78
SZ		 3388 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3389 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ		 3390}
3391
3392static void
3393jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3394{
3395 struct jme_softc *sc = ifp->if_softc;
3396
29890f78
SZ		 3397 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3398 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ		 3399}
3400
3401static int
3402jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3403{
3404 struct jme_softc *sc = ifp->if_softc;
3405
29890f78
SZ		 3406 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3407 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ		 3408}
3409
3410#ifdef INVARIANTS
3411
3412static void
3413jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3414 boolean_t serialized)
3415{
3416 struct jme_softc *sc = ifp->if_softc;
31f0d5a2 3417
29890f78
SZ		 3418 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3419 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3420 slz, serialized);
31f0d5a2
SZ		 3421}
3422
3423#endif /* INVARIANTS */
58880b0d
SZ		 3424
3425static void
3426jme_msix_try_alloc(device_t dev)
3427{
3428 struct jme_softc *sc = device_get_softc(dev);
3429 struct jme_msix_data *msix;
3430 int error, i, r, msix_enable, msix_count;
58880b0d 3431
7b040092 3432 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
58880b0d
SZ		 3433 KKASSERT(msix_count <= JME_NMSIX);
3434
1cc217a9 3435 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
58880b0d
SZ		 3436
3437 /*
3438 * We leave the 1st MSI-X vector unused, so we
3439 * actually need msix_count + 1 MSI-X vectors.
3440 */
3441 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3442 return;
3443
3444 for (i = 0; i < msix_count; ++i)
3445 sc->jme_msix[i].jme_msix_rid = -1;
3446
3447 i = 0;
3448
3449 msix = &sc->jme_msix[i++];
3450 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3451 msix->jme_msix_arg = &sc->jme_cdata;
3452 msix->jme_msix_func = jme_msix_tx;
3453 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3454 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3455 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3456 device_get_nameunit(dev));
3457
7b040092 3458 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
58880b0d
SZ		 3459 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3460
3461 msix = &sc->jme_msix[i++];
3462 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3463 msix->jme_msix_arg = rdata;
3464 msix->jme_msix_func = jme_msix_rx;
3465 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3466 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3467 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3468 "%s rx%d", device_get_nameunit(dev), r);
3469 }
3470
3471 KKASSERT(i == msix_count);
3472
3473 error = pci_setup_msix(dev);
3474 if (error)
3475 return;
3476
3477 /* Setup jme_msix_cnt early, so we could cleanup */
3478 sc->jme_msix_cnt = msix_count;
3479
3480 for (i = 0; i < msix_count; ++i) {
3481 msix = &sc->jme_msix[i];
3482
3483 msix->jme_msix_vector = i + 1;
3484 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3485 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3486 if (error)
3487 goto back;
3488
3489 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3490 &msix->jme_msix_rid, RF_ACTIVE);
3491 if (msix->jme_msix_res == NULL) {
3492 error = ENOMEM;
3493 goto back;
3494 }
3495 }
3496
3497 for (i = 0; i < JME_INTR_CNT; ++i) {
3498 uint32_t intr_mask = (1 << i);
3499 int x;
3500
3501 if ((JME_INTRS & intr_mask) == 0)
3502 continue;
3503
3504 for (x = 0; x < msix_count; ++x) {
3505 msix = &sc->jme_msix[x];
3506 if (msix->jme_msix_intrs & intr_mask) {
3507 int reg, shift;
3508
3509 reg = i / JME_MSINUM_FACTOR;
3510 KKASSERT(reg < JME_MSINUM_CNT);
3511
3512 shift = (i % JME_MSINUM_FACTOR) * 4;
3513
3514 sc->jme_msinum[reg] |=
3515 (msix->jme_msix_vector << shift);
3516
3517 break;
3518 }
3519 }
3520 }
3521
3522 if (bootverbose) {
3523 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3524 device_printf(dev, "MSINUM%d: %#x\n", i,
3525 sc->jme_msinum[i]);
3526 }
3527 }
3528
3529 pci_enable_msix(dev);
3530 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3531
3532back:
3533 if (error)
3534 jme_msix_free(dev);
3535}
3536
3537static int
3538jme_intr_alloc(device_t dev)
3539{
3540 struct jme_softc *sc = device_get_softc(dev);
3541 u_int irq_flags;
3542
3543 jme_msix_try_alloc(dev);
3544
3545 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3546 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3547 &sc->jme_irq_rid, &irq_flags);
3548
3549 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3550 &sc->jme_irq_rid, irq_flags);
3551 if (sc->jme_irq_res == NULL) {
3552 device_printf(dev, "can't allocate irq\n");
3553 return ENXIO;
3554 }
3555 }
3556 return 0;
3557}
3558
3559static void
3560jme_msix_free(device_t dev)
3561{
3562 struct jme_softc *sc = device_get_softc(dev);
3563 int i;
3564
3565 KKASSERT(sc->jme_msix_cnt > 1);
3566
3567 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3568 struct jme_msix_data *msix = &sc->jme_msix[i];
3569
3570 if (msix->jme_msix_res != NULL) {
3571 bus_release_resource(dev, SYS_RES_IRQ,
3572 msix->jme_msix_rid, msix->jme_msix_res);
3573 msix->jme_msix_res = NULL;
3574 }
3575 if (msix->jme_msix_rid >= 0) {
3576 pci_release_msix_vector(dev, msix->jme_msix_rid);
3577 msix->jme_msix_rid = -1;
3578 }
3579 }
3580 pci_teardown_msix(dev);
3581}
3582
3583static void
3584jme_intr_free(device_t dev)
3585{
3586 struct jme_softc *sc = device_get_softc(dev);
3587
3588 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3589 if (sc->jme_irq_res != NULL) {
3590 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3591 sc->jme_irq_res);
3592 }
3593 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3594 pci_release_msi(dev);
3595 } else {
3596 jme_msix_free(dev);
3597 }
3598}
3599
3600static void
3601jme_msix_tx(void *xcd)