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igb: Define macros for wreg_nsegs, instead of using magic number
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
CommitLineData
1f7e3916
SZ		 1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
d0f59cad 32#include "opt_ifpoll.h"
8d6600da 33#include "opt_igb.h"
1f7e3916
SZ		 34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/interrupt.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/serialize2.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <sys/sysctl.h>
49#include <sys/systm.h>
50
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/ifq_var.h>
58#include <net/toeplitz.h>
59#include <net/toeplitz2.h>
60#include <net/vlan/if_vlan_var.h>
61#include <net/vlan/if_vlan_ether.h>
62#include <net/if_poll.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <bus/pci/pcivar.h>
71#include <bus/pci/pcireg.h>
72
73#include <dev/netif/ig_hal/e1000_api.h>
74#include <dev/netif/ig_hal/e1000_82575.h>
75#include <dev/netif/igb/if_igb.h>
76
8d6600da
SZ		 77#ifdef IGB_RSS_DEBUG
78#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79do { \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82} while (0)
83#else /* !IGB_RSS_DEBUG */
84#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85#endif /* IGB_RSS_DEBUG */
86
1f7e3916
SZ		 87#define IGB_NAME "Intel(R) PRO/1000 "
88#define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90#define IGB_DEVICE_NULL { 0, 0, NULL }
91
92static struct igb_device {
93 uint16_t vid;
94 uint16_t did;
95 const char *desc;
96} igb_devices[] = {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
123 IGB_DEVICE(I350_VF),
124
125 /* required last entry */
126 IGB_DEVICE_NULL
127};
128
129static int igb_probe(device_t);
130static int igb_attach(device_t);
131static int igb_detach(device_t);
132static int igb_shutdown(device_t);
133static int igb_suspend(device_t);
134static int igb_resume(device_t);
135
136static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137static void igb_setup_ifp(struct igb_softc *);
48faa653 138static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
23f6ffe4
SZ		 139static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
1f7e3916
SZ		 141static void igb_add_sysctl(struct igb_softc *);
142static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
9c0ecdcc 143static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
b6220144 144static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
708575bb 145static int igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
9d8e892a 146static int igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
9c0ecdcc 147static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
4b21dd0f 148static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
d802cc67 149static int igb_get_txring_inuse(const struct igb_softc *, boolean_t);
d0f59cad
SZ		 150#ifdef IFPOLL_ENABLE
151static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
152static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
153#endif
1f7e3916
SZ		 154
155static void igb_vf_init_stats(struct igb_softc *);
156static void igb_reset(struct igb_softc *);
157static void igb_update_stats_counters(struct igb_softc *);
158static void igb_update_vf_stats_counters(struct igb_softc *);
159static void igb_update_link_status(struct igb_softc *);
160static void igb_init_tx_unit(struct igb_softc *);
161static void igb_init_rx_unit(struct igb_softc *);
162
163static void igb_set_vlan(struct igb_softc *);
164static void igb_set_multi(struct igb_softc *);
165static void igb_set_promisc(struct igb_softc *);
166static void igb_disable_promisc(struct igb_softc *);
167
a619b256
SZ		 168static int igb_alloc_rings(struct igb_softc *);
169static void igb_free_rings(struct igb_softc *);
1f7e3916
SZ		 170static int igb_create_tx_ring(struct igb_tx_ring *);
171static int igb_create_rx_ring(struct igb_rx_ring *);
172static void igb_free_tx_ring(struct igb_tx_ring *);
173static void igb_free_rx_ring(struct igb_rx_ring *);
174static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
175static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
176static void igb_init_tx_ring(struct igb_tx_ring *);
177static int igb_init_rx_ring(struct igb_rx_ring *);
178static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
871c0e2b 179static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
b56e8196 180static void igb_rx_refresh(struct igb_rx_ring *, int);
1f7e3916
SZ		 181
182static void igb_stop(struct igb_softc *);
183static void igb_init(void *);
184static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
185static void igb_media_status(struct ifnet *, struct ifmediareq *);
186static int igb_media_change(struct ifnet *);
187static void igb_timer(void *);
16109efc 188static void igb_watchdog(struct ifaltq_subque *);
f0a26983 189static void igb_start(struct ifnet *, struct ifaltq_subque *);
d0f59cad
SZ		 190#ifdef IFPOLL_ENABLE
191static void igb_npoll(struct ifnet *, struct ifpoll_info *);
192static void igb_npoll_rx(struct ifnet *, void *, int);
193static void igb_npoll_tx(struct ifnet *, void *, int);
2f00683b 194static void igb_npoll_status(struct ifnet *);
1f7e3916 195#endif
7d235eb5
SZ		 196static void igb_serialize(struct ifnet *, enum ifnet_serialize);
197static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
198static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
199#ifdef INVARIANTS
200static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
201 boolean_t);
202#endif
1f7e3916
SZ		 203
204static void igb_intr(void *);
9c0ecdcc 205static void igb_intr_shared(void *);
1f7e3916
SZ		 206static void igb_rxeof(struct igb_rx_ring *, int);
207static void igb_txeof(struct igb_tx_ring *);
9c0ecdcc 208static void igb_set_eitr(struct igb_softc *, int, int);
1f7e3916
SZ		 209static void igb_enable_intr(struct igb_softc *);
210static void igb_disable_intr(struct igb_softc *);
f6167a56
SZ		 211static void igb_init_unshared_intr(struct igb_softc *);
212static void igb_init_intr(struct igb_softc *);
213static int igb_setup_intr(struct igb_softc *);
9c0ecdcc
SZ		 214static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
215static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
be922da6 216static void igb_set_intr_mask(struct igb_softc *);
3c7cc5e2
SZ		 217static int igb_alloc_intr(struct igb_softc *);
218static void igb_free_intr(struct igb_softc *);
9c0ecdcc
SZ		 219static void igb_teardown_intr(struct igb_softc *);
220static void igb_msix_try_alloc(struct igb_softc *);
221static void igb_msix_free(struct igb_softc *, boolean_t);
222static int igb_msix_setup(struct igb_softc *);
223static void igb_msix_teardown(struct igb_softc *, int);
224static void igb_msix_rx(void *);
225static void igb_msix_tx(void *);
226static void igb_msix_status(void *);
1f7e3916
SZ		 227
228/* Management and WOL Support */
229static void igb_get_mgmt(struct igb_softc *);
230static void igb_rel_mgmt(struct igb_softc *);
231static void igb_get_hw_control(struct igb_softc *);
73a4e8ed
SZ		 232static void igb_rel_hw_control(struct igb_softc *);
233static void igb_enable_wol(device_t);
1f7e3916
SZ		 234
235static device_method_t igb_methods[] = {
236 /* Device interface */
237 DEVMETHOD(device_probe, igb_probe),
238 DEVMETHOD(device_attach, igb_attach),
239 DEVMETHOD(device_detach, igb_detach),
240 DEVMETHOD(device_shutdown, igb_shutdown),
241 DEVMETHOD(device_suspend, igb_suspend),
242 DEVMETHOD(device_resume, igb_resume),
243 { 0, 0 }
244};
245
246static driver_t igb_driver = {
247 "igb",
248 igb_methods,
249 sizeof(struct igb_softc),
250};
251
252static devclass_t igb_devclass;
253
254DECLARE_DUMMY_MODULE(if_igb);
255MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
256DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
257
258static int igb_rxd = IGB_DEFAULT_RXD;
259static int igb_txd = IGB_DEFAULT_TXD;
8d6600da 260static int igb_rxr = 0;
d802cc67 261static int igb_txr = 0;
1f7e3916
SZ		 262static int igb_msi_enable = 1;
263static int igb_msix_enable = 1;
264static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
265static int igb_fc_setting = e1000_fc_full;
266
267/*
268 * DMA Coalescing, only for i350 - default to off,
269 * this feature is for power savings
270 */
271static int igb_dma_coalesce = 0;
272
273TUNABLE_INT("hw.igb.rxd", &igb_rxd);
274TUNABLE_INT("hw.igb.txd", &igb_txd);
8d6600da 275TUNABLE_INT("hw.igb.rxr", &igb_rxr);
d802cc67 276TUNABLE_INT("hw.igb.txr", &igb_txr);
1f7e3916
SZ		 277TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
278TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
279TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
280
281/* i350 specific */
282TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
283TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
284
285static __inline void
286igb_rxcsum(uint32_t staterr, struct mbuf *mp)
287{
288 /* Ignore Checksum bit is set */
289 if (staterr & E1000_RXD_STAT_IXSM)
290 return;
291
292 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
293 E1000_RXD_STAT_IPCS)
294 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
295
296 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
297 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
298 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
299 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
300 mp->m_pkthdr.csum_data = htons(0xffff);
301 }
302 }
303}
304
8d6600da
SZ		 305static __inline struct pktinfo *
306igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
307 uint32_t hash, uint32_t hashtype, uint32_t staterr)
308{
309 switch (hashtype) {
310 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
311 pi->pi_netisr = NETISR_IP;
312 pi->pi_flags = 0;
313 pi->pi_l3proto = IPPROTO_TCP;
314 break;
315
316 case E1000_RXDADV_RSSTYPE_IPV4:
317 if (staterr & E1000_RXD_STAT_IXSM)
318 return NULL;
319
320 if ((staterr &
321 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
322 E1000_RXD_STAT_TCPCS) {
323 pi->pi_netisr = NETISR_IP;
324 pi->pi_flags = 0;
325 pi->pi_l3proto = IPPROTO_UDP;
326 break;
327 }
328 /* FALL THROUGH */
329 default:
330 return NULL;
331 }
332
333 m->m_flags |= M_HASH;
334 m->m_pkthdr.hash = toeplitz_hash(hash);
335 return pi;
336}
337
1f7e3916
SZ		 338static int
339igb_probe(device_t dev)
340{
341 const struct igb_device *d;
342 uint16_t vid, did;
343
344 vid = pci_get_vendor(dev);
345 did = pci_get_device(dev);
346
347 for (d = igb_devices; d->desc != NULL; ++d) {
348 if (vid == d->vid && did == d->did) {
349 device_set_desc(dev, d->desc);
350 return 0;
351 }
352 }
353 return ENXIO;
354}
355
356static int
357igb_attach(device_t dev)
358{
359 struct igb_softc *sc = device_get_softc(dev);
1f7e3916 360 uint16_t eeprom_data;
8d6600da 361 int error = 0, i, j, ring_max;
d0f59cad
SZ		 362#ifdef IFPOLL_ENABLE
363 int offset, offset_def;
364#endif
1f7e3916
SZ		 365
366#ifdef notyet
367 /* SYSCTL stuff */
368 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
369 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
370 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
371 igb_sysctl_nvm_info, "I", "NVM Information");
1f7e3916
SZ		 372 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
373 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
374 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
375 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
376#endif
377
378 callout_init_mp(&sc->timer);
9c0ecdcc 379 lwkt_serialize_init(&sc->main_serialize);
1f7e3916 380
62be5890
SZ		 381 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
382 device_get_unit(dev));
1f7e3916
SZ		 383 sc->dev = sc->osdep.dev = dev;
384
385 /*
386 * Determine hardware and mac type
387 */
388 sc->hw.vendor_id = pci_get_vendor(dev);
389 sc->hw.device_id = pci_get_device(dev);
390 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
391 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
392 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
393
394 if (e1000_set_mac_type(&sc->hw))
395 return ENXIO;
396
397 /* Are we a VF device? */
398 if (sc->hw.mac.type == e1000_vfadapt ||
399 sc->hw.mac.type == e1000_vfadapt_i350)
400 sc->vf_ifp = 1;
401 else
402 sc->vf_ifp = 0;
403
9b7aa975
SZ		 404 /*
405 * Configure total supported RX/TX ring count
406 */
407 switch (sc->hw.mac.type) {
408 case e1000_82575:
409 ring_max = IGB_MAX_RING_82575;
410 break;
411 case e1000_82580:
412 ring_max = IGB_MAX_RING_82580;
413 break;
414 case e1000_i350:
415 ring_max = IGB_MAX_RING_I350;
416 break;
417 case e1000_82576:
418 ring_max = IGB_MAX_RING_82576;
419 break;
420 default:
421 ring_max = IGB_MIN_RING;
422 break;
423 }
d802cc67 424
9b7aa975
SZ		 425 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
426 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
427#ifdef IGB_RSS_DEBUG
428 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
429#endif
430 sc->rx_ring_inuse = sc->rx_ring_cnt;
d802cc67
SZ		 431
432 sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
433 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
434#ifdef IGB_TSS_DEBUG
435 sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
436#endif
437 sc->tx_ring_inuse = sc->tx_ring_cnt;
9b7aa975 438
23f6ffe4
SZ		 439 if (sc->hw.mac.type == e1000_82575)
440 sc->flags |= IGB_FLAG_TSO_IPLEN0;
441
1f7e3916
SZ		 442 /* Enable bus mastering */
443 pci_enable_busmaster(dev);
444
445 /*
446 * Allocate IO memory
447 */
448 sc->mem_rid = PCIR_BAR(0);
449 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
450 RF_ACTIVE);
451 if (sc->mem_res == NULL) {
452 device_printf(dev, "Unable to allocate bus resource: memory\n");
453 error = ENXIO;
454 goto failed;
455 }
456 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
457 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
458
459 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
460
1f7e3916
SZ		 461 /* Save PCI command register for Shared Code */
462 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
463 sc->hw.back = &sc->osdep;
464
1f7e3916
SZ		 465 /* Do Shared Code initialization */
466 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
467 device_printf(dev, "Setup of Shared code failed\n");
468 error = ENXIO;
469 goto failed;
470 }
471
472 e1000_get_bus_info(&sc->hw);
473
474 sc->hw.mac.autoneg = DO_AUTO_NEG;
475 sc->hw.phy.autoneg_wait_to_complete = FALSE;
476 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
477
478 /* Copper options */
479 if (sc->hw.phy.media_type == e1000_media_type_copper) {
480 sc->hw.phy.mdix = AUTO_ALL_MODES;
481 sc->hw.phy.disable_polarity_correction = FALSE;
482 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
483 }
484
485 /* Set the frame limits assuming standard ethernet sized frames. */
486 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
1f7e3916 487
a619b256
SZ		 488 /* Allocate RX/TX rings */
489 error = igb_alloc_rings(sc);
1f7e3916
SZ		 490 if (error)
491 goto failed;
492
d0f59cad
SZ		 493#ifdef IFPOLL_ENABLE
494 /*
495 * NPOLLING RX CPU offset
496 */
497 if (sc->rx_ring_cnt == ncpus2) {
498 offset = 0;
499 } else {
500 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
501 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
502 if (offset >= ncpus2 ||
503 offset % sc->rx_ring_cnt != 0) {
504 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
505 offset, offset_def);
506 offset = offset_def;
507 }
508 }
509 sc->rx_npoll_off = offset;
510
511 /*
512 * NPOLLING TX CPU offset
513 */
d802cc67
SZ		 514 if (sc->tx_ring_cnt == ncpus2) {
515 offset = 0;
516 } else {
517 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
518 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
519 if (offset >= ncpus2 ||
520 offset % sc->tx_ring_cnt != 0) {
521 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
522 offset, offset_def);
523 offset = offset_def;
524 }
d0f59cad
SZ		 525 }
526 sc->tx_npoll_off = offset;
527#endif
528
3c7cc5e2
SZ		 529 /* Allocate interrupt */
530 error = igb_alloc_intr(sc);
531 if (error)
a1647e40 532 goto failed;
a1647e40 533
7d235eb5
SZ		 534 /*
535 * Setup serializers
536 */
7d235eb5
SZ		 537 i = 0;
538 sc->serializes[i++] = &sc->main_serialize;
539
540 sc->tx_serialize = i;
541 for (j = 0; j < sc->tx_ring_cnt; ++j)
542 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
543
544 sc->rx_serialize = i;
545 for (j = 0; j < sc->rx_ring_cnt; ++j)
546 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
547
548 sc->serialize_cnt = i;
549 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
550
1f7e3916
SZ		 551 /* Allocate the appropriate stats memory */
552 if (sc->vf_ifp) {
553 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
554 M_WAITOK | M_ZERO);
555 igb_vf_init_stats(sc);
556 } else {
557 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
558 M_WAITOK | M_ZERO);
559 }
560
561 /* Allocate multicast array memory. */
562 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
563 M_DEVBUF, M_WAITOK);
564
565 /* Some adapter-specific advanced features */
566 if (sc->hw.mac.type >= e1000_i350) {
567#ifdef notyet
568 igb_set_sysctl_value(adapter, "dma_coalesce",
569 "configure dma coalesce",
570 &adapter->dma_coalesce, igb_dma_coalesce);
571 igb_set_sysctl_value(adapter, "eee_disabled",
572 "enable Energy Efficient Ethernet",
573 &adapter->hw.dev_spec._82575.eee_disable,
574 igb_eee_disabled);
575#else
576 sc->dma_coalesce = igb_dma_coalesce;
577 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
578#endif
579 e1000_set_eee_i350(&sc->hw);
580 }
581
582 /*
583 * Start from a known state, this is important in reading the nvm and
584 * mac from that.
585 */
586 e1000_reset_hw(&sc->hw);
587
588 /* Make sure we have a good EEPROM before we read from it */
589 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
590 /*
591 * Some PCI-E parts fail the first check due to
592 * the link being in sleep state, call it again,
593 * if it fails a second time its a real issue.
594 */
595 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
596 device_printf(dev,
597 "The EEPROM Checksum Is Not Valid\n");
598 error = EIO;
599 goto failed;
600 }
601 }
602
603 /* Copy the permanent MAC address out of the EEPROM */
604 if (e1000_read_mac_addr(&sc->hw) < 0) {
605 device_printf(dev, "EEPROM read error while reading MAC"
606 " address\n");
607 error = EIO;
608 goto failed;
609 }
610 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
611 device_printf(dev, "Invalid MAC address\n");
612 error = EIO;
613 goto failed;
614 }
615
1f7e3916
SZ		 616 /* Setup OS specific network interface */
617 igb_setup_ifp(sc);
618
619 /* Add sysctl tree, must after igb_setup_ifp() */
620 igb_add_sysctl(sc);
621
622 /* Now get a good starting state */
623 igb_reset(sc);
624
625 /* Initialize statistics */
626 igb_update_stats_counters(sc);
627
628 sc->hw.mac.get_link_status = 1;
629 igb_update_link_status(sc);
630
631 /* Indicate SOL/IDER usage */
632 if (e1000_check_reset_block(&sc->hw)) {
633 device_printf(dev,
634 "PHY reset is blocked due to SOL/IDER session.\n");
635 }
636
637 /* Determine if we have to control management hardware */
396b7048
SZ		 638 if (e1000_enable_mng_pass_thru(&sc->hw))
639 sc->flags |= IGB_FLAG_HAS_MGMT;
1f7e3916
SZ		 640
641 /*
642 * Setup Wake-on-Lan
643 */
644 /* APME bit in EEPROM is mapped to WUC.APME */
645 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
646 if (eeprom_data)
647 sc->wol = E1000_WUFC_MAG;
648 /* XXX disable WOL */
649 sc->wol = 0;
650
651#ifdef notyet
652 /* Register for VLAN events */
653 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
654 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
655 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
656 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
657#endif
658
659#ifdef notyet
660 igb_add_hw_stats(adapter);
661#endif
662
f6167a56 663 error = igb_setup_intr(sc);
1f7e3916 664 if (error) {
1f7e3916
SZ		 665 ether_ifdetach(&sc->arpcom.ac_if);
666 goto failed;
667 }
f0a26983
SZ		 668
669 for (i = 0; i < sc->tx_ring_cnt; ++i) {
670 struct ifaltq_subque *ifsq =
671 ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
672 struct igb_tx_ring *txr = &sc->tx_rings[i];
673
674 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
675 ifsq_set_priv(ifsq, txr);
676 txr->ifsq = ifsq;
16109efc
SZ		 677
678 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
f0a26983 679 }
0e23628a 680
1f7e3916
SZ		 681 return 0;
682
683failed:
684 igb_detach(dev);
685 return error;
686}
687
688static int
689igb_detach(device_t dev)
690{
691 struct igb_softc *sc = device_get_softc(dev);
692
693 if (device_is_attached(dev)) {
694 struct ifnet *ifp = &sc->arpcom.ac_if;
695
696 ifnet_serialize_all(ifp);
697
698 igb_stop(sc);
699
700 e1000_phy_hw_reset(&sc->hw);
701
702 /* Give control back to firmware */
703 igb_rel_mgmt(sc);
704 igb_rel_hw_control(sc);
705
706 if (sc->wol) {
707 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
708 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
709 igb_enable_wol(dev);
710 }
711
9c0ecdcc 712 igb_teardown_intr(sc);
1f7e3916
SZ		 713
714 ifnet_deserialize_all(ifp);
715
716 ether_ifdetach(ifp);
717 } else if (sc->mem_res != NULL) {
718 igb_rel_hw_control(sc);
719 }
720 bus_generic_detach(dev);
721
9c0ecdcc
SZ		 722 if (sc->sysctl_tree != NULL)
723 sysctl_ctx_free(&sc->sysctl_ctx);
724
3c7cc5e2 725 igb_free_intr(sc);
1f7e3916 726
9c0ecdcc
SZ		 727 if (sc->msix_mem_res != NULL) {
728 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
729 sc->msix_mem_res);
730 }
1f7e3916
SZ		 731 if (sc->mem_res != NULL) {
732 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
733 sc->mem_res);
734 }
735
a619b256 736 igb_free_rings(sc);
1f7e3916
SZ		 737
738 if (sc->mta != NULL)
739 kfree(sc->mta, M_DEVBUF);
740 if (sc->stats != NULL)
741 kfree(sc->stats, M_DEVBUF);
742
1f7e3916
SZ		 743 return 0;
744}
745
746static int
747igb_shutdown(device_t dev)
748{
749 return igb_suspend(dev);
750}
751
752static int
753igb_suspend(device_t dev)
754{
755 struct igb_softc *sc = device_get_softc(dev);
756 struct ifnet *ifp = &sc->arpcom.ac_if;
757
758 ifnet_serialize_all(ifp);
759
760 igb_stop(sc);
761
762 igb_rel_mgmt(sc);
763 igb_rel_hw_control(sc);
764
765 if (sc->wol) {
766 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
767 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
768 igb_enable_wol(dev);
769 }
770
771 ifnet_deserialize_all(ifp);
772
773 return bus_generic_suspend(dev);
774}
775
776static int
777igb_resume(device_t dev)
778{
779 struct igb_softc *sc = device_get_softc(dev);
780 struct ifnet *ifp = &sc->arpcom.ac_if;
f0a26983 781 int i;
1f7e3916
SZ		 782
783 ifnet_serialize_all(ifp);
784
785 igb_init(sc);
786 igb_get_mgmt(sc);
787
d802cc67 788 for (i = 0; i < sc->tx_ring_inuse; ++i)
73397ddb 789 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
1f7e3916
SZ		 790
791 ifnet_deserialize_all(ifp);
792
793 return bus_generic_resume(dev);
794}
795
796static int
797igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
798{
799 struct igb_softc *sc = ifp->if_softc;
800 struct ifreq *ifr = (struct ifreq *)data;
801 int max_frame_size, mask, reinit;
802 int error = 0;
803
804 ASSERT_IFNET_SERIALIZED_ALL(ifp);
805
806 switch (command) {
807 case SIOCSIFMTU:
808 max_frame_size = 9234;
809 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
810 ETHER_CRC_LEN) {
811 error = EINVAL;
812 break;
813 }
814
815 ifp->if_mtu = ifr->ifr_mtu;
816 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
817 ETHER_CRC_LEN;
818
819 if (ifp->if_flags & IFF_RUNNING)
820 igb_init(sc);
821 break;
822
823 case SIOCSIFFLAGS:
824 if (ifp->if_flags & IFF_UP) {
825 if (ifp->if_flags & IFF_RUNNING) {
826 if ((ifp->if_flags ^ sc->if_flags) &
827 (IFF_PROMISC | IFF_ALLMULTI)) {
828 igb_disable_promisc(sc);
829 igb_set_promisc(sc);
830 }
831 } else {
832 igb_init(sc);
833 }
834 } else if (ifp->if_flags & IFF_RUNNING) {
835 igb_stop(sc);
836 }
837 sc->if_flags = ifp->if_flags;
838 break;
839
840 case SIOCADDMULTI:
841 case SIOCDELMULTI:
842 if (ifp->if_flags & IFF_RUNNING) {
843 igb_disable_intr(sc);
844 igb_set_multi(sc);
d0f59cad
SZ		 845#ifdef IFPOLL_ENABLE
846 if (!(ifp->if_flags & IFF_NPOLLING))
1f7e3916
SZ		 847#endif
848 igb_enable_intr(sc);
849 }
850 break;
851
852 case SIOCSIFMEDIA:
853 /*
854 * As the speed/duplex settings are being
855 * changed, we need toreset the PHY.
856 */
857 sc->hw.phy.reset_disable = FALSE;
858
859 /* Check SOL/IDER usage */
860 if (e1000_check_reset_block(&sc->hw)) {
861 if_printf(ifp, "Media change is "
862 "blocked due to SOL/IDER session.\n");
863 break;
864 }
865 /* FALL THROUGH */
866
867 case SIOCGIFMEDIA:
868 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
869 break;
870
871 case SIOCSIFCAP:
872 reinit = 0;
873 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
77d8cab9
SZ		 874 if (mask & IFCAP_RXCSUM) {
875 ifp->if_capenable ^= IFCAP_RXCSUM;
1f7e3916
SZ		 876 reinit = 1;
877 }
878 if (mask & IFCAP_VLAN_HWTAGGING) {
879 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
880 reinit = 1;
881 }
77d8cab9
SZ		 882 if (mask & IFCAP_TXCSUM) {
883 ifp->if_capenable ^= IFCAP_TXCSUM;
884 if (ifp->if_capenable & IFCAP_TXCSUM)
885 ifp->if_hwassist |= IGB_CSUM_FEATURES;
886 else
887 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
888 }
23f6ffe4
SZ		 889 if (mask & IFCAP_TSO) {
890 ifp->if_capenable ^= IFCAP_TSO;
891 if (ifp->if_capenable & IFCAP_TSO)
892 ifp->if_hwassist |= CSUM_TSO;
893 else
894 ifp->if_hwassist &= ~CSUM_TSO;
895 }
8d6600da
SZ		 896 if (mask & IFCAP_RSS)
897 ifp->if_capenable ^= IFCAP_RSS;
1f7e3916
SZ		 898 if (reinit && (ifp->if_flags & IFF_RUNNING))
899 igb_init(sc);
900 break;
901
902 default:
903 error = ether_ioctl(ifp, command, data);
904 break;
905 }
906 return error;
907}
908
909static void
910igb_init(void *xsc)
911{
912 struct igb_softc *sc = xsc;
913 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 914 boolean_t polling;
1f7e3916
SZ		 915 int i;
916
917 ASSERT_IFNET_SERIALIZED_ALL(ifp);
918
919 igb_stop(sc);
920
921 /* Get the latest mac address, User can use a LAA */
922 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
923
924 /* Put the address into the Receive Address Array */
925 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
926
927 igb_reset(sc);
928 igb_update_link_status(sc);
929
930 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
931
1f7e3916
SZ		 932 /* Configure for OS presence */
933 igb_get_mgmt(sc);
934
9c0ecdcc 935 polling = FALSE;
d0f59cad
SZ		 936#ifdef IFPOLL_ENABLE
937 if (ifp->if_flags & IFF_NPOLLING)
9c0ecdcc 938 polling = TRUE;
be922da6 939#endif
9c0ecdcc
SZ		 940
941 /* Configured used RX/TX rings */
942 igb_set_ring_inuse(sc, polling);
943
944 /* Initialize interrupt */
945 igb_init_intr(sc);
be922da6 946
1f7e3916 947 /* Prepare transmit descriptors and buffers */
d802cc67 948 for (i = 0; i < sc->tx_ring_inuse; ++i)
1f7e3916
SZ		 949 igb_init_tx_ring(&sc->tx_rings[i]);
950 igb_init_tx_unit(sc);
951
952 /* Setup Multicast table */
953 igb_set_multi(sc);
954
955#if 0
956 /*
957 * Figure out the desired mbuf pool
958 * for doing jumbo/packetsplit
959 */
960 if (adapter->max_frame_size <= 2048)
961 adapter->rx_mbuf_sz = MCLBYTES;
962 else if (adapter->max_frame_size <= 4096)
963 adapter->rx_mbuf_sz = MJUMPAGESIZE;
964 else
965 adapter->rx_mbuf_sz = MJUM9BYTES;
1f7e3916
SZ		 966#endif
967
968 /* Prepare receive descriptors and buffers */
be922da6 969 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ		 970 int error;
971
972 error = igb_init_rx_ring(&sc->rx_rings[i]);
973 if (error) {
974 if_printf(ifp, "Could not setup receive structures\n");
975 igb_stop(sc);
976 return;
977 }
978 }
979 igb_init_rx_unit(sc);
980
981 /* Enable VLAN support */
982 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
983 igb_set_vlan(sc);
984
985 /* Don't lose promiscuous settings */
986 igb_set_promisc(sc);
987
1f7e3916 988 ifp->if_flags |= IFF_RUNNING;
d802cc67 989 for (i = 0; i < sc->tx_ring_inuse; ++i) {
f0a26983 990 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
16109efc
SZ		 991 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
992 }
1f7e3916 993
7b61c9f2
SZ		 994 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
995 sc->timer_cpuid = 0; /* XXX fixed */
996 else
997 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
998 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1f7e3916
SZ		 999 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1000
9c0ecdcc 1001 /* This clears any pending interrupts */
1f7e3916 1002 E1000_READ_REG(&sc->hw, E1000_ICR);
9c0ecdcc 1003
1f7e3916
SZ		 1004 /*
1005 * Only enable interrupts if we are not polling, make sure
1006 * they are off otherwise.
1007 */
9c0ecdcc 1008 if (polling) {
1f7e3916 1009 igb_disable_intr(sc);
9c0ecdcc 1010 } else {
1f7e3916
SZ		 1011 igb_enable_intr(sc);
1012 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1013 }
1014
1015 /* Set Energy Efficient Ethernet */
1016 e1000_set_eee_i350(&sc->hw);
1017
1018 /* Don't reset the phy next time init gets called */
1019 sc->hw.phy.reset_disable = TRUE;
1020}
1021
1022static void
1023igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1024{
1025 struct igb_softc *sc = ifp->if_softc;
1026 u_char fiber_type = IFM_1000_SX;
1027
1028 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1029
1030 igb_update_link_status(sc);
1031
1032 ifmr->ifm_status = IFM_AVALID;
1033 ifmr->ifm_active = IFM_ETHER;
1034
1035 if (!sc->link_active)
1036 return;
1037
1038 ifmr->ifm_status |= IFM_ACTIVE;
1039
1040 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1041 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1042 ifmr->ifm_active |= fiber_type | IFM_FDX;
1043 } else {
1044 switch (sc->link_speed) {
1045 case 10:
1046 ifmr->ifm_active |= IFM_10_T;
1047 break;
1048
1049 case 100:
1050 ifmr->ifm_active |= IFM_100_TX;
1051 break;
1052
1053 case 1000:
1054 ifmr->ifm_active |= IFM_1000_T;
1055 break;
1056 }
1057 if (sc->link_duplex == FULL_DUPLEX)
1058 ifmr->ifm_active |= IFM_FDX;
1059 else
1060 ifmr->ifm_active |= IFM_HDX;
1061 }
1062}
1063
1064static int
1065igb_media_change(struct ifnet *ifp)
1066{
1067 struct igb_softc *sc = ifp->if_softc;
1068 struct ifmedia *ifm = &sc->media;
1069
1070 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1071
1072 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1073 return EINVAL;
1074
1075 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1076 case IFM_AUTO:
1077 sc->hw.mac.autoneg = DO_AUTO_NEG;
1078 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1079 break;
1080
1081 case IFM_1000_LX:
1082 case IFM_1000_SX:
1083 case IFM_1000_T:
1084 sc->hw.mac.autoneg = DO_AUTO_NEG;
1085 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1086 break;
1087
1088 case IFM_100_TX:
1089 sc->hw.mac.autoneg = FALSE;
1090 sc->hw.phy.autoneg_advertised = 0;
1091 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1092 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1093 else
1094 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1095 break;
1096
1097 case IFM_10_T:
1098 sc->hw.mac.autoneg = FALSE;
1099 sc->hw.phy.autoneg_advertised = 0;
1100 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1101 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1102 else
1103 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1104 break;
1105
1106 default:
1107 if_printf(ifp, "Unsupported media type\n");
1108 break;
1109 }
1110
1111 igb_init(sc);
1112
1113 return 0;
1114}
1115
1116static void
1117igb_set_promisc(struct igb_softc *sc)
1118{
1119 struct ifnet *ifp = &sc->arpcom.ac_if;
1120 struct e1000_hw *hw = &sc->hw;
1121 uint32_t reg;
1122
1123 if (sc->vf_ifp) {
1124 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1125 return;
1126 }
1127
1128 reg = E1000_READ_REG(hw, E1000_RCTL);
1129 if (ifp->if_flags & IFF_PROMISC) {
1130 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1131 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1132 } else if (ifp->if_flags & IFF_ALLMULTI) {
1133 reg |= E1000_RCTL_MPE;
1134 reg &= ~E1000_RCTL_UPE;
1135 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1136 }
1137}
1138
1139static void
1140igb_disable_promisc(struct igb_softc *sc)
1141{
1142 struct e1000_hw *hw = &sc->hw;
1143 uint32_t reg;
1144
1145 if (sc->vf_ifp) {
1146 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1147 return;
1148 }
1149 reg = E1000_READ_REG(hw, E1000_RCTL);
1150 reg &= ~E1000_RCTL_UPE;
1151 reg &= ~E1000_RCTL_MPE;
1152 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1153}
1154
1155static void
1156igb_set_multi(struct igb_softc *sc)
1157{
1158 struct ifnet *ifp = &sc->arpcom.ac_if;
1159 struct ifmultiaddr *ifma;
1160 uint32_t reg_rctl = 0;
1161 uint8_t *mta;
1162 int mcnt = 0;
1163
1164 mta = sc->mta;
1165 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1166
1167 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1168 if (ifma->ifma_addr->sa_family != AF_LINK)
1169 continue;
1170
1171 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1172 break;
1173
1174 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1175 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1176 mcnt++;
1177 }
1178
1179 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1180 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1181 reg_rctl |= E1000_RCTL_MPE;
1182 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1183 } else {
1184 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1185 }
1186}
1187
1188static void
1189igb_timer(void *xsc)
1190{
1191 struct igb_softc *sc = xsc;
1f7e3916 1192
27dd00d6 1193 lwkt_serialize_enter(&sc->main_serialize);
1f7e3916
SZ		 1194
1195 igb_update_link_status(sc);
1196 igb_update_stats_counters(sc);
1197
7b61c9f2 1198 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1f7e3916 1199
27dd00d6 1200 lwkt_serialize_exit(&sc->main_serialize);
1f7e3916
SZ		 1201}
1202
1203static void
1204igb_update_link_status(struct igb_softc *sc)
1205{
1206 struct ifnet *ifp = &sc->arpcom.ac_if;
1207 struct e1000_hw *hw = &sc->hw;
1208 uint32_t link_check, thstat, ctrl;
1209
1210 link_check = thstat = ctrl = 0;
1211
1212 /* Get the cached link value or read for real */
1213 switch (hw->phy.media_type) {
1214 case e1000_media_type_copper:
1215 if (hw->mac.get_link_status) {
1216 /* Do the work to read phy */
1217 e1000_check_for_link(hw);
1218 link_check = !hw->mac.get_link_status;
1219 } else {
1220 link_check = TRUE;
1221 }
1222 break;
1223
1224 case e1000_media_type_fiber:
1225 e1000_check_for_link(hw);
1226 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1227 break;
1228
1229 case e1000_media_type_internal_serdes:
1230 e1000_check_for_link(hw);
1231 link_check = hw->mac.serdes_has_link;
1232 break;
1233
1234 /* VF device is type_unknown */
1235 case e1000_media_type_unknown:
1236 e1000_check_for_link(hw);
1237 link_check = !hw->mac.get_link_status;
1238 /* Fall thru */
1239 default:
1240 break;
1241 }
1242
1243 /* Check for thermal downshift or shutdown */
1244 if (hw->mac.type == e1000_i350) {
1245 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1246 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1247 }
1248
1249 /* Now we check if a transition has happened */
1250 if (link_check && sc->link_active == 0) {
1251 e1000_get_speed_and_duplex(hw,
1252 &sc->link_speed, &sc->link_duplex);
1253 if (bootverbose) {
1254 if_printf(ifp, "Link is up %d Mbps %s\n",
1255 sc->link_speed,
1256 sc->link_duplex == FULL_DUPLEX ?
1257 "Full Duplex" : "Half Duplex");
1258 }
1259 sc->link_active = 1;
1260
1261 ifp->if_baudrate = sc->link_speed * 1000000;
1262 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1263 (thstat & E1000_THSTAT_LINK_THROTTLE))
1264 if_printf(ifp, "Link: thermal downshift\n");
1265 /* This can sleep */
1266 ifp->if_link_state = LINK_STATE_UP;
1267 if_link_state_change(ifp);
1268 } else if (!link_check && sc->link_active == 1) {
1269 ifp->if_baudrate = sc->link_speed = 0;
1270 sc->link_duplex = 0;
1271 if (bootverbose)
1272 if_printf(ifp, "Link is Down\n");
1273 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1274 (thstat & E1000_THSTAT_PWR_DOWN))
1275 if_printf(ifp, "Link: thermal shutdown\n");
1276 sc->link_active = 0;
1277 /* This can sleep */
1278 ifp->if_link_state = LINK_STATE_DOWN;
1279 if_link_state_change(ifp);
1280 }
1281}
1282
1283static void
1284igb_stop(struct igb_softc *sc)
1285{
1286 struct ifnet *ifp = &sc->arpcom.ac_if;
1287 int i;
1288
1289 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1290
1291 igb_disable_intr(sc);
1292
1293 callout_stop(&sc->timer);
1294
9ed293e0 1295 ifp->if_flags &= ~IFF_RUNNING;
16109efc 1296 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f0a26983 1297 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
16109efc
SZ		 1298 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1299 }
1f7e3916
SZ		 1300
1301 e1000_reset_hw(&sc->hw);
1302 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1303
1304 e1000_led_off(&sc->hw);
1305 e1000_cleanup_led(&sc->hw);
1306
27866bf1 1307 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916 1308 igb_free_tx_ring(&sc->tx_rings[i]);
27866bf1 1309 for (i = 0; i < sc->rx_ring_cnt; ++i)
1f7e3916
SZ		 1310 igb_free_rx_ring(&sc->rx_rings[i]);
1311}
1312
1313static void
1314igb_reset(struct igb_softc *sc)
1315{
1316 struct ifnet *ifp = &sc->arpcom.ac_if;
1317 struct e1000_hw *hw = &sc->hw;
1318 struct e1000_fc_info *fc = &hw->fc;
1319 uint32_t pba = 0;
1320 uint16_t hwm;
1321
1322 /* Let the firmware know the OS is in control */
1323 igb_get_hw_control(sc);
1324
1325 /*
1326 * Packet Buffer Allocation (PBA)
1327 * Writing PBA sets the receive portion of the buffer
1328 * the remainder is used for the transmit buffer.
1329 */
1330 switch (hw->mac.type) {
1331 case e1000_82575:
1332 pba = E1000_PBA_32K;
1333 break;
1334
1335 case e1000_82576:
1336 case e1000_vfadapt:
1337 pba = E1000_READ_REG(hw, E1000_RXPBS);
1338 pba &= E1000_RXPBS_SIZE_MASK_82576;
1339 break;
1340
1341 case e1000_82580:
1342 case e1000_i350:
1343 case e1000_vfadapt_i350:
1344 pba = E1000_READ_REG(hw, E1000_RXPBS);
1345 pba = e1000_rxpbs_adjust_82580(pba);
1346 break;
1347 /* XXX pba = E1000_PBA_35K; */
1348
1349 default:
1350 break;
1351 }
1352
1353 /* Special needs in case of Jumbo frames */
1354 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1355 uint32_t tx_space, min_tx, min_rx;
1356
1357 pba = E1000_READ_REG(hw, E1000_PBA);
1358 tx_space = pba >> 16;
1359 pba &= 0xffff;
1360
1361 min_tx = (sc->max_frame_size +
1362 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1363 min_tx = roundup2(min_tx, 1024);
1364 min_tx >>= 10;
1365 min_rx = sc->max_frame_size;
1366 min_rx = roundup2(min_rx, 1024);
1367 min_rx >>= 10;
1368 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1369 pba = pba - (min_tx - tx_space);
1370 /*
1371 * if short on rx space, rx wins
1372 * and must trump tx adjustment
1373 */
1374 if (pba < min_rx)
1375 pba = min_rx;
1376 }
1377 E1000_WRITE_REG(hw, E1000_PBA, pba);
1378 }
1379
1380 /*
1381 * These parameters control the automatic generation (Tx) and
1382 * response (Rx) to Ethernet PAUSE frames.
1383 * - High water mark should allow for at least two frames to be
1384 * received after sending an XOFF.
1385 * - Low water mark works best when it is very near the high water mark.
1386 * This allows the receiver to restart by sending XON when it has
1387 * drained a bit.
1388 */
1389 hwm = min(((pba << 10) * 9 / 10),
1390 ((pba << 10) - 2 * sc->max_frame_size));
1391
1392 if (hw->mac.type < e1000_82576) {
1393 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1394 fc->low_water = fc->high_water - 8;
1395 } else {
1396 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1397 fc->low_water = fc->high_water - 16;
1398 }
1399 fc->pause_time = IGB_FC_PAUSE_TIME;
1400 fc->send_xon = TRUE;
1401
1402 /* Issue a global reset */
1403 e1000_reset_hw(hw);
1404 E1000_WRITE_REG(hw, E1000_WUC, 0);
1405
1406 if (e1000_init_hw(hw) < 0)
1407 if_printf(ifp, "Hardware Initialization Failed\n");
1408
1409 /* Setup DMA Coalescing */
1410 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1411 uint32_t reg;
1412
1413 hwm = (pba - 4) << 10;
1414 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1415 & E1000_DMACR_DMACTHR_MASK;
1416
1417 /* transition to L0x or L1 if available..*/
1418 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1419
1420 /* timer = +-1000 usec in 32usec intervals */
1421 reg |= (1000 >> 5);
1422 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1423
1424 /* No lower threshold */
1425 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1426
1427 /* set hwm to PBA - 2 * max frame size */
1428 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1429
1430 /* Set the interval before transition */
1431 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1432 reg |= 0x800000FF; /* 255 usec */
1433 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1434
1435 /* free space in tx packet buffer to wake from DMA coal */
1436 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1437 (20480 - (2 * sc->max_frame_size)) >> 6);
1438
1439 /* make low power state decision controlled by DMA coal */
1440 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1441 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1442 reg | E1000_PCIEMISC_LX_DECISION);
1443 if_printf(ifp, "DMA Coalescing enabled\n");
1444 }
1445
1446 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1447 e1000_get_phy_info(hw);
1448 e1000_check_for_link(hw);
1449}
1450
1451static void
1452igb_setup_ifp(struct igb_softc *sc)
1453{
1454 struct ifnet *ifp = &sc->arpcom.ac_if;
1455
1f7e3916
SZ		 1456 ifp->if_softc = sc;
1457 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c0ecdcc 1458 ifp->if_init = igb_init;
1f7e3916
SZ		 1459 ifp->if_ioctl = igb_ioctl;
1460 ifp->if_start = igb_start;
7d235eb5
SZ		 1461 ifp->if_serialize = igb_serialize;
1462 ifp->if_deserialize = igb_deserialize;
1463 ifp->if_tryserialize = igb_tryserialize;
1464#ifdef INVARIANTS
1465 ifp->if_serialize_assert = igb_serialize_assert;
1466#endif
d0f59cad
SZ		 1467#ifdef IFPOLL_ENABLE
1468 ifp->if_npoll = igb_npoll;
1f7e3916 1469#endif
1f7e3916 1470
91b8700a 1471 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1f7e3916
SZ		 1472 ifq_set_ready(&ifp->if_snd);
1473
1474 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1475
1476 ifp->if_capabilities =
23f6ffe4 1477 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
8d6600da
SZ		 1478 if (IGB_ENABLE_HWRSS(sc))
1479 ifp->if_capabilities |= IFCAP_RSS;
1f7e3916 1480 ifp->if_capenable = ifp->if_capabilities;
23f6ffe4 1481 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1f7e3916
SZ		 1482
1483 /*
1484 * Tell the upper layer(s) we support long frames
1485 */
1486 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1487
1488 /*
1489 * Specify the media types supported by this adapter and register
1490 * callbacks to update media and link information
1491 */
1492 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1493 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1494 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1495 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1496 0, NULL);
1497 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1498 } else {
1499 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1500 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1501 0, NULL);
1502 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1503 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1504 0, NULL);
1505 if (sc->hw.phy.type != e1000_phy_ife) {
1506 ifmedia_add(&sc->media,
1507 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1508 ifmedia_add(&sc->media,
1509 IFM_ETHER | IFM_1000_T, 0, NULL);
1510 }
1511 }
1512 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1513 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1514}
1515
1516static void
1517igb_add_sysctl(struct igb_softc *sc)
1518{
9c0ecdcc 1519 char node[32];
8d6600da 1520 int i;
8d6600da 1521
1f7e3916
SZ		 1522 sysctl_ctx_init(&sc->sysctl_ctx);
1523 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1524 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1525 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1526 if (sc->sysctl_tree == NULL) {
1527 device_printf(sc->dev, "can't add sysctl node\n");
1528 return;
1529 }
1530
1531 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da 1532 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
be922da6
SZ		 1533 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1534 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1535 "# of RX rings used");
d802cc67
SZ		 1536 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537 OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1538 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1539 OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1540 "# of TX rings used");
8d6600da
SZ		 1541 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1542 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1543 "# of RX descs");
1f7e3916 1544 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ		 1545 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1546 "# of TX descs");
1f7e3916 1547
9c0ecdcc
SZ		 1548 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1549 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1550 SYSCTL_CHILDREN(sc->sysctl_tree),
1551 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1552 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1553 } else {
1554 for (i = 0; i < sc->msix_cnt; ++i) {
1555 struct igb_msix_data *msix = &sc->msix_data[i];
1556
1557 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1558 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1559 SYSCTL_CHILDREN(sc->sysctl_tree),
1560 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1561 msix, 0, igb_sysctl_msix_rate, "I",
1562 msix->msix_rate_desc);
1563 }
1564 }
b6220144
SZ		 1565
1566 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1567 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1568 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
8d6600da
SZ		 1569 "# of segments per TX interrupt");
1570
708575bb
SZ		 1571 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1572 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1573 sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
9d8e892a
SZ		 1574 "# of segments sent before write to hardware register");
1575
1576 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1577 OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1578 sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1579 "# of segments received before write to hardware register");
871c0e2b 1580
d0f59cad
SZ		 1581#ifdef IFPOLL_ENABLE
1582 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1583 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1584 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1585 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1586 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1587 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1588#endif
1589
8d6600da
SZ		 1590#ifdef IGB_RSS_DEBUG
1591 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1592 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1593 "RSS debug level");
1594 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9c0ecdcc 1595 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
8d6600da 1596 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
9c0ecdcc 1597 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
8d6600da 1598 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
b56e8196 1599 }
9d8e892a 1600#endif
1f7e3916
SZ		 1601}
1602
1603static int
a619b256 1604igb_alloc_rings(struct igb_softc *sc)
1f7e3916
SZ		 1605{
1606 int error, i;
1607
1f7e3916
SZ		 1608 /*
1609 * Create top level busdma tag
1610 */
1611 error = bus_dma_tag_create(NULL, 1, 0,
1612 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1613 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1614 &sc->parent_tag);
1615 if (error) {
1616 device_printf(sc->dev, "could not create top level DMA tag\n");
1617 return error;
1618 }
1619
1620 /*
1621 * Allocate TX descriptor rings and buffers
1622 */
7b269c72
SZ		 1623 sc->tx_rings = kmalloc_cachealign(
1624 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1f7e3916 1625 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1626 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ		 1627 struct igb_tx_ring *txr = &sc->tx_rings[i];
1628
1629 /* Set up some basics */
1630 txr->sc = sc;
1631 txr->me = i;
7d235eb5 1632 lwkt_serialize_init(&txr->tx_serialize);
1f7e3916
SZ		 1633
1634 error = igb_create_tx_ring(txr);
1635 if (error)
1636 return error;
1637 }
1638
1639 /*
1640 * Allocate RX descriptor rings and buffers
1641 */
7b269c72
SZ		 1642 sc->rx_rings = kmalloc_cachealign(
1643 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1f7e3916 1644 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1645 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1f7e3916
SZ		 1646 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1647
1648 /* Set up some basics */
1649 rxr->sc = sc;
1650 rxr->me = i;
7d235eb5 1651 lwkt_serialize_init(&rxr->rx_serialize);
1f7e3916
SZ		 1652
1653 error = igb_create_rx_ring(rxr);
1654 if (error)
1655 return error;
1656 }
1657
1f7e3916
SZ		 1658 return 0;
1659}
1660
1661static void
a619b256 1662igb_free_rings(struct igb_softc *sc)
1f7e3916
SZ		 1663{
1664 int i;
1665
1f7e3916 1666 if (sc->tx_rings != NULL) {
91b8700a
SZ		 1667 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1668 struct igb_tx_ring *txr = &sc->tx_rings[i];
1669
1670 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1671 }
1f7e3916
SZ		 1672 kfree(sc->tx_rings, M_DEVBUF);
1673 }
1674
1675 if (sc->rx_rings != NULL) {
91b8700a
SZ		 1676 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1677 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1678
1679 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1680 }
1f7e3916
SZ		 1681 kfree(sc->rx_rings, M_DEVBUF);
1682 }
1683}
1684
1685static int
1686igb_create_tx_ring(struct igb_tx_ring *txr)
1687{
c1a8a339 1688 int tsize, error, i, ntxd;
1f7e3916
SZ		 1689
1690 /*
1691 * Validate number of transmit descriptors. It must not exceed
1692 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1693 */
c1a8a339
SZ		 1694 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1695 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1696 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1f7e3916
SZ		 1697 device_printf(txr->sc->dev,
1698 "Using %d TX descriptors instead of %d!\n",
c1a8a339 1699 IGB_DEFAULT_TXD, ntxd);
91b8700a 1700 txr->num_tx_desc = IGB_DEFAULT_TXD;
1f7e3916 1701 } else {
c1a8a339 1702 txr->num_tx_desc = ntxd;
1f7e3916
SZ		 1703 }
1704
1705 /*
1706 * Allocate TX descriptor ring
1707 */
91b8700a 1708 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1f7e3916
SZ		 1709 IGB_DBA_ALIGN);
1710 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1711 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1712 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1713 if (txr->txdma.dma_vaddr == NULL) {
1714 device_printf(txr->sc->dev,
1715 "Unable to allocate TX Descriptor memory\n");
1716 return ENOMEM;
1717 }
1718 txr->tx_base = txr->txdma.dma_vaddr;
1719 bzero(txr->tx_base, tsize);
1720
e2a02a4c
SZ		 1721 tsize = __VM_CACHELINE_ALIGN(
1722 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1723 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1f7e3916 1724
b6220144
SZ		 1725 /*
1726 * Allocate TX head write-back buffer
1727 */
1728 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1729 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1730 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1731 if (txr->tx_hdr == NULL) {
1732 device_printf(txr->sc->dev,
1733 "Unable to allocate TX head write-back buffer\n");
1734 return ENOMEM;
1735 }
1736
1f7e3916
SZ		 1737 /*
1738 * Create DMA tag for TX buffers
1739 */
1740 error = bus_dma_tag_create(txr->sc->parent_tag,
1741 1, 0, /* alignment, bounds */
1742 BUS_SPACE_MAXADDR, /* lowaddr */
1743 BUS_SPACE_MAXADDR, /* highaddr */
1744 NULL, NULL, /* filter, filterarg */
1745 IGB_TSO_SIZE, /* maxsize */
1746 IGB_MAX_SCATTER, /* nsegments */
1747 PAGE_SIZE, /* maxsegsize */
1748 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1749 BUS_DMA_ONEBPAGE, /* flags */
1750 &txr->tx_tag);
1751 if (error) {
1752 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1753 kfree(txr->tx_buf, M_DEVBUF);
1754 txr->tx_buf = NULL;
1755 return error;
1756 }
1757
1758 /*
1759 * Create DMA maps for TX buffers
1760 */
91b8700a 1761 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ		 1762 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1763
1764 error = bus_dmamap_create(txr->tx_tag,
1765 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1766 if (error) {
1767 device_printf(txr->sc->dev,
1768 "Unable to create TX DMA map\n");
1769 igb_destroy_tx_ring(txr, i);
1770 return error;
1771 }
1772 }
b6220144
SZ		 1773
1774 /*
1775 * Initialize various watermark
1776 */
1777 txr->spare_desc = IGB_TX_SPARE;
91b8700a 1778 txr->intr_nsegs = txr->num_tx_desc / 16;
5a612d02 1779 txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
91b8700a
SZ		 1780 txr->oact_hi_desc = txr->num_tx_desc / 2;
1781 txr->oact_lo_desc = txr->num_tx_desc / 8;
b6220144
SZ		 1782 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1783 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1784 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1785 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1786
1f7e3916
SZ		 1787 return 0;
1788}
1789
1790static void
1791igb_free_tx_ring(struct igb_tx_ring *txr)
1792{
1793 int i;
1794
91b8700a 1795 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ		 1796 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1797
1798 if (txbuf->m_head != NULL) {
1799 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1800 m_freem(txbuf->m_head);
1801 txbuf->m_head = NULL;
1802 }
1803 }
1804}
1805
1806static void
1807igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1808{
1809 int i;
1810
1811 if (txr->txdma.dma_vaddr != NULL) {
1812 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1813 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1814 txr->txdma.dma_map);
1815 bus_dma_tag_destroy(txr->txdma.dma_tag);
1816 txr->txdma.dma_vaddr = NULL;
1817 }
1818
b6220144
SZ		 1819 if (txr->tx_hdr != NULL) {
1820 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1821 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1822 txr->tx_hdr_dmap);
1823 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1824 txr->tx_hdr = NULL;
1825 }
1826
1f7e3916
SZ		 1827 if (txr->tx_buf == NULL)
1828 return;
1829
1830 for (i = 0; i < ndesc; ++i) {
1831 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1832
1833 KKASSERT(txbuf->m_head == NULL);
1834 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1835 }
1836 bus_dma_tag_destroy(txr->tx_tag);
1837
1838 kfree(txr->tx_buf, M_DEVBUF);
1839 txr->tx_buf = NULL;
1840}
1841
1842static void
1843igb_init_tx_ring(struct igb_tx_ring *txr)
1844{
1f7e3916
SZ		 1845 /* Clear the old descriptor contents */
1846 bzero(txr->tx_base,
91b8700a 1847 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1f7e3916 1848
b6220144
SZ		 1849 /* Clear TX head write-back buffer */
1850 *(txr->tx_hdr) = 0;
1851
1f7e3916
SZ		 1852 /* Reset indices */
1853 txr->next_avail_desc = 0;
1854 txr->next_to_clean = 0;
b6220144 1855 txr->tx_nsegs = 0;
1f7e3916
SZ		 1856
1857 /* Set number of descriptors available */
91b8700a 1858 txr->tx_avail = txr->num_tx_desc;
1f7e3916
SZ		 1859}
1860
1861static void
1862igb_init_tx_unit(struct igb_softc *sc)
1863{
1864 struct e1000_hw *hw = &sc->hw;
1865 uint32_t tctl;
1866 int i;
1867
1868 /* Setup the Tx Descriptor Rings */
d802cc67 1869 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1f7e3916
SZ		 1870 struct igb_tx_ring *txr = &sc->tx_rings[i];
1871 uint64_t bus_addr = txr->txdma.dma_paddr;
c3162c4e 1872 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1f7e3916 1873 uint32_t txdctl = 0;
b6220144 1874 uint32_t dca_txctrl;
1f7e3916
SZ		 1875
1876 E1000_WRITE_REG(hw, E1000_TDLEN(i),
91b8700a 1877 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1f7e3916
SZ		 1878 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1879 (uint32_t)(bus_addr >> 32));
1880 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1881 (uint32_t)bus_addr);
1882
1883 /* Setup the HW Tx Head and Tail descriptor pointers */
1884 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1885 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1886
b6220144
SZ		 1887 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1888 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1889 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1890
54691ff1
SZ		 1891 /*
1892 * Don't set WB_on_EITR:
1893 * - 82575 does not have it
1894 * - It almost has no effect on 82576, see:
1895 * 82576 specification update errata #26
1896 * - It causes unnecessary bus traffic
1897 */
b6220144 1898 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
c3162c4e 1899 (uint32_t)(hdr_paddr >> 32));
b6220144 1900 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
c3162c4e 1901 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
c7c6ca44
SZ		 1902
1903 /*
1904 * WTHRESH is ignored by the hardware, since header
1905 * write back mode is used.
1906 */
1907 txdctl |= IGB_TX_PTHRESH;
1908 txdctl |= IGB_TX_HTHRESH << 8;
1909 txdctl |= IGB_TX_WTHRESH << 16;
1910 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1911 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1f7e3916
SZ		 1912 }
1913
1914 if (sc->vf_ifp)
1915 return;
1916
1917 e1000_config_collision_dist(hw);
1918
1919 /* Program the Transmit Control Register */
1920 tctl = E1000_READ_REG(hw, E1000_TCTL);
1921 tctl &= ~E1000_TCTL_CT;
1922 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1923 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1924
1925 /* This write will effectively turn on the transmit unit. */
1926 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1927}
1928
1929static boolean_t
48faa653 1930igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1f7e3916
SZ		 1931{
1932 struct e1000_adv_tx_context_desc *TXD;
1f7e3916 1933 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1f7e3916 1934 int ehdrlen, ctxd, ip_hlen = 0;
1f7e3916
SZ		 1935 boolean_t offload = TRUE;
1936
1937 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1938 offload = FALSE;
1939
1940 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
48faa653 1941
1f7e3916 1942 ctxd = txr->next_avail_desc;
1f7e3916
SZ		 1943 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1944
1945 /*
1946 * In advanced descriptors the vlan tag must
1947 * be placed into the context descriptor, thus
1948 * we need to be here just for that setup.
1949 */
1950 if (mp->m_flags & M_VLANTAG) {
23f6ffe4
SZ		 1951 uint16_t vlantag;
1952
1f7e3916
SZ		 1953 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1954 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1955 } else if (!offload) {
1956 return FALSE;
1957 }
1958
48faa653
SZ		 1959 ehdrlen = mp->m_pkthdr.csum_lhlen;
1960 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1f7e3916
SZ		 1961
1962 /* Set the ether header length */
1963 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
48faa653
SZ		 1964 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1965 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1966 ip_hlen = mp->m_pkthdr.csum_iphlen;
1967 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1f7e3916 1968 }
1f7e3916 1969 vlan_macip_lens |= ip_hlen;
1f7e3916 1970
23f6ffe4 1971 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1f7e3916
SZ		 1972 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1973 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1974 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1975 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1976
1977 /* 82575 needs the queue index added */
1978 if (txr->sc->hw.mac.type == e1000_82575)
1979 mss_l4len_idx = txr->me << 4;
1980
1981 /* Now copy bits into descriptor */
1982 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1983 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1984 TXD->seqnum_seed = htole32(0);
1985 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1986
1f7e3916 1987 /* We've consumed the first desc, adjust counters */
91b8700a 1988 if (++ctxd == txr->num_tx_desc)
1f7e3916
SZ		 1989 ctxd = 0;
1990 txr->next_avail_desc = ctxd;
1991 --txr->tx_avail;
1992
1993 return offload;
1994}
1995
1996static void
1997igb_txeof(struct igb_tx_ring *txr)
1998{
1999 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
b6220144 2000 int first, hdr, avail;
1f7e3916 2001
91b8700a 2002 if (txr->tx_avail == txr->num_tx_desc)
1f7e3916
SZ		 2003 return;
2004
2005 first = txr->next_to_clean;
b6220144 2006 hdr = *(txr->tx_hdr);
1f7e3916 2007
b6220144
SZ		 2008 if (first == hdr)
2009 return;
1f7e3916 2010
b6220144
SZ		 2011 avail = txr->tx_avail;
2012 while (first != hdr) {
2013 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1f7e3916 2014
b6220144
SZ		 2015 ++avail;
2016 if (txbuf->m_head) {
2017 bus_dmamap_unload(txr->tx_tag, txbuf->map);
2018 m_freem(txbuf->m_head);
2019 txbuf->m_head = NULL;
2020 ++ifp->if_opackets;
1f7e3916 2021 }
91b8700a 2022 if (++first == txr->num_tx_desc)
b6220144 2023 first = 0;
1f7e3916
SZ		 2024 }
2025 txr->next_to_clean = first;
b6220144 2026 txr->tx_avail = avail;
1f7e3916
SZ		 2027
2028 /*
9ed293e0 2029 * If we have a minimum free, clear OACTIVE
1f7e3916
SZ		 2030 * to tell the stack that it is OK to send packets.
2031 */
b6220144 2032 if (IGB_IS_NOT_OACTIVE(txr)) {
f0a26983 2033 ifsq_clr_oactive(txr->ifsq);
1f7e3916 2034
1f7e3916
SZ		 2035 /*
2036 * We have enough TX descriptors, turn off
b6220144
SZ		 2037 * the watchdog. We allow small amount of
2038 * packets (roughly intr_nsegs) pending on
2039 * the transmit ring.
1f7e3916 2040 */
16109efc 2041 txr->tx_watchdog.wd_timer = 0;
1f7e3916
SZ		 2042 }
2043}
2044
2045static int
2046igb_create_rx_ring(struct igb_rx_ring *rxr)
2047{
c1a8a339 2048 int rsize, i, error, nrxd;
1f7e3916
SZ		 2049
2050 /*
2051 * Validate number of receive descriptors. It must not exceed
2052 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2053 */
c1a8a339
SZ		 2054 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2055 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2056 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
1f7e3916
SZ		 2057 device_printf(rxr->sc->dev,
2058 "Using %d RX descriptors instead of %d!\n",
c1a8a339 2059 IGB_DEFAULT_RXD, nrxd);
91b8700a 2060 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1f7e3916 2061 } else {
c1a8a339 2062 rxr->num_rx_desc = nrxd;
1f7e3916
SZ		 2063 }
2064
2065 /*
2066 * Allocate RX descriptor ring
2067 */
91b8700a 2068 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1f7e3916
SZ		 2069 IGB_DBA_ALIGN);
2070 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2071 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2072 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2073 &rxr->rxdma.dma_paddr);
2074 if (rxr->rxdma.dma_vaddr == NULL) {
2075 device_printf(rxr->sc->dev,
2076 "Unable to allocate RxDescriptor memory\n");
2077 return ENOMEM;
2078 }
2079 rxr->rx_base = rxr->rxdma.dma_vaddr;
2080 bzero(rxr->rx_base, rsize);
2081
e2a02a4c
SZ		 2082 rsize = __VM_CACHELINE_ALIGN(
2083 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2084 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
1f7e3916
SZ		 2085
2086 /*
2087 * Create DMA tag for RX buffers
2088 */
2089 error = bus_dma_tag_create(rxr->sc->parent_tag,
2090 1, 0, /* alignment, bounds */
2091 BUS_SPACE_MAXADDR, /* lowaddr */
2092 BUS_SPACE_MAXADDR, /* highaddr */
2093 NULL, NULL, /* filter, filterarg */
2094 MCLBYTES, /* maxsize */
2095 1, /* nsegments */
2096 MCLBYTES, /* maxsegsize */
2097 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2098 &rxr->rx_tag);
2099 if (error) {
2100 device_printf(rxr->sc->dev,
2101 "Unable to create RX payload DMA tag\n");
2102 kfree(rxr->rx_buf, M_DEVBUF);
2103 rxr->rx_buf = NULL;
2104 return error;
2105 }
2106
2107 /*
2108 * Create spare DMA map for RX buffers
2109 */
2110 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2111 &rxr->rx_sparemap);
2112 if (error) {
2113 device_printf(rxr->sc->dev,
2114 "Unable to create spare RX DMA maps\n");
2115 bus_dma_tag_destroy(rxr->rx_tag);
2116 kfree(rxr->rx_buf, M_DEVBUF);
2117 rxr->rx_buf = NULL;
2118 return error;
2119 }
2120
2121 /*
2122 * Create DMA maps for RX buffers
2123 */
91b8700a 2124 for (i = 0; i < rxr->num_rx_desc; i++) {
1f7e3916
SZ		 2125 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2126
2127 error = bus_dmamap_create(rxr->rx_tag,
2128 BUS_DMA_WAITOK, &rxbuf->map);
2129 if (error) {
2130 device_printf(rxr->sc->dev,
2131 "Unable to create RX DMA maps\n");
2132 igb_destroy_rx_ring(rxr, i);
2133 return error;
2134 }
2135 }
b56e8196
SZ		 2136
2137 /*
2138 * Initialize various watermark
2139 */
5a612d02 2140 rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
b56e8196 2141
1f7e3916
SZ		 2142 return 0;
2143}
2144
2145static void
2146igb_free_rx_ring(struct igb_rx_ring *rxr)
2147{
2148 int i;
2149
91b8700a 2150 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ		 2151 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2152
2153 if (rxbuf->m_head != NULL) {
2154 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2155 m_freem(rxbuf->m_head);
2156 rxbuf->m_head = NULL;
2157 }
2158 }
2159
2160 if (rxr->fmp != NULL)
2161 m_freem(rxr->fmp);
2162 rxr->fmp = NULL;
2163 rxr->lmp = NULL;
2164}
2165
2166static void
2167igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2168{
2169 int i;
2170
2171 if (rxr->rxdma.dma_vaddr != NULL) {
2172 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2173 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2174 rxr->rxdma.dma_map);
2175 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2176 rxr->rxdma.dma_vaddr = NULL;
2177 }
2178
2179 if (rxr->rx_buf == NULL)
2180 return;
2181
2182 for (i = 0; i < ndesc; ++i) {
2183 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2184
2185 KKASSERT(rxbuf->m_head == NULL);
2186 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2187 }
2188 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2189 bus_dma_tag_destroy(rxr->rx_tag);
2190
2191 kfree(rxr->rx_buf, M_DEVBUF);
2192 rxr->rx_buf = NULL;
2193}
2194
2195static void
2196igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2197{
2198 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2199 rxd->wb.upper.status_error = 0;
2200}
2201
2202static int
2203igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2204{
2205 struct mbuf *m;
2206 bus_dma_segment_t seg;
2207 bus_dmamap_t map;
2208 struct igb_rx_buf *rxbuf;
2209 int error, nseg;
2210
2211 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2212 if (m == NULL) {
2213 if (wait) {
2214 if_printf(&rxr->sc->arpcom.ac_if,
2215 "Unable to allocate RX mbuf\n");
2216 }
2217 return ENOBUFS;
2218 }
2219 m->m_len = m->m_pkthdr.len = MCLBYTES;
2220
2221 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2222 m_adj(m, ETHER_ALIGN);
2223
2224 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2225 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2226 if (error) {
2227 m_freem(m);
2228 if (wait) {
2229 if_printf(&rxr->sc->arpcom.ac_if,
2230 "Unable to load RX mbuf\n");
2231 }
2232 return error;
2233 }
2234
2235 rxbuf = &rxr->rx_buf[i];
2236 if (rxbuf->m_head != NULL)
2237 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2238
2239 map = rxbuf->map;
2240 rxbuf->map = rxr->rx_sparemap;
2241 rxr->rx_sparemap = map;
2242
2243 rxbuf->m_head = m;
2244 rxbuf->paddr = seg.ds_addr;
2245
2246 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2247 return 0;
2248}
2249
2250static int
2251igb_init_rx_ring(struct igb_rx_ring *rxr)
2252{
2253 int i;
2254
2255 /* Clear the ring contents */
2256 bzero(rxr->rx_base,
91b8700a 2257 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
1f7e3916
SZ		 2258
2259 /* Now replenish the ring mbufs */
91b8700a 2260 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ		 2261 int error;
2262
2263 error = igb_newbuf(rxr, i, TRUE);
2264 if (error)
2265 return error;
2266 }
2267
2268 /* Setup our descriptor indices */
2269 rxr->next_to_check = 0;
2270
2271 rxr->fmp = NULL;
2272 rxr->lmp = NULL;
2273 rxr->discard = FALSE;
2274
2275 return 0;
2276}
2277
2278static void
2279igb_init_rx_unit(struct igb_softc *sc)
2280{
2281 struct ifnet *ifp = &sc->arpcom.ac_if;
2282 struct e1000_hw *hw = &sc->hw;
2283 uint32_t rctl, rxcsum, srrctl = 0;
2284 int i;
2285
2286 /*
2287 * Make sure receives are disabled while setting
2288 * up the descriptor ring
2289 */
2290 rctl = E1000_READ_REG(hw, E1000_RCTL);
2291 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2292
2293#if 0
2294 /*
2295 ** Set up for header split
2296 */
2297 if (igb_header_split) {
2298 /* Use a standard mbuf for the header */
2299 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2300 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2301 } else
2302#endif
2303 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2304
2305 /*
2306 ** Set up for jumbo frames
2307 */
2308 if (ifp->if_mtu > ETHERMTU) {
2309 rctl |= E1000_RCTL_LPE;
2310#if 0
2311 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2312 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2313 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2314 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2315 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2316 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2317 }
2318 /* Set maximum packet len */
2319 psize = adapter->max_frame_size;
2320 /* are we on a vlan? */
2321 if (adapter->ifp->if_vlantrunk != NULL)
2322 psize += VLAN_TAG_SIZE;
2323 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2324#else
2325 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2326 rctl |= E1000_RCTL_SZ_2048;
2327#endif
2328 } else {
2329 rctl &= ~E1000_RCTL_LPE;
2330 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2331 rctl |= E1000_RCTL_SZ_2048;
2332 }
2333
2334 /* Setup the Base and Length of the Rx Descriptor Rings */
be922da6 2335 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ		 2336 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2337 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2338 uint32_t rxdctl;
2339
2340 E1000_WRITE_REG(hw, E1000_RDLEN(i),
91b8700a 2341 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
1f7e3916
SZ		 2342 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2343 (uint32_t)(bus_addr >> 32));
2344 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2345 (uint32_t)bus_addr);
2346 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2347 /* Enable this Queue */
2348 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2349 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2350 rxdctl &= 0xFFF00000;
2351 rxdctl |= IGB_RX_PTHRESH;
2352 rxdctl |= IGB_RX_HTHRESH << 8;
54691ff1
SZ		 2353 /*
2354 * Don't set WTHRESH to a value above 1 on 82576, see:
2355 * 82576 specification update errata #26
2356 */
1f7e3916
SZ		 2357 rxdctl |= IGB_RX_WTHRESH << 16;
2358 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2359 }
2360
8d6600da
SZ		 2361 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2362 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2363
1f7e3916 2364 /*
8d6600da
SZ		 2365 * Receive Checksum Offload for TCP and UDP
2366 *
2367 * Checksum offloading is also enabled if multiple receive
2368 * queue is to be supported, since we need it to figure out
2369 * fragments.
1f7e3916 2370 */
8d6600da
SZ		 2371 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2372 /*
2373 * NOTE:
2374 * PCSD must be enabled to enable multiple
2375 * receive queues.
2376 */
2377 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2378 E1000_RXCSUM_PCSD;
2379 } else {
2380 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2381 E1000_RXCSUM_PCSD);
2382 }
2383 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2384
2385 if (IGB_ENABLE_HWRSS(sc)) {
2386 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
d1218435
SZ		 2387 uint32_t reta_shift;
2388 int j, r;
8d6600da
SZ		 2389
2390 /*
2391 * NOTE:
2392 * When we reach here, RSS has already been disabled
2393 * in igb_stop(), so we could safely configure RSS key
2394 * and redirect table.
2395 */
2396
2397 /*
2398 * Configure RSS key
2399 */
2400 toeplitz_get_key(key, sizeof(key));
2401 for (i = 0; i < IGB_NRSSRK; ++i) {
2402 uint32_t rssrk;
2403
2404 rssrk = IGB_RSSRK_VAL(key, i);
2405 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2406
2407 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
1f7e3916 2408 }
1f7e3916
SZ		 2409
2410 /*
8d6600da
SZ		 2411 * Configure RSS redirect table in following fashion:
2412 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2413 */
2414 reta_shift = IGB_RETA_SHIFT;
2415 if (hw->mac.type == e1000_82575)
2416 reta_shift = IGB_RETA_SHIFT_82575;
8d6600da 2417
d1218435
SZ		 2418 r = 0;
2419 for (j = 0; j < IGB_NRETA; ++j) {
2420 uint32_t reta = 0;
8d6600da 2421
d1218435
SZ		 2422 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2423 uint32_t q;
2424
be922da6 2425 q = (r % sc->rx_ring_inuse) << reta_shift;
d1218435
SZ		 2426 reta |= q << (8 * i);
2427 ++r;
2428 }
2429 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2430 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2431 }
8d6600da
SZ		 2432
2433 /*
2434 * Enable multiple receive queues.
2435 * Enable IPv4 RSS standard hash functions.
2436 * Disable RSS interrupt on 82575
2437 */
2438 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2439 E1000_MRQC_ENABLE_RSS_4Q |
2440 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2441 E1000_MRQC_RSS_FIELD_IPV4);
1f7e3916 2442 }
1f7e3916
SZ		 2443
2444 /* Setup the Receive Control Register */
2445 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2446 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2447 E1000_RCTL_RDMTS_HALF |
2448 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2449 /* Strip CRC bytes. */
2450 rctl |= E1000_RCTL_SECRC;
2451 /* Make sure VLAN Filters are off */
2452 rctl &= ~E1000_RCTL_VFE;
2453 /* Don't store bad packets */
2454 rctl &= ~E1000_RCTL_SBP;
2455
2456 /* Enable Receives */
2457 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2458
2459 /*
2460 * Setup the HW Rx Head and Tail Descriptor Pointers
2461 * - needs to be after enable
2462 */
be922da6 2463 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ		 2464 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2465
2466 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
91b8700a 2467 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
1f7e3916
SZ		 2468 }
2469}
2470
b56e8196
SZ		 2471static void
2472igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2473{
2474 if (--i < 0)
2475 i = rxr->num_rx_desc - 1;
2476 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2477}
2478
1f7e3916
SZ		 2479static void
2480igb_rxeof(struct igb_rx_ring *rxr, int count)
2481{
2482 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2483 union e1000_adv_rx_desc *cur;
2484 uint32_t staterr;
b56e8196 2485 int i, ncoll = 0;
1f7e3916
SZ		 2486
2487 i = rxr->next_to_check;
2488 cur = &rxr->rx_base[i];
2489 staterr = le32toh(cur->wb.upper.status_error);
2490
2491 if ((staterr & E1000_RXD_STAT_DD) == 0)
2492 return;
2493
2494 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
8d6600da 2495 struct pktinfo *pi = NULL, pi0;
1f7e3916
SZ		 2496 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2497 struct mbuf *m = NULL;
2498 boolean_t eop;
2499
2500 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2501 if (eop)
2502 --count;
2503
b56e8196 2504 ++ncoll;
1f7e3916
SZ		 2505 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2506 !rxr->discard) {
2507 struct mbuf *mp = rxbuf->m_head;
8d6600da 2508 uint32_t hash, hashtype;
1f7e3916
SZ		 2509 uint16_t vlan;
2510 int len;
2511
2512 len = le16toh(cur->wb.upper.length);
2513 if (rxr->sc->hw.mac.type == e1000_i350 &&
2514 (staterr & E1000_RXDEXT_STATERR_LB))
2515 vlan = be16toh(cur->wb.upper.vlan);
2516 else
2517 vlan = le16toh(cur->wb.upper.vlan);
2518
8d6600da
SZ		 2519 hash = le32toh(cur->wb.lower.hi_dword.rss);
2520 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2521 E1000_RXDADV_RSSTYPE_MASK;
2522
2523 IGB_RSS_DPRINTF(rxr->sc, 10,
2524 "ring%d, hash 0x%08x, hashtype %u\n",
2525 rxr->me, hash, hashtype);
2526
1f7e3916
SZ		 2527 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2528 BUS_DMASYNC_POSTREAD);
2529
2530 if (igb_newbuf(rxr, i, FALSE) != 0) {
2531 ifp->if_iqdrops++;
2532 goto discard;
2533 }
2534
2535 mp->m_len = len;
2536 if (rxr->fmp == NULL) {
2537 mp->m_pkthdr.len = len;
2538 rxr->fmp = mp;
2539 rxr->lmp = mp;
2540 } else {
2541 rxr->lmp->m_next = mp;
2542 rxr->lmp = rxr->lmp->m_next;
2543 rxr->fmp->m_pkthdr.len += len;
2544 }
2545
2546 if (eop) {
2547 m = rxr->fmp;
2548 rxr->fmp = NULL;
2549 rxr->lmp = NULL;
2550
2551 m->m_pkthdr.rcvif = ifp;
2552 ifp->if_ipackets++;
2553
2554 if (ifp->if_capenable & IFCAP_RXCSUM)
2555 igb_rxcsum(staterr, m);
2556
2557 if (staterr & E1000_RXD_STAT_VP) {
2558 m->m_pkthdr.ether_vlantag = vlan;
2559 m->m_flags |= M_VLANTAG;
2560 }
2561
1f7e3916 2562 if (ifp->if_capenable & IFCAP_RSS) {
8d6600da
SZ		 2563 pi = igb_rssinfo(m, &pi0,
2564 hash, hashtype, staterr);
1f7e3916 2565 }
8d6600da
SZ		 2566#ifdef IGB_RSS_DEBUG
2567 rxr->rx_packets++;
1f7e3916
SZ		 2568#endif
2569 }
2570 } else {
2571 ifp->if_ierrors++;
2572discard:
2573 igb_setup_rxdesc(cur, rxbuf);
2574 if (!eop)
2575 rxr->discard = TRUE;
2576 else
2577 rxr->discard = FALSE;
2578 if (rxr->fmp != NULL) {
2579 m_freem(rxr->fmp);
2580 rxr->fmp = NULL;
2581 rxr->lmp = NULL;
2582 }
2583 m = NULL;
2584 }
2585
2586 if (m != NULL)
8d6600da 2587 ether_input_pkt(ifp, m, pi);
1f7e3916
SZ		 2588
2589 /* Advance our pointers to the next descriptor. */
91b8700a 2590 if (++i == rxr->num_rx_desc)
1f7e3916
SZ		 2591 i = 0;
2592
9d8e892a 2593 if (ncoll >= rxr->wreg_nsegs) {
b56e8196
SZ		 2594 igb_rx_refresh(rxr, i);
2595 ncoll = 0;
2596 }
2597
1f7e3916
SZ		 2598 cur = &rxr->rx_base[i];
2599 staterr = le32toh(cur->wb.upper.status_error);
2600 }
2601 rxr->next_to_check = i;
2602
b56e8196
SZ		 2603 if (ncoll > 0)
2604 igb_rx_refresh(rxr, i);
1f7e3916
SZ		 2605}
2606
2607
2608static void
2609igb_set_vlan(struct igb_softc *sc)
2610{
2611 struct e1000_hw *hw = &sc->hw;
2612 uint32_t reg;
2613#if 0
2614 struct ifnet *ifp = sc->arpcom.ac_if;
2615#endif
2616
2617 if (sc->vf_ifp) {
2618 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2619 return;
2620 }
2621
2622 reg = E1000_READ_REG(hw, E1000_CTRL);
2623 reg |= E1000_CTRL_VME;
2624 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2625
2626#if 0
2627 /* Enable the Filter Table */
2628 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2629 reg = E1000_READ_REG(hw, E1000_RCTL);
2630 reg &= ~E1000_RCTL_CFIEN;
2631 reg |= E1000_RCTL_VFE;
2632 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2633 }
2634#endif
2635
2636 /* Update the frame size */
2637 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2638 sc->max_frame_size + VLAN_TAG_SIZE);
2639
2640#if 0
2641 /* Don't bother with table if no vlans */
2642 if ((adapter->num_vlans == 0) ||
2643 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2644 return;
2645 /*
2646 ** A soft reset zero's out the VFTA, so
2647 ** we need to repopulate it now.
2648 */
2649 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2650 if (adapter->shadow_vfta[i] != 0) {
2651 if (adapter->vf_ifp)
2652 e1000_vfta_set_vf(hw,
2653 adapter->shadow_vfta[i], TRUE);
2654 else
2655 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2656 i, adapter->shadow_vfta[i]);
2657 }
2658#endif
2659}
2660
2661static void
2662igb_enable_intr(struct igb_softc *sc)
2663{
9c0ecdcc
SZ		 2664 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2665 lwkt_serialize_handler_enable(&sc->main_serialize);
2666 } else {
2667 int i;
2668
2669 for (i = 0; i < sc->msix_cnt; ++i) {
2670 lwkt_serialize_handler_enable(
2671 sc->msix_data[i].msix_serialize);
2672 }
2673 }
1f7e3916 2674
f6167a56 2675 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
9c0ecdcc
SZ		 2676 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2677 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2678 else
2679 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56
SZ		 2680 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2681 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
1f7e3916
SZ		 2682 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2683 } else {
2684 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2685 }
2686 E1000_WRITE_FLUSH(&sc->hw);
2687}
2688
2689static void
2690igb_disable_intr(struct igb_softc *sc)
2691{
f6167a56 2692 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
1f7e3916
SZ		 2693 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2694 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56 2695 }
1f7e3916
SZ		 2696 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2697 E1000_WRITE_FLUSH(&sc->hw);
2698
9c0ecdcc
SZ		 2699 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2700 lwkt_serialize_handler_disable(&sc->main_serialize);
2701 } else {
2702 int i;
2703
2704 for (i = 0; i < sc->msix_cnt; ++i) {
2705 lwkt_serialize_handler_disable(
2706 sc->msix_data[i].msix_serialize);
2707 }
2708 }
1f7e3916
SZ		 2709}
2710
2711/*
2712 * Bit of a misnomer, what this really means is
2713 * to enable OS management of the system... aka
2714 * to disable special hardware management features
2715 */
2716static void
2717igb_get_mgmt(struct igb_softc *sc)
2718{
396b7048 2719 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ		 2720 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2721 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2722
2723 /* disable hardware interception of ARP */
2724 manc &= ~E1000_MANC_ARP_EN;
2725
2726 /* enable receiving management packets to the host */
2727 manc |= E1000_MANC_EN_MNG2HOST;
2728 manc2h |= 1 << 5; /* Mng Port 623 */
2729 manc2h |= 1 << 6; /* Mng Port 664 */
2730 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2731 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2732 }
2733}
2734
2735/*
2736 * Give control back to hardware management controller
2737 * if there is one.
2738 */
2739static void
2740igb_rel_mgmt(struct igb_softc *sc)
2741{
396b7048 2742 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ		 2743 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2744
2745 /* Re-enable hardware interception of ARP */
2746 manc |= E1000_MANC_ARP_EN;
2747 manc &= ~E1000_MANC_EN_MNG2HOST;
2748
2749 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2750 }
2751}
2752
2753/*
2754 * Sets CTRL_EXT:DRV_LOAD bit.
2755 *
2756 * For ASF and Pass Through versions of f/w this means that
2757 * the driver is loaded.
2758 */
2759static void
2760igb_get_hw_control(struct igb_softc *sc)
2761{
2762 uint32_t ctrl_ext;
2763
2764 if (sc->vf_ifp)
2765 return;
2766
2767 /* Let firmware know the driver has taken over */
2768 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2769 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2770 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2771}
2772
2773/*
2774 * Resets CTRL_EXT:DRV_LOAD bit.
2775 *
2776 * For ASF and Pass Through versions of f/w this means that the
2777 * driver is no longer loaded.
2778 */
2779static void
2780igb_rel_hw_control(struct igb_softc *sc)
2781{
2782 uint32_t ctrl_ext;
2783
2784 if (sc->vf_ifp)
2785 return;
2786
2787 /* Let firmware taken over control of h/w */
2788 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2789 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2790 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2791}
2792
2793static int
2794igb_is_valid_ether_addr(const uint8_t *addr)
2795{
2796 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2797
2798 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2799 return FALSE;
2800 return TRUE;
2801}
2802
2803/*
2804 * Enable PCI Wake On Lan capability
2805 */
2806static void
2807igb_enable_wol(device_t dev)
2808{
2809 uint16_t cap, status;
2810 uint8_t id;
2811
2812 /* First find the capabilities pointer*/
2813 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2814
2815 /* Read the PM Capabilities */
2816 id = pci_read_config(dev, cap, 1);
2817 if (id != PCIY_PMG) /* Something wrong */
2818 return;
2819
2820 /*
2821 * OK, we have the power capabilities,
2822 * so now get the status register
2823 */
2824 cap += PCIR_POWER_STATUS;
2825 status = pci_read_config(dev, cap, 2);
2826 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2827 pci_write_config(dev, cap, status, 2);
2828}
2829
2830static void
2831igb_update_stats_counters(struct igb_softc *sc)
2832{
2833 struct e1000_hw *hw = &sc->hw;
2834 struct e1000_hw_stats *stats;
2835 struct ifnet *ifp = &sc->arpcom.ac_if;
2836
2837 /*
2838 * The virtual function adapter has only a
2839 * small controlled set of stats, do only
2840 * those and return.
2841 */
2842 if (sc->vf_ifp) {
2843 igb_update_vf_stats_counters(sc);
2844 return;
2845 }
2846 stats = sc->stats;
2847
2848 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2849 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2850 stats->symerrs +=
2851 E1000_READ_REG(hw,E1000_SYMERRS);
2852 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2853 }
2854
2855 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2856 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2857 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2858 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2859
2860 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2861 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2862 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2863 stats->dc += E1000_READ_REG(hw, E1000_DC);
2864 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2865 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2866 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2867
2868 /*
2869 * For watchdog management we need to know if we have been
2870 * paused during the last interval, so capture that here.
2871 */
2872 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2873 stats->xoffrxc += sc->pause_frames;
2874 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2875 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2876 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2877 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2878 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2879 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2880 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2881 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2882 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2883 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2884 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2885 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2886
2887 /* For the 64-bit byte counters the low dword must be read first. */
2888 /* Both registers clear on the read of the high dword */
2889
2890 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2891 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2892 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2893 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2894
2895 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2896 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2897 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2898 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2899 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2900
2901 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2902 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2903
2904 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2905 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2906 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2907 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2908 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2909 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2910 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2911 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2912 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2913 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2914
2915 /* Interrupt Counts */
2916
2917 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2918 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2919 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2920 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2921 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2922 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2923 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2924 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2925 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2926
2927 /* Host to Card Statistics */
2928
2929 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2930 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2931 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2932 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2933 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2934 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2935 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2936 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2937 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2938 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2939 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2940 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2941 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2942 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2943
2944 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2945 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2946 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2947 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2948 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2949 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2950
2951 ifp->if_collisions = stats->colc;
2952
2953 /* Rx Errors */
2954 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2955 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2956
2957 /* Tx Errors */
2958 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2959
2960 /* Driver specific counters */
2961 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2962 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2963 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2964 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2965 sc->packet_buf_alloc_tx =
2966 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2967 sc->packet_buf_alloc_rx =
2968 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2969}
2970
2971static void
2972igb_vf_init_stats(struct igb_softc *sc)
2973{
2974 struct e1000_hw *hw = &sc->hw;
2975 struct e1000_vf_stats *stats;
2976
2977 stats = sc->stats;
2978 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2979 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2980 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2981 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2982 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2983}
2984
2985static void
2986igb_update_vf_stats_counters(struct igb_softc *sc)
2987{
2988 struct e1000_hw *hw = &sc->hw;
2989 struct e1000_vf_stats *stats;
2990
2991 if (sc->link_speed == 0)
2992 return;
2993
2994 stats = sc->stats;
2995 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2996 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2997 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2998 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2999 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3000}
3001
d0f59cad 3002#ifdef IFPOLL_ENABLE
1f7e3916
SZ		 3003
3004static void
2f00683b 3005igb_npoll_status(struct ifnet *ifp)
1f7e3916
SZ		 3006{
3007 struct igb_softc *sc = ifp->if_softc;
3008 uint32_t reg_icr;
3009
d0f59cad 3010 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916 3011
d0f59cad
SZ		 3012 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3013 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3014 sc->hw.mac.get_link_status = 1;
3015 igb_update_link_status(sc);
3016 }
3017}
7d235eb5 3018
d0f59cad
SZ		 3019static void
3020igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3021{
3022 struct igb_tx_ring *txr = arg;
7d235eb5 3023
d0f59cad 3024 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3025
d0f59cad 3026 igb_txeof(txr);
f0a26983
SZ		 3027 if (!ifsq_is_empty(txr->ifsq))
3028 ifsq_devstart(txr->ifsq);
d0f59cad
SZ		 3029}
3030
3031static void
3032igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3033{
3034 struct igb_rx_ring *rxr = arg;
3035
3036 ASSERT_SERIALIZED(&rxr->rx_serialize);
3037
3038 igb_rxeof(rxr, cycle);
3039}
3040
3041static void
3042igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3043{
3044 struct igb_softc *sc = ifp->if_softc;
d802cc67 3045 int i, txr_cnt, rxr_cnt;
d0f59cad
SZ		 3046
3047 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3048
3049 if (info) {
f0a26983 3050 int off;
d0f59cad
SZ		 3051
3052 info->ifpi_status.status_func = igb_npoll_status;
3053 info->ifpi_status.serializer = &sc->main_serialize;
3054
d802cc67 3055 txr_cnt = igb_get_txring_inuse(sc, TRUE);
d0f59cad 3056 off = sc->tx_npoll_off;
d802cc67 3057 for (i = 0; i < txr_cnt; ++i) {
f0a26983
SZ		 3058 struct igb_tx_ring *txr = &sc->tx_rings[i];
3059 int idx = i + off;
3060
3061 KKASSERT(idx < ncpus2);
3062 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3063 info->ifpi_tx[idx].arg = txr;
3064 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3065 ifsq_set_cpuid(txr->ifsq, idx);
3066 }
d0f59cad 3067
d802cc67 3068 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
d0f59cad 3069 off = sc->rx_npoll_off;
d802cc67 3070 for (i = 0; i < rxr_cnt; ++i) {
d0f59cad
SZ		 3071 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3072 int idx = i + off;
3073
3074 KKASSERT(idx < ncpus2);
3075 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3076 info->ifpi_rx[idx].arg = rxr;
3077 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
1f7e3916 3078 }
d0f59cad
SZ		 3079
3080 if (ifp->if_flags & IFF_RUNNING) {
d802cc67
SZ		 3081 if (rxr_cnt == sc->rx_ring_inuse &&
3082 txr_cnt == sc->tx_ring_inuse)
d0f59cad
SZ		 3083 igb_disable_intr(sc);
3084 else
3085 igb_init(sc);
3086 }
d0f59cad 3087 } else {
343c1194
SZ		 3088 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3089 struct igb_tx_ring *txr = &sc->tx_rings[i];
3090
3091 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3092 }
3093
d0f59cad 3094 if (ifp->if_flags & IFF_RUNNING) {
d802cc67
SZ		 3095 txr_cnt = igb_get_txring_inuse(sc, FALSE);
3096 rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3097
3098 if (rxr_cnt == sc->rx_ring_inuse &&
3099 txr_cnt == sc->tx_ring_inuse)
d0f59cad
SZ		 3100 igb_enable_intr(sc);
3101 else
3102 igb_init(sc);
3103 }
1f7e3916
SZ		 3104 }
3105}
3106
d0f59cad 3107#endif /* IFPOLL_ENABLE */
1f7e3916
SZ		 3108
3109static void
3110igb_intr(void *xsc)
f6167a56
SZ		 3111{
3112 struct igb_softc *sc = xsc;
3113 struct ifnet *ifp = &sc->arpcom.ac_if;
3114 uint32_t eicr;
3115
7d235eb5 3116 ASSERT_SERIALIZED(&sc->main_serialize);
f6167a56
SZ		 3117
3118 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3119
3120 if (eicr == 0)
3121 return;
3122
3123 if (ifp->if_flags & IFF_RUNNING) {
f0a26983 3124 struct igb_tx_ring *txr = &sc->tx_rings[0];
7d235eb5 3125 int i;
f6167a56 3126
be922da6 3127 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ		 3128 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3129
3130 if (eicr & rxr->rx_intr_mask) {
3131 lwkt_serialize_enter(&rxr->rx_serialize);
3132 igb_rxeof(rxr, -1);
3133 lwkt_serialize_exit(&rxr->rx_serialize);
3134 }
3135 }
3136
7d235eb5
SZ		 3137 if (eicr & txr->tx_intr_mask) {
3138 lwkt_serialize_enter(&txr->tx_serialize);
3139 igb_txeof(txr);
f0a26983
SZ		 3140 if (!ifsq_is_empty(txr->ifsq))
3141 ifsq_devstart(txr->ifsq);
7d235eb5 3142 lwkt_serialize_exit(&txr->tx_serialize);
f6167a56
SZ		 3143 }
3144 }
3145
3146 if (eicr & E1000_EICR_OTHER) {
3147 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3148
3149 /* Link status change */
3150 if (icr & E1000_ICR_LSC) {
3151 sc->hw.mac.get_link_status = 1;
3152 igb_update_link_status(sc);
3153 }
3154 }
3155
3156 /*
3157 * Reading EICR has the side effect to clear interrupt mask,
3158 * so all interrupts need to be enabled here.
3159 */
3160 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3161}
3162
3163static void
9c0ecdcc 3164igb_intr_shared(void *xsc)
1f7e3916
SZ		 3165{
3166 struct igb_softc *sc = xsc;
3167 struct ifnet *ifp = &sc->arpcom.ac_if;
3168 uint32_t reg_icr;
3169
7d235eb5 3170 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ		 3171
3172 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3173
3174 /* Hot eject? */
3175 if (reg_icr == 0xffffffff)
3176 return;
3177
3178 /* Definitely not our interrupt. */
3179 if (reg_icr == 0x0)
3180 return;
3181
3182 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3183 return;
3184
3185 if (ifp->if_flags & IFF_RUNNING) {
71b8b086
SZ		 3186 if (reg_icr &
3187 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3188 int i;
7d235eb5 3189
71b8b086
SZ		 3190 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3191 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1f7e3916 3192
71b8b086
SZ		 3193 lwkt_serialize_enter(&rxr->rx_serialize);
3194 igb_rxeof(rxr, -1);
3195 lwkt_serialize_exit(&rxr->rx_serialize);
3196 }
7d235eb5
SZ		 3197 }
3198
71b8b086
SZ		 3199 if (reg_icr & E1000_ICR_TXDW) {
3200 struct igb_tx_ring *txr = &sc->tx_rings[0];
3201
3202 lwkt_serialize_enter(&txr->tx_serialize);
3203 igb_txeof(txr);
f0a26983
SZ		 3204 if (!ifsq_is_empty(txr->ifsq))
3205 ifsq_devstart(txr->ifsq);
71b8b086
SZ		 3206 lwkt_serialize_exit(&txr->tx_serialize);
3207 }
1f7e3916
SZ		 3208 }
3209
3210 /* Link status change */
3211 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3212 sc->hw.mac.get_link_status = 1;
3213 igb_update_link_status(sc);
3214 }
3215
3216 if (reg_icr & E1000_ICR_RXO)
3217 sc->rx_overruns++;
3218}
3219
1f7e3916 3220static int
871c0e2b
SZ		 3221igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3222 int *segs_used, int *idx)
1f7e3916
SZ		 3223{
3224 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3225 bus_dmamap_t map;
3226 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3227 union e1000_adv_tx_desc *txd = NULL;
3228 struct mbuf *m_head = *m_headp;
b6220144 3229 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
07e9f7c0 3230 int maxsegs, nsegs, i, j, error;
1f7e3916
SZ		 3231 uint32_t hdrlen = 0;
3232
23f6ffe4
SZ		 3233 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3234 error = igb_tso_pullup(txr, m_headp);
3235 if (error)
3236 return error;
3237 m_head = *m_headp;
3238 }
3239
1f7e3916
SZ		 3240 /* Set basic descriptor constants */
3241 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3242 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3243 if (m_head->m_flags & M_VLANTAG)
3244 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3245
3246 /*
3247 * Map the packet for DMA.
1f7e3916 3248 */
b6220144 3249 tx_buf = &txr->tx_buf[txr->next_avail_desc];
1f7e3916
SZ		 3250 tx_buf_mapped = tx_buf;
3251 map = tx_buf->map;
3252
b6220144
SZ		 3253 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3254 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
1f7e3916
SZ		 3255 if (maxsegs > IGB_MAX_SCATTER)
3256 maxsegs = IGB_MAX_SCATTER;
3257
3258 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3259 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3260 if (error) {
3261 if (error == ENOBUFS)
3262 txr->sc->mbuf_defrag_failed++;
3263 else
3264 txr->sc->no_tx_dma_setup++;
3265
3266 m_freem(*m_headp);
3267 *m_headp = NULL;
3268 return error;
3269 }
3270 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3271
3272 m_head = *m_headp;
3273
1f7e3916 3274 /*
66c68b4b
SZ		 3275 * Set up the TX context descriptor, if any hardware offloading is
3276 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3277 * TX descriptor.
3278 *
3279 * Unlike these chips' predecessors (em/emx), TX context descriptor
3280 * will _not_ interfere TX data fetching pipelining.
1f7e3916 3281 */
23f6ffe4
SZ		 3282 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3283 igb_tso_ctx(txr, m_head, &hdrlen);
3284 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3285 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3286 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3287 txr->tx_nsegs++;
871c0e2b 3288 (*segs_used)++;
23f6ffe4 3289 } else if (igb_txcsum_ctx(txr, m_head)) {
48faa653
SZ		 3290 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3291 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
1f7e3916
SZ		 3292 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3293 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
b6220144 3294 txr->tx_nsegs++;
871c0e2b 3295 (*segs_used)++;
1f7e3916 3296 }
1f7e3916 3297
871c0e2b 3298 *segs_used += nsegs;
b6220144
SZ		 3299 txr->tx_nsegs += nsegs;
3300 if (txr->tx_nsegs >= txr->intr_nsegs) {
3301 /*
3302 * Report Status (RS) is turned on every intr_nsegs
3303 * descriptors (roughly).
3304 */
3305 txr->tx_nsegs = 0;
3306 cmd_rs = E1000_ADVTXD_DCMD_RS;
3307 }
3308
1f7e3916
SZ		 3309 /* Calculate payload length */
3310 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3311 << E1000_ADVTXD_PAYLEN_SHIFT);
3312
3313 /* 82575 needs the queue index added */
3314 if (txr->sc->hw.mac.type == e1000_82575)
3315 olinfo_status |= txr->me << 4;
3316
3317 /* Set up our transmit descriptors */
3318 i = txr->next_avail_desc;
3319 for (j = 0; j < nsegs; j++) {
3320 bus_size_t seg_len;
3321 bus_addr_t seg_addr;
3322
3323 tx_buf = &txr->tx_buf[i];
3324 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3325 seg_addr = segs[j].ds_addr;
3326 seg_len = segs[j].ds_len;
3327
3328 txd->read.buffer_addr = htole64(seg_addr);
3329 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3330 txd->read.olinfo_status = htole32(olinfo_status);
91b8700a 3331 if (++i == txr->num_tx_desc)
1f7e3916
SZ		 3332 i = 0;
3333 tx_buf->m_head = NULL;
1f7e3916
SZ		 3334 }
3335
3336 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3337 txr->next_avail_desc = i;
3338 txr->tx_avail -= nsegs;
3339
3340 tx_buf->m_head = m_head;
3341 tx_buf_mapped->map = tx_buf->map;
3342 tx_buf->map = map;
3343
3344 /*
b6220144 3345 * Last Descriptor of Packet needs End Of Packet (EOP)
1f7e3916 3346 */
b6220144 3347 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
1f7e3916
SZ		 3348
3349 /*
5d94c328 3350 * Defer TDT updating, until enough descrptors are setup
1f7e3916 3351 */
871c0e2b 3352 *idx = i;
1f7e3916
SZ		 3353 ++txr->tx_packets;
3354
3355 return 0;
3356}
3357
3358static void
f0a26983 3359igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1f7e3916
SZ		 3360{
3361 struct igb_softc *sc = ifp->if_softc;
f0a26983 3362 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
1f7e3916 3363 struct mbuf *m_head;
871c0e2b 3364 int idx = -1, nsegs = 0;
1f7e3916 3365
f0a26983 3366 KKASSERT(txr->ifsq == ifsq);
7d235eb5 3367 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3368
f0a26983 3369 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1f7e3916
SZ		 3370 return;
3371
3372 if (!sc->link_active) {
f0a26983 3373 ifsq_purge(ifsq);
1f7e3916
SZ		 3374 return;
3375 }
3376
b6220144 3377 if (!IGB_IS_NOT_OACTIVE(txr))
1f7e3916
SZ		 3378 igb_txeof(txr);
3379
f0a26983 3380 while (!ifsq_is_empty(ifsq)) {
b6220144 3381 if (IGB_IS_OACTIVE(txr)) {
f0a26983 3382 ifsq_set_oactive(ifsq);
1f7e3916 3383 /* Set watchdog on */
16109efc 3384 txr->tx_watchdog.wd_timer = 5;
1f7e3916
SZ		 3385 break;
3386 }
3387
f0a26983 3388 m_head = ifsq_dequeue(ifsq, NULL);
1f7e3916
SZ		 3389 if (m_head == NULL)
3390 break;
3391
871c0e2b 3392 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
1f7e3916
SZ		 3393 ifp->if_oerrors++;
3394 continue;
3395 }
3396
871c0e2b
SZ		 3397 if (nsegs >= txr->wreg_nsegs) {
3398 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3399 idx = -1;
3400 nsegs = 0;
3401 }
3402
1f7e3916
SZ		 3403 /* Send a copy of the frame to the BPF listener */
3404 ETHER_BPF_MTAP(ifp, m_head);
3405 }
871c0e2b
SZ		 3406 if (idx >= 0)
3407 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
1f7e3916
SZ		 3408}
3409
3410static void
16109efc 3411igb_watchdog(struct ifaltq_subque *ifsq)
1f7e3916 3412{
16109efc
SZ		 3413 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3414 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1f7e3916 3415 struct igb_softc *sc = ifp->if_softc;
73397ddb 3416 int i;
1f7e3916 3417
16109efc 3418 KKASSERT(txr->ifsq == ifsq);
1f7e3916
SZ		 3419 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3420
3421 /*
3422 * If flow control has paused us since last checking
3423 * it invalidates the watchdog timing, so dont run it.
3424 */
3425 if (sc->pause_frames) {
3426 sc->pause_frames = 0;
16109efc 3427 txr->tx_watchdog.wd_timer = 5;
1f7e3916
SZ		 3428 return;
3429 }
3430
3431 if_printf(ifp, "Watchdog timeout -- resetting\n");
3432 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3433 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3434 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3435 if_printf(ifp, "TX(%d) desc avail = %d, "
3436 "Next TX to Clean = %d\n",
3437 txr->me, txr->tx_avail, txr->next_to_clean);
3438
3439 ifp->if_oerrors++;
3440 sc->watchdog_events++;
3441
3442 igb_init(sc);
d802cc67 3443 for (i = 0; i < sc->tx_ring_inuse; ++i)
73397ddb 3444 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
1f7e3916
SZ		 3445}
3446
3447static void
9c0ecdcc 3448igb_set_eitr(struct igb_softc *sc, int idx, int rate)
1f7e3916 3449{
9c0ecdcc 3450 uint32_t eitr = 0;
1f7e3916 3451
9c0ecdcc 3452 if (rate > 0) {
1f7e3916 3453 if (sc->hw.mac.type == e1000_82575) {
9c0ecdcc 3454 eitr = 1000000000 / 256 / rate;
1f7e3916
SZ		 3455 /*
3456 * NOTE:
3457 * Document is wrong on the 2 bits left shift
3458 */
3459 } else {
9c0ecdcc 3460 eitr = 1000000 / rate;
d4beffa9
SZ		 3461 eitr <<= IGB_EITR_INTVL_SHIFT;
3462 }
3463
3464 if (eitr == 0) {
3465 /* Don't disable it */
3466 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3467 } else if (eitr > IGB_EITR_INTVL_MASK) {
3468 /* Don't allow it to be too large */
3469 eitr = IGB_EITR_INTVL_MASK;
1f7e3916 3470 }
1f7e3916
SZ		 3471 }
3472 if (sc->hw.mac.type == e1000_82575)
9c0ecdcc 3473 eitr |= eitr << 16;
1f7e3916 3474 else
9c0ecdcc
SZ		 3475 eitr |= E1000_EITR_CNT_IGNR;
3476 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
1f7e3916
SZ		 3477}
3478
3479static int
3480igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3481{
3482 struct igb_softc *sc = (void *)arg1;
3483 struct ifnet *ifp = &sc->arpcom.ac_if;
3484 int error, intr_rate;
3485
3486 intr_rate = sc->intr_rate;
3487 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3488 if (error || req->newptr == NULL)
3489 return error;
3490 if (intr_rate < 0)
3491 return EINVAL;
3492
3493 ifnet_serialize_all(ifp);
3494
3495 sc->intr_rate = intr_rate;
3496 if (ifp->if_flags & IFF_RUNNING)
9c0ecdcc
SZ		 3497 igb_set_eitr(sc, 0, sc->intr_rate);
3498
3499 if (bootverbose)
3500 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
1f7e3916
SZ		 3501
3502 ifnet_deserialize_all(ifp);
3503
9c0ecdcc
SZ		 3504 return 0;
3505}
3506
3507static int
3508igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3509{
3510 struct igb_msix_data *msix = (void *)arg1;
3511 struct igb_softc *sc = msix->msix_sc;
3512 struct ifnet *ifp = &sc->arpcom.ac_if;
3513 int error, msix_rate;
3514
3515 msix_rate = msix->msix_rate;
3516 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3517 if (error || req->newptr == NULL)
3518 return error;
3519 if (msix_rate < 0)
3520 return EINVAL;
3521
3522 lwkt_serialize_enter(msix->msix_serialize);
3523
3524 msix->msix_rate = msix_rate;
3525 if (ifp->if_flags & IFF_RUNNING)
3526 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3527
3528 if (bootverbose) {
3529 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3530 msix->msix_rate);
3531 }
3532
3533 lwkt_serialize_exit(msix->msix_serialize);
3534
1f7e3916
SZ		 3535 return 0;
3536}
b6220144
SZ		 3537
3538static int
3539igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3540{
3541 struct igb_softc *sc = (void *)arg1;
3542 struct ifnet *ifp = &sc->arpcom.ac_if;
27866bf1 3543 struct igb_tx_ring *txr = &sc->tx_rings[0];
b6220144
SZ		 3544 int error, nsegs;
3545
3546 nsegs = txr->intr_nsegs;
3547 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3548 if (error || req->newptr == NULL)
3549 return error;
3550 if (nsegs <= 0)
3551 return EINVAL;
3552
3553 ifnet_serialize_all(ifp);
3554
91b8700a 3555 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
b6220144
SZ		 3556 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3557 error = EINVAL;
3558 } else {
708575bb
SZ		 3559 int i;
3560
b6220144 3561 error = 0;
708575bb
SZ		 3562 for (i = 0; i < sc->tx_ring_cnt; ++i)
3563 sc->tx_rings[i].intr_nsegs = nsegs;
b6220144
SZ		 3564 }
3565
3566 ifnet_deserialize_all(ifp);
3567
3568 return error;
3569}
f6167a56 3570
9d8e892a
SZ		 3571static int
3572igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3573{
3574 struct igb_softc *sc = (void *)arg1;
3575 struct ifnet *ifp = &sc->arpcom.ac_if;
3576 int error, nsegs, i;
3577
3578 nsegs = sc->rx_rings[0].wreg_nsegs;
3579 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3580 if (error || req->newptr == NULL)
3581 return error;
3582
3583 ifnet_serialize_all(ifp);
3584 for (i = 0; i < sc->rx_ring_cnt; ++i)
3585 sc->rx_rings[i].wreg_nsegs =nsegs;
3586 ifnet_deserialize_all(ifp);
3587
3588 return 0;
3589}
3590
708575bb
SZ		 3591static int
3592igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3593{
3594 struct igb_softc *sc = (void *)arg1;
3595 struct ifnet *ifp = &sc->arpcom.ac_if;
3596 int error, nsegs, i;
3597
3598 nsegs = sc->tx_rings[0].wreg_nsegs;
3599 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3600 if (error || req->newptr == NULL)
3601 return error;
3602
3603 ifnet_serialize_all(ifp);
3604 for (i = 0; i < sc->tx_ring_cnt; ++i)
3605 sc->tx_rings[i].wreg_nsegs =nsegs;
3606 ifnet_deserialize_all(ifp);
3607
3608 return 0;
3609}
3610
d0f59cad
SZ		 3611#ifdef IFPOLL_ENABLE
3612
3613static int
3614igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3615{
3616 struct igb_softc *sc = (void *)arg1;
3617 struct ifnet *ifp = &sc->arpcom.ac_if;
3618 int error, off;
3619
3620 off = sc->rx_npoll_off;
3621 error = sysctl_handle_int(oidp, &off, 0, req);
3622 if (error || req->newptr == NULL)
3623 return error;
3624 if (off < 0)
3625 return EINVAL;
3626
3627 ifnet_serialize_all(ifp);
3628 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3629 error = EINVAL;
3630 } else {
3631 error = 0;
3632 sc->rx_npoll_off = off;
3633 }
3634 ifnet_deserialize_all(ifp);
3635
3636 return error;
3637}
3638
3639static int
3640igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3641{
3642 struct igb_softc *sc = (void *)arg1;
3643 struct ifnet *ifp = &sc->arpcom.ac_if;
3644 int error, off;
3645
3646 off = sc->tx_npoll_off;
3647 error = sysctl_handle_int(oidp, &off, 0, req);
3648 if (error || req->newptr == NULL)
3649 return error;
3650 if (off < 0)
3651 return EINVAL;
3652
3653 ifnet_serialize_all(ifp);
d802cc67 3654 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
d0f59cad
SZ		 3655 error = EINVAL;
3656 } else {
3657 error = 0;
3658 sc->tx_npoll_off = off;
3659 }
3660 ifnet_deserialize_all(ifp);
3661
3662 return error;
3663}
3664
3665#endif /* IFPOLL_ENABLE */
3666
f6167a56
SZ		 3667static void
3668igb_init_intr(struct igb_softc *sc)
3669{
be922da6 3670 igb_set_intr_mask(sc);
9c0ecdcc
SZ		 3671
3672 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
f6167a56 3673 igb_init_unshared_intr(sc);
9c0ecdcc
SZ		 3674
3675 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3676 igb_set_eitr(sc, 0, sc->intr_rate);
3677 } else {
3678 int i;
3679
3680 for (i = 0; i < sc->msix_cnt; ++i)
3681 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3682 }
f6167a56
SZ		 3683}
3684
3685static void
3686igb_init_unshared_intr(struct igb_softc *sc)
3687{
3688 struct e1000_hw *hw = &sc->hw;
3689 const struct igb_rx_ring *rxr;
3690 const struct igb_tx_ring *txr;
3691 uint32_t ivar, index;
3692 int i;
3693
3694 /*
3695 * Enable extended mode
3696 */
3697 if (sc->hw.mac.type != e1000_82575) {
9c0ecdcc
SZ		 3698 uint32_t gpie;
3699 int ivar_max;
3700
3701 gpie = E1000_GPIE_NSICR;
3702 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3703 gpie |= E1000_GPIE_MSIX_MODE |
3704 E1000_GPIE_EIAME |
3705 E1000_GPIE_PBA;
3706 }
3707 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3708
3709 /*
3710 * Clear IVARs
3711 */
3712 switch (sc->hw.mac.type) {
3713 case e1000_82580:
3714 ivar_max = IGB_MAX_IVAR_82580;
3715 break;
3716
3717 case e1000_i350:
3718 ivar_max = IGB_MAX_IVAR_I350;
3719 break;
3720
3721 case e1000_vfadapt:
3722 case e1000_vfadapt_i350:
3723 ivar_max = IGB_MAX_IVAR_VF;
3724 break;
3725
3726 case e1000_82576:
3727 ivar_max = IGB_MAX_IVAR_82576;
3728 break;
3729
3730 default:
3731 panic("unknown mac type %d\n", sc->hw.mac.type);
3732 }
3733 for (i = 0; i < ivar_max; ++i)
3734 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3735 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
f6167a56
SZ		 3736 } else {
3737 uint32_t tmp;
3738
9c0ecdcc
SZ		 3739 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3740 ("82575 w/ MSI-X"));
f6167a56
SZ		 3741 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3742 tmp |= E1000_CTRL_EXT_IRCA;
3743 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3744 }
3745
3746 /*
3747 * Map TX/RX interrupts to EICR
3748 */
3749 switch (sc->hw.mac.type) {
3750 case e1000_82580:
3751 case e1000_i350:
3752 case e1000_vfadapt:
3753 case e1000_vfadapt_i350:
3754 /* RX entries */
be922da6 3755 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ		 3756 rxr = &sc->rx_rings[i];
3757
3758 index = i >> 1;
3759 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3760
3761 if (i & 1) {
3762 ivar &= 0xff00ffff;
3763 ivar |=
3764 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3765 } else {
3766 ivar &= 0xffffff00;
3767 ivar |=
3768 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3769 }
3770 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3771 }
3772 /* TX entries */