bfe(4): Utilize bus_dmamap_load_mbuf_segment()
[dragonfly.git] / sys / dev / netif / bfe / if_bfe.c
CommitLineData
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1/*
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
7 */
8
9/*
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
2ba09803 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
a75a1559 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
7f186839
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33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/sockio.h>
38#include <sys/mbuf.h>
39#include <sys/malloc.h>
9db4b353 40#include <sys/interrupt.h>
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41#include <sys/kernel.h>
42#include <sys/socket.h>
43#include <sys/queue.h>
1f7ab7c9
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44#include <sys/bus.h>
45#include <sys/rman.h>
0f20326f 46#include <sys/thread2.h>
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47
48#include <net/if.h>
0bf9a476 49#include <net/ifq_var.h>
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50#include <net/if_arp.h>
51#include <net/ethernet.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
54
55#include <net/bpf.h>
56
57#include <net/if_types.h>
58#include <net/vlan/if_vlan_var.h>
59
60#include <netinet/in_systm.h>
61#include <netinet/in.h>
62#include <netinet/ip.h>
63
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64#include <bus/pci/pcireg.h>
65#include <bus/pci/pcivar.h>
66#include <bus/pci/pcidevs.h>
67
68#include <dev/netif/mii_layer/mii.h>
69#include <dev/netif/mii_layer/miivar.h>
70
bd1a73d5 71#include <dev/netif/bfe/if_bfereg.h>
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72
73MODULE_DEPEND(bfe, pci, 1, 1, 1);
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74MODULE_DEPEND(bfe, miibus, 1, 1, 1);
75
76/* "controller miibus0" required. See GENERIC if you get errors here. */
77#include "miibus_if.h"
78
79#define BFE_DEVDESC_MAX 64 /* Maximum device description length */
80
81static struct bfe_type bfe_devs[] = {
82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
83 "Broadcom BCM4401 Fast Ethernet" },
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84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
85 "Broadcom BCM4401-B0 Fast Ethernet" },
bd1a73d5
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86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
87 "Broadcom BCM4402 Fast Ethernet" },
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88 { 0, 0, NULL }
89};
90
91static int bfe_probe(device_t);
92static int bfe_attach(device_t);
93static int bfe_detach(device_t);
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94static void bfe_intr(void *);
95static void bfe_start(struct ifnet *);
bd4539cc 96static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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97static void bfe_init(void *);
98static void bfe_stop(struct bfe_softc *);
99static void bfe_watchdog(struct ifnet *);
100static void bfe_shutdown(device_t);
101static void bfe_tick(void *);
102static void bfe_txeof(struct bfe_softc *);
103static void bfe_rxeof(struct bfe_softc *);
104static void bfe_set_rx_mode(struct bfe_softc *);
105static int bfe_list_rx_init(struct bfe_softc *);
fbb9cf99
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106static int bfe_newbuf(struct bfe_softc *, int, int);
107static void bfe_setup_rxdesc(struct bfe_softc *, int);
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108static void bfe_rx_ring_free(struct bfe_softc *);
109
110static void bfe_pci_setup(struct bfe_softc *, uint32_t);
111static int bfe_ifmedia_upd(struct ifnet *);
112static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113static int bfe_miibus_readreg(device_t, int, int);
114static int bfe_miibus_writereg(device_t, int, int, int);
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115static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 u_long, const int);
117static void bfe_get_config(struct bfe_softc *sc);
118static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
119static void bfe_stats_update(struct bfe_softc *);
120static void bfe_clear_stats (struct bfe_softc *);
121static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
122static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
123static int bfe_resetphy(struct bfe_softc *);
124static int bfe_setupphy(struct bfe_softc *);
125static void bfe_chip_reset(struct bfe_softc *);
126static void bfe_chip_halt(struct bfe_softc *);
127static void bfe_core_reset(struct bfe_softc *);
128static void bfe_core_disable(struct bfe_softc *);
129static int bfe_dma_alloc(device_t);
250ace3d 130static void bfe_dma_free(struct bfe_softc *);
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131static void bfe_cam_write(struct bfe_softc *, u_char *, int);
132
133static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
139
140 /* bus interface */
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
143
144 /* MII interface */
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
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147
148 { 0, 0 }
149};
150
151static driver_t bfe_driver = {
152 "bfe",
153 bfe_methods,
154 sizeof(struct bfe_softc)
155};
156
157static devclass_t bfe_devclass;
158
159DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
161
162/*
163 * Probe for a Broadcom 4401 chip.
164 */
165static int
166bfe_probe(device_t dev)
167{
168 struct bfe_type *t;
97293ee3 169 uint16_t vendor, product;
7f186839 170
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171 vendor = pci_get_vendor(dev);
172 product = pci_get_device(dev);
7f186839 173
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174 for (t = bfe_devs; t->bfe_name != NULL; t++) {
175 if (vendor == t->bfe_vid && product == t->bfe_did) {
250ace3d 176 device_set_desc(dev, t->bfe_name);
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177 return(0);
178 }
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179 }
180
181 return(ENXIO);
182}
183
184static int
185bfe_dma_alloc(device_t dev)
186{
28488fd3 187 struct bfe_softc *sc = device_get_softc(dev);
b320a7b1 188 bus_dmamem_t dmem;
96f2b7e7 189 int error, i, tx_pos = 0, rx_pos = 0;
7f186839 190
28488fd3 191 /*
884508cf
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192 * Parent tag. Apparently the chip cannot handle any DMA address
193 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
28488fd3
SZ
194 */
195 error = bus_dma_tag_create(NULL, /* parent */
884508cf
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196 1, 0, /* alignment, boundary */
197 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
45e49764 198 BUS_SPACE_MAXADDR, /* highaddr */
7f186839 199 NULL, NULL, /* filter, filterarg */
884508cf
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200 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
201 0, /* num of segments */
7f186839 202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
28488fd3 203 0, /* flags */
7f186839 204 &sc->bfe_parent_tag);
7f186839 205 if (error) {
250ace3d
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206 device_printf(dev, "could not allocate parent dma tag\n");
207 return(error);
7f186839 208 }
7f186839 209
b320a7b1
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210 /* Allocate TX ring */
211 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
213 BFE_TX_LIST_SIZE,
214 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
7f186839 215 if (error) {
b320a7b1 216 device_printf(dev, "could not allocate TX list\n");
250ace3d 217 return(error);
7f186839 218 }
b320a7b1
SZ
219 sc->bfe_tx_tag = dmem.dmem_tag;
220 sc->bfe_tx_map = dmem.dmem_map;
221 sc->bfe_tx_list = dmem.dmem_addr;
222 sc->bfe_tx_dma = dmem.dmem_busaddr;
7f186839 223
b320a7b1
SZ
224 /* Allocate RX ring */
225 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
226 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
227 BFE_RX_LIST_SIZE,
228 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
7f186839 229 if (error) {
b320a7b1 230 device_printf(dev, "could not allocate RX list\n");
250ace3d 231 return(error);
7f186839 232 }
b320a7b1
SZ
233 sc->bfe_rx_tag = dmem.dmem_tag;
234 sc->bfe_rx_map = dmem.dmem_map;
235 sc->bfe_rx_list = dmem.dmem_addr;
236 sc->bfe_rx_dma = dmem.dmem_busaddr;
7f186839 237
96f2b7e7 238 /* Tag for RX mbufs */
f7768771 239 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
28488fd3
SZ
240 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
241 NULL, NULL,
884508cf 242 MCLBYTES, 1, MCLBYTES,
b77f5f80
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243 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
244 &sc->bfe_rxbuf_tag);
7f186839 245 if (error) {
96f2b7e7 246 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
250ace3d 247 return(error);
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248 }
249
b472fecc
SZ
250 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
251 &sc->bfe_rx_tmpmap);
96f2b7e7
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252 if (error) {
253 device_printf(dev, "could not create RX mbuf tmp map\n");
254 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
255 sc->bfe_rxbuf_tag = NULL;
256 return error;
257 }
250ace3d 258
96f2b7e7 259 /* Allocate dma maps for RX list */
7f186839 260 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
b77f5f80 261 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
28488fd3 262 &sc->bfe_rx_ring[i].bfe_map);
7f186839 263 if (error) {
250ace3d 264 rx_pos = i;
7f186839 265 device_printf(dev, "cannot create DMA map for RX\n");
250ace3d 266 goto ring_fail;
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267 }
268 }
250ace3d 269 rx_pos = BFE_RX_LIST_CNT;
7f186839 270
96f2b7e7 271 /* Tag for TX mbufs */
f7768771 272 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
96f2b7e7
SZ
273 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
274 NULL, NULL,
c35e788d 275 MCLBYTES, BFE_MAXSEGS, MCLBYTES,
b77f5f80
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276 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
277 &sc->bfe_txbuf_tag);
96f2b7e7
SZ
278 if (error) {
279 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
280 return(error);
281 }
282
283 /* Allocate dmamaps for TX list */
7f186839 284 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
b77f5f80 285 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK,
28488fd3 286 &sc->bfe_tx_ring[i].bfe_map);
7f186839 287 if (error) {
250ace3d 288 tx_pos = i;
7f186839 289 device_printf(dev, "cannot create DMA map for TX\n");
250ace3d 290 goto ring_fail;
7f186839
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291 }
292 }
293
7f186839 294 return(0);
250ace3d
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295
296ring_fail:
96f2b7e7
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297 if (sc->bfe_rxbuf_tag != NULL) {
298 for (i = 0; i < rx_pos; ++i) {
299 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
300 sc->bfe_rx_ring[i].bfe_map);
301 }
302 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
303 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
304 sc->bfe_rxbuf_tag = NULL;
305 }
250ace3d 306
96f2b7e7
SZ
307 if (sc->bfe_txbuf_tag != NULL) {
308 for (i = 0; i < tx_pos; ++i) {
309 bus_dmamap_destroy(sc->bfe_txbuf_tag,
310 sc->bfe_tx_ring[i].bfe_map);
311 }
312 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
313 sc->bfe_txbuf_tag = NULL;
314 }
250ace3d 315 return error;
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316}
317
318static int
319bfe_attach(device_t dev)
320{
321 struct ifnet *ifp;
322 struct bfe_softc *sc;
50b872f3 323 int error = 0, rid;
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324
325 sc = device_get_softc(dev);
326
7f186839 327 sc->bfe_dev = dev;
7fa4e3c3 328 callout_init(&sc->bfe_stat_timer);
7f186839 329
9db4b353 330#ifndef BURN_BRIDGES
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331 /*
332 * Handle power management nonsense.
333 */
334 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
335 uint32_t membase, irq;
336
337 /* Save important PCI config data. */
338 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
339 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
340
341 /* Reset the power state. */
0e17b030 342 device_printf(dev, "chip is in D%d power mode"
50b872f3 343 " -- setting to D0\n", pci_get_powerstate(dev));
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344
345 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
346
347 /* Restore PCI config data. */
348 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
349 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
350 }
9db4b353 351#endif /* !BURN_BRIDGE */
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352
353 /*
354 * Map control/status registers.
355 */
356 pci_enable_busmaster(dev);
357
358 rid = BFE_PCI_MEMLO;
4e6d744d
JS
359 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
360 RF_ACTIVE);
7f186839 361 if (sc->bfe_res == NULL) {
50b872f3 362 device_printf(dev, "couldn't map memory\n");
250ace3d 363 return ENXIO;
7f186839
JS
364 }
365
366 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
367 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
368
369 /* Allocate interrupt */
370 rid = 0;
371
4e6d744d
JS
372 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
373 RF_SHAREABLE | RF_ACTIVE);
7f186839 374 if (sc->bfe_irq == NULL) {
50b872f3 375 device_printf(dev, "couldn't map interrupt\n");
7f186839
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376 error = ENXIO;
377 goto fail;
378 }
379
250ace3d
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380 error = bfe_dma_alloc(dev);
381 if (error != 0) {
50b872f3 382 device_printf(dev, "failed to allocate DMA resources\n");
7f186839
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383 goto fail;
384 }
385
386 /* Set up ifnet structure */
387 ifp = &sc->arpcom.ac_if;
388 ifp->if_softc = sc;
389 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
391 ifp->if_ioctl = bfe_ioctl;
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392 ifp->if_start = bfe_start;
393 ifp->if_watchdog = bfe_watchdog;
394 ifp->if_init = bfe_init;
395 ifp->if_mtu = ETHERMTU;
0e557a3c
JS
396 ifp->if_baudrate = 100000000;
397 ifp->if_capabilities |= IFCAP_VLAN_MTU;
398 ifp->if_capenable |= IFCAP_VLAN_MTU;
399 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
0bf9a476
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400 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
401 ifq_set_ready(&ifp->if_snd);
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402
403 bfe_get_config(sc);
404
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405 /* Reset the chip and turn on the PHY */
406 bfe_chip_reset(sc);
407
408 if (mii_phy_probe(dev, &sc->bfe_miibus,
409 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
50b872f3 410 device_printf(dev, "MII without any PHY!\n");
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411 error = ENXIO;
412 goto fail;
413 }
414
78195a76 415 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
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416
417 /*
418 * Hook interrupt last to avoid having to lock softc
419 */
95893fe4 420 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
78195a76
MD
421 bfe_intr, sc, &sc->bfe_intrhand,
422 sc->arpcom.ac_if.if_serializer);
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423
424 if (error) {
0f20326f 425 ether_ifdetach(ifp);
50b872f3 426 device_printf(dev, "couldn't set up irq\n");
7f186839
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427 goto fail;
428 }
9db4b353
SZ
429
430 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
431 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
250ace3d 432 return 0;
7f186839 433fail:
250ace3d 434 bfe_detach(dev);
7f186839
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435 return(error);
436}
437
438static int
439bfe_detach(device_t dev)
440{
0f20326f
JS
441 struct bfe_softc *sc = device_get_softc(dev);
442 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 443
7f186839 444 if (device_is_attached(dev)) {
cdf89432 445 lwkt_serialize_enter(ifp->if_serializer);
7f186839 446 bfe_stop(sc);
250ace3d 447 bfe_chip_reset(sc);
cdf89432
SZ
448 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
449 lwkt_serialize_exit(ifp->if_serializer);
450
451 ether_ifdetach(ifp);
7f186839 452 }
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JS
453 if (sc->bfe_miibus != NULL)
454 device_delete_child(dev, sc->bfe_miibus);
0f20326f 455 bus_generic_detach(dev);
7f186839 456
250ace3d
JS
457 if (sc->bfe_irq != NULL)
458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
459
460 if (sc->bfe_res != NULL) {
461 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
462 sc->bfe_res);
463 }
250ace3d 464 bfe_dma_free(sc);
cdf89432 465
7f186839
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466 return(0);
467}
468
469/*
470 * Stop all chip I/O so that the kernel's probe routines don't
471 * get confused by errant DMAs when rebooting.
472 */
473static void
474bfe_shutdown(device_t dev)
475{
0f20326f 476 struct bfe_softc *sc = device_get_softc(dev);
78195a76 477 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 478
78195a76 479 lwkt_serialize_enter(ifp->if_serializer);
7f186839 480 bfe_stop(sc);
78195a76 481 lwkt_serialize_exit(ifp->if_serializer);
7f186839
JS
482}
483
484static int
485bfe_miibus_readreg(device_t dev, int phy, int reg)
486{
487 struct bfe_softc *sc;
488 uint32_t ret;
489
490 sc = device_get_softc(dev);
491 if (phy != sc->bfe_phyaddr)
492 return(0);
493 bfe_readphy(sc, reg, &ret);
494
495 return(ret);
496}
497
498static int
499bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
500{
501 struct bfe_softc *sc;
502
503 sc = device_get_softc(dev);
504 if (phy != sc->bfe_phyaddr)
505 return(0);
506 bfe_writephy(sc, reg, val);
507
508 return(0);
509}
510
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511static void
512bfe_tx_ring_free(struct bfe_softc *sc)
513{
514 int i;
515
28488fd3 516 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
7f186839 517 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
c35e788d
SZ
518 bus_dmamap_unload(sc->bfe_txbuf_tag,
519 sc->bfe_tx_ring[i].bfe_map);
7f186839
JS
520 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
521 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
7f186839 522 }
28488fd3 523 }
7f186839 524 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
28488fd3 525 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
526}
527
528static void
529bfe_rx_ring_free(struct bfe_softc *sc)
530{
531 int i;
532
28488fd3 533 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
7f186839 534 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
96f2b7e7 535 bus_dmamap_unload(sc->bfe_rxbuf_tag,
7f186839 536 sc->bfe_rx_ring[i].bfe_map);
28488fd3
SZ
537 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
538 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
7f186839 539 }
28488fd3 540 }
7f186839 541 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
28488fd3 542 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
543}
544
7f186839
JS
545static int
546bfe_list_rx_init(struct bfe_softc *sc)
547{
fbb9cf99 548 int i, error;
7f186839 549
fbb9cf99
SZ
550 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
551 error = bfe_newbuf(sc, i, 1);
552 if (error)
553 return(error);
554 }
7f186839 555
28488fd3 556 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
557 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
558
559 sc->bfe_rx_cons = 0;
560
561 return(0);
562}
563
564static int
fbb9cf99
SZ
565bfe_newbuf(struct bfe_softc *sc, int c, int init)
566{
567 struct bfe_data *r;
568 bus_dmamap_t map;
569 bus_dma_segment_t seg;
fbb9cf99 570 struct mbuf *m;
5ae4196e 571 int error, nsegs;
fbb9cf99
SZ
572
573 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
574 if (m == NULL)
575 return ENOBUFS;
576 m->m_len = m->m_pkthdr.len = MCLBYTES;
577
5ae4196e
SZ
578 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag,
579 sc->bfe_rx_tmpmap, m,
580 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
581 if (error) {
fbb9cf99 582 m_freem(m);
fbb9cf99
SZ
583 if (init)
584 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
585 return error;
586 }
587
588 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
589 r = &sc->bfe_rx_ring[c];
590
591 if (r->bfe_mbuf != NULL)
592 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
593
594 map = r->bfe_map;
595 r->bfe_map = sc->bfe_rx_tmpmap;
596 sc->bfe_rx_tmpmap = map;
597
598 r->bfe_mbuf = m;
599 r->bfe_paddr = seg.ds_addr;
600
601 bfe_setup_rxdesc(sc, c);
602 return 0;
603}
604
605static void
606bfe_setup_rxdesc(struct bfe_softc *sc, int c)
7f186839
JS
607{
608 struct bfe_rxheader *rx_header;
fbb9cf99 609 struct mbuf *m;
7f186839
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610 struct bfe_desc *d;
611 struct bfe_data *r;
612 uint32_t ctrl;
613
fbb9cf99
SZ
614 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
615 r = &sc->bfe_rx_ring[c];
616 d = &sc->bfe_rx_list[c];
7f186839 617
fbb9cf99 618 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
7f186839 619
fbb9cf99 620 m = r->bfe_mbuf;
7f186839
JS
621 rx_header = mtod(m, struct bfe_rxheader *);
622 rx_header->len = 0;
623 rx_header->flags = 0;
96f2b7e7 624 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
625
626 ctrl = ETHER_MAX_LEN + 32;
fbb9cf99 627 if (c == BFE_RX_LIST_CNT - 1)
7f186839
JS
628 ctrl |= BFE_DESC_EOT;
629
fbb9cf99 630 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
7f186839 631 d->bfe_ctrl = ctrl;
28488fd3 632 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
633}
634
635static void
636bfe_get_config(struct bfe_softc *sc)
637{
638 uint8_t eeprom[128];
639
640 bfe_read_eeprom(sc, eeprom);
641
642 sc->arpcom.ac_enaddr[0] = eeprom[79];
643 sc->arpcom.ac_enaddr[1] = eeprom[78];
644 sc->arpcom.ac_enaddr[2] = eeprom[81];
645 sc->arpcom.ac_enaddr[3] = eeprom[80];
646 sc->arpcom.ac_enaddr[4] = eeprom[83];
647 sc->arpcom.ac_enaddr[5] = eeprom[82];
648
649 sc->bfe_phyaddr = eeprom[90] & 0x1f;
650 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
651
652 sc->bfe_core_unit = 0;
653 sc->bfe_dma_offset = BFE_PCI_DMA;
654}
655
656static void
657bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
658{
659 uint32_t bar_orig, pci_rev, val;
660
661 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
662 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
663 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
664
665 val = CSR_READ_4(sc, BFE_SBINTVEC);
666 val |= cores;
667 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
668
669 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
670 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
671 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
672
673 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
674}
675
676static void
677bfe_clear_stats(struct bfe_softc *sc)
678{
679 u_long reg;
7f186839 680
7f186839
JS
681 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
682 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
683 CSR_READ_4(sc, reg);
684 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
685 CSR_READ_4(sc, reg);
7f186839
JS
686}
687
688static int
689bfe_resetphy(struct bfe_softc *sc)
690{
691 uint32_t val;
7f186839 692
7f186839
JS
693 bfe_writephy(sc, 0, BMCR_RESET);
694 DELAY(100);
695 bfe_readphy(sc, 0, &val);
696 if (val & BMCR_RESET) {
50b872f3
JS
697 if_printf(&sc->arpcom.ac_if,
698 "PHY Reset would not complete.\n");
7f186839
JS
699 return(ENXIO);
700 }
7f186839
JS
701 return(0);
702}
703
704static void
705bfe_chip_halt(struct bfe_softc *sc)
706{
7f186839
JS
707 /* disable interrupts - not that it actually does..*/
708 CSR_WRITE_4(sc, BFE_IMASK, 0);
709 CSR_READ_4(sc, BFE_IMASK);
710
711 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
712 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
713
714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
715 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
716 DELAY(10);
7f186839
JS
717}
718
719static void
720bfe_chip_reset(struct bfe_softc *sc)
721{
722 uint32_t val;
7f186839 723
7f186839
JS
724 /* Set the interrupt vector for the enet core */
725 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
726
727 /* is core up? */
728 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
729 if (val == BFE_CLOCK) {
730 /* It is, so shut it down */
731 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
733 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
734 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
735 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
736 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
737 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
738 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
40be5c8e 739 sc->bfe_rx_cons = 0;
7f186839
JS
740 }
741
742 bfe_core_reset(sc);
743 bfe_clear_stats(sc);
744
745 /*
746 * We want the phy registers to be accessible even when
747 * the driver is "downed" so initialize MDC preamble, frequency,
748 * and whether internal or external phy here.
749 */
750
751 /* 4402 has 62.5Mhz SB clock and internal phy */
752 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
753
754 /* Internal or external PHY? */
755 val = CSR_READ_4(sc, BFE_DEVCTRL);
756 if (!(val & BFE_IPP))
757 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
758 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
759 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
760 DELAY(100);
761 }
762
1bcc3431
JS
763 /* Enable CRC32 generation and set proper LED modes */
764 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
765
766 /* Reset or clear powerdown control bit */
767 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
768
7f186839
JS
769 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
770 BFE_LAZY_FC_MASK));
771
772 /*
773 * We don't want lazy interrupts, so just send them at the end of a
774 * frame, please
775 */
776 BFE_OR(sc, BFE_RCV_LAZY, 0);
777
778 /* Set max lengths, accounting for VLAN tags */
779 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
780 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
781
782 /* Set watermark XXX - magic */
783 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
784
785 /*
786 * Initialise DMA channels - not forgetting dma addresses need to be
787 * added to BFE_PCI_DMA
788 */
789 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
790 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
791
792 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
793 BFE_RX_CTRL_ENABLE);
794 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
795
796 bfe_resetphy(sc);
797 bfe_setupphy(sc);
7f186839
JS
798}
799
800static void
801bfe_core_disable(struct bfe_softc *sc)
802{
803 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
804 return;
805
806 /*
807 * Set reject, wait for it set, then wait for the core to stop being busy
808 * Then set reset and reject and enable the clocks
809 */
810 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
811 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
812 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
814 BFE_RESET));
815 CSR_READ_4(sc, BFE_SBTMSLOW);
816 DELAY(10);
817 /* Leave reset and reject set */
818 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
819 DELAY(10);
820}
821
822static void
823bfe_core_reset(struct bfe_softc *sc)
824{
825 uint32_t val;
826
827 /* Disable the core */
828 bfe_core_disable(sc);
829
830 /* and bring it back up */
831 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
832 CSR_READ_4(sc, BFE_SBTMSLOW);
833 DELAY(10);
834
835 /* Chip bug, clear SERR, IB and TO if they are set. */
836 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
837 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
838 val = CSR_READ_4(sc, BFE_SBIMSTATE);
839 if (val & (BFE_IBE | BFE_TO))
840 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
841
842 /* Clear reset and allow it to move through the core */
843 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
844 CSR_READ_4(sc, BFE_SBTMSLOW);
845 DELAY(10);
846
847 /* Leave the clock set */
848 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
849 CSR_READ_4(sc, BFE_SBTMSLOW);
850 DELAY(10);
851}
852
853static void
854bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
855{
856 uint32_t val;
857
858 val = ((uint32_t) data[2]) << 24;
859 val |= ((uint32_t) data[3]) << 16;
860 val |= ((uint32_t) data[4]) << 8;
861 val |= ((uint32_t) data[5]);
862 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
863 val = (BFE_CAM_HI_VALID |
864 (((uint32_t) data[0]) << 8) |
865 (((uint32_t) data[1])));
866 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
867 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1bcc3431 868 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
7f186839
JS
869 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
870}
871
872static void
873bfe_set_rx_mode(struct bfe_softc *sc)
874{
875 struct ifnet *ifp = &sc->arpcom.ac_if;
faeb7d30 876 struct ifmultiaddr *ifma;
7f186839
JS
877 uint32_t val;
878 int i = 0;
879
880 val = CSR_READ_4(sc, BFE_RXCONF);
881
882 if (ifp->if_flags & IFF_PROMISC)
883 val |= BFE_RXCONF_PROMISC;
884 else
885 val &= ~BFE_RXCONF_PROMISC;
886
887 if (ifp->if_flags & IFF_BROADCAST)
888 val &= ~BFE_RXCONF_DBCAST;
889 else
890 val |= BFE_RXCONF_DBCAST;
891
892
893 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
894 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
895
faeb7d30
JS
896 if (ifp->if_flags & IFF_ALLMULTI) {
897 val |= BFE_RXCONF_ALLMULTI;
898 } else {
899 val &= ~BFE_RXCONF_ALLMULTI;
900 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
901 if (ifma->ifma_addr->sa_family != AF_LINK)
902 continue;
903 bfe_cam_write(sc,
904 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
905 }
906 }
907
7f186839
JS
908 CSR_WRITE_4(sc, BFE_RXCONF, val);
909 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
910}
911
7f186839 912static void
250ace3d 913bfe_dma_free(struct bfe_softc *sc)
7f186839 914{
96f2b7e7
SZ
915 int i;
916
7f186839
JS
917 if (sc->bfe_tx_tag != NULL) {
918 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
250ace3d
JS
919 if (sc->bfe_tx_list != NULL) {
920 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
921 sc->bfe_tx_map);
922 sc->bfe_tx_list = NULL;
923 }
7f186839
JS
924 bus_dma_tag_destroy(sc->bfe_tx_tag);
925 sc->bfe_tx_tag = NULL;
926 }
927
928 if (sc->bfe_rx_tag != NULL) {
929 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
250ace3d
JS
930 if (sc->bfe_rx_list != NULL) {
931 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
932 sc->bfe_rx_map);
933 sc->bfe_rx_list = NULL;
934 }
7f186839
JS
935 bus_dma_tag_destroy(sc->bfe_rx_tag);
936 sc->bfe_rx_tag = NULL;
937 }
938
96f2b7e7 939 if (sc->bfe_txbuf_tag != NULL) {
7f186839 940 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
96f2b7e7 941 bus_dmamap_destroy(sc->bfe_txbuf_tag,
7f186839
JS
942 sc->bfe_tx_ring[i].bfe_map);
943 }
96f2b7e7
SZ
944 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
945 sc->bfe_txbuf_tag = NULL;
946 }
947
948 if (sc->bfe_rxbuf_tag != NULL) {
250ace3d 949 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
96f2b7e7 950 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
250ace3d
JS
951 sc->bfe_rx_ring[i].bfe_map);
952 }
96f2b7e7
SZ
953 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
954 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
955 sc->bfe_rxbuf_tag = NULL;
7f186839
JS
956 }
957
250ace3d 958 if (sc->bfe_parent_tag != NULL) {
7f186839 959 bus_dma_tag_destroy(sc->bfe_parent_tag);
250ace3d
JS
960 sc->bfe_parent_tag = NULL;
961 }
7f186839
JS
962}
963
964static void
965bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
966{
967 long i;
968 uint16_t *ptr = (uint16_t *)data;
969
970 for (i = 0; i < 128; i += 2)
971 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
972}
973
974static int
975bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
976 u_long timeout, const int clear)
977{
978 u_long i;
979
980 for (i = 0; i < timeout; i++) {
981 uint32_t val = CSR_READ_4(sc, reg);
982
983 if (clear && !(val & bit))
984 break;
985 if (!clear && (val & bit))
986 break;
987 DELAY(10);
988 }
989 if (i == timeout) {
50b872f3
JS
990 if_printf(&sc->arpcom.ac_if,
991 "BUG! Timeout waiting for bit %08x of register "
992 "%x to %s.\n", bit, reg,
993 (clear ? "clear" : "set"));
7f186839
JS
994 return -1;
995 }
996 return 0;
997}
998
999static int
1000bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1001{
1002 int err;
7f186839 1003
7f186839
JS
1004 /* Clear MII ISR */
1005 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1006 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1007 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1008 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1009 (reg << BFE_MDIO_RA_SHIFT) |
1010 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1011 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1012 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
7f186839
JS
1013 return(err);
1014}
1015
1016static int
1017bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1018{
1019 int status;
7f186839 1020
7f186839
JS
1021 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1022 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1023 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1024 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1025 (reg << BFE_MDIO_RA_SHIFT) |
1026 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1027 (val & BFE_MDIO_DATA_DATA)));
1028 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1029
7f186839
JS
1030 return status;
1031}
1032
1033/*
1034 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1035 * twice
1036 */
1037static int
1038bfe_setupphy(struct bfe_softc *sc)
1039{
1040 uint32_t val;
7f186839 1041
7f186839
JS
1042 /* Enable activity LED */
1043 bfe_readphy(sc, 26, &val);
1044 bfe_writephy(sc, 26, val & 0x7fff);
1045 bfe_readphy(sc, 26, &val);
1046
1047 /* Enable traffic meter LED mode */
1048 bfe_readphy(sc, 27, &val);
1049 bfe_writephy(sc, 27, val | (1 << 6));
1050
7f186839
JS
1051 return(0);
1052}
1053
1054static void
1055bfe_stats_update(struct bfe_softc *sc)
1056{
1057 u_long reg;
1058 uint32_t *val;
1059
1060 val = &sc->bfe_hwstats.tx_good_octets;
1061 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1062 *val++ += CSR_READ_4(sc, reg);
1063 val = &sc->bfe_hwstats.rx_good_octets;
1064 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1065 *val++ += CSR_READ_4(sc, reg);
1066}
1067
1068static void
1069bfe_txeof(struct bfe_softc *sc)
1070{
0f20326f 1071 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839
JS
1072 uint32_t i, chipidx;
1073
7f186839
JS
1074 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1075 chipidx /= sizeof(struct bfe_desc);
1076
1077 i = sc->bfe_tx_cons;
c35e788d 1078
7f186839
JS
1079 /* Go through the mbufs and free those that have been transmitted */
1080 while (i != chipidx) {
1081 struct bfe_data *r = &sc->bfe_tx_ring[i];
28488fd3 1082
7f186839
JS
1083 if (r->bfe_mbuf != NULL) {
1084 ifp->if_opackets++;
c35e788d 1085 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
7f186839
JS
1086 m_freem(r->bfe_mbuf);
1087 r->bfe_mbuf = NULL;
7f186839 1088 }
c35e788d
SZ
1089
1090 KKASSERT(sc->bfe_tx_cnt > 0);
7f186839
JS
1091 sc->bfe_tx_cnt--;
1092 BFE_INC(i, BFE_TX_LIST_CNT);
1093 }
1094
1095 if (i != sc->bfe_tx_cons) {
7f186839 1096 sc->bfe_tx_cons = i;
c35e788d
SZ
1097
1098 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT)
1099 ifp->if_flags &= ~IFF_OACTIVE;
7f186839
JS
1100 }
1101 if (sc->bfe_tx_cnt == 0)
1102 ifp->if_timer = 0;
7f186839
JS
1103}
1104
1105/* Pass a received packet up the stack */
1106static void
1107bfe_rxeof(struct bfe_softc *sc)
1108{
0f20326f 1109 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1110 struct mbuf *m;
7f186839
JS
1111 struct bfe_rxheader *rxheader;
1112 struct bfe_data *r;
1113 uint32_t cons, status, current, len, flags;
f9142ddd 1114 struct mbuf_chain chain[MAXCPU];
7f186839 1115
7f186839
JS
1116 cons = sc->bfe_rx_cons;
1117 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1118 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1119
f9142ddd 1120 ether_input_chain_init(chain);
f9142ddd 1121
7f186839
JS
1122 while (current != cons) {
1123 r = &sc->bfe_rx_ring[cons];
fbb9cf99
SZ
1124 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1125 BUS_DMASYNC_POSTREAD);
1126
1127 KKASSERT(r->bfe_mbuf != NULL);
7f186839
JS
1128 m = r->bfe_mbuf;
1129 rxheader = mtod(m, struct bfe_rxheader*);
fbb9cf99 1130 len = rxheader->len - ETHER_CRC_LEN;
7f186839
JS
1131 flags = rxheader->flags;
1132
7f186839 1133 /* flag an error and try again */
fbb9cf99 1134 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
7f186839
JS
1135 ifp->if_ierrors++;
1136 if (flags & BFE_RX_FLAG_SERR)
1137 ifp->if_collisions++;
fbb9cf99
SZ
1138
1139 bfe_setup_rxdesc(sc, cons);
2ba09803 1140 BFE_INC(cons, BFE_RX_LIST_CNT);
7f186839
JS
1141 continue;
1142 }
1143
1144 /* Go past the rx header */
fbb9cf99
SZ
1145 if (bfe_newbuf(sc, cons, 0) != 0) {
1146 bfe_setup_rxdesc(sc, cons);
7f186839 1147 ifp->if_ierrors++;
fbb9cf99 1148 BFE_INC(cons, BFE_RX_LIST_CNT);
7f186839
JS
1149 continue;
1150 }
1151
3013ac0e
JS
1152 m_adj(m, BFE_RX_OFFSET);
1153 m->m_len = m->m_pkthdr.len = len;
1154
7f186839
JS
1155 ifp->if_ipackets++;
1156 m->m_pkthdr.rcvif = ifp;
1157
50098e2e 1158 ether_input_chain(ifp, m, chain);
7f186839
JS
1159 BFE_INC(cons, BFE_RX_LIST_CNT);
1160 }
f9142ddd 1161
f9142ddd 1162 ether_input_dispatch(chain);
f9142ddd 1163
7f186839 1164 sc->bfe_rx_cons = cons;
7f186839
JS
1165}
1166
1167static void
1168bfe_intr(void *xsc)
1169{
1170 struct bfe_softc *sc = xsc;
0f20326f 1171 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1172 uint32_t istat, imask, flag;
7f186839 1173
7f186839
JS
1174 istat = CSR_READ_4(sc, BFE_ISTAT);
1175 imask = CSR_READ_4(sc, BFE_IMASK);
1176
1177 /*
1178 * Defer unsolicited interrupts - This is necessary because setting the
1179 * chips interrupt mask register to 0 doesn't actually stop the
1180 * interrupts
1181 */
1182 istat &= imask;
1183 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1184 CSR_READ_4(sc, BFE_ISTAT);
1185
1186 /* not expecting this interrupt, disregard it */
1187 if (istat == 0) {
7f186839
JS
1188 return;
1189 }
1190
1191 if (istat & BFE_ISTAT_ERRORS) {
1192 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1193 if (flag & BFE_STAT_EMASK)
1194 ifp->if_oerrors++;
1195
1196 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1197 if (flag & BFE_RX_FLAG_ERRORS)
1198 ifp->if_ierrors++;
1199
1200 ifp->if_flags &= ~IFF_RUNNING;
1201 bfe_init(sc);
1202 }
1203
1204 /* A packet was received */
1205 if (istat & BFE_ISTAT_RX)
1206 bfe_rxeof(sc);
1207
1208 /* A packet was sent */
1209 if (istat & BFE_ISTAT_TX)
1210 bfe_txeof(sc);
1211
1212 /* We have packets pending, fire them out */
0bf9a476 1213 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
9db4b353 1214 if_devstart(ifp);
7f186839
JS
1215}
1216
1217static int
28488fd3 1218bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
7f186839 1219{
c35e788d 1220 struct mbuf *m = *m_head;
c35e788d
SZ
1221 bus_dma_segment_t segs[BFE_MAXSEGS];
1222 bus_dmamap_t map;
5ae4196e 1223 int i, first_idx, last_idx, cur, error, maxsegs, nsegs;
c35e788d
SZ
1224
1225 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT);
1226 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC;
1227 if (maxsegs > BFE_MAXSEGS)
1228 maxsegs = BFE_MAXSEGS;
1229
1230 first_idx = *txidx;
1231 map = sc->bfe_tx_ring[first_idx].bfe_map;
1232
5ae4196e
SZ
1233 error = bus_dmamap_load_mbuf_segment(sc->bfe_txbuf_tag, map, m,
1234 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
c35e788d 1235 if (error && error != EFBIG)
b77f5f80 1236 goto fail;
c35e788d
SZ
1237 if (error) { /* error == EFBIG */
1238 struct mbuf *m_new;
1239
1240 m_new = m_defrag(m, MB_DONTWAIT);
1241 if (m_new == NULL) {
b77f5f80
SZ
1242 error = ENOBUFS;
1243 goto fail;
c35e788d
SZ
1244 } else {
1245 *m_head = m = m_new;
1246 }
28488fd3 1247
5ae4196e
SZ
1248 error = bus_dmamap_load_mbuf_segment(sc->bfe_txbuf_tag, map, m,
1249 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1250 if (error)
b77f5f80 1251 goto fail;
28488fd3 1252 }
c35e788d
SZ
1253 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1254
1255 last_idx = -1;
1256 cur = first_idx;
5ae4196e 1257 for (i = 0; i < nsegs; ++i) {
c35e788d
SZ
1258 struct bfe_desc *d;
1259 uint32_t ctrl;
1260
1261 ctrl = BFE_DESC_LEN & segs[i].ds_len;
1262 ctrl |= BFE_DESC_IOC; /* always interrupt */
1263 if (cur == BFE_TX_LIST_CNT - 1) {
1264 /*
1265 * Tell the chip to wrap to the
1266 * start of the descriptor list.
1267 */
1268 ctrl |= BFE_DESC_EOT;
1269 }
7f186839 1270
c35e788d
SZ
1271 d = &sc->bfe_tx_list[cur];
1272 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA;
1273 d->bfe_ctrl = ctrl;
28488fd3 1274
c35e788d
SZ
1275 last_idx = cur;
1276 BFE_INC(cur, BFE_TX_LIST_CNT);
1277 }
1278 KKASSERT(last_idx >= 0);
7f186839 1279
c35e788d
SZ
1280 /* End of the frame */
1281 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF;
7f186839 1282
c35e788d
SZ
1283 /*
1284 * Set start of the frame on the first fragment,
1285 * _after_ all of the fragments are setup.
1286 */
1287 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF;
1288
1289 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map;
1290 sc->bfe_tx_ring[last_idx].bfe_map = map;
1291 sc->bfe_tx_ring[last_idx].bfe_mbuf = m;
7f186839 1292
28488fd3 1293 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
1294
1295 *txidx = cur;
5ae4196e 1296 sc->bfe_tx_cnt += nsegs;
c35e788d 1297 return 0;
b77f5f80
SZ
1298fail:
1299 m_freem(m);
1300 *m_head = NULL;
1301 return error;
7f186839
JS
1302}
1303
1304/*
1305 * Set up to transmit a packet
1306 */
1307static void
1308bfe_start(struct ifnet *ifp)
1309{
0f20326f 1310 struct bfe_softc *sc = ifp->if_softc;
7f186839 1311 struct mbuf *m_head = NULL;
efb8ae81 1312 int idx, need_trans;
7f186839 1313
603a5653
SZ
1314 ASSERT_SERIALIZED(ifp->if_serializer);
1315
7f186839 1316 /*
efb8ae81
JS
1317 * Not much point trying to send if the link is down
1318 * or we have nothing to send.
7f186839 1319 */
9db4b353
SZ
1320 if (!sc->bfe_link) {
1321 ifq_purge(&ifp->if_snd);
7f186839 1322 return;
9db4b353 1323 }
7f186839 1324
78195a76 1325 if (ifp->if_flags & IFF_OACTIVE)
7f186839 1326 return;
7f186839 1327
0f20326f
JS
1328 idx = sc->bfe_tx_prod;
1329
efb8ae81 1330 need_trans = 0;
c35e788d
SZ
1331 while (!ifq_is_empty(&ifp->if_snd)) {
1332 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) {
28488fd3
SZ
1333 ifp->if_flags |= IFF_OACTIVE;
1334 break;
1335 }
1336
1337 m_head = ifq_dequeue(&ifp->if_snd, NULL);
7f186839
JS
1338 if (m_head == NULL)
1339 break;
1340
1341 /*
efb8ae81
JS
1342 * Pack the data into the tx ring. If we don't have
1343 * enough room, let the chip drain the ring.
7f186839 1344 */
28488fd3 1345 if (bfe_encap(sc, &m_head, &idx)) {
b77f5f80
SZ
1346 /* m_head is freed by re_encap(), if we reach here */
1347 ifp->if_oerrors++;
1348
1349 if (sc->bfe_tx_cnt > 0) {
1350 ifp->if_flags |= IFF_OACTIVE;
1351 break;
1352 } else {
1353 /*
1354 * IFF_OACTIVE could not be set under
1355 * this situation, since except up/down,
1356 * nothing will clear IFF_OACTIVE.
1357 *
1358 * Let's just keep draining the ifq ...
1359 */
1360 continue;
1361 }
7f186839 1362 }
efb8ae81 1363 need_trans = 1;
7f186839
JS
1364
1365 /*
1366 * If there's a BPF listener, bounce a copy of this frame
1367 * to him.
1368 */
1369 BPF_MTAP(ifp, m_head);
1370 }
1371
78195a76 1372 if (!need_trans)
efb8ae81 1373 return;
efb8ae81 1374
7f186839 1375 sc->bfe_tx_prod = idx;
c35e788d 1376
7f186839
JS
1377 /* Transmit - twice due to apparent hardware bug */
1378 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1379 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1380
1381 /*
1382 * Set a timeout in case the chip goes out to lunch.
1383 */
1384 ifp->if_timer = 5;
7f186839
JS
1385}
1386
1387static void
1388bfe_init(void *xsc)
1389{
1390 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1391 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1392
603a5653
SZ
1393 ASSERT_SERIALIZED(ifp->if_serializer);
1394
78195a76 1395 if (ifp->if_flags & IFF_RUNNING)
7f186839 1396 return;
7f186839
JS
1397
1398 bfe_stop(sc);
1399 bfe_chip_reset(sc);
1400
1401 if (bfe_list_rx_init(sc) == ENOBUFS) {
50b872f3
JS
1402 if_printf(ifp, "bfe_init failed. "
1403 " Not enough memory for list buffers\n");
7f186839
JS
1404 bfe_stop(sc);
1405 return;
1406 }
1407
1408 bfe_set_rx_mode(sc);
1409
1410 /* Enable the chip and core */
1411 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1412 /* Enable interrupts */
1413 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1414
1415 bfe_ifmedia_upd(ifp);
1416 ifp->if_flags |= IFF_RUNNING;
1417 ifp->if_flags &= ~IFF_OACTIVE;
1418
7fa4e3c3 1419 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
7f186839
JS
1420}
1421
1422/*
1423 * Set media options.
1424 */
1425static int
1426bfe_ifmedia_upd(struct ifnet *ifp)
1427{
0f20326f 1428 struct bfe_softc *sc = ifp->if_softc;
7f186839 1429 struct mii_data *mii;
7f186839 1430
603a5653
SZ
1431 ASSERT_SERIALIZED(ifp->if_serializer);
1432
7f186839
JS
1433 mii = device_get_softc(sc->bfe_miibus);
1434 sc->bfe_link = 0;
1435 if (mii->mii_instance) {
1436 struct mii_softc *miisc;
1437 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1438 miisc = LIST_NEXT(miisc, mii_list))
1439 mii_phy_reset(miisc);
1440 }
1441 mii_mediachg(mii);
1442
9e61439d
SZ
1443 bfe_setupphy(sc);
1444
7f186839
JS
1445 return(0);
1446}
1447
1448/*
1449 * Report current media status.
1450 */
1451static void
1452bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1453{
1454 struct bfe_softc *sc = ifp->if_softc;
1455 struct mii_data *mii;
7f186839 1456
603a5653
SZ
1457 ASSERT_SERIALIZED(ifp->if_serializer);
1458
7f186839
JS
1459 mii = device_get_softc(sc->bfe_miibus);
1460 mii_pollstat(mii);
1461 ifmr->ifm_active = mii->mii_media_active;
1462 ifmr->ifm_status = mii->mii_media_status;
7f186839
JS
1463}
1464
1465static int
bd4539cc 1466bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
7f186839
JS
1467{
1468 struct bfe_softc *sc = ifp->if_softc;
1469 struct ifreq *ifr = (struct ifreq *) data;
1470 struct mii_data *mii;
1471 int error = 0;
7f186839 1472
603a5653
SZ
1473 ASSERT_SERIALIZED(ifp->if_serializer);
1474
7f186839
JS
1475 switch (command) {
1476 case SIOCSIFFLAGS:
1477 if (ifp->if_flags & IFF_UP)
1478 if (ifp->if_flags & IFF_RUNNING)
1479 bfe_set_rx_mode(sc);
1480 else
1481 bfe_init(sc);
1482 else if (ifp->if_flags & IFF_RUNNING)
1483 bfe_stop(sc);
1484 break;
1485 case SIOCADDMULTI:
1486 case SIOCDELMULTI:
1487 if (ifp->if_flags & IFF_RUNNING)
1488 bfe_set_rx_mode(sc);
1489 break;
1490 case SIOCGIFMEDIA:
1491 case SIOCSIFMEDIA:
1492 mii = device_get_softc(sc->bfe_miibus);
1493 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1494 command);
1495 break;
7f186839 1496 default:
4cde4dd5 1497 error = ether_ioctl(ifp, command, data);
7f186839
JS
1498 break;
1499 }
7f186839
JS
1500 return error;
1501}
1502
1503static void
1504bfe_watchdog(struct ifnet *ifp)
1505{
0f20326f 1506 struct bfe_softc *sc = ifp->if_softc;
7f186839 1507
603a5653
SZ
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1509
50b872f3 1510 if_printf(ifp, "watchdog timeout -- resetting\n");
7f186839
JS
1511
1512 ifp->if_flags &= ~IFF_RUNNING;
1513 bfe_init(sc);
1514
1515 ifp->if_oerrors++;
7f186839
JS
1516}
1517
1518static void
1519bfe_tick(void *xsc)
1520{
1521 struct bfe_softc *sc = xsc;
1522 struct mii_data *mii;
78195a76 1523 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839
JS
1524
1525 mii = device_get_softc(sc->bfe_miibus);
1526
78195a76
MD
1527 lwkt_serialize_enter(ifp->if_serializer);
1528
7f186839 1529 bfe_stats_update(sc);
7fa4e3c3 1530 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
7f186839 1531
3641b7ca 1532 if (sc->bfe_link == 0) {
78195a76
MD
1533 mii_tick(mii);
1534 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1535 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1536 sc->bfe_link++;
1537 }
1538 if (!sc->bfe_link)
1539 sc->bfe_link++;
7f186839 1540 }
78195a76 1541 lwkt_serialize_exit(ifp->if_serializer);
7f186839
JS
1542}
1543
1544/*
1545 * Stop the adapter and free any mbufs allocated to the
1546 * RX and TX lists.
1547 */
1548static void
1549bfe_stop(struct bfe_softc *sc)
1550{
0f20326f 1551 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1552
603a5653
SZ
1553 ASSERT_SERIALIZED(ifp->if_serializer);
1554
7fa4e3c3 1555 callout_stop(&sc->bfe_stat_timer);
7f186839 1556
7f186839
JS
1557 bfe_chip_halt(sc);
1558 bfe_tx_ring_free(sc);
1559 bfe_rx_ring_free(sc);
1560
1561 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
7f186839 1562}