kernel - Introduce lightweight buffers
[dragonfly.git] / sys / platform / pc32 / i386 / globals.s
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) Peter Wemm <peter@netplex.com.au>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/i386/i386/globals.s,v 1.13.2.1 2000/05/16 06:58:06 dillon Exp $
c7954a5c 27 * $DragonFly: src/sys/platform/pc32/i386/globals.s,v 1.25 2006/12/26 20:43:56 dillon Exp $
984263bc
MD
28 */
29
984263bc
MD
30#include <machine/asmacros.h>
31#include <machine/pmap.h>
32
33#include "assym.s"
34
984263bc 35 /*
8ad65e08
MD
36 * Define the layout of the per-cpu address space. This is
37 * "constructed" in locore.s on the BSP and in mp_machdep.c for
38 * each AP. DO NOT REORDER THESE WITHOUT UPDATING THE REST!
39 *
b8337f35 40 * On UP the per-cpu address space is simply placed in the data
8ad65e08 41 * segment.
984263bc 42 */
8ad65e08 43 .data
2954c92f
MD
44 .globl CPU_prvspace, lapic
45 .set CPU_prvspace,(MPPTDI << PDRSHIFT)
46 .set lapic,CPU_prvspace + (NPTEPG-1) * PAGE_SIZE
984263bc 47
8ad65e08
MD
48 .globl globaldata
49 .set globaldata,0
984263bc
MD
50
51 /*
52 * Define layout of the global data. On SMP this lives in
53 * the per-cpu address space, otherwise it's in the data segment.
54 */
235957ed 55 .globl gd_curthread, gd_npxthread, gd_reqflags, gd_common_tss
84b592ba 56 .set gd_curthread,globaldata + GD_CURTHREAD
af0bff84 57 .set gd_npxthread,globaldata + GD_NPXTHREAD
235957ed 58 .set gd_reqflags,globaldata + GD_REQFLAGS
984263bc 59 .set gd_common_tss,globaldata + GD_COMMON_TSS
984263bc 60
5c5185ae
SG
61 .globl gd_lwbuf_fpages
62 .set gd_lwbuf_fpages,globaldata + GD_LWBUF_FPAGES
63
984263bc
MD
64 .globl gd_common_tssd, gd_tss_gdt
65 .set gd_common_tssd,globaldata + GD_COMMON_TSSD
66 .set gd_tss_gdt,globaldata + GD_TSS_GDT
67
984263bc
MD
68 .globl gd_currentldt
69 .set gd_currentldt,globaldata + GD_CURRENTLDT
984263bc 70
a02705a9
MD
71 .globl gd_fpu_lock, gd_savefpu
72 .set gd_fpu_lock, globaldata + GD_FPU_LOCK
73 .set gd_savefpu, globaldata + GD_SAVEFPU
263541db 74
984263bc
MD
75 /*
76 * The BSP version of these get setup in locore.s and pmap.c, while
77 * the AP versions are setup in mp_machdep.c.
78 */
c2fb025d 79 .globl gd_cpuid, gd_cpumask, gd_other_cpus
ef0fdad1 80 .globl gd_ss_eflags, gd_intr_nesting_level
85100692
MD
81 .globl gd_CMAP1, gd_CMAP2, gd_CMAP3, gd_PMAP1
82 .globl gd_CADDR1, gd_CADDR2, gd_CADDR3, gd_PADDR1
729e15a8 83 .globl gd_spending, gd_fpending
5f456c40 84 .globl gd_cnt, gd_private_tss
984263bc 85
d0e06f83 86 .set gd_cpuid,globaldata + GD_CPUID
c2fb025d 87 .set gd_cpumask,globaldata + GD_CPUMASK
a2a5ad0d 88 .set gd_private_tss,globaldata + GD_PRIVATE_TSS
984263bc
MD
89 .set gd_other_cpus,globaldata + GD_OTHER_CPUS
90 .set gd_ss_eflags,globaldata + GD_SS_EFLAGS
ef0fdad1 91 .set gd_intr_nesting_level,globaldata + GD_INTR_NESTING_LEVEL
85100692
MD
92 .set gd_CMAP1,globaldata + GD_PRV_CMAP1
93 .set gd_CMAP2,globaldata + GD_PRV_CMAP2
94 .set gd_CMAP3,globaldata + GD_PRV_CMAP3
95 .set gd_PMAP1,globaldata + GD_PRV_PMAP1
96 .set gd_CADDR1,globaldata + GD_PRV_CADDR1
97 .set gd_CADDR2,globaldata + GD_PRV_CADDR2
98 .set gd_CADDR3,globaldata + GD_PRV_CADDR3
99 .set gd_PADDR1,globaldata + GD_PRV_PADDR1
ef0fdad1 100 .set gd_fpending,globaldata + GD_FPENDING
5f456c40 101 .set gd_spending,globaldata + GD_SPENDING
12e4aaff 102 .set gd_cnt,globaldata + GD_CNT
984263bc 103
97359a5b 104#ifdef SMP
984263bc
MD
105 .globl lapic_eoi, lapic_svr, lapic_tpr, lapic_irr1, lapic_ver
106 .globl lapic_icr_lo,lapic_icr_hi,lapic_isr1
107/*
108 * Do not clutter our namespace with these unless we need them in other
109 * assembler code. The C code uses different definitions.
110 */
111#if 0
112 .globl lapic_id,lapic_ver,lapic_tpr,lapic_apr,lapic_ppr,lapic_eoi
113 .globl lapic_ldr,lapic_dfr,lapic_svr,lapic_isr,lapic_isr0
114 .globl lapic_isr2,lapic_isr3,lapic_isr4,lapic_isr5,lapic_isr6
115 .globl lapic_isr7,lapic_tmr,lapic_tmr0,lapic_tmr1,lapic_tmr2
116 .globl lapic_tmr3,lapic_tmr4,lapic_tmr5,lapic_tmr6,lapic_tmr7
117 .globl lapic_irr,lapic_irr0,lapic_irr1,lapic_irr2,lapic_irr3
118 .globl lapic_irr4,lapic_irr5,lapic_irr6,lapic_irr7,lapic_esr
119 .globl lapic_lvtt,lapic_pcint,lapic_lvt1
120 .globl lapic_lvt2,lapic_lvt3,lapic_ticr,lapic_tccr,lapic_tdcr
121#endif
2954c92f
MD
122 .set lapic_id, lapic + 0x020
123 .set lapic_ver, lapic + 0x030
124 .set lapic_tpr, lapic + 0x080
125 .set lapic_apr, lapic + 0x090
126 .set lapic_ppr, lapic + 0x0a0
127 .set lapic_eoi, lapic + 0x0b0
128 .set lapic_ldr, lapic + 0x0d0
129 .set lapic_dfr, lapic + 0x0e0
130 .set lapic_svr, lapic + 0x0f0
131 .set lapic_isr, lapic + 0x100
132 .set lapic_isr0, lapic + 0x100
133 .set lapic_isr1, lapic + 0x110
134 .set lapic_isr2, lapic + 0x120
135 .set lapic_isr3, lapic + 0x130
136 .set lapic_isr4, lapic + 0x140
137 .set lapic_isr5, lapic + 0x150
138 .set lapic_isr6, lapic + 0x160
139 .set lapic_isr7, lapic + 0x170
140 .set lapic_tmr, lapic + 0x180
141 .set lapic_tmr0, lapic + 0x180
142 .set lapic_tmr1, lapic + 0x190
143 .set lapic_tmr2, lapic + 0x1a0
144 .set lapic_tmr3, lapic + 0x1b0
145 .set lapic_tmr4, lapic + 0x1c0
146 .set lapic_tmr5, lapic + 0x1d0
147 .set lapic_tmr6, lapic + 0x1e0
148 .set lapic_tmr7, lapic + 0x1f0
149 .set lapic_irr, lapic + 0x200
150 .set lapic_irr0, lapic + 0x200
151 .set lapic_irr1, lapic + 0x210
152 .set lapic_irr2, lapic + 0x220
153 .set lapic_irr3, lapic + 0x230
154 .set lapic_irr4, lapic + 0x240
155 .set lapic_irr5, lapic + 0x250
156 .set lapic_irr6, lapic + 0x260
157 .set lapic_irr7, lapic + 0x270
158 .set lapic_esr, lapic + 0x280
159 .set lapic_icr_lo, lapic + 0x300
160 .set lapic_icr_hi, lapic + 0x310
161 .set lapic_lvtt, lapic + 0x320
162 .set lapic_pcint, lapic + 0x340
163 .set lapic_lvt1, lapic + 0x350
164 .set lapic_lvt2, lapic + 0x360
165 .set lapic_lvt3, lapic + 0x370
166 .set lapic_ticr, lapic + 0x380
167 .set lapic_tccr, lapic + 0x390
168 .set lapic_tdcr, lapic + 0x3e0
984263bc 169#endif
2954c92f 170