bce(4): - Added a workaround for NC-SI management firmware
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
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1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
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31 */
32
33/*
34 * The following controllers are supported by this driver:
35 * BCM5706C A2, A3
d0092544 36 * BCM5706S A2, A3
43c2aeb0 37 * BCM5708C B1, B2
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38 * BCM5708S B1, B2
39 * BCM5709C A1, C0
40 * BCM5716 C0
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41 *
42 * The following controllers are not supported by this driver:
43 * BCM5706C A0, A1
d0092544 44 * BCM5706S A0, A1
43c2aeb0 45 * BCM5708C A0, B0
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46 * BCM5708S A0, B0
47 * BCM5709C A0, B0, B1
48 * BCM5709S A0, A1, B0, B1, B2, C0
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49 */
50
51#include "opt_bce.h"
52#include "opt_polling.h"
53
54#include <sys/param.h>
55#include <sys/bus.h>
56#include <sys/endian.h>
57#include <sys/kernel.h>
9db4b353 58#include <sys/interrupt.h>
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59#include <sys/mbuf.h>
60#include <sys/malloc.h>
61#include <sys/queue.h>
62#ifdef BCE_DEBUG
63#include <sys/random.h>
64#endif
65#include <sys/rman.h>
66#include <sys/serialize.h>
67#include <sys/socket.h>
68#include <sys/sockio.h>
69#include <sys/sysctl.h>
70
71#include <net/bpf.h>
72#include <net/ethernet.h>
73#include <net/if.h>
74#include <net/if_arp.h>
75#include <net/if_dl.h>
76#include <net/if_media.h>
77#include <net/if_types.h>
78#include <net/ifq_var.h>
79#include <net/vlan/if_vlan_var.h>
b637f170 80#include <net/vlan/if_vlan_ether.h>
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81
82#include <dev/netif/mii_layer/mii.h>
83#include <dev/netif/mii_layer/miivar.h>
84
85#include <bus/pci/pcireg.h>
86#include <bus/pci/pcivar.h>
87
88#include "miibus_if.h"
89
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90#include <dev/netif/bce/if_bcereg.h>
91#include <dev/netif/bce/if_bcefw.h>
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92
93/****************************************************************************/
94/* BCE Debug Options */
95/****************************************************************************/
96#ifdef BCE_DEBUG
97
98static uint32_t bce_debug = BCE_WARN;
99
100/*
101 * 0 = Never
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
107 * 268435456 = 1 in 8
108 * 536870912 = 1 in 4
109 * 1073741824 = 1 in 2
110 *
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
113 *
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
116 *
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
119 *
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
122 *
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
125 */
126static int bce_debug_l2fhdr_status_check = 0;
127static int bce_debug_unexpected_attention = 0;
128static int bce_debug_mbuf_allocation_failure = 0;
129static int bce_debug_dma_map_addr_failure = 0;
130static int bce_debug_bootcode_running_failure = 0;
131
132#endif /* BCE_DEBUG */
133
134
135/****************************************************************************/
136/* PCI Device ID Table */
137/* */
138/* Used by bce_probe() to identify the devices supported by this driver. */
139/****************************************************************************/
140#define BCE_DEVDESC_MAX 64
141
142static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
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148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
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152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
154
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
160
161 /* BCM5708C controllers and OEM boards. */
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162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
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168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
170
171 /* BCM5708S controllers and OEM boards. */
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172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
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178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
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180
181 /* BCM5709C controllers and OEM boards. */
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182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
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186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
188
189 /* BCM5709S controllers and OEM boards. */
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190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
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194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
196
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
200
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201 { 0, 0, 0, 0, NULL }
202};
203
204
205/****************************************************************************/
206/* Supported Flash NVRAM device data. */
207/****************************************************************************/
208static const struct flash_spec flash_table[] =
209{
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210#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211#define NONBUFFERED_FLAGS (BCE_NV_WREN)
212
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213 /* Slow EEPROM */
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217 "EEPROM - slow"},
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 "Entry 0001"},
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239 "Entry 0100"},
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
256 /* Fast EEPROM */
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
260 "EEPROM - fast"},
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265 "Entry 1001"},
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270 "Entry 1010"},
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280 "Entry 1100"},
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285 "Entry 1101"},
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
296};
297
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298/*
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
303 * driver.
304 */
305static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
312};
313
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314
315/****************************************************************************/
316/* DragonFly device entry points. */
317/****************************************************************************/
318static int bce_probe(device_t);
319static int bce_attach(device_t);
320static int bce_detach(device_t);
321static void bce_shutdown(device_t);
322
323/****************************************************************************/
324/* BCE Debug Data Structure Dump Routines */
325/****************************************************************************/
326#ifdef BCE_DEBUG
327static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334static void bce_dump_tx_chain(struct bce_softc *, int, int);
335static void bce_dump_rx_chain(struct bce_softc *, int, int);
336static void bce_dump_status_block(struct bce_softc *);
337static void bce_dump_driver_state(struct bce_softc *);
338static void bce_dump_stats_block(struct bce_softc *) __unused;
339static void bce_dump_hw_state(struct bce_softc *);
340static void bce_dump_txp_state(struct bce_softc *);
341static void bce_dump_rxp_state(struct bce_softc *) __unused;
342static void bce_dump_tpat_state(struct bce_softc *) __unused;
343static void bce_freeze_controller(struct bce_softc *) __unused;
344static void bce_unfreeze_controller(struct bce_softc *) __unused;
345static void bce_breakpoint(struct bce_softc *);
346#endif /* BCE_DEBUG */
347
348
349/****************************************************************************/
350/* BCE Register/Memory Access Routines */
351/****************************************************************************/
352static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
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354static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355static uint32_t bce_shmem_rd(struct bce_softc *, u32);
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356static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357static int bce_miibus_read_reg(device_t, int, int);
358static int bce_miibus_write_reg(device_t, int, int, int);
359static void bce_miibus_statchg(device_t);
360
361
362/****************************************************************************/
363/* BCE NVRAM Access Routines */
364/****************************************************************************/
365static int bce_acquire_nvram_lock(struct bce_softc *);
366static int bce_release_nvram_lock(struct bce_softc *);
367static void bce_enable_nvram_access(struct bce_softc *);
368static void bce_disable_nvram_access(struct bce_softc *);
369static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
370 uint32_t);
371static int bce_init_nvram(struct bce_softc *);
372static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373static int bce_nvram_test(struct bce_softc *);
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374
375/****************************************************************************/
376/* BCE DMA Allocate/Free Routines */
377/****************************************************************************/
378static int bce_dma_alloc(struct bce_softc *);
379static void bce_dma_free(struct bce_softc *);
380static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
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381
382/****************************************************************************/
383/* BCE Firmware Synchronization and Load */
384/****************************************************************************/
385static int bce_fw_sync(struct bce_softc *, uint32_t);
386static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
387 uint32_t, uint32_t);
388static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
389 struct fw_info *);
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390static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392static void bce_start_rxp_cpu(struct bce_softc *);
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393static void bce_init_rxp_cpu(struct bce_softc *);
394static void bce_init_txp_cpu(struct bce_softc *);
395static void bce_init_tpat_cpu(struct bce_softc *);
396static void bce_init_cp_cpu(struct bce_softc *);
397static void bce_init_com_cpu(struct bce_softc *);
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398static void bce_init_cpus(struct bce_softc *);
399
400static void bce_stop(struct bce_softc *);
401static int bce_reset(struct bce_softc *, uint32_t);
402static int bce_chipinit(struct bce_softc *);
403static int bce_blockinit(struct bce_softc *);
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404static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
405 uint32_t *, int);
314a2fcc 406static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
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407static void bce_probe_pci_caps(struct bce_softc *);
408static void bce_print_adapter_info(struct bce_softc *);
409static void bce_get_media(struct bce_softc *);
43c2aeb0 410
d0092544 411static void bce_init_tx_context(struct bce_softc *);
43c2aeb0 412static int bce_init_tx_chain(struct bce_softc *);
d0092544 413static void bce_init_rx_context(struct bce_softc *);
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414static int bce_init_rx_chain(struct bce_softc *);
415static void bce_free_rx_chain(struct bce_softc *);
416static void bce_free_tx_chain(struct bce_softc *);
417
418static int bce_encap(struct bce_softc *, struct mbuf **);
419static void bce_start(struct ifnet *);
420static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421static void bce_watchdog(struct ifnet *);
422static int bce_ifmedia_upd(struct ifnet *);
423static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424static void bce_init(void *);
425static void bce_mgmt_init(struct bce_softc *);
426
3a41a80b 427static void bce_init_ctx(struct bce_softc *);
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428static void bce_get_mac_addr(struct bce_softc *);
429static void bce_set_mac_addr(struct bce_softc *);
430static void bce_phy_intr(struct bce_softc *);
431static void bce_rx_intr(struct bce_softc *, int);
432static void bce_tx_intr(struct bce_softc *);
433static void bce_disable_intr(struct bce_softc *);
d0092544 434static void bce_enable_intr(struct bce_softc *, int);
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435
436#ifdef DEVICE_POLLING
437static void bce_poll(struct ifnet *, enum poll_cmd, int);
438#endif
439static void bce_intr(void *);
440static void bce_set_rx_mode(struct bce_softc *);
441static void bce_stats_update(struct bce_softc *);
442static void bce_tick(void *);
443static void bce_tick_serialized(struct bce_softc *);
d0092544 444static void bce_pulse(void *);
43c2aeb0
SZ
445static void bce_add_sysctls(struct bce_softc *);
446
bdeb8fff
SZ
447static void bce_coal_change(struct bce_softc *);
448static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
449static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
450static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
451static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
452static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
453static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
454static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
455static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
456static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
457 uint32_t *, uint32_t);
458
3fb4bb6c
SZ
459/*
460 * NOTE:
461 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
462 * takes 1023 as the TX ticks limit. However, using 1023 will
463 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
464 * there is _no_ network activity on the NIC.
3fb4bb6c
SZ
465 */
466static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
467static uint32_t bce_tx_bds = 255; /* bcm: 20 */
468static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
469static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
1af951ab
SZ
470static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
471static uint32_t bce_rx_bds = 128; /* bcm: 6 */
472static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
473static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
bdeb8fff
SZ
474
475TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
476TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
477TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
478TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
479TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
480TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
481TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
482TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
43c2aeb0
SZ
483
484/****************************************************************************/
485/* DragonFly device dispatch table. */
486/****************************************************************************/
487static device_method_t bce_methods[] = {
488 /* Device interface */
489 DEVMETHOD(device_probe, bce_probe),
490 DEVMETHOD(device_attach, bce_attach),
491 DEVMETHOD(device_detach, bce_detach),
492 DEVMETHOD(device_shutdown, bce_shutdown),
493
494 /* bus interface */
495 DEVMETHOD(bus_print_child, bus_generic_print_child),
496 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
497
498 /* MII interface */
499 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
500 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
501 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
502
503 { 0, 0 }
504};
505
506static driver_t bce_driver = {
507 "bce",
508 bce_methods,
509 sizeof(struct bce_softc)
510};
511
512static devclass_t bce_devclass;
513
43c2aeb0 514
d0092544 515DECLARE_DUMMY_MODULE(if_bce);
1be78fa8 516MODULE_DEPEND(bce, miibus, 1, 1, 1);
aa2b9d05
SW
517DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
518DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
43c2aeb0
SZ
519
520
521/****************************************************************************/
522/* Device probe function. */
523/* */
524/* Compares the device to the driver's list of supported devices and */
525/* reports back to the OS whether this is the right driver for the device. */
526/* */
527/* Returns: */
528/* BUS_PROBE_DEFAULT on success, positive value on failure. */
529/****************************************************************************/
530static int
531bce_probe(device_t dev)
532{
533 struct bce_type *t;
534 uint16_t vid, did, svid, sdid;
535
536 /* Get the data for the device to be probed. */
537 vid = pci_get_vendor(dev);
538 did = pci_get_device(dev);
539 svid = pci_get_subvendor(dev);
540 sdid = pci_get_subdevice(dev);
541
542 /* Look through the list of known devices for a match. */
543 for (t = bce_devs; t->bce_name != NULL; ++t) {
544 if (vid == t->bce_vid && did == t->bce_did &&
545 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
546 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
547 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
548 char *descbuf;
549
550 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
551
552 /* Print out the device identity. */
553 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
554 t->bce_name,
555 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
556
557 device_set_desc_copy(dev, descbuf);
558 kfree(descbuf, M_TEMP);
559 return 0;
560 }
561 }
562 return ENXIO;
563}
564
565
566/****************************************************************************/
d0092544
SZ
567/* PCI Capabilities Probe Function. */
568/* */
569/* Walks the PCI capabiites list for the device to find what features are */
570/* supported. */
571/* */
572/* Returns: */
573/* None. */
574/****************************************************************************/
575static void
576bce_print_adapter_info(struct bce_softc *sc)
577{
578 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
579
580 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
581 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
582
583 /* Bus info. */
584 if (sc->bce_flags & BCE_PCIE_FLAG) {
585 kprintf("Bus (PCIe x%d, ", sc->link_width);
586 switch (sc->link_speed) {
587 case 1:
588 kprintf("2.5Gbps); ");
589 break;
590 case 2:
591 kprintf("5Gbps); ");
592 break;
593 default:
594 kprintf("Unknown link speed); ");
595 break;
596 }
597 } else {
598 kprintf("Bus (PCI%s, %s, %dMHz); ",
599 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
600 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
601 sc->bus_speed_mhz);
602 }
603
604 /* Firmware version and device features. */
bc30d40d 605 kprintf("B/C (%s)", sc->bce_bc_ver);
cff16e71
SZ
606
607 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
608 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
609 kprintf("; Flags(");
610 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
bc30d40d 611 kprintf("MFW[%s]", sc->bce_mfw_ver);
cff16e71
SZ
612 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
613 kprintf(" 2.5G");
614 kprintf(")");
615 }
616 kprintf("\n");
d0092544
SZ
617}
618
619
620/****************************************************************************/
621/* PCI Capabilities Probe Function. */
622/* */
623/* Walks the PCI capabiites list for the device to find what features are */
624/* supported. */
625/* */
626/* Returns: */
627/* None. */
628/****************************************************************************/
629static void
630bce_probe_pci_caps(struct bce_softc *sc)
631{
632 device_t dev = sc->bce_dev;
633 uint8_t ptr;
634
635 if (pci_is_pcix(dev))
636 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
637
638 ptr = pci_get_pciecap_ptr(dev);
639 if (ptr) {
640 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
641
642 sc->link_speed = link_status & 0xf;
643 sc->link_width = (link_status >> 4) & 0x3f;
644 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
645 sc->bce_flags |= BCE_PCIE_FLAG;
646 }
647}
648
649
650/****************************************************************************/
43c2aeb0
SZ
651/* Device attach function. */
652/* */
653/* Allocates device resources, performs secondary chip identification, */
654/* resets and initializes the hardware, and initializes driver instance */
655/* variables. */
656/* */
657/* Returns: */
658/* 0 on success, positive value on failure. */
659/****************************************************************************/
660static int
661bce_attach(device_t dev)
662{
663 struct bce_softc *sc = device_get_softc(dev);
664 struct ifnet *ifp = &sc->arpcom.ac_if;
665 uint32_t val;
666 int rid, rc = 0;
bc30d40d 667 int i, j;
43c2aeb0
SZ
668#ifdef notyet
669 int count;
670#endif
671
672 sc->bce_dev = dev;
673 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
674
675 pci_enable_busmaster(dev);
676
d0092544
SZ
677 bce_probe_pci_caps(sc);
678
43c2aeb0
SZ
679 /* Allocate PCI memory resources. */
680 rid = PCIR_BAR(0);
681 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
682 RF_ACTIVE | PCI_RF_DENSE);
683 if (sc->bce_res_mem == NULL) {
684 device_printf(dev, "PCI memory allocation failed\n");
685 return ENXIO;
686 }
687 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
688 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
689
690 /* Allocate PCI IRQ resources. */
691#ifdef notyet
692 count = pci_msi_count(dev);
693 if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
694 rid = 1;
695 sc->bce_flags |= BCE_USING_MSI_FLAG;
696 } else
697#endif
698 rid = 0;
699 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
700 RF_SHAREABLE | RF_ACTIVE);
701 if (sc->bce_res_irq == NULL) {
702 device_printf(dev, "PCI map interrupt failed\n");
703 rc = ENXIO;
704 goto fail;
705 }
706
707 /*
708 * Configure byte swap and enable indirect register access.
709 * Rely on CPU to do target byte swapping on big endian systems.
710 * Access to registers outside of PCI configurtion space are not
711 * valid until this is done.
712 */
713 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
714 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
715 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
716
717 /* Save ASIC revsion info. */
718 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
719
720 /* Weed out any non-production controller revisions. */
bc30d40d 721 switch (BCE_CHIP_ID(sc)) {
43c2aeb0
SZ
722 case BCE_CHIP_ID_5706_A0:
723 case BCE_CHIP_ID_5706_A1:
724 case BCE_CHIP_ID_5708_A0:
725 case BCE_CHIP_ID_5708_B0:
d0092544
SZ
726 case BCE_CHIP_ID_5709_A0:
727 case BCE_CHIP_ID_5709_B0:
728 case BCE_CHIP_ID_5709_B1:
729#ifdef foo
730 /* 5709C B2 seems to work fine */
731 case BCE_CHIP_ID_5709_B2:
732#endif
43c2aeb0
SZ
733 device_printf(dev, "Unsupported chip id 0x%08x!\n",
734 BCE_CHIP_ID(sc));
735 rc = ENODEV;
736 goto fail;
737 }
738
43c2aeb0
SZ
739 /*
740 * Find the base address for shared memory access.
741 * Newer versions of bootcode use a signature and offset
742 * while older versions use a fixed address.
743 */
744 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
d0092544
SZ
745 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
746 BCE_SHM_HDR_SIGNATURE_SIG) {
747 /* Multi-port devices use different offsets in shared memory. */
748 sc->bce_shmem_base = REG_RD_IND(sc,
749 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
750 } else {
43c2aeb0 751 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
d0092544 752 }
43c2aeb0
SZ
753 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
754
d0092544 755 /* Fetch the bootcode revision. */
bc30d40d
SZ
756 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
757 for (i = 0, j = 0; i < 3; i++) {
758 uint8_t num;
759 int k, skip0;
760
761 num = (uint8_t)(val >> (24 - (i * 8)));
762 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
763 if (num >= k || !skip0 || k == 1) {
764 sc->bce_bc_ver[j++] = (num / k) + '0';
765 skip0 = 0;
766 }
767 }
768 if (i != 2)
769 sc->bce_bc_ver[j++] = '.';
770 }
d0092544 771
bc30d40d
SZ
772 /* Check if any management firwmare is running. */
773 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
774 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
d0092544
SZ
775 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
776
bc30d40d
SZ
777 /* Allow time for firmware to enter the running state. */
778 for (i = 0; i < 30; i++) {
779 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
780 if (val & BCE_CONDITION_MFW_RUN_MASK)
781 break;
782 DELAY(10000);
783 }
784 }
785
786 /* Check the current bootcode state. */
787 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
788 BCE_CONDITION_MFW_RUN_MASK;
789 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
790 val != BCE_CONDITION_MFW_RUN_NONE) {
791 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
792
793 for (i = 0, j = 0; j < 3; j++) {
794 val = bce_reg_rd_ind(sc, addr + j * 4);
795 val = bswap32(val);
796 memcpy(&sc->bce_mfw_ver[i], &val, 4);
797 i += 4;
798 }
799 }
800
43c2aeb0
SZ
801 /* Get PCI bus information (speed and type). */
802 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
803 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
804 uint32_t clkreg;
805
806 sc->bce_flags |= BCE_PCIX_FLAG;
807
808 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
809 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
810 switch (clkreg) {
811 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
812 sc->bus_speed_mhz = 133;
813 break;
814
815 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
816 sc->bus_speed_mhz = 100;
817 break;
818
819 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
820 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
821 sc->bus_speed_mhz = 66;
822 break;
823
824 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
825 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
826 sc->bus_speed_mhz = 50;
827 break;
828
829 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
830 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
831 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
832 sc->bus_speed_mhz = 33;
833 break;
834 }
835 } else {
836 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
837 sc->bus_speed_mhz = 66;
838 else
839 sc->bus_speed_mhz = 33;
840 }
841
842 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
843 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
844
43c2aeb0
SZ
845 /* Reset the controller. */
846 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
847 if (rc != 0)
848 goto fail;
849
850 /* Initialize the controller. */
851 rc = bce_chipinit(sc);
852 if (rc != 0) {
853 device_printf(dev, "Controller initialization failed!\n");
854 goto fail;
855 }
856
857 /* Perform NVRAM test. */
858 rc = bce_nvram_test(sc);
859 if (rc != 0) {
860 device_printf(dev, "NVRAM test failed!\n");
861 goto fail;
862 }
863
864 /* Fetch the permanent Ethernet MAC address. */
865 bce_get_mac_addr(sc);
866
867 /*
868 * Trip points control how many BDs
869 * should be ready before generating an
870 * interrupt while ticks control how long
871 * a BD can sit in the chain before
872 * generating an interrupt. Set the default
873 * values for the RX and TX rings.
874 */
875
876#ifdef BCE_DRBUG
877 /* Force more frequent interrupts. */
878 sc->bce_tx_quick_cons_trip_int = 1;
879 sc->bce_tx_quick_cons_trip = 1;
880 sc->bce_tx_ticks_int = 0;
881 sc->bce_tx_ticks = 0;
882
883 sc->bce_rx_quick_cons_trip_int = 1;
884 sc->bce_rx_quick_cons_trip = 1;
885 sc->bce_rx_ticks_int = 0;
886 sc->bce_rx_ticks = 0;
887#else
bdeb8fff
SZ
888 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
889 sc->bce_tx_quick_cons_trip = bce_tx_bds;
890 sc->bce_tx_ticks_int = bce_tx_ticks_int;
891 sc->bce_tx_ticks = bce_tx_ticks;
892
893 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
894 sc->bce_rx_quick_cons_trip = bce_rx_bds;
895 sc->bce_rx_ticks_int = bce_rx_ticks_int;
896 sc->bce_rx_ticks = bce_rx_ticks;
43c2aeb0
SZ
897#endif
898
899 /* Update statistics once every second. */
900 sc->bce_stats_ticks = 1000000 & 0xffff00;
901
d0092544
SZ
902 /* Find the media type for the adapter. */
903 bce_get_media(sc);
43c2aeb0
SZ
904
905 /* Allocate DMA memory resources. */
906 rc = bce_dma_alloc(sc);
907 if (rc != 0) {
908 device_printf(dev, "DMA resource allocation failed!\n");
909 goto fail;
910 }
911
912 /* Initialize the ifnet interface. */
913 ifp->if_softc = sc;
914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
915 ifp->if_ioctl = bce_ioctl;
916 ifp->if_start = bce_start;
917 ifp->if_init = bce_init;
918 ifp->if_watchdog = bce_watchdog;
919#ifdef DEVICE_POLLING
920 ifp->if_poll = bce_poll;
921#endif
922 ifp->if_mtu = ETHERMTU;
923 ifp->if_hwassist = BCE_IF_HWASSIST;
924 ifp->if_capabilities = BCE_IF_CAPABILITIES;
925 ifp->if_capenable = ifp->if_capabilities;
926 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
927 ifq_set_ready(&ifp->if_snd);
928
929 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
930 ifp->if_baudrate = IF_Gbps(2.5);
931 else
932 ifp->if_baudrate = IF_Gbps(1);
933
934 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
935 sc->mbuf_alloc_size = MCLBYTES;
936
937 /* Look for our PHY. */
938 rc = mii_phy_probe(dev, &sc->bce_miibus,
939 bce_ifmedia_upd, bce_ifmedia_sts);
940 if (rc != 0) {
941 device_printf(dev, "PHY probe failed!\n");
942 goto fail;
943 }
944
945 /* Attach to the Ethernet interface list. */
946 ether_ifattach(ifp, sc->eaddr, NULL);
947
d0092544
SZ
948 callout_init(&sc->bce_tick_callout);
949 callout_init(&sc->bce_pulse_callout);
43c2aeb0
SZ
950
951 /* Hookup IRQ last. */
95893fe4 952 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
43c2aeb0
SZ
953 &sc->bce_intrhand, ifp->if_serializer);
954 if (rc != 0) {
955 device_printf(dev, "Failed to setup IRQ!\n");
956 ether_ifdetach(ifp);
957 goto fail;
958 }
959
9db4b353
SZ
960 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
961 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
962
43c2aeb0
SZ
963 /* Print some important debugging info. */
964 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
965
966 /* Add the supported sysctls to the kernel. */
967 bce_add_sysctls(sc);
968
d0092544
SZ
969 /*
970 * The chip reset earlier notified the bootcode that
971 * a driver is present. We now need to start our pulse
972 * routine so that the bootcode is reminded that we're
973 * still running.
974 */
975 bce_pulse(sc);
976
43c2aeb0
SZ
977 /* Get the firmware running so IPMI still works */
978 bce_mgmt_init(sc);
979
d0092544
SZ
980 bce_print_adapter_info(sc);
981
43c2aeb0
SZ
982 return 0;
983fail:
984 bce_detach(dev);
985 return(rc);
986}
987
988
989/****************************************************************************/
990/* Device detach function. */
991/* */
992/* Stops the controller, resets the controller, and releases resources. */
993/* */
994/* Returns: */
995/* 0 on success, positive value on failure. */
996/****************************************************************************/
997static int
998bce_detach(device_t dev)
999{
1000 struct bce_softc *sc = device_get_softc(dev);
1001
1002 if (device_is_attached(dev)) {
1003 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1004 uint32_t msg;
43c2aeb0
SZ
1005
1006 /* Stop and reset the controller. */
1007 lwkt_serialize_enter(ifp->if_serializer);
d0092544 1008 callout_stop(&sc->bce_pulse_callout);
43c2aeb0 1009 bce_stop(sc);
d0092544
SZ
1010 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1011 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1012 else
1013 msg = BCE_DRV_MSG_CODE_UNLOAD;
1014 bce_reset(sc, msg);
43c2aeb0
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1015 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1016 lwkt_serialize_exit(ifp->if_serializer);
1017
1018 ether_ifdetach(ifp);
1019 }
1020
1021 /* If we have a child device on the MII bus remove it too. */
1022 if (sc->bce_miibus)
1023 device_delete_child(dev, sc->bce_miibus);
1024 bus_generic_detach(dev);
1025
1026 if (sc->bce_res_irq != NULL) {
1027 bus_release_resource(dev, SYS_RES_IRQ,
1028 sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
1029 sc->bce_res_irq);
1030 }
1031
1032#ifdef notyet
1033 if (sc->bce_flags & BCE_USING_MSI_FLAG)
1034 pci_release_msi(dev);
1035#endif
1036
1037 if (sc->bce_res_mem != NULL) {
1038 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1039 sc->bce_res_mem);
1040 }
1041
1042 bce_dma_free(sc);
1043
1044 if (sc->bce_sysctl_tree != NULL)
1045 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1046
1047 return 0;
1048}
1049
1050
1051/****************************************************************************/
1052/* Device shutdown function. */
1053/* */
1054/* Stops and resets the controller. */
1055/* */
1056/* Returns: */
1057/* Nothing */
1058/****************************************************************************/
1059static void
1060bce_shutdown(device_t dev)
1061{
1062 struct bce_softc *sc = device_get_softc(dev);
1063 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1064 uint32_t msg;
43c2aeb0
SZ
1065
1066 lwkt_serialize_enter(ifp->if_serializer);
1067 bce_stop(sc);
d0092544
SZ
1068 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1069 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1070 else
1071 msg = BCE_DRV_MSG_CODE_UNLOAD;
1072 bce_reset(sc, msg);
43c2aeb0
SZ
1073 lwkt_serialize_exit(ifp->if_serializer);
1074}
1075
1076
1077/****************************************************************************/
1078/* Indirect register read. */
1079/* */
1080/* Reads NetXtreme II registers using an index/data register pair in PCI */
1081/* configuration space. Using this mechanism avoids issues with posted */
1082/* reads but is much slower than memory-mapped I/O. */
1083/* */
1084/* Returns: */
1085/* The value of the register. */
1086/****************************************************************************/
1087static uint32_t
1088bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1089{
1090 device_t dev = sc->bce_dev;
1091
1092 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1093#ifdef BCE_DEBUG
1094 {
1095 uint32_t val;
1096 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1097 DBPRINT(sc, BCE_EXCESSIVE,
1098 "%s(); offset = 0x%08X, val = 0x%08X\n",
1099 __func__, offset, val);
1100 return val;
1101 }
1102#else
1103 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1104#endif
1105}
1106
1107
1108/****************************************************************************/
1109/* Indirect register write. */
1110/* */
1111/* Writes NetXtreme II registers using an index/data register pair in PCI */
1112/* configuration space. Using this mechanism avoids issues with posted */
1113/* writes but is muchh slower than memory-mapped I/O. */
1114/* */
1115/* Returns: */
1116/* Nothing. */
1117/****************************************************************************/
1118static void
1119bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1120{
1121 device_t dev = sc->bce_dev;
1122
1123 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1124 __func__, offset, val);
1125
1126 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1127 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1128}
1129
1130
1131/****************************************************************************/
bc30d40d
SZ
1132/* Shared memory write. */
1133/* */
1134/* Writes NetXtreme II shared memory region. */
1135/* */
1136/* Returns: */
1137/* Nothing. */
1138/****************************************************************************/
1139static void
1140bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1141{
1142 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1143}
1144
1145
1146/****************************************************************************/
1147/* Shared memory read. */
1148/* */
1149/* Reads NetXtreme II shared memory region. */
1150/* */
1151/* Returns: */
1152/* The 32 bit value read. */
1153/****************************************************************************/
1154static u32
1155bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1156{
1157 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1158}
1159
1160
1161/****************************************************************************/
43c2aeb0
SZ
1162/* Context memory write. */
1163/* */
1164/* The NetXtreme II controller uses context memory to track connection */
1165/* information for L2 and higher network protocols. */
1166/* */
1167/* Returns: */
1168/* Nothing. */
1169/****************************************************************************/
1170static void
d0092544
SZ
1171bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1172 uint32_t ctx_val)
43c2aeb0 1173{
d0092544
SZ
1174 uint32_t idx, offset = ctx_offset + cid_addr;
1175 uint32_t val, retry_cnt = 5;
43c2aeb0 1176
d0092544
SZ
1177 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1178 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1179 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1180 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1181
1182 for (idx = 0; idx < retry_cnt; idx++) {
1183 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1184 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1185 break;
1186 DELAY(5);
1187 }
1188
1189 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1190 device_printf(sc->bce_dev,
1191 "Unable to write CTX memory: "
1192 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1193 cid_addr, ctx_offset);
1194 }
1195 } else {
1196 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1197 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1198 }
43c2aeb0
SZ
1199}
1200
1201
1202/****************************************************************************/
1203/* PHY register read. */
1204/* */
1205/* Implements register reads on the MII bus. */
1206/* */
1207/* Returns: */
1208/* The value of the register. */
1209/****************************************************************************/
1210static int
1211bce_miibus_read_reg(device_t dev, int phy, int reg)
1212{
1213 struct bce_softc *sc = device_get_softc(dev);
1214 uint32_t val;
1215 int i;
1216
1217 /* Make sure we are accessing the correct PHY address. */
1218 if (phy != sc->bce_phy_addr) {
1219 DBPRINT(sc, BCE_VERBOSE,
1220 "Invalid PHY address %d for PHY read!\n", phy);
1221 return 0;
1222 }
1223
1224 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1225 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1226 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1227
1228 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1229 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1230
1231 DELAY(40);
1232 }
1233
1234 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1235 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1236 BCE_EMAC_MDIO_COMM_START_BUSY;
1237 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1238
1239 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1240 DELAY(10);
1241
1242 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1243 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1244 DELAY(5);
1245
1246 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1247 val &= BCE_EMAC_MDIO_COMM_DATA;
1248 break;
1249 }
1250 }
1251
1252 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1253 if_printf(&sc->arpcom.ac_if,
1254 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1255 phy, reg);
1256 val = 0x0;
1257 } else {
1258 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1259 }
1260
1261 DBPRINT(sc, BCE_EXCESSIVE,
1262 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1263 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1264
1265 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1266 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1267 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1268
1269 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1270 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1271
1272 DELAY(40);
1273 }
1274 return (val & 0xffff);
1275}
1276
1277
1278/****************************************************************************/
1279/* PHY register write. */
1280/* */
1281/* Implements register writes on the MII bus. */
1282/* */
1283/* Returns: */
1284/* The value of the register. */
1285/****************************************************************************/
1286static int
1287bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1288{
1289 struct bce_softc *sc = device_get_softc(dev);
1290 uint32_t val1;
1291 int i;
1292
1293 /* Make sure we are accessing the correct PHY address. */
1294 if (phy != sc->bce_phy_addr) {
1295 DBPRINT(sc, BCE_WARN,
1296 "Invalid PHY address %d for PHY write!\n", phy);
1297 return(0);
1298 }
1299
1300 DBPRINT(sc, BCE_EXCESSIVE,
1301 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1302 __func__, phy, (uint16_t)(reg & 0xffff),
1303 (uint16_t)(val & 0xffff));
1304
1305 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1306 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1307 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1308
1309 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1310 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1311
1312 DELAY(40);
1313 }
1314
1315 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1316 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1317 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1318 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1319
1320 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1321 DELAY(10);
1322
1323 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1324 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1325 DELAY(5);
1326 break;
1327 }
1328 }
1329
1330 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1331 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1332
1333 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1334 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1335 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1336
1337 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1338 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1339
1340 DELAY(40);
1341 }
1342 return 0;
1343}
1344
1345
1346/****************************************************************************/
1347/* MII bus status change. */
1348/* */
1349/* Called by the MII bus driver when the PHY establishes link to set the */
1350/* MAC interface registers. */
1351/* */
1352/* Returns: */
1353/* Nothing. */
1354/****************************************************************************/
1355static void
1356bce_miibus_statchg(device_t dev)
1357{
1358 struct bce_softc *sc = device_get_softc(dev);
1359 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1360
1361 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1362 mii->mii_media_active);
1363
1364#ifdef BCE_DEBUG
1365 /* Decode the interface media flags. */
1366 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1367 switch(IFM_TYPE(mii->mii_media_active)) {
1368 case IFM_ETHER:
1369 kprintf("Ethernet )");
1370 break;
1371 default:
1372 kprintf("Unknown )");
1373 break;
1374 }
1375
1376 kprintf(" Media Options: ( ");
1377 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1378 case IFM_AUTO:
1379 kprintf("Autoselect )");
1380 break;
1381 case IFM_MANUAL:
1382 kprintf("Manual )");
1383 break;
1384 case IFM_NONE:
1385 kprintf("None )");
1386 break;
1387 case IFM_10_T:
1388 kprintf("10Base-T )");
1389 break;
1390 case IFM_100_TX:
1391 kprintf("100Base-TX )");
1392 break;
1393 case IFM_1000_SX:
1394 kprintf("1000Base-SX )");
1395 break;
1396 case IFM_1000_T:
1397 kprintf("1000Base-T )");
1398 break;
1399 default:
1400 kprintf("Other )");
1401 break;
1402 }
1403
1404 kprintf(" Global Options: (");
1405 if (mii->mii_media_active & IFM_FDX)
1406 kprintf(" FullDuplex");
1407 if (mii->mii_media_active & IFM_HDX)
1408 kprintf(" HalfDuplex");
1409 if (mii->mii_media_active & IFM_LOOP)
1410 kprintf(" Loopback");
1411 if (mii->mii_media_active & IFM_FLAG0)
1412 kprintf(" Flag0");
1413 if (mii->mii_media_active & IFM_FLAG1)
1414 kprintf(" Flag1");
1415 if (mii->mii_media_active & IFM_FLAG2)
1416 kprintf(" Flag2");
1417 kprintf(" )\n");
1418#endif
1419
1420 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1421
1422 /*
1423 * Set MII or GMII interface based on the speed negotiated
1424 * by the PHY.
1425 */
1426 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1427 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1428 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1429 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1430 } else {
1431 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1432 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1433 }
1434
1435 /*
1436 * Set half or full duplex based on the duplicity negotiated
1437 * by the PHY.
1438 */
1439 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1440 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1441 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1442 } else {
1443 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1444 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1445 }
1446}
1447
1448
1449/****************************************************************************/
1450/* Acquire NVRAM lock. */
1451/* */
1452/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1453/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1454/* for use by the driver. */
1455/* */
1456/* Returns: */
1457/* 0 on success, positive value on failure. */
1458/****************************************************************************/
1459static int
1460bce_acquire_nvram_lock(struct bce_softc *sc)
1461{
1462 uint32_t val;
1463 int j;
1464
1465 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1466
1467 /* Request access to the flash interface. */
1468 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1469 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1470 val = REG_RD(sc, BCE_NVM_SW_ARB);
1471 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1472 break;
1473
1474 DELAY(5);
1475 }
1476
1477 if (j >= NVRAM_TIMEOUT_COUNT) {
1478 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1479 return EBUSY;
1480 }
1481 return 0;
1482}
1483
1484
1485/****************************************************************************/
1486/* Release NVRAM lock. */
1487/* */
1488/* When the caller is finished accessing NVRAM the lock must be released. */
1489/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1490/* for use by the driver. */
1491/* */
1492/* Returns: */
1493/* 0 on success, positive value on failure. */
1494/****************************************************************************/
1495static int
1496bce_release_nvram_lock(struct bce_softc *sc)
1497{
1498 int j;
1499 uint32_t val;
1500
1501 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1502
1503 /*
1504 * Relinquish nvram interface.
1505 */
1506 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1507
1508 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1509 val = REG_RD(sc, BCE_NVM_SW_ARB);
1510 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1511 break;
1512
1513 DELAY(5);
1514 }
1515
1516 if (j >= NVRAM_TIMEOUT_COUNT) {
1517 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1518 return EBUSY;
1519 }
1520 return 0;
1521}
1522
1523
43c2aeb0
SZ
1524/****************************************************************************/
1525/* Enable NVRAM access. */
1526/* */
1527/* Before accessing NVRAM for read or write operations the caller must */
1528/* enabled NVRAM access. */
1529/* */
1530/* Returns: */
1531/* Nothing. */
1532/****************************************************************************/
1533static void
1534bce_enable_nvram_access(struct bce_softc *sc)
1535{
1536 uint32_t val;
1537
1538 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1539
1540 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1541 /* Enable both bits, even on read. */
1542 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1543 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1544}
1545
1546
1547/****************************************************************************/
1548/* Disable NVRAM access. */
1549/* */
1550/* When the caller is finished accessing NVRAM access must be disabled. */
1551/* */
1552/* Returns: */
1553/* Nothing. */
1554/****************************************************************************/
1555static void
1556bce_disable_nvram_access(struct bce_softc *sc)
1557{
1558 uint32_t val;
1559
1560 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1561
1562 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1563
1564 /* Disable both bits, even after read. */
1565 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1566 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1567}
1568
1569
43c2aeb0
SZ
1570/****************************************************************************/
1571/* Read a dword (32 bits) from NVRAM. */
1572/* */
1573/* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1574/* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1575/* */
1576/* Returns: */
1577/* 0 on success and the 32 bit value read, positive value on failure. */
1578/****************************************************************************/
1579static int
1580bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1581 uint32_t cmd_flags)
1582{
1583 uint32_t cmd;
1584 int i, rc = 0;
1585
1586 /* Build the command word. */
1587 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1588
1589 /* Calculate the offset for buffered flash. */
d0092544 1590 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
43c2aeb0
SZ
1591 offset = ((offset / sc->bce_flash_info->page_size) <<
1592 sc->bce_flash_info->page_bits) +
1593 (offset % sc->bce_flash_info->page_size);
1594 }
1595
1596 /*
1597 * Clear the DONE bit separately, set the address to read,
1598 * and issue the read.
1599 */
1600 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1601 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1602 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1603
1604 /* Wait for completion. */
1605 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1606 uint32_t val;
1607
1608 DELAY(5);
1609
1610 val = REG_RD(sc, BCE_NVM_COMMAND);
1611 if (val & BCE_NVM_COMMAND_DONE) {
1612 val = REG_RD(sc, BCE_NVM_READ);
1613
1614 val = be32toh(val);
1615 memcpy(ret_val, &val, 4);
1616 break;
1617 }
1618 }
1619
1620 /* Check for errors. */
1621 if (i >= NVRAM_TIMEOUT_COUNT) {
1622 if_printf(&sc->arpcom.ac_if,
1623 "Timeout error reading NVRAM at offset 0x%08X!\n",
1624 offset);
1625 rc = EBUSY;
1626 }
1627 return rc;
1628}
1629
1630
43c2aeb0
SZ
1631/****************************************************************************/
1632/* Initialize NVRAM access. */
1633/* */
1634/* Identify the NVRAM device in use and prepare the NVRAM interface to */
1635/* access that device. */
1636/* */
1637/* Returns: */
1638/* 0 on success, positive value on failure. */
1639/****************************************************************************/
1640static int
1641bce_init_nvram(struct bce_softc *sc)
1642{
1643 uint32_t val;
1644 int j, entry_count, rc = 0;
1645 const struct flash_spec *flash;
1646
1647 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1648
d0092544
SZ
1649 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1650 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1651 sc->bce_flash_info = &flash_5709;
1652 goto bce_init_nvram_get_flash_size;
1653 }
1654
43c2aeb0
SZ
1655 /* Determine the selected interface. */
1656 val = REG_RD(sc, BCE_NVM_CFG1);
1657
1658 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1659
1660 /*
1661 * Flash reconfiguration is required to support additional
1662 * NVRAM devices not directly supported in hardware.
1663 * Check if the flash interface was reconfigured
1664 * by the bootcode.
1665 */
1666
1667 if (val & 0x40000000) {
1668 /* Flash interface reconfigured by bootcode. */
1669
1670 DBPRINT(sc, BCE_INFO_LOAD,
1671 "%s(): Flash WAS reconfigured.\n", __func__);
1672
1673 for (j = 0, flash = flash_table; j < entry_count;
1674 j++, flash++) {
1675 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1676 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1677 sc->bce_flash_info = flash;
1678 break;
1679 }
1680 }
1681 } else {
1682 /* Flash interface not yet reconfigured. */
1683 uint32_t mask;
1684
1685 DBPRINT(sc, BCE_INFO_LOAD,
1686 "%s(): Flash was NOT reconfigured.\n", __func__);
1687
1688 if (val & (1 << 23))
1689 mask = FLASH_BACKUP_STRAP_MASK;
1690 else
1691 mask = FLASH_STRAP_MASK;
1692
1693 /* Look for the matching NVRAM device configuration data. */
1694 for (j = 0, flash = flash_table; j < entry_count;
1695 j++, flash++) {
1696 /* Check if the device matches any of the known devices. */
1697 if ((val & mask) == (flash->strapping & mask)) {
1698 /* Found a device match. */
1699 sc->bce_flash_info = flash;
1700
1701 /* Request access to the flash interface. */
1702 rc = bce_acquire_nvram_lock(sc);
1703 if (rc != 0)
1704 return rc;
1705
1706 /* Reconfigure the flash interface. */
1707 bce_enable_nvram_access(sc);
1708 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1709 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1710 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1711 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1712 bce_disable_nvram_access(sc);
1713 bce_release_nvram_lock(sc);
1714 break;
1715 }
1716 }
1717 }
1718
1719 /* Check if a matching device was found. */
1720 if (j == entry_count) {
1721 sc->bce_flash_info = NULL;
1722 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1723 rc = ENODEV;
1724 }
1725
d0092544 1726bce_init_nvram_get_flash_size:
43c2aeb0 1727 /* Write the flash config data to the shared memory interface. */
bc30d40d
SZ
1728 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1729 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
43c2aeb0
SZ
1730 if (val)
1731 sc->bce_flash_size = val;
1732 else
1733 sc->bce_flash_size = sc->bce_flash_info->total_size;
1734
1735 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1736 __func__, sc->bce_flash_info->total_size);
1737
1738 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1739
1740 return rc;
1741}
1742
1743
1744/****************************************************************************/
1745/* Read an arbitrary range of data from NVRAM. */
1746/* */
1747/* Prepares the NVRAM interface for access and reads the requested data */
1748/* into the supplied buffer. */
1749/* */
1750/* Returns: */
1751/* 0 on success and the data read, positive value on failure. */
1752/****************************************************************************/
1753static int
1754bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1755 int buf_size)
1756{
1757 uint32_t cmd_flags, offset32, len32, extra;
1758 int rc = 0;
1759
1760 if (buf_size == 0)
1761 return 0;
1762
1763 /* Request access to the flash interface. */
1764 rc = bce_acquire_nvram_lock(sc);
1765 if (rc != 0)
1766 return rc;
1767
1768 /* Enable access to flash interface */
1769 bce_enable_nvram_access(sc);
1770
1771 len32 = buf_size;
1772 offset32 = offset;
1773 extra = 0;
1774
1775 cmd_flags = 0;
1776
1777 /* XXX should we release nvram lock if read_dword() fails? */
1778 if (offset32 & 3) {
1779 uint8_t buf[4];
1780 uint32_t pre_len;
1781
1782 offset32 &= ~3;
1783 pre_len = 4 - (offset & 3);
1784
1785 if (pre_len >= len32) {
1786 pre_len = len32;
1787 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1788 } else {
1789 cmd_flags = BCE_NVM_COMMAND_FIRST;
1790 }
1791
1792 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1793 if (rc)
1794 return rc;
1795
1796 memcpy(ret_buf, buf + (offset & 3), pre_len);
1797
1798 offset32 += 4;
1799 ret_buf += pre_len;
1800 len32 -= pre_len;
1801 }
1802
1803 if (len32 & 3) {
1804 extra = 4 - (len32 & 3);
1805 len32 = (len32 + 4) & ~3;
1806 }
1807
1808 if (len32 == 4) {
1809 uint8_t buf[4];
1810
1811 if (cmd_flags)
1812 cmd_flags = BCE_NVM_COMMAND_LAST;
1813 else
1814 cmd_flags = BCE_NVM_COMMAND_FIRST |
1815 BCE_NVM_COMMAND_LAST;
1816
1817 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1818
1819 memcpy(ret_buf, buf, 4 - extra);
1820 } else if (len32 > 0) {
1821 uint8_t buf[4];
1822
1823 /* Read the first word. */
1824 if (cmd_flags)
1825 cmd_flags = 0;
1826 else
1827 cmd_flags = BCE_NVM_COMMAND_FIRST;
1828
1829 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1830
1831 /* Advance to the next dword. */
1832 offset32 += 4;
1833 ret_buf += 4;
1834 len32 -= 4;
1835
1836 while (len32 > 4 && rc == 0) {
1837 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1838
1839 /* Advance to the next dword. */
1840 offset32 += 4;
1841 ret_buf += 4;
1842 len32 -= 4;
1843 }
1844
1845 if (rc)
d0092544 1846 goto bce_nvram_read_locked_exit;
43c2aeb0
SZ
1847
1848 cmd_flags = BCE_NVM_COMMAND_LAST;
1849 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1850
1851 memcpy(ret_buf, buf, 4 - extra);
1852 }
1853
d0092544 1854bce_nvram_read_locked_exit:
43c2aeb0
SZ
1855 /* Disable access to flash interface and release the lock. */
1856 bce_disable_nvram_access(sc);
1857 bce_release_nvram_lock(sc);
1858
1859 return rc;
1860}
1861
1862
43c2aeb0
SZ
1863/****************************************************************************/
1864/* Verifies that NVRAM is accessible and contains valid data. */
1865/* */
1866/* Reads the configuration data from NVRAM and verifies that the CRC is */
1867/* correct. */
1868/* */
1869/* Returns: */
1870/* 0 on success, positive value on failure. */
1871/****************************************************************************/
1872static int
1873bce_nvram_test(struct bce_softc *sc)
1874{
1875 uint32_t buf[BCE_NVRAM_SIZE / 4];
1876 uint32_t magic, csum;
1877 uint8_t *data = (uint8_t *)buf;
1878 int rc = 0;
1879
1880 /*
1881 * Check that the device NVRAM is valid by reading
1882 * the magic value at offset 0.
1883 */
1884 rc = bce_nvram_read(sc, 0, data, 4);
1885 if (rc != 0)
1886 return rc;
1887
1888 magic = be32toh(buf[0]);
1889 if (magic != BCE_NVRAM_MAGIC) {
1890 if_printf(&sc->arpcom.ac_if,
1891 "Invalid NVRAM magic value! Expected: 0x%08X, "
1892 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1893 return ENODEV;
1894 }
1895
1896 /*
1897 * Verify that the device NVRAM includes valid
1898 * configuration data.
1899 */
1900 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1901 if (rc != 0)
1902 return rc;
1903
1904 csum = ether_crc32_le(data, 0x100);
1905 if (csum != BCE_CRC32_RESIDUAL) {
1906 if_printf(&sc->arpcom.ac_if,
1907 "Invalid Manufacturing Information NVRAM CRC! "
1908 "Expected: 0x%08X, Found: 0x%08X\n",
1909 BCE_CRC32_RESIDUAL, csum);
1910 return ENODEV;
1911 }
1912
1913 csum = ether_crc32_le(data + 0x100, 0x100);
1914 if (csum != BCE_CRC32_RESIDUAL) {
1915 if_printf(&sc->arpcom.ac_if,
1916 "Invalid Feature Configuration Information "
1917 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1918 BCE_CRC32_RESIDUAL, csum);
1919 rc = ENODEV;
1920 }
1921 return rc;
1922}
1923
1924
1925/****************************************************************************/
d0092544
SZ
1926/* Identifies the current media type of the controller and sets the PHY */
1927/* address. */
1928/* */
1929/* Returns: */
1930/* Nothing. */
1931/****************************************************************************/
1932static void
1933bce_get_media(struct bce_softc *sc)
1934{
1935 uint32_t val;
1936
1937 sc->bce_phy_addr = 1;
1938
1939 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1940 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1941 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1942 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1943 uint32_t strap;
1944
1945 /*
1946 * The BCM5709S is software configurable
1947 * for Copper or SerDes operation.
1948 */
1949 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1950 return;
1951 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1952 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1953 return;
1954 }
1955
1956 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1957 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1958 } else {
1959 strap =
1960 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1961 }
1962
1963 if (pci_get_function(sc->bce_dev) == 0) {
1964 switch (strap) {
1965 case 0x4:
1966 case 0x5:
1967 case 0x6:
1968 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1969 break;
1970 }
1971 } else {
1972 switch (strap) {
1973 case 0x1:
1974 case 0x2:
1975 case 0x4:
1976 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1977 break;
1978 }
1979 }
1980 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1981 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1982 }
1983
1984 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1985 sc->bce_flags |= BCE_NO_WOL_FLAG;
1986 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1987 sc->bce_phy_addr = 2;
bc30d40d 1988 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
d0092544
SZ
1989 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1990 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1991 }
1992 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1993 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1994 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1995 }
1996}
1997
1998
1999/****************************************************************************/
43c2aeb0
SZ
2000/* Free any DMA memory owned by the driver. */
2001/* */
2002/* Scans through each data structre that requires DMA memory and frees */
2003/* the memory if allocated. */
2004/* */
2005/* Returns: */
2006/* Nothing. */
2007/****************************************************************************/
2008static void
2009bce_dma_free(struct bce_softc *sc)
2010{
2011 int i;
2012
2013 /* Destroy the status block. */
2014 if (sc->status_tag != NULL) {
2015 if (sc->status_block != NULL) {
2016 bus_dmamap_unload(sc->status_tag, sc->status_map);
2017 bus_dmamem_free(sc->status_tag, sc->status_block,
2018 sc->status_map);
2019 }
2020 bus_dma_tag_destroy(sc->status_tag);
2021 }
2022
2023
2024 /* Destroy the statistics block. */
2025 if (sc->stats_tag != NULL) {
2026 if (sc->stats_block != NULL) {
2027 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2028 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2029 sc->stats_map);
2030 }
2031 bus_dma_tag_destroy(sc->stats_tag);
2032 }
2033
d0092544
SZ
2034 /* Destroy the CTX DMA stuffs. */
2035 if (sc->ctx_tag != NULL) {
2036 for (i = 0; i < sc->ctx_pages; i++) {
2037 if (sc->ctx_block[i] != NULL) {
2038 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2039 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2040 sc->ctx_map[i]);
2041 }
2042 }
2043 bus_dma_tag_destroy(sc->ctx_tag);
2044 }
2045
43c2aeb0
SZ
2046 /* Destroy the TX buffer descriptor DMA stuffs. */
2047 if (sc->tx_bd_chain_tag != NULL) {
2048 for (i = 0; i < TX_PAGES; i++) {
2049 if (sc->tx_bd_chain[i] != NULL) {
2050 bus_dmamap_unload(sc->tx_bd_chain_tag,
2051 sc->tx_bd_chain_map[i]);
2052 bus_dmamem_free(sc->tx_bd_chain_tag,
2053 sc->tx_bd_chain[i],
2054 sc->tx_bd_chain_map[i]);
2055 }
2056 }
2057 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2058 }
2059
2060 /* Destroy the RX buffer descriptor DMA stuffs. */
2061 if (sc->rx_bd_chain_tag != NULL) {
2062 for (i = 0; i < RX_PAGES; i++) {
2063 if (sc->rx_bd_chain[i] != NULL) {
2064 bus_dmamap_unload(sc->rx_bd_chain_tag,
2065 sc->rx_bd_chain_map[i]);
2066 bus_dmamem_free(sc->rx_bd_chain_tag,
2067 sc->rx_bd_chain[i],
2068 sc->rx_bd_chain_map[i]);
2069 }
2070 }
2071 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2072 }
2073
2074 /* Destroy the TX mbuf DMA stuffs. */
2075 if (sc->tx_mbuf_tag != NULL) {
2076 for (i = 0; i < TOTAL_TX_BD; i++) {
2077 /* Must have been unloaded in bce_stop() */
2078 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2079 bus_dmamap_destroy(sc->tx_mbuf_tag,
2080 sc->tx_mbuf_map[i]);
2081 }
2082 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2083 }
2084
2085 /* Destroy the RX mbuf DMA stuffs. */
2086 if (sc->rx_mbuf_tag != NULL) {
2087 for (i = 0; i < TOTAL_RX_BD; i++) {
2088 /* Must have been unloaded in bce_stop() */
2089 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2090 bus_dmamap_destroy(sc->rx_mbuf_tag,
2091 sc->rx_mbuf_map[i]);
2092 }
c36fd9ee 2093 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
43c2aeb0
SZ
2094 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2095 }
2096
2097 /* Destroy the parent tag */
2098 if (sc->parent_tag != NULL)
2099 bus_dma_tag_destroy(sc->parent_tag);
2100}
2101
2102
2103/****************************************************************************/
2104/* Get DMA memory from the OS. */
2105/* */
2106/* Validates that the OS has provided DMA buffers in response to a */
2107/* bus_dmamap_load() call and saves the physical address of those buffers. */
2108/* When the callback is used the OS will return 0 for the mapping function */
2109/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2110/* failures back to the caller. */
2111/* */
2112/* Returns: */
2113/* Nothing. */
2114/****************************************************************************/
2115static void
2116bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2117{
2118 bus_addr_t *busaddr = arg;
2119
2120 /*
2121 * Simulate a mapping failure.
2122 * XXX not correct.
2123 */
2124 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2125 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2126 __FILE__, __LINE__);
2127 error = ENOMEM);
2128
2129 /* Check for an error and signal the caller that an error occurred. */
2130 if (error)
2131 return;
2132
2133 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2134 *busaddr = segs->ds_addr;
2135}
2136
2137
43c2aeb0
SZ
2138/****************************************************************************/
2139/* Allocate any DMA memory needed by the driver. */
2140/* */
2141/* Allocates DMA memory needed for the various global structures needed by */
2142/* hardware. */
2143/* */
cffea833 2144/* Memory alignment requirements: */
d0092544
SZ
2145/* -----------------+----------+----------+----------+----------+ */
2146/* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2147/* -----------------+----------+----------+----------+----------+ */
2148/* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2149/* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2150/* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2151/* PG Buffers | none | none | none | none | */
2152/* TX Buffers | none | none | none | none | */
2153/* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2154/* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2155/* -----------------+----------+----------+----------+----------+ */
cffea833
SZ
2156/* */
2157/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2158/* */
43c2aeb0
SZ
2159/* Returns: */
2160/* 0 for success, positive value for failure. */
2161/****************************************************************************/
2162static int
2163bce_dma_alloc(struct bce_softc *sc)
2164{
2165 struct ifnet *ifp = &sc->arpcom.ac_if;
2166 int i, j, rc = 0;
d0092544
SZ
2167 bus_addr_t busaddr, max_busaddr;
2168 bus_size_t status_align, stats_align;
2169
2170 /*
2171 * The embedded PCIe to PCI-X bridge (EPB)
2172 * in the 5708 cannot address memory above
2173 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2174 */
2175 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2176 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2177 else
2178 max_busaddr = BUS_SPACE_MAXADDR;
2179
2180 /*
2181 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2182 */
2183 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2184 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2185 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2186 if (sc->ctx_pages == 0)
2187 sc->ctx_pages = 1;
2188 if (sc->ctx_pages > BCE_CTX_PAGES) {
2189 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2190 sc->ctx_pages);
2191 return ENOMEM;
2192 }
2193 status_align = 16;
2194 stats_align = 16;
2195 } else {
2196 status_align = 8;
2197 stats_align = 8;
2198 }
43c2aeb0
SZ
2199
2200 /*
2201 * Allocate the parent bus DMA tag appropriate for PCI.
2202 */
2203 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
d0092544 2204 max_busaddr, BUS_SPACE_MAXADDR,
43c2aeb0 2205 NULL, NULL,
45010e4d 2206 BUS_SPACE_MAXSIZE_32BIT, 0,
43c2aeb0
SZ
2207 BUS_SPACE_MAXSIZE_32BIT,
2208 0, &sc->parent_tag);
2209 if (rc != 0) {
2210 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2211 return rc;
2212 }
2213
2214 /*
4a458e9d 2215 * Allocate status block.
43c2aeb0 2216 */
4a458e9d 2217 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2218 status_align, BCE_STATUS_BLK_SZ,
4a458e9d
SZ
2219 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2220 &sc->status_tag, &sc->status_map,
2221 &sc->status_block_paddr);
2222 if (sc->status_block == NULL) {
2223 if_printf(ifp, "Could not allocate status block!\n");
2224 return ENOMEM;
43c2aeb0
SZ
2225 }
2226
43c2aeb0 2227 /*
4a458e9d 2228 * Allocate statistics block.
43c2aeb0 2229 */
4a458e9d 2230 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2231 stats_align, BCE_STATS_BLK_SZ,
4a458e9d
SZ
2232 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2233 &sc->stats_tag, &sc->stats_map,
2234 &sc->stats_block_paddr);
2235 if (sc->stats_block == NULL) {
2236 if_printf(ifp, "Could not allocate statistics block!\n");
2237 return ENOMEM;
43c2aeb0
SZ
2238 }
2239
43c2aeb0 2240 /*
d0092544
SZ
2241 * Allocate context block, if needed
2242 */
2243 if (sc->ctx_pages != 0) {
2244 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2245 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2246 NULL, NULL,
2247 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2248 0, &sc->ctx_tag);
2249 if (rc != 0) {
2250 if_printf(ifp, "Could not allocate "
2251 "context block DMA tag!\n");
2252 return rc;
2253 }
2254
2255 for (i = 0; i < sc->ctx_pages; i++) {
2256 rc = bus_dmamem_alloc(sc->ctx_tag,
2257 (void **)&sc->ctx_block[i],
2258 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2259 BUS_DMA_COHERENT,
2260 &sc->ctx_map[i]);
2261 if (rc != 0) {
2262 if_printf(ifp, "Could not allocate %dth context "
2263 "DMA memory!\n", i);
2264 return rc;
2265 }
2266
2267 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2268 sc->ctx_block[i], BCM_PAGE_SIZE,
2269 bce_dma_map_addr, &busaddr,
2270 BUS_DMA_WAITOK);
2271 if (rc != 0) {
2272 if (rc == EINPROGRESS) {
2273 panic("%s coherent memory loading "
2274 "is still in progress!", ifp->if_xname);
2275 }
2276 if_printf(ifp, "Could not map %dth context "
2277 "DMA memory!\n", i);
2278 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2279 sc->ctx_map[i]);
2280 sc->ctx_block[i] = NULL;
2281 return rc;
2282 }
2283 sc->ctx_paddr[i] = busaddr;
2284 }
2285 }
2286
2287 /*
43c2aeb0
SZ
2288 * Create a DMA tag for the TX buffer descriptor chain,
2289 * allocate and clear the memory, and fetch the
2290 * physical address of the block.
2291 */
4a458e9d
SZ
2292 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2293 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ
2294 NULL, NULL,
2295 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2296 0, &sc->tx_bd_chain_tag);
2297 if (rc != 0) {
2298 if_printf(ifp, "Could not allocate "
2299 "TX descriptor chain DMA tag!\n");
2300 return rc;
2301 }
2302
2303 for (i = 0; i < TX_PAGES; i++) {
2304 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2305 (void **)&sc->tx_bd_chain[i],
4a458e9d
SZ
2306 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2307 BUS_DMA_COHERENT,
2308 &sc->tx_bd_chain_map[i]);
43c2aeb0
SZ
2309 if (rc != 0) {
2310 if_printf(ifp, "Could not allocate %dth TX descriptor "
2311 "chain DMA memory!\n", i);
2312 return rc;
2313 }
2314
2315 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2316 sc->tx_bd_chain_map[i],
2317 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2318 bce_dma_map_addr, &busaddr,
2319 BUS_DMA_WAITOK);
2320 if (rc != 0) {
4a458e9d
SZ
2321 if (rc == EINPROGRESS) {
2322 panic("%s coherent memory loading "
2323 "is still in progress!", ifp->if_xname);
2324 }
43c2aeb0
SZ
2325 if_printf(ifp, "Could not map %dth TX descriptor "
2326 "chain DMA memory!\n", i);
2327 bus_dmamem_free(sc->tx_bd_chain_tag,
2328 sc->tx_bd_chain[i],
2329 sc->tx_bd_chain_map[i]);
2330 sc->tx_bd_chain[i] = NULL;
2331 return rc;
2332 }
2333
2334 sc->tx_bd_chain_paddr[i] = busaddr;
2335 /* DRC - Fix for 64 bit systems. */
2336 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2337 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2338 }
2339
2340 /* Create a DMA tag for TX mbufs. */
45010e4d
SZ
2341 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2342 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2343 NULL, NULL,
45010e4d 2344 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
43c2aeb0 2345 BCE_MAX_SEGMENTS, MCLBYTES,
45010e4d
SZ
2346 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2347 BUS_DMA_ONEBPAGE,
2348 &sc->tx_mbuf_tag);
43c2aeb0
SZ
2349 if (rc != 0) {
2350 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2351 return rc;
2352 }
2353
2354 /* Create DMA maps for the TX mbufs clusters. */
2355 for (i = 0; i < TOTAL_TX_BD; i++) {
45010e4d
SZ
2356 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2357 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
43c2aeb0
SZ
2358 &sc->tx_mbuf_map[i]);
2359 if (rc != 0) {
2360 for (j = 0; j < i; ++j) {
2361 bus_dmamap_destroy(sc->tx_mbuf_tag,
2362 sc->tx_mbuf_map[i]);
2363 }
2364 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2365 sc->tx_mbuf_tag = NULL;
2366
2367 if_printf(ifp, "Unable to create "
2368 "%dth TX mbuf DMA map!\n", i);
2369 return rc;
2370 }
2371 }
2372
2373 /*
2374 * Create a DMA tag for the RX buffer descriptor chain,
2375 * allocate and clear the memory, and fetch the physical
2376 * address of the blocks.
2377 */
4a458e9d
SZ
2378 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2379 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ
2380 NULL, NULL,
2381 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2382 0, &sc->rx_bd_chain_tag);
2383 if (rc != 0) {
2384 if_printf(ifp, "Could not allocate "
2385 "RX descriptor chain DMA tag!\n");
2386 return rc;
2387 }
2388
2389 for (i = 0; i < RX_PAGES; i++) {
2390 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2391 (void **)&sc->rx_bd_chain[i],
4a458e9d
SZ
2392 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2393 BUS_DMA_COHERENT,
43c2aeb0
SZ
2394 &sc->rx_bd_chain_map[i]);
2395 if (rc != 0) {
2396 if_printf(ifp, "Could not allocate %dth RX descriptor "
2397 "chain DMA memory!\n", i);
2398 return rc;
2399 }
2400
2401 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2402 sc->rx_bd_chain_map[i],
2403 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2404 bce_dma_map_addr, &busaddr,
2405 BUS_DMA_WAITOK);
2406 if (rc != 0) {
4a458e9d
SZ
2407 if (rc == EINPROGRESS) {
2408 panic("%s coherent memory loading "
2409 "is still in progress!", ifp->if_xname);
2410 }
43c2aeb0
SZ
2411 if_printf(ifp, "Could not map %dth RX descriptor "
2412 "chain DMA memory!\n", i);
2413 bus_dmamem_free(sc->rx_bd_chain_tag,
2414 sc->rx_bd_chain[i],
2415 sc->rx_bd_chain_map[i]);
2416 sc->rx_bd_chain[i] = NULL;
2417 return rc;
2418 }
2419
2420 sc->rx_bd_chain_paddr[i] = busaddr;
2421 /* DRC - Fix for 64 bit systems. */
2422 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2423 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2424 }
2425
2426 /* Create a DMA tag for RX mbufs. */
cffea833 2427 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
45010e4d 2428 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2429 NULL, NULL,
45010e4d 2430 MCLBYTES, 1, MCLBYTES,
cffea833
SZ
2431 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2432 BUS_DMA_WAITOK,
45010e4d 2433 &sc->rx_mbuf_tag);
43c2aeb0
SZ
2434 if (rc != 0) {
2435 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2436 return rc;
2437 }
2438
c36fd9ee
SZ
2439 /* Create tmp DMA map for RX mbuf clusters. */
2440 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2441 &sc->rx_mbuf_tmpmap);
2442 if (rc != 0) {
2443 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2444 sc->rx_mbuf_tag = NULL;
2445
2446 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2447 return rc;
2448 }
2449
43c2aeb0
SZ
2450 /* Create DMA maps for the RX mbuf clusters. */
2451 for (i = 0; i < TOTAL_RX_BD; i++) {
2452 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2453 &sc->rx_mbuf_map[i]);
2454 if (rc != 0) {
2455 for (j = 0; j < i; ++j) {
2456 bus_dmamap_destroy(sc->rx_mbuf_tag,
2457 sc->rx_mbuf_map[j]);
2458 }
2459 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2460 sc->rx_mbuf_tag = NULL;
2461
2462 if_printf(ifp, "Unable to create "
2463 "%dth RX mbuf DMA map!\n", i);
2464 return rc;
2465 }
2466 }
2467 return 0;
2468}
2469
2470
2471/****************************************************************************/
2472/* Firmware synchronization. */
2473/* */
2474/* Before performing certain events such as a chip reset, synchronize with */
2475/* the firmware first. */
2476/* */
2477/* Returns: */
2478/* 0 for success, positive value for failure. */
2479/****************************************************************************/
2480static int
2481bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2482{
2483 int i, rc = 0;
2484 uint32_t val;
2485
2486 /* Don't waste any time if we've timed out before. */
2487 if (sc->bce_fw_timed_out)
2488 return EBUSY;
2489
2490 /* Increment the message sequence number. */
2491 sc->bce_fw_wr_seq++;
2492 msg_data |= sc->bce_fw_wr_seq;
2493
2494 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2495
2496 /* Send the message to the bootcode driver mailbox. */
bc30d40d 2497 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ
2498
2499 /* Wait for the bootcode to acknowledge the message. */
2500 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2501 /* Check for a response in the bootcode firmware mailbox. */
bc30d40d 2502 val = bce_shmem_rd(sc, BCE_FW_MB);
43c2aeb0
SZ
2503 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2504 break;
2505 DELAY(1000);
2506 }
2507
2508 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2509 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2510 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2511 if_printf(&sc->arpcom.ac_if,
2512 "Firmware synchronization timeout! "
2513 "msg_data = 0x%08X\n", msg_data);
2514
2515 msg_data &= ~BCE_DRV_MSG_CODE;
2516 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2517
bc30d40d 2518 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ
2519
2520 sc->bce_fw_timed_out = 1;
2521 rc = EBUSY;
2522 }
2523 return rc;
2524}
2525
2526
2527/****************************************************************************/
2528/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2529/* */
2530/* Returns: */
2531/* Nothing. */
2532/****************************************************************************/
2533static void
2534bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2535 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2536{
2537 int i;
2538 uint32_t val;
2539
2540 for (i = 0; i < rv2p_code_len; i += 8) {
2541 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2542 rv2p_code++;
2543 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2544 rv2p_code++;
2545
2546 if (rv2p_proc == RV2P_PROC1) {
2547 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2548 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2549 } else {
2550 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2551 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2552 }
2553 }
2554
2555 /* Reset the processor, un-stall is done later. */
2556 if (rv2p_proc == RV2P_PROC1)
2557 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2558 else
2559 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2560}
2561
2562
2563/****************************************************************************/
2564/* Load RISC processor firmware. */
2565/* */
2566/* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2567/* associated with a particular processor. */
2568/* */
2569/* Returns: */
2570/* Nothing. */
2571/****************************************************************************/
2572static void
2573bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2574 struct fw_info *fw)
2575{
5d05a208 2576 uint32_t offset;
43c2aeb0
SZ
2577 int j;
2578
5d05a208 2579 bce_halt_cpu(sc, cpu_reg);
43c2aeb0
SZ
2580
2581 /* Load the Text area. */
2582 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2583 if (fw->text) {
2584 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2585 REG_WR_IND(sc, offset, fw->text[j]);
2586 }
2587
2588 /* Load the Data area. */
2589 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2590 if (fw->data) {
2591 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2592 REG_WR_IND(sc, offset, fw->data[j]);
2593 }
2594
2595 /* Load the SBSS area. */
2596 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2597 if (fw->sbss) {
2598 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2599 REG_WR_IND(sc, offset, fw->sbss[j]);
2600 }
2601
2602 /* Load the BSS area. */
2603 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2604 if (fw->bss) {
2605 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2606 REG_WR_IND(sc, offset, fw->bss[j]);
2607 }
2608
2609 /* Load the Read-Only area. */
2610 offset = cpu_reg->spad_base +
2611 (fw->rodata_addr - cpu_reg->mips_view_base);
2612 if (fw->rodata) {
2613 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2614 REG_WR_IND(sc, offset, fw->rodata[j]);
2615 }
2616
5d05a208 2617 /* Clear the pre-fetch instruction and set the FW start address. */
43c2aeb0
SZ
2618 REG_WR_IND(sc, cpu_reg->inst, 0);
2619 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
5d05a208
SZ
2620}
2621
2622
2623/****************************************************************************/
2624/* Starts the RISC processor. */
2625/* */
2626/* Assumes the CPU starting address has already been set. */
2627/* */
2628/* Returns: */
2629/* Nothing. */
2630/****************************************************************************/
2631static void
2632bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2633{
2634 uint32_t val;
43c2aeb0
SZ
2635
2636 /* Start the CPU. */
2637 val = REG_RD_IND(sc, cpu_reg->mode);
2638 val &= ~cpu_reg->mode_value_halt;
2639 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2640 REG_WR_IND(sc, cpu_reg->mode, val);
2641}
2642
2643
2644/****************************************************************************/
5d05a208
SZ
2645/* Halts the RISC processor. */
2646/* */
2647/* Returns: */
2648/* Nothing. */
2649/****************************************************************************/
2650static void
2651bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2652{
2653 uint32_t val;
2654
2655 /* Halt the CPU. */
2656 val = REG_RD_IND(sc, cpu_reg->mode);
2657 val |= cpu_reg->mode_value_halt;
2658 REG_WR_IND(sc, cpu_reg->mode, val);
2659 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2660}
2661
2662
2663/****************************************************************************/
2664/* Start the RX CPU. */
2665/* */
2666/* Returns: */
2667/* Nothing. */
2668/****************************************************************************/
2669static void
2670bce_start_rxp_cpu(struct bce_softc *sc)
2671{
2672 struct cpu_reg cpu_reg;
2673
2674 cpu_reg.mode = BCE_RXP_CPU_MODE;
2675 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2676 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2677 cpu_reg.state = BCE_RXP_CPU_STATE;
2678 cpu_reg.state_value_clear = 0xffffff;
2679 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2680 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2681 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2682 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2683 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2684 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2685 cpu_reg.mips_view_base = 0x8000000;
2686
2687 bce_start_cpu(sc, &cpu_reg);
2688}
2689
2690
2691/****************************************************************************/
d0092544 2692/* Initialize the RX CPU. */
43c2aeb0
SZ
2693/* */
2694/* Returns: */
2695/* Nothing. */
2696/****************************************************************************/
2697static void
d0092544 2698bce_init_rxp_cpu(struct bce_softc *sc)
43c2aeb0
SZ
2699{
2700 struct cpu_reg cpu_reg;
2701 struct fw_info fw;
2702
43c2aeb0
SZ
2703 cpu_reg.mode = BCE_RXP_CPU_MODE;
2704 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2705 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2706 cpu_reg.state = BCE_RXP_CPU_STATE;
2707 cpu_reg.state_value_clear = 0xffffff;
2708 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2709 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2710 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2711 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2712 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2713 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2714 cpu_reg.mips_view_base = 0x8000000;
2715
d0092544
SZ
2716 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2717 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2718 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2719 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2720 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2721 fw.start_addr = bce_RXP_b09FwStartAddr;
2722
2723 fw.text_addr = bce_RXP_b09FwTextAddr;
2724 fw.text_len = bce_RXP_b09FwTextLen;
2725 fw.text_index = 0;
2726 fw.text = bce_RXP_b09FwText;
2727
2728 fw.data_addr = bce_RXP_b09FwDataAddr;
2729 fw.data_len = bce_RXP_b09FwDataLen;
2730 fw.data_index = 0;
2731 fw.data = bce_RXP_b09FwData;
2732
2733 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2734 fw.sbss_len = bce_RXP_b09FwSbssLen;
2735 fw.sbss_index = 0;
2736 fw.sbss = bce_RXP_b09FwSbss;
2737
2738 fw.bss_addr = bce_RXP_b09FwBssAddr;
2739 fw.bss_len = bce_RXP_b09FwBssLen;
2740 fw.bss_index = 0;
2741 fw.bss = bce_RXP_b09FwBss;
2742
2743 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2744 fw.rodata_len = bce_RXP_b09FwRodataLen;
2745 fw.rodata_index = 0;
2746 fw.rodata = bce_RXP_b09FwRodata;
2747 } else {
2748 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2749 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2750 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2751 fw.start_addr = bce_RXP_b06FwStartAddr;
2752
2753 fw.text_addr = bce_RXP_b06FwTextAddr;
2754 fw.text_len = bce_RXP_b06FwTextLen;
2755 fw.text_index = 0;
2756 fw.text = bce_RXP_b06FwText;
2757
2758 fw.data_addr = bce_RXP_b06FwDataAddr;
2759 fw.data_len = bce_RXP_b06FwDataLen;
2760 fw.data_index = 0;
2761 fw.data = bce_RXP_b06FwData;
2762
2763 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2764 fw.sbss_len = bce_RXP_b06FwSbssLen;
2765 fw.sbss_index = 0;
2766 fw.sbss = bce_RXP_b06FwSbss;
2767
2768 fw.bss_addr = bce_RXP_b06FwBssAddr;
2769 fw.bss_len = bce_RXP_b06FwBssLen;
2770 fw.bss_index = 0;
2771 fw.bss = bce_RXP_b06FwBss;
2772
2773 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2774 fw.rodata_len = bce_RXP_b06FwRodataLen;
2775 fw.rodata_index = 0;
2776 fw.rodata = bce_RXP_b06FwRodata;
2777 }
43c2aeb0
SZ
2778
2779 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2780 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2781 /* Delay RXP start until initialization is complete. */
d0092544
SZ
2782}
2783
2784
2785/****************************************************************************/
2786/* Initialize the TX CPU. */
2787/* */
2788/* Returns: */
2789/* Nothing. */
2790/****************************************************************************/
2791static void
2792bce_init_txp_cpu(struct bce_softc *sc)
2793{
2794 struct cpu_reg cpu_reg;
2795 struct fw_info fw;
43c2aeb0 2796
43c2aeb0
SZ
2797 cpu_reg.mode = BCE_TXP_CPU_MODE;
2798 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2799 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2800 cpu_reg.state = BCE_TXP_CPU_STATE;
2801 cpu_reg.state_value_clear = 0xffffff;
2802 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2803 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2804 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2805 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2806 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2807 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2808 cpu_reg.mips_view_base = 0x8000000;
2809
d0092544
SZ
2810 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2811 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2812 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2813 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2814 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2815 fw.start_addr = bce_TXP_b09FwStartAddr;
2816
2817 fw.text_addr = bce_TXP_b09FwTextAddr;
2818 fw.text_len = bce_TXP_b09FwTextLen;
2819 fw.text_index = 0;
2820 fw.text = bce_TXP_b09FwText;
2821
2822 fw.data_addr = bce_TXP_b09FwDataAddr;
2823 fw.data_len = bce_TXP_b09FwDataLen;
2824 fw.data_index = 0;
2825 fw.data = bce_TXP_b09FwData;
2826
2827 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2828 fw.sbss_len = bce_TXP_b09FwSbssLen;
2829 fw.sbss_index = 0;
2830 fw.sbss = bce_TXP_b09FwSbss;
2831
2832 fw.bss_addr = bce_TXP_b09FwBssAddr;
2833 fw.bss_len = bce_TXP_b09FwBssLen;
2834 fw.bss_index = 0;
2835 fw.bss = bce_TXP_b09FwBss;
2836
2837 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2838 fw.rodata_len = bce_TXP_b09FwRodataLen;
2839 fw.rodata_index = 0;
2840 fw.rodata = bce_TXP_b09FwRodata;
2841 } else {
2842 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2843 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2844 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2845 fw.start_addr = bce_TXP_b06FwStartAddr;
2846
2847 fw.text_addr = bce_TXP_b06FwTextAddr;
2848 fw.text_len = bce_TXP_b06FwTextLen;
2849 fw.text_index = 0;
2850 fw.text = bce_TXP_b06FwText;
2851
2852 fw.data_addr = bce_TXP_b06FwDataAddr;
2853 fw.data_len = bce_TXP_b06FwDataLen;
2854 fw.data_index = 0;
2855 fw.data = bce_TXP_b06FwData;
2856
2857 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2858 fw.sbss_len = bce_TXP_b06FwSbssLen;
2859 fw.sbss_index = 0;
2860 fw.sbss = bce_TXP_b06FwSbss;
2861
2862 fw.bss_addr = bce_TXP_b06FwBssAddr;
2863 fw.bss_len = bce_TXP_b06FwBssLen;
2864 fw.bss_index = 0;
2865 fw.bss = bce_TXP_b06FwBss;
2866
2867 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2868 fw.rodata_len = bce_TXP_b06FwRodataLen;
2869 fw.rodata_index = 0;
2870 fw.rodata = bce_TXP_b06FwRodata;
2871 }
43c2aeb0
SZ
2872
2873 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2874 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2875 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ
2876}
2877
2878
2879/****************************************************************************/
2880/* Initialize the TPAT CPU. */
2881/* */
2882/* Returns: */
2883/* Nothing. */
2884/****************************************************************************/
2885static void
2886bce_init_tpat_cpu(struct bce_softc *sc)
2887{
2888 struct cpu_reg cpu_reg;
2889 struct fw_info fw;
43c2aeb0 2890
43c2aeb0
SZ
2891 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2892 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2893 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2894 cpu_reg.state = BCE_TPAT_CPU_STATE;
2895 cpu_reg.state_value_clear = 0xffffff;
2896 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2897 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2898 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2899 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2900 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2901 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2902 cpu_reg.mips_view_base = 0x8000000;
2903
d0092544
SZ
2904 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2905 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2906 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2907 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2908 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2909 fw.start_addr = bce_TPAT_b09FwStartAddr;
2910
2911 fw.text_addr = bce_TPAT_b09FwTextAddr;
2912 fw.text_len = bce_TPAT_b09FwTextLen;
2913 fw.text_index = 0;
2914 fw.text = bce_TPAT_b09FwText;
2915
2916 fw.data_addr = bce_TPAT_b09FwDataAddr;
2917 fw.data_len = bce_TPAT_b09FwDataLen;
2918 fw.data_index = 0;
2919 fw.data = bce_TPAT_b09FwData;
2920
2921 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2922 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2923 fw.sbss_index = 0;
2924 fw.sbss = bce_TPAT_b09FwSbss;
2925
2926 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2927 fw.bss_len = bce_TPAT_b09FwBssLen;
2928 fw.bss_index = 0;
2929 fw.bss = bce_TPAT_b09FwBss;
2930
2931 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2932 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2933 fw.rodata_index = 0;
2934 fw.rodata = bce_TPAT_b09FwRodata;
2935 } else {
2936 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2937 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2938 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2939 fw.start_addr = bce_TPAT_b06FwStartAddr;
2940
2941 fw.text_addr = bce_TPAT_b06FwTextAddr;
2942 fw.text_len = bce_TPAT_b06FwTextLen;
2943 fw.text_index = 0;
2944 fw.text = bce_TPAT_b06FwText;
2945
2946 fw.data_addr = bce_TPAT_b06FwDataAddr;
2947 fw.data_len = bce_TPAT_b06FwDataLen;
2948 fw.data_index = 0;
2949 fw.data = bce_TPAT_b06FwData;
2950
2951 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2952 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2953 fw.sbss_index = 0;
2954 fw.sbss = bce_TPAT_b06FwSbss;
2955
2956 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2957 fw.bss_len = bce_TPAT_b06FwBssLen;
2958 fw.bss_index = 0;
2959 fw.bss = bce_TPAT_b06FwBss;
2960
2961 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2962 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2963 fw.rodata_index = 0;
2964 fw.rodata = bce_TPAT_b06FwRodata;
2965 }
43c2aeb0 2966
d0092544
SZ
2967 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2968 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2969 bce_start_cpu(sc, &cpu_reg);
d0092544 2970}
43c2aeb0 2971
43c2aeb0 2972
d0092544
SZ
2973/****************************************************************************/
2974/* Initialize the CP CPU. */
2975/* */
2976/* Returns: */
2977/* Nothing. */
2978/****************************************************************************/
2979static void
2980bce_init_cp_cpu(struct bce_softc *sc)
2981{
2982 struct cpu_reg cpu_reg;
2983 struct fw_info fw;
43c2aeb0 2984
d0092544
SZ
2985 cpu_reg.mode = BCE_CP_CPU_MODE;
2986 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2987 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2988 cpu_reg.state = BCE_CP_CPU_STATE;
2989 cpu_reg.state_value_clear = 0xffffff;
2990 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2991 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2992 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2993 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2994 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2995 cpu_reg.spad_base = BCE_CP_SCRATCH;
2996 cpu_reg.mips_view_base = 0x8000000;
43c2aeb0 2997
d0092544
SZ
2998 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2999 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3000 fw.ver_major = bce_CP_b09FwReleaseMajor;
3001 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3002 fw.ver_fix = bce_CP_b09FwReleaseFix;
3003 fw.start_addr = bce_CP_b09FwStartAddr;
3004
3005 fw.text_addr = bce_CP_b09FwTextAddr;
3006 fw.text_len = bce_CP_b09FwTextLen;
3007 fw.text_index = 0;
3008 fw.text = bce_CP_b09FwText;
3009
3010 fw.data_addr = bce_CP_b09FwDataAddr;
3011 fw.data_len = bce_CP_b09FwDataLen;
3012 fw.data_index = 0;
3013 fw.data = bce_CP_b09FwData;
3014
3015 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3016 fw.sbss_len = bce_CP_b09FwSbssLen;
3017 fw.sbss_index = 0;
3018 fw.sbss = bce_CP_b09FwSbss;
3019
3020 fw.bss_addr = bce_CP_b09FwBssAddr;
3021 fw.bss_len = bce_CP_b09FwBssLen;
3022 fw.bss_index = 0;
3023 fw.bss = bce_CP_b09FwBss;
3024
3025 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3026 fw.rodata_len = bce_CP_b09FwRodataLen;
3027 fw.rodata_index = 0;
3028 fw.rodata = bce_CP_b09FwRodata;
3029 } else {
3030 fw.ver_major = bce_CP_b06FwReleaseMajor;
3031 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3032 fw.ver_fix = bce_CP_b06FwReleaseFix;
3033 fw.start_addr = bce_CP_b06FwStartAddr;
3034
3035 fw.text_addr = bce_CP_b06FwTextAddr;
3036 fw.text_len = bce_CP_b06FwTextLen;
3037 fw.text_index = 0;
3038 fw.text = bce_CP_b06FwText;
3039
3040 fw.data_addr = bce_CP_b06FwDataAddr;
3041 fw.data_len = bce_CP_b06FwDataLen;
3042 fw.data_index = 0;
3043 fw.data = bce_CP_b06FwData;
3044
3045 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3046 fw.sbss_len = bce_CP_b06FwSbssLen;
3047 fw.sbss_index = 0;
3048 fw.sbss = bce_CP_b06FwSbss;
3049
3050 fw.bss_addr = bce_CP_b06FwBssAddr;
3051 fw.bss_len = bce_CP_b06FwBssLen;
3052 fw.bss_index = 0;
3053 fw.bss = bce_CP_b06FwBss;
3054
3055 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3056 fw.rodata_len = bce_CP_b06FwRodataLen;
3057 fw.rodata_index = 0;
3058 fw.rodata = bce_CP_b06FwRodata;
3059 }
43c2aeb0 3060
d0092544 3061 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
43c2aeb0 3062 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3063 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ
3064}
3065
3066
3067/****************************************************************************/
3068/* Initialize the COM CPU. */
3069/* */
3070/* Returns: */
3071/* Nothing. */
3072/****************************************************************************/
3073static void
3074bce_init_com_cpu(struct bce_softc *sc)
3075{
3076 struct cpu_reg cpu_reg;
3077 struct fw_info fw;
43c2aeb0 3078
43c2aeb0
SZ
3079 cpu_reg.mode = BCE_COM_CPU_MODE;
3080 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3081 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3082 cpu_reg.state = BCE_COM_CPU_STATE;
3083 cpu_reg.state_value_clear = 0xffffff;
3084 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3085 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3086 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3087 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3088 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3089 cpu_reg.spad_base = BCE_COM_SCRATCH;
3090 cpu_reg.mips_view_base = 0x8000000;
3091
d0092544
SZ
3092 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3093 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3094 fw.ver_major = bce_COM_b09FwReleaseMajor;
3095 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3096 fw.ver_fix = bce_COM_b09FwReleaseFix;
3097 fw.start_addr = bce_COM_b09FwStartAddr;
3098
3099 fw.text_addr = bce_COM_b09FwTextAddr;
3100 fw.text_len = bce_COM_b09FwTextLen;
3101 fw.text_index = 0;
3102 fw.text = bce_COM_b09FwText;
3103
3104 fw.data_addr = bce_COM_b09FwDataAddr;
3105 fw.data_len = bce_COM_b09FwDataLen;
3106 fw.data_index = 0;
3107 fw.data = bce_COM_b09FwData;
3108
3109 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3110 fw.sbss_len = bce_COM_b09FwSbssLen;
3111 fw.sbss_index = 0;
3112 fw.sbss = bce_COM_b09FwSbss;
3113
3114 fw.bss_addr = bce_COM_b09FwBssAddr;
3115 fw.bss_len = bce_COM_b09FwBssLen;
3116 fw.bss_index = 0;
3117 fw.bss = bce_COM_b09FwBss;
3118
3119 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3120 fw.rodata_len = bce_COM_b09FwRodataLen;
3121 fw.rodata_index = 0;
3122 fw.rodata = bce_COM_b09FwRodata;
3123 } else {
3124 fw.ver_major = bce_COM_b06FwReleaseMajor;
3125 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3126 fw.ver_fix = bce_COM_b06FwReleaseFix;
3127 fw.start_addr = bce_COM_b06FwStartAddr;
3128
3129 fw.text_addr = bce_COM_b06FwTextAddr;
3130 fw.text_len = bce_COM_b06FwTextLen;
3131 fw.text_index = 0;
3132 fw.text = bce_COM_b06FwText;
3133
3134 fw.data_addr = bce_COM_b06FwDataAddr;
3135 fw.data_len = bce_COM_b06FwDataLen;
3136 fw.data_index = 0;
3137 fw.data = bce_COM_b06FwData;
3138
3139 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3140 fw.sbss_len = bce_COM_b06FwSbssLen;
3141 fw.sbss_index = 0;
3142 fw.sbss = bce_COM_b06FwSbss;
3143
3144 fw.bss_addr = bce_COM_b06FwBssAddr;
3145 fw.bss_len = bce_COM_b06FwBssLen;
3146 fw.bss_index = 0;
3147 fw.bss = bce_COM_b06FwBss;
3148
3149 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3150 fw.rodata_len = bce_COM_b06FwRodataLen;
3151 fw.rodata_index = 0;
3152 fw.rodata = bce_COM_b06FwRodata;
3153 }
43c2aeb0 3154
d0092544
SZ
3155 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3156 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3157 bce_start_cpu(sc, &cpu_reg);
d0092544 3158}
43c2aeb0 3159
43c2aeb0 3160
d0092544
SZ
3161/****************************************************************************/
3162/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3163/* */
3164/* Loads the firmware for each CPU and starts the CPU. */
3165/* */
3166/* Returns: */
3167/* Nothing. */
3168/****************************************************************************/
3169static void
3170bce_init_cpus(struct bce_softc *sc)
3171{
3172 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3173 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
cff16e71
SZ
3174 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3175 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3176 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3177 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3178 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3179 } else {
3180 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3181 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3182 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3183 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3184 }
d0092544 3185 } else {
cff16e71
SZ
3186 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3187 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3188 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3189 sizeof(bce_rv2p_proc2), RV2P_PROC2);
d0092544 3190 }
43c2aeb0 3191
d0092544
SZ
3192 bce_init_rxp_cpu(sc);
3193 bce_init_txp_cpu(sc);
3194 bce_init_tpat_cpu(sc);
3195 bce_init_com_cpu(sc);
3196 bce_init_cp_cpu(sc);
43c2aeb0
SZ
3197}
3198
3199
3200/****************************************************************************/
3201/* Initialize context memory. */
3202/* */
3203/* Clears the memory associated with each Context ID (CID). */
3204/* */
3205/* Returns: */
3206/* Nothing. */
3207/****************************************************************************/
3208static void
3a41a80b 3209bce_init_ctx(struct bce_softc *sc)
43c2aeb0 3210{
d0092544
SZ
3211 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3212 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3213 /* DRC: Replace this constant value with a #define. */
3214 int i, retry_cnt = 10;
3215 uint32_t val;
3216
3217 /*
3218 * BCM5709 context memory may be cached
3219 * in host memory so prepare the host memory
3220 * for access.
3221 */
3222 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3223 (1 << 12);
3224 val |= (BCM_PAGE_BITS - 8) << 16;
3225 REG_WR(sc, BCE_CTX_COMMAND, val);
3226
3227 /* Wait for mem init command to complete. */
3228 for (i = 0; i < retry_cnt; i++) {
3229 val = REG_RD(sc, BCE_CTX_COMMAND);
3230 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3231 break;
3232 DELAY(2);
3233 }
3234
3235 for (i = 0; i < sc->ctx_pages; i++) {
3236 int j;
43c2aeb0 3237
d0092544
SZ
3238 /*
3239 * Set the physical address of the context
3240 * memory cache.
3241 */
3242 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3243 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3244 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3245 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3246 BCE_ADDR_HI(sc->ctx_paddr[i]));
3247 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3248 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
43c2aeb0 3249
d0092544
SZ
3250 /*
3251 * Verify that the context memory write was successful.
3252 */
3253 for (j = 0; j < retry_cnt; j++) {
3254 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3255 if ((val &
3256 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3257 break;
3258 DELAY(5);
3259 }
3260 }
3261 } else {
3262 uint32_t vcid_addr, offset;
43c2aeb0 3263
d0092544
SZ
3264 /*
3265 * For the 5706/5708, context memory is local to
3266 * the controller, so initialize the controller
3267 * context memory.
3268 */
43c2aeb0 3269
d0092544
SZ
3270 vcid_addr = GET_CID_ADDR(96);
3271 while (vcid_addr) {
3272 vcid_addr -= PHY_CTX_SIZE;
43c2aeb0 3273
d0092544
SZ
3274 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3275 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
43c2aeb0 3276
3a41a80b 3277 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
d0092544
SZ
3278 CTX_WR(sc, 0x00, offset, 0);
3279
3280 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3281 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3a41a80b 3282 }
43c2aeb0
SZ
3283 }
3284}
3285
3286
3287/****************************************************************************/
3288/* Fetch the permanent MAC address of the controller. */
3289/* */
3290/* Returns: */
3291/* Nothing. */
3292/****************************************************************************/
3293static void
3294bce_get_mac_addr(struct bce_softc *sc)
3295{
3296 uint32_t mac_lo = 0, mac_hi = 0;
3297
3298 /*
3299 * The NetXtreme II bootcode populates various NIC
3300 * power-on and runtime configuration items in a
3301 * shared memory area. The factory configured MAC
3302 * address is available from both NVRAM and the
3303 * shared memory area so we'll read the value from
3304 * shared memory for speed.
3305 */
3306
bc30d40d
SZ
3307 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3308 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
43c2aeb0
SZ
3309
3310 if (mac_lo == 0 && mac_hi == 0) {
3311 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3312 } else {
3313 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3314 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3315 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3316 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3317 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3318 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3319 }
3320
3321 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3322}
3323
3324
3325/****************************************************************************/
3326/* Program the MAC address. */
3327/* */
3328/* Returns: */
3329/* Nothing. */
3330/****************************************************************************/
3331static void
3332bce_set_mac_addr(struct bce_softc *sc)
3333{
3334 const uint8_t *mac_addr = sc->eaddr;
3335 uint32_t val;
3336
3337 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3338 sc->eaddr, ":");
3339
3340 val = (mac_addr[0] << 8) | mac_addr[1];
3341 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3342
3343 val = (mac_addr[2] << 24) |
3344 (mac_addr[3] << 16) |
3345 (mac_addr[4] << 8) |
3346 mac_addr[5];
3347 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3348}
3349
3350
3351/****************************************************************************/
3352/* Stop the controller. */
3353/* */
3354/* Returns: */
3355/* Nothing. */
3356/****************************************************************************/
3357static void
3358bce_stop(struct bce_softc *sc)
3359{
3360 struct ifnet *ifp = &sc->arpcom.ac_if;
3361 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3362 struct ifmedia_entry *ifm;
3363 int mtmp, itmp;
3364
3365 ASSERT_SERIALIZED(ifp->if_serializer);
3366
d0092544 3367 callout_stop(&sc->bce_tick_callout);
43c2aeb0
SZ
3368
3369 /* Disable the transmit/receive blocks. */
d0092544 3370 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
43c2aeb0
SZ
3371 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3372 DELAY(20);
3373
3374 bce_disable_intr(sc);
3375
43c2aeb0
SZ
3376 /* Free the RX lists. */
3377 bce_free_rx_chain(sc);
3378
3379 /* Free TX buffers. */
3380 bce_free_tx_chain(sc);
3381
3382 /*
3383 * Isolate/power down the PHY, but leave the media selection
3384 * unchanged so that things will be put back to normal when
3385 * we bring the interface back up.
db1e7fc4
SZ
3386 *
3387 * 'mii' may be NULL if bce_stop() is called by bce_detach().
43c2aeb0 3388 */
db1e7fc4
SZ
3389 if (mii != NULL) {
3390 itmp = ifp->if_flags;
3391 ifp->if_flags |= IFF_UP;
3392 ifm = mii->mii_media.ifm_cur;
3393 mtmp = ifm->ifm_media;
3394 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3395 mii_mediachg(mii);
3396 ifm->ifm_media = mtmp;
3397 ifp->if_flags = itmp;
3398 }
43c2aeb0
SZ
3399
3400 sc->bce_link = 0;
bdeb8fff 3401 sc->bce_coalchg_mask = 0;
43c2aeb0
SZ
3402
3403 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3404 ifp->if_timer = 0;
43c2aeb0
SZ
3405}
3406
3407
3408static int
3409bce_reset(struct bce_softc *sc, uint32_t reset_code)
3410{
3411 uint32_t val;
3412 int i, rc = 0;
3413
3414 /* Wait for pending PCI transactions to complete. */
3415 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3416 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3417 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3418 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3419 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3420 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3421 DELAY(5);
3422
d0092544
SZ
3423 /* Disable DMA */
3424 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3425 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3426 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3427 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3428 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3429 }
3430
43c2aeb0
SZ
3431 /* Assume bootcode is running. */
3432 sc->bce_fw_timed_out = 0;
3433
3434 /* Give the firmware a chance to prepare for the reset. */
3435 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3436 if (rc) {
3437 if_printf(&sc->arpcom.ac_if,
3438 "Firmware is not ready for reset\n");
3439 return rc;
3440 }
3441
3442 /* Set a firmware reminder that this is a soft reset. */
bc30d40d
SZ
3443 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3444 BCE_DRV_RESET_SIGNATURE_MAGIC);
43c2aeb0
SZ
3445
3446 /* Dummy read to force the chip to complete all current transactions. */
3447 val = REG_RD(sc, BCE_MISC_ID);
3448
3449 /* Chip reset. */
d0092544
SZ
3450 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3451 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3452 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3453 REG_RD(sc, BCE_MISC_COMMAND);
3454 DELAY(5);
3455
3456 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3457 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3458
3459 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3460 } else {
3461 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3462 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3463 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3464 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3465
3466 /* Allow up to 30us for reset to complete. */
3467 for (i = 0; i < 10; i++) {
3468 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3469 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3470 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3471 break;
3472 DELAY(10);
43c2aeb0 3473 }
43c2aeb0 3474
d0092544
SZ
3475 /* Check that reset completed successfully. */
3476 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3477 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3478 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3479 return EBUSY;
3480 }
43c2aeb0
SZ
3481 }
3482
3483 /* Make sure byte swapping is properly configured. */
3484 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3485 if (val != 0x01020304) {
3486 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3487 return ENODEV;
3488 }
3489
3490 /* Just completed a reset, assume that firmware is running again. */
3491 sc->bce_fw_timed_out = 0;
3492
3493 /* Wait for the firmware to finish its initialization. */
3494 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3495 if (rc) {
3496 if_printf(&sc->arpcom.ac_if,
3497 "Firmware did not complete initialization!\n");
3498 }
3499 return rc;
3500}
3501
3502
3503static int
3504bce_chipinit(struct bce_softc *sc)
3505{
3506 uint32_t val;
3507 int rc = 0;
3508
3509 /* Make sure the interrupt is not active. */
3510 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
d0092544 3511 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
43c2aeb0
SZ
3512
3513 /*
3514 * Initialize DMA byte/word swapping, configure the number of DMA
3515 * channels and PCI clock compensation delay.
3516 */
3517 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3518 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3519#if BYTE_ORDER == BIG_ENDIAN
3520 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3521#endif
3522 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3523 DMA_READ_CHANS << 12 |
3524 DMA_WRITE_CHANS << 16;
3525
3526 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3527
3528 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3529 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3530
3531 /*
3532 * This setting resolves a problem observed on certain Intel PCI
3533 * chipsets that cannot handle multiple outstanding DMA operations.
3534 * See errata E9_5706A1_65.
3535 */
3536 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3537 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3538 !(sc->bce_flags & BCE_PCIX_FLAG))
3539 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3540
3541 REG_WR(sc, BCE_DMA_CONFIG, val);
3542
43c2aeb0
SZ
3543 /* Enable the RX_V2P and Context state machines before access. */
3544 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3545 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3546 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3547 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3548
3549 /* Initialize context mapping and zero out the quick contexts. */
3a41a80b 3550 bce_init_ctx(sc);
43c2aeb0
SZ
3551
3552 /* Initialize the on-boards CPUs */
3553 bce_init_cpus(sc);
3554
5d05a208
SZ
3555 /* Enable management frames (NC-SI) to flow to the MCP. */
3556 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3557 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3558 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3559 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3560 }
3561
43c2aeb0
SZ
3562 /* Prepare NVRAM for access. */
3563 rc = bce_init_nvram(sc);
3564 if (rc != 0)
3565 return rc;
3566
3567 /* Set the kernel bypass block size */
3568 val = REG_RD(sc, BCE_MQ_CONFIG);
3569 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3570 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
d0092544
SZ
3571
3572 /* Enable bins used on the 5709/5716. */
3573 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3574 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3575 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3576 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3577 val |= BCE_MQ_CONFIG_HALT_DIS;
3578 }
3579
43c2aeb0
SZ
3580 REG_WR(sc, BCE_MQ_CONFIG, val);
3581
3582 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3583 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3584 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3585
3586 /* Set the page size and clear the RV2P processor stall bits. */
3587 val = (BCM_PAGE_BITS - 8) << 24;
3588 REG_WR(sc, BCE_RV2P_CONFIG, val);
3589
3590 /* Configure page size. */
3591 val = REG_RD(sc, BCE_TBDR_CONFIG);
3592 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3593 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3594 REG_WR(sc, BCE_TBDR_CONFIG, val);
3595
d0092544
SZ
3596 /* Set the perfect match control register to default. */
3597 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3598
43c2aeb0
SZ
3599 return 0;
3600}
3601
3602
3603/****************************************************************************/
3604/* Initialize the controller in preparation to send/receive traffic. */
3605/* */
3606/* Returns: */
3607/* 0 for success, positive value for failure. */
3608/****************************************************************************/
3609static int
3610bce_blockinit(struct bce_softc *sc)
3611{
3612 uint32_t reg, val;
3613 int rc = 0;
3614
3615 /* Load the hardware default MAC address. */
3616 bce_set_mac_addr(sc);
3617
3618 /* Set the Ethernet backoff seed value */
3619 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3620 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3621 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3622
3623 sc->last_status_idx = 0;
3624 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3625
3626 /* Set up link change interrupt generation. */
3627 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3628
3629 /* Program the physical address of the status block. */
3630 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3631 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3632
3633 /* Program the physical address of the statistics block. */
3634 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3635 BCE_ADDR_LO(sc->stats_block_paddr));
3636 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3637 BCE_ADDR_HI(sc->stats_block_paddr));
3638
3639 /* Program various host coalescing parameters. */
3640 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3641 (sc->bce_tx_quick_cons_trip_int << 16) |
3642 sc->bce_tx_quick_cons_trip);
3643 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3644 (sc->bce_rx_quick_cons_trip_int << 16) |
3645 sc->bce_rx_quick_cons_trip);
3646 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3647 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3648 REG_WR(sc, BCE_HC_TX_TICKS,
3649 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3650 REG_WR(sc, BCE_HC_RX_TICKS,
3651 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3652 REG_WR(sc, BCE_HC_COM_TICKS,
3653 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3654 REG_WR(sc, BCE_HC_CMD_TICKS,
3655 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3656 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3657 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3658 REG_WR(sc, BCE_HC_CONFIG,
43c2aeb0
SZ
3659 BCE_HC_CONFIG_TX_TMR_MODE |
3660 BCE_HC_CONFIG_COLLECT_STATS);
3661
3662 /* Clear the internal statistics counters. */
3663 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3664
3665 /* Verify that bootcode is running. */
bc30d40d 3666 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
43c2aeb0
SZ
3667
3668 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3669 if_printf(&sc->arpcom.ac_if,
3670 "%s(%d): Simulating bootcode failure.\n",
3671 __FILE__, __LINE__);
3672 reg = 0);
3673
3674 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3675 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3676 if_printf(&sc->arpcom.ac_if,
3677 "Bootcode not running! Found: 0x%08X, "
3678 "Expected: 08%08X\n",
3679 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3680 BCE_DEV_INFO_SIGNATURE_MAGIC);
3681 return ENODEV;
3682 }
3683
d0092544
SZ
3684 /* Enable DMA */
3685 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3686 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3687 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3688 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3689 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
43c2aeb0
SZ
3690 }
3691
43c2aeb0
SZ
3692 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3693 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3694
3695 /* Enable link state change interrupt generation. */
3696 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3697
5d05a208
SZ
3698 /* Enable the RXP. */
3699 bce_start_rxp_cpu(sc);
3700
3701 /* Disable management frames (NC-SI) from flowing to the MCP. */
3702 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3703 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3704 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3705 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3706 }
3707
43c2aeb0 3708 /* Enable all remaining blocks in the MAC. */
d0092544
SZ
3709 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3710 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3711 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3712 BCE_MISC_ENABLE_DEFAULT_XI);
3713 } else {
3714 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3715 }
43c2aeb0
SZ
3716 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3717 DELAY(20);
3718
d0092544
SZ
3719 /* Save the current host coalescing block settings. */
3720 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3721
43c2aeb0
SZ
3722 return 0;
3723}
3724
3725
3726/****************************************************************************/
3727/* Encapsulate an mbuf cluster into the rx_bd chain. */
3728/* */
3729/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3730/* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3731/* necessary. */
3732/* */
3733/* Returns: */
3734/* 0 for success, positive value for failure. */
3735/****************************************************************************/
3736static int
c36fd9ee
SZ
3737bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3738 uint32_t *prod_bseq, int init)
43c2aeb0
SZ
3739{
3740 bus_dmamap_t map;
43c2aeb0
SZ
3741 bus_dma_segment_t seg;
3742 struct mbuf *m_new;
c36fd9ee 3743 int error, nseg;
43c2aeb0
SZ
3744#ifdef BCE_DEBUG
3745 uint16_t debug_chain_prod = *chain_prod;
3746#endif
3747
3748 /* Make sure the inputs are valid. */
3749 DBRUNIF((*chain_prod > MAX_RX_BD),
3750 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3751 "RX producer out of range: 0x%04X > 0x%04X\n",
3752 __FILE__, __LINE__,
3753 *chain_prod, (uint16_t)MAX_RX_BD));
3754
3755 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3756 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3757
c36fd9ee
SZ
3758 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3759 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3760 "Simulating mbuf allocation failure.\n",
3761 __FILE__, __LINE__);
3762 sc->mbuf_alloc_failed++;
3763 return ENOBUFS);
43c2aeb0 3764
c36fd9ee
SZ
3765 /* This is a new mbuf allocation. */
3766 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3767 if (m_new == NULL)
3768 return ENOBUFS;
3769 DBRUNIF(1, sc->rx_mbuf_alloc++);
43c2aeb0 3770
c36fd9ee 3771 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
43c2aeb0 3772
c36fd9ee
SZ
3773 /* Map the mbuf cluster into device memory. */
3774 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3775 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3776 BUS_DMA_NOWAIT);
3777 if (error) {
3778 m_freem(m_new);
3779 if (init) {
3780 if_printf(&sc->arpcom.ac_if,
3781 "Error mapping mbuf into RX chain!\n");
3782 }
43c2aeb0 3783 DBRUNIF(1, sc->rx_mbuf_alloc--);
c36fd9ee 3784 return error;
43c2aeb0
SZ
3785 }
3786
c36fd9ee
SZ
3787 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3788 bus_dmamap_unload(sc->rx_mbuf_tag,
3789 sc->rx_mbuf_map[*chain_prod]);
3790 }
3791
3792 map = sc->rx_mbuf_map[*chain_prod];
3793 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3794 sc->rx_mbuf_tmpmap = map;
3795
43c2aeb0
SZ
3796 /* Watch for overflow. */
3797 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3798 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3799 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3800 __FILE__, __LINE__, sc->free_rx_bd,
3801 (uint16_t)USABLE_RX_BD));
3802
3803 /* Update some debug statistic counters */
3804 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3805 sc->rx_low_watermark = sc->free_rx_bd);
3806 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3807
43c2aeb0
SZ
3808 /* Save the mbuf and update our counter. */
3809 sc->rx_mbuf_ptr[*chain_prod] = m_new;
314a2fcc 3810 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
43c2aeb0
SZ
3811 sc->free_rx_bd--;
3812
314a2fcc
SZ
3813 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3814
43c2aeb0
SZ
3815 DBRUN(BCE_VERBOSE_RECV,
3816 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3817
3818 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3819 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3820
3821 return 0;
3822}
3823
3824
314a2fcc
SZ
3825static void
3826bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3827{
3828 struct rx_bd *rxbd;
3829 bus_addr_t paddr;
3830 int len;
3831
3832 paddr = sc->rx_mbuf_paddr[chain_prod];
3833 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3834
3835 /* Setup the rx_bd for the first segment. */
3836 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3837
3838 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3839 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3840 rxbd->rx_bd_len = htole32(len);
3841 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3842 *prod_bseq += len;
3843