intr: Enable ELCR by default
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
87cf6827 51#include <machine/intr_machdep.h>
0b692e79 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
5f456c40 56
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57#include <machine_base/apic/ioapic_abi.h>
58
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59#include "icu.h"
60#include "icu_ipl.h"
37e7efec 61
10ff1029 62extern inthand_t
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63 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
64 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
65 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
66 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
67 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
68 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
69 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
70 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 71
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72static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
73 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
74 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
75 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
76 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
77 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
78 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
79 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
80 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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81};
82
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83extern void ICU_INTREN(int);
84extern void ICU_INTRDIS(int);
85
86static int icu_vectorctl(int, int, int);
87static int icu_setvar(int, const void *);
88static int icu_getvar(int, void *);
89static void icu_finalize(void);
90static void icu_cleanup(void);
91static void icu_setdefault(void);
7bf5fa56 92static void icu_stabilize(void);
10db3cc6 93
30c5f287 94struct machintr_abi MachIntrABI_ICU = {
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95 MACHINTR_ICU,
96 .intrdis = ICU_INTRDIS,
97 .intren = ICU_INTREN,
98 .vectorctl = icu_vectorctl,
99 .setvar = icu_setvar,
100 .getvar = icu_getvar,
101 .finalize = icu_finalize,
10db3cc6 102 .cleanup = icu_cleanup,
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103 .setdefault = icu_setdefault,
104 .stabilize = icu_stabilize
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105};
106
54e1df6b 107static int icu_imcr_present;
e96ee753 108
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109/*
110 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
111 */
54e1df6b 112static int
d916dbc1 113icu_setvar(int varid, const void *buf)
37e7efec 114{
54e1df6b 115 int error = 0;
e96ee753 116
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117 switch (varid) {
118 case MACHINTR_VAR_IMCR_PRESENT:
119 icu_imcr_present = *(const int *)buf;
120 break;
121
122 default:
123 error = ENOENT;
124 break;
125 }
126 return error;
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127}
128
54e1df6b 129static int
d916dbc1 130icu_getvar(int varid, void *buf)
37e7efec 131{
54e1df6b 132 int error = 0;
e96ee753 133
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134 switch (varid) {
135 case MACHINTR_VAR_IMCR_PRESENT:
136 *(int *)buf = icu_imcr_present;
137 break;
138
139 default:
140 error = ENOENT;
141 break;
142 }
143 return error;
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144}
145
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146/*
147 * Called before interrupts are physically enabled
148 */
37e7efec 149static void
7bf5fa56 150icu_stabilize(void)
37e7efec 151{
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152 int intr;
153
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154 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
155 machintr_intrdis(intr);
156 machintr_intren(ICU_IRQ_SLAVE);
157}
158
159/*
160 * Called after interrupts physically enabled but before the
161 * critical section is released.
162 */
163static void
164icu_cleanup(void)
165{
166 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
167}
168
169/*
170 * Called after stablize and cleanup; critical section is not
171 * held and interrupts are not physically disabled.
172 *
173 * For SMP:
174 * Further delayed after BSP's LAPIC is initialized
175 */
176static void
177icu_finalize(void)
178{
179 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
180
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181#ifdef SMP
182 if (apic_io_enable) {
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183 /*
184 * MachIntrABI switching will happen in
185 * MachIntrABI_IOAPIC.finalize()
186 */
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187 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
188 &icu_imcr_present);
189 MachIntrABI_IOAPIC.finalize();
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190 return;
191 }
54e1df6b 192
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193 /*
194 * If an IMCR is present, programming bit 0 disconnects the 8259
195 * from the BSP. The 8259 may still be connected to LINT0 on the
196 * BSP's LAPIC.
197 *
198 * If we are running SMP the LAPIC is active, try to use virtual
199 * wire mode so we can use other interrupt sources within the LAPIC
200 * in addition to the 8259.
201 */
202 if (icu_imcr_present) {
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203 u_long ef;
204
205 crit_enter();
206
207 ef = read_eflags();
208 cpu_disable_intr();
209
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210 outb(0x22, 0x70);
211 outb(0x23, 0x01);
37e7efec 212
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213 write_eflags(ef);
214
215 crit_exit();
216 }
217#endif /* SMP */
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218}
219
54e1df6b 220static int
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221icu_vectorctl(int op, int intr, int flags)
222{
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223 int error;
224 u_long ef;
225
226 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
227 return EINVAL;
228
229 ef = read_eflags();
230 cpu_disable_intr();
231 error = 0;
232
233 switch (op) {
234 case MACHINTR_VECTOR_SETUP:
081be8a5 235 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
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236 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
237 machintr_intren(intr);
238 break;
239
240 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 241 machintr_intrdis(intr);
081be8a5 242 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b 243 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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244 break;
245
246 default:
247 error = EOPNOTSUPP;
248 break;
249 }
250 write_eflags(ef);
251 return error;
10ff1029 252}
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253
254static void
255icu_setdefault(void)
256{
257 int intr;
258
259 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
260 if (intr == ICU_IRQ_SLAVE)
261 continue;
262 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
263 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
264 }
265}