Document the fact that the vm86 instruction emulator is MPSAFE.
[dragonfly.git] / sys / kern / kern_intr.c
CommitLineData
984263bc 1/*
033a4603 2 * Copyright (c) 2003 Matthew Dillon <dillon@backplane.com> All rights reserved.
ef0fdad1 3 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> All rights reserved.
984263bc
MD
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/kern/kern_intr.c,v 1.24.2.1 2001/10/14 20:05:50 luigi Exp $
0e6beaa3 27 * $DragonFly: src/sys/kern/kern_intr.c,v 1.36 2005/11/21 22:54:16 dillon Exp $
984263bc
MD
28 *
29 */
30
984263bc
MD
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/malloc.h>
34#include <sys/kernel.h>
35#include <sys/sysctl.h>
ef0fdad1
MD
36#include <sys/thread.h>
37#include <sys/proc.h>
38#include <sys/thread2.h>
7e071e7a 39#include <sys/random.h>
477d3c1c
MD
40#include <sys/serialize.h>
41#include <sys/bus.h>
37e7efec 42#include <sys/machintr.h>
984263bc
MD
43
44#include <machine/ipl.h>
477d3c1c 45#include <machine/frame.h>
984263bc
MD
46
47#include <sys/interrupt.h>
48
9d522d14
MD
49struct info_info;
50
ef0fdad1
MD
51typedef struct intrec {
52 struct intrec *next;
9d522d14 53 struct intr_info *info;
ef0fdad1
MD
54 inthand2_t *handler;
55 void *argument;
477d3c1c 56 char *name;
ef0fdad1 57 int intr;
477d3c1c
MD
58 int intr_flags;
59 struct lwkt_serialize *serializer;
60} *intrec_t;
61
62struct intr_info {
63 intrec_t i_reclist;
64 struct thread i_thread;
65 struct random_softc i_random;
66 int i_running;
862f2618
MD
67 long i_count; /* interrupts dispatched */
68 int i_mplock_required;
477d3c1c
MD
69 int i_fast;
70 int i_slow;
f33e9c1c 71 int i_state;
5f456c40
MD
72} intr_info_ary[MAX_INTS];
73
74int max_installed_hard_intr;
75int max_installed_soft_intr;
477d3c1c 76
a9d00ec1
MD
77#define EMERGENCY_INTR_POLLING_FREQ_MAX 20000
78
79static int sysctl_emergency_freq(SYSCTL_HANDLER_ARGS);
80static int sysctl_emergency_enable(SYSCTL_HANDLER_ARGS);
81static void emergency_intr_timer_callback(systimer_t, struct intrframe *);
82static void ithread_handler(void *arg);
83static void ithread_emergency(void *arg);
84
477d3c1c 85int intr_info_size = sizeof(intr_info_ary) / sizeof(intr_info_ary[0]);
37d44089 86
a9d00ec1
MD
87static struct systimer emergency_intr_timer;
88static struct thread emergency_intr_thread;
89
f33e9c1c
MD
90#define ISTATE_NOTHREAD 0
91#define ISTATE_NORMAL 1
92#define ISTATE_LIVELOCKED 2
37d44089 93
0e6beaa3 94#ifdef SMP
862f2618 95static int intr_mpsafe = 0;
862f2618
MD
96TUNABLE_INT("kern.intr_mpsafe", &intr_mpsafe);
97SYSCTL_INT(_kern, OID_AUTO, intr_mpsafe,
98 CTLFLAG_RW, &intr_mpsafe, 0, "Run INTR_MPSAFE handlers without the BGL");
0e6beaa3
MD
99#endif
100static int livelock_limit = 50000;
101static int livelock_lowater = 20000;
37d44089
MD
102SYSCTL_INT(_kern, OID_AUTO, livelock_limit,
103 CTLFLAG_RW, &livelock_limit, 0, "Livelock interrupt rate limit");
f33e9c1c
MD
104SYSCTL_INT(_kern, OID_AUTO, livelock_lowater,
105 CTLFLAG_RW, &livelock_lowater, 0, "Livelock low-water mark restore");
984263bc 106
a9d00ec1
MD
107static int emergency_intr_enable = 0; /* emergency interrupt polling */
108TUNABLE_INT("kern.emergency_intr_enable", &emergency_intr_enable);
109SYSCTL_PROC(_kern, OID_AUTO, emergency_intr_enable, CTLTYPE_INT | CTLFLAG_RW,
110 0, 0, sysctl_emergency_enable, "I", "Emergency Interrupt Poll Enable");
111
112static int emergency_intr_freq = 10; /* emergency polling frequency */
113TUNABLE_INT("kern.emergency_intr_freq", &emergency_intr_freq);
114SYSCTL_PROC(_kern, OID_AUTO, emergency_intr_freq, CTLTYPE_INT | CTLFLAG_RW,
115 0, 0, sysctl_emergency_freq, "I", "Emergency Interrupt Poll Frequency");
116
117/*
118 * Sysctl support routines
119 */
120static int
121sysctl_emergency_enable(SYSCTL_HANDLER_ARGS)
122{
123 int error, enabled;
124
125 enabled = emergency_intr_enable;
126 error = sysctl_handle_int(oidp, &enabled, 0, req);
127 if (error || req->newptr == NULL)
128 return error;
129 emergency_intr_enable = enabled;
130 if (emergency_intr_enable) {
131 emergency_intr_timer.periodic =
132 sys_cputimer->fromhz(emergency_intr_freq);
133 } else {
134 emergency_intr_timer.periodic = sys_cputimer->fromhz(1);
135 }
136 return 0;
137}
138
139static int
140sysctl_emergency_freq(SYSCTL_HANDLER_ARGS)
141{
142 int error, phz;
143
144 phz = emergency_intr_freq;
145 error = sysctl_handle_int(oidp, &phz, 0, req);
146 if (error || req->newptr == NULL)
147 return error;
148 if (phz <= 0)
149 return EINVAL;
150 else if (phz > EMERGENCY_INTR_POLLING_FREQ_MAX)
151 phz = EMERGENCY_INTR_POLLING_FREQ_MAX;
152
153 emergency_intr_freq = phz;
154 if (emergency_intr_enable) {
155 emergency_intr_timer.periodic =
156 sys_cputimer->fromhz(emergency_intr_freq);
157 } else {
158 emergency_intr_timer.periodic = sys_cputimer->fromhz(1);
159 }
160 return 0;
161}
984263bc 162
45d76888
MD
163/*
164 * Register an SWI or INTerrupt handler.
45d76888 165 */
477d3c1c
MD
166void *
167register_swi(int intr, inthand2_t *handler, void *arg, const char *name,
168 struct lwkt_serialize *serializer)
984263bc 169{
5f456c40 170 if (intr < FIRST_SOFTINT || intr >= MAX_INTS)
ef0fdad1 171 panic("register_swi: bad intr %d", intr);
477d3c1c 172 return(register_int(intr, handler, arg, name, serializer, 0));
984263bc
MD
173}
174
477d3c1c
MD
175void *
176register_int(int intr, inthand2_t *handler, void *arg, const char *name,
177 struct lwkt_serialize *serializer, int intr_flags)
984263bc 178{
477d3c1c
MD
179 struct intr_info *info;
180 struct intrec **list;
181 intrec_t rec;
ef0fdad1 182
5f456c40 183 if (intr < 0 || intr >= MAX_INTS)
ef0fdad1 184 panic("register_int: bad intr %d", intr);
477d3c1c
MD
185 if (name == NULL)
186 name = "???";
187 info = &intr_info_ary[intr];
188
9d522d14
MD
189 /*
190 * Construct an interrupt handler record
191 */
477d3c1c
MD
192 rec = malloc(sizeof(struct intrec), M_DEVBUF, M_INTWAIT);
193 rec->name = malloc(strlen(name) + 1, M_DEVBUF, M_INTWAIT);
194 strcpy(rec->name, name);
ef0fdad1 195
9d522d14 196 rec->info = info;
ef0fdad1
MD
197 rec->handler = handler;
198 rec->argument = arg;
ef0fdad1 199 rec->intr = intr;
477d3c1c 200 rec->intr_flags = intr_flags;
ef0fdad1 201 rec->next = NULL;
477d3c1c 202 rec->serializer = serializer;
ef0fdad1 203
a9d00ec1
MD
204 /*
205 * Create an emergency polling thread and set up a systimer to wake
206 * it up.
207 */
208 if (emergency_intr_thread.td_kstack == NULL) {
209 lwkt_create(ithread_emergency, NULL, NULL,
210 &emergency_intr_thread, TDF_STOPREQ|TDF_INTTHREAD, -1,
211 "ithread emerg");
212 systimer_init_periodic_nq(&emergency_intr_timer,
213 emergency_intr_timer_callback, &emergency_intr_thread,
214 (emergency_intr_enable ? emergency_intr_freq : 1));
215 }
216
ef0fdad1
MD
217 /*
218 * Create an interrupt thread if necessary, leave it in an unscheduled
45d76888 219 * state.
ef0fdad1 220 */
f33e9c1c
MD
221 if (info->i_state == ISTATE_NOTHREAD) {
222 info->i_state = ISTATE_NORMAL;
477d3c1c 223 lwkt_create((void *)ithread_handler, (void *)intr, NULL,
862f2618 224 &info->i_thread, TDF_STOPREQ|TDF_INTTHREAD|TDF_MPSAFE, -1,
75cdbe6c 225 "ithread %d", intr);
5f456c40 226 if (intr >= FIRST_SOFTINT)
477d3c1c 227 lwkt_setpri(&info->i_thread, TDPRI_SOFT_NORM);
4b5f931b 228 else
477d3c1c
MD
229 lwkt_setpri(&info->i_thread, TDPRI_INT_MED);
230 info->i_thread.td_preemptable = lwkt_preempt;
ef0fdad1
MD
231 }
232
9d522d14
MD
233 list = &info->i_reclist;
234
ef0fdad1 235 /*
9d522d14 236 * Keep track of how many fast and slow interrupts we have.
862f2618
MD
237 * Set i_mplock_required if any handler in the chain requires
238 * the MP lock to operate.
ef0fdad1 239 */
862f2618
MD
240 if ((intr_flags & INTR_MPSAFE) == 0)
241 info->i_mplock_required = 1;
9d522d14
MD
242 if (intr_flags & INTR_FAST)
243 ++info->i_fast;
244 else
245 ++info->i_slow;
246
247 /*
248 * Add the record to the interrupt list.
249 */
250 crit_enter();
ef0fdad1
MD
251 while (*list != NULL)
252 list = &(*list)->next;
253 *list = rec;
254 crit_exit();
5f456c40
MD
255
256 /*
257 * Update max_installed_hard_intr to make the emergency intr poll
258 * a bit more efficient.
259 */
260 if (intr < FIRST_SOFTINT) {
261 if (max_installed_hard_intr <= intr)
262 max_installed_hard_intr = intr + 1;
263 } else {
264 if (max_installed_soft_intr <= intr)
265 max_installed_soft_intr = intr + 1;
266 }
9d522d14
MD
267
268 /*
269 * Setup the machine level interrupt vector
270 */
271 if (info->i_slow + info->i_fast == 1) {
272 if (machintr_vector_setup(intr, intr_flags))
273 printf("machintr_vector_setup: failed on irq %d\n", intr);
274 }
275
477d3c1c 276 return(rec);
ef0fdad1 277}
984263bc 278
9d522d14 279void
477d3c1c 280unregister_swi(void *id)
ef0fdad1 281{
9d522d14 282 unregister_int(id);
984263bc
MD
283}
284
9d522d14 285void
477d3c1c 286unregister_int(void *id)
984263bc 287{
477d3c1c
MD
288 struct intr_info *info;
289 struct intrec **list;
290 intrec_t rec;
291 int intr;
292
293 intr = ((intrec_t)id)->intr;
ef0fdad1 294
5f456c40 295 if (intr < 0 || intr >= MAX_INTS)
ef0fdad1 296 panic("register_int: bad intr %d", intr);
477d3c1c
MD
297
298 info = &intr_info_ary[intr];
299
300 /*
9d522d14
MD
301 * Remove the interrupt descriptor, adjust the descriptor count,
302 * and teardown the machine level vector if this was the last interrupt.
477d3c1c 303 */
ef0fdad1 304 crit_enter();
477d3c1c 305 list = &info->i_reclist;
ef0fdad1 306 while ((rec = *list) != NULL) {
9d522d14 307 if (rec == id)
ef0fdad1 308 break;
ef0fdad1
MD
309 list = &rec->next;
310 }
9d522d14
MD
311 if (rec) {
312 *list = rec->next;
313 if (rec->intr_flags & INTR_FAST)
314 --info->i_fast;
315 else
316 --info->i_slow;
317 if (info->i_fast + info->i_slow == 0)
318 machintr_vector_teardown(intr);
319 }
862f2618
MD
320
321 /*
322 * Clear i_mplock_required if no handlers in the chain require the
323 * MP lock.
324 */
325 for (rec = info->i_reclist; rec; rec = rec->next) {
326 if ((rec->intr_flags & INTR_MPSAFE) == 0)
327 break;
328 }
329 if (rec == NULL)
330 info->i_mplock_required = 0;
331
ef0fdad1 332 crit_exit();
477d3c1c
MD
333
334 /*
9d522d14 335 * Free the record.
477d3c1c 336 */
ef0fdad1 337 if (rec != NULL) {
477d3c1c 338 free(rec->name, M_DEVBUF);
ef0fdad1
MD
339 free(rec, M_DEVBUF);
340 } else {
477d3c1c
MD
341 printf("warning: unregister_int: int %d handler for %s not found\n",
342 intr, ((intrec_t)id)->name);
ef0fdad1 343 }
477d3c1c
MD
344}
345
346const char *
347get_registered_name(int intr)
348{
349 intrec_t rec;
350
5f456c40 351 if (intr < 0 || intr >= MAX_INTS)
477d3c1c
MD
352 panic("register_int: bad intr %d", intr);
353
354 if ((rec = intr_info_ary[intr].i_reclist) == NULL)
355 return(NULL);
356 else if (rec->next)
357 return("mux");
358 else
359 return(rec->name);
984263bc
MD
360}
361
477d3c1c
MD
362int
363count_registered_ints(int intr)
364{
365 struct intr_info *info;
366
5f456c40 367 if (intr < 0 || intr >= MAX_INTS)
477d3c1c
MD
368 panic("register_int: bad intr %d", intr);
369 info = &intr_info_ary[intr];
370 return(info->i_fast + info->i_slow);
371}
372
373long
374get_interrupt_counter(int intr)
375{
376 struct intr_info *info;
377
5f456c40 378 if (intr < 0 || intr >= MAX_INTS)
477d3c1c
MD
379 panic("register_int: bad intr %d", intr);
380 info = &intr_info_ary[intr];
381 return(info->i_count);
382}
383
384
4b5f931b
MD
385void
386swi_setpriority(int intr, int pri)
387{
477d3c1c 388 struct intr_info *info;
4b5f931b 389
5f456c40 390 if (intr < FIRST_SOFTINT || intr >= MAX_INTS)
4b5f931b 391 panic("register_swi: bad intr %d", intr);
477d3c1c 392 info = &intr_info_ary[intr];
f33e9c1c 393 if (info->i_state != ISTATE_NOTHREAD)
477d3c1c 394 lwkt_setpri(&info->i_thread, pri);
4b5f931b
MD
395}
396
7e071e7a
MD
397void
398register_randintr(int intr)
399{
477d3c1c
MD
400 struct intr_info *info;
401
5f456c40 402 if (intr < 0 || intr >= MAX_INTS)
417c990a 403 panic("register_randintr: bad intr %d", intr);
477d3c1c
MD
404 info = &intr_info_ary[intr];
405 info->i_random.sc_intr = intr;
406 info->i_random.sc_enabled = 1;
7e071e7a
MD
407}
408
409void
410unregister_randintr(int intr)
411{
477d3c1c
MD
412 struct intr_info *info;
413
5f456c40 414 if (intr < 0 || intr >= MAX_INTS)
477d3c1c
MD
415 panic("register_swi: bad intr %d", intr);
416 info = &intr_info_ary[intr];
417 info->i_random.sc_enabled = 0;
7e071e7a
MD
418}
419
5f456c40
MD
420int
421next_registered_randintr(int intr)
422{
423 struct intr_info *info;
424
425 if (intr < 0 || intr >= MAX_INTS)
426 panic("register_swi: bad intr %d", intr);
427 while (intr < MAX_INTS) {
428 info = &intr_info_ary[intr];
429 if (info->i_random.sc_enabled)
430 break;
431 ++intr;
432 }
433 return(intr);
434}
435
ef0fdad1 436/*
b68b7282
MD
437 * Dispatch an interrupt. If there's nothing to do we have a stray
438 * interrupt and can just return, leaving the interrupt masked.
96728c05 439 *
477d3c1c 440 * We need to schedule the interrupt and set its i_running bit. If
96728c05
MD
441 * we are not on the interrupt thread's cpu we have to send a message
442 * to the correct cpu that will issue the desired action (interlocking
f33e9c1c
MD
443 * with the interrupt thread's critical section). We do NOT attempt to
444 * reschedule interrupts whos i_running bit is already set because
445 * this would prematurely wakeup a livelock-limited interrupt thread.
446 *
447 * i_running is only tested/set on the same cpu as the interrupt thread.
96728c05
MD
448 *
449 * We are NOT in a critical section, which will allow the scheduled
71ef2f5c 450 * interrupt to preempt us. The MP lock might *NOT* be held here.
ef0fdad1 451 */
b8a98473
MD
452#ifdef SMP
453
96728c05
MD
454static void
455sched_ithd_remote(void *arg)
456{
457 sched_ithd((int)arg);
458}
459
b8a98473
MD
460#endif
461
ef0fdad1
MD
462void
463sched_ithd(int intr)
464{
477d3c1c 465 struct intr_info *info;
ef0fdad1 466
477d3c1c
MD
467 info = &intr_info_ary[intr];
468
469 ++info->i_count;
f33e9c1c 470 if (info->i_state != ISTATE_NOTHREAD) {
477d3c1c 471 if (info->i_reclist == NULL) {
ef0fdad1 472 printf("sched_ithd: stray interrupt %d\n", intr);
b68b7282 473 } else {
b8a98473 474#ifdef SMP
477d3c1c 475 if (info->i_thread.td_gd == mycpu) {
f33e9c1c
MD
476 if (info->i_running == 0) {
477 info->i_running = 1;
478 if (info->i_state != ISTATE_LIVELOCKED)
479 lwkt_schedule(&info->i_thread); /* MIGHT PREEMPT */
480 }
96728c05 481 } else {
477d3c1c
MD
482 lwkt_send_ipiq(info->i_thread.td_gd,
483 sched_ithd_remote, (void *)intr);
96728c05 484 }
b8a98473 485#else
f33e9c1c
MD
486 if (info->i_running == 0) {
487 info->i_running = 1;
488 if (info->i_state != ISTATE_LIVELOCKED)
489 lwkt_schedule(&info->i_thread); /* MIGHT PREEMPT */
490 }
b8a98473 491#endif
b68b7282 492 }
ef0fdad1
MD
493 } else {
494 printf("sched_ithd: stray interrupt %d\n", intr);
495 }
496}
497
37d44089
MD
498/*
499 * This is run from a periodic SYSTIMER (and thus must be MP safe, the BGL
500 * might not be held).
501 */
502static void
477d3c1c 503ithread_livelock_wakeup(systimer_t st)
37d44089 504{
477d3c1c 505 struct intr_info *info;
37d44089 506
477d3c1c 507 info = &intr_info_ary[(int)st->data];
f33e9c1c 508 if (info->i_state != ISTATE_NOTHREAD)
477d3c1c 509 lwkt_schedule(&info->i_thread);
37d44089
MD
510}
511
67b9bb39 512/*
477d3c1c
MD
513 * This function is called drectly from the ICU or APIC vector code assembly
514 * to process an interrupt. The critical section and interrupt deferral
515 * checks have already been done but the function is entered WITHOUT
516 * a critical section held. The BGL may or may not be held.
517 *
518 * Must return non-zero if we do not want the vector code to re-enable
519 * the interrupt (which we don't if we have to schedule the interrupt)
67b9bb39 520 */
477d3c1c
MD
521int ithread_fast_handler(struct intrframe frame);
522
523int
524ithread_fast_handler(struct intrframe frame)
525{
526 int intr;
527 struct intr_info *info;
528 struct intrec **list;
529 int must_schedule;
530#ifdef SMP
531 int got_mplock;
532#endif
533 intrec_t rec, next_rec;
534 globaldata_t gd;
535
536 intr = frame.if_vec;
537 gd = mycpu;
538
539 info = &intr_info_ary[intr];
540
541 /*
542 * If we are not processing any FAST interrupts, just schedule the thing.
543 * (since we aren't in a critical section, this can result in a
544 * preemption)
545 */
546 if (info->i_fast == 0) {
547 sched_ithd(intr);
548 return(1);
549 }
550
551 /*
552 * This should not normally occur since interrupts ought to be
553 * masked if the ithread has been scheduled or is running.
554 */
555 if (info->i_running)
556 return(1);
557
558 /*
559 * Bump the interrupt nesting level to process any FAST interrupts.
560 * Obtain the MP lock as necessary. If the MP lock cannot be obtained,
561 * schedule the interrupt thread to deal with the issue instead.
562 *
563 * To reduce overhead, just leave the MP lock held once it has been
564 * obtained.
565 */
566 crit_enter_gd(gd);
567 ++gd->gd_intr_nesting_level;
568 ++gd->gd_cnt.v_intr;
569 must_schedule = info->i_slow;
570#ifdef SMP
571 got_mplock = 0;
572#endif
573
574 list = &info->i_reclist;
575 for (rec = *list; rec; rec = next_rec) {
576 next_rec = rec->next; /* rec may be invalid after call */
577
578 if (rec->intr_flags & INTR_FAST) {
579#ifdef SMP
580 if ((rec->intr_flags & INTR_MPSAFE) == 0 && got_mplock == 0) {
581 if (try_mplock() == 0) {
afd7b1c0
MD
582 int owner;
583
477d3c1c 584 /*
afd7b1c0
MD
585 * If we couldn't get the MP lock try to forward it
586 * to the cpu holding the MP lock, setting must_schedule
587 * to -1 so we do not schedule and also do not unmask
588 * the interrupt. Otherwise just schedule it.
477d3c1c 589 */
afd7b1c0
MD
590 owner = owner_mplock();
591 if (owner >= 0 && owner != gd->gd_cpuid) {
592 lwkt_send_ipiq_bycpu(owner, forward_fastint_remote,
7e2d9bde 593 (void *)intr);
afd7b1c0
MD
594 must_schedule = -1;
595 ++gd->gd_cnt.v_forwarded_ints;
596 } else {
597 must_schedule = 1;
598 }
477d3c1c
MD
599 break;
600 }
601 got_mplock = 1;
602 }
603#endif
604 if (rec->serializer) {
605 must_schedule += lwkt_serialize_handler_try(
606 rec->serializer, rec->handler,
607 rec->argument, &frame);
608 } else {
609 rec->handler(rec->argument, &frame);
610 }
611 }
612 }
613
614 /*
615 * Cleanup
616 */
617 --gd->gd_intr_nesting_level;
618#ifdef SMP
619 if (got_mplock)
620 rel_mplock();
621#endif
622 crit_exit_gd(gd);
623
624 /*
625 * If we had a problem, schedule the thread to catch the missed
626 * records (it will just re-run all of them). A return value of 0
627 * indicates that all handlers have been run and the interrupt can
628 * be re-enabled, and a non-zero return indicates that the interrupt
629 * thread controls re-enablement.
630 */
afd7b1c0 631 if (must_schedule > 0)
477d3c1c 632 sched_ithd(intr);
afd7b1c0 633 else if (must_schedule == 0)
477d3c1c
MD
634 ++info->i_count;
635 return(must_schedule);
636}
637
638#if 0
639
6406: ; \
641 /* could not get the MP lock, forward the interrupt */ \
642 movl mp_lock, %eax ; /* check race */ \
643 cmpl $MP_FREE_LOCK,%eax ; \
644 je 2b ; \
645 incl PCPU(cnt)+V_FORWARDED_INTS ; \
646 subl $12,%esp ; \
647 movl $irq_num,8(%esp) ; \
648 movl $forward_fastint_remote,4(%esp) ; \
649 movl %eax,(%esp) ; \
650 call lwkt_send_ipiq_bycpu ; \
651 addl $12,%esp ; \
652 jmp 5f ;
653
654#endif
67b9bb39 655
37d44089 656
b68b7282 657/*
45d76888
MD
658 * Interrupt threads run this as their main loop.
659 *
660 * The handler begins execution outside a critical section and with the BGL
661 * held.
37d44089 662 *
477d3c1c 663 * The i_running state starts at 0. When an interrupt occurs, the hardware
37d44089
MD
664 * interrupt is disabled and sched_ithd() The HW interrupt remains disabled
665 * until all routines have run. We then call ithread_done() to reenable
45d76888
MD
666 * the HW interrupt and deschedule us until the next interrupt.
667 *
477d3c1c 668 * We are responsible for atomically checking i_running and ithread_done()
45d76888 669 * is responsible for atomically checking for platform-specific delayed
477d3c1c 670 * interrupts. i_running for our irq is only set in the context of our cpu,
45d76888 671 * so a critical section is a sufficient interlock.
b68b7282 672 */
93781523
MD
673#define LIVELOCK_TIMEFRAME(freq) ((freq) >> 2) /* 1/4 second */
674
ef0fdad1
MD
675static void
676ithread_handler(void *arg)
677{
477d3c1c 678 struct intr_info *info;
f33e9c1c
MD
679 int use_limit;
680 int lticks;
681 int lcount;
477d3c1c 682 int intr;
9d522d14 683 int mpheld;
477d3c1c
MD
684 struct intrec **list;
685 intrec_t rec, nrec;
f33e9c1c 686 globaldata_t gd;
67b9bb39 687 struct systimer ill_timer; /* enforced freq. timer */
f33e9c1c 688 u_int ill_count; /* interrupt livelock counter */
45d76888 689
f33e9c1c
MD
690 ill_count = 0;
691 lticks = ticks;
692 lcount = 0;
477d3c1c
MD
693 intr = (int)arg;
694 info = &intr_info_ary[intr];
695 list = &info->i_reclist;
696 gd = mycpu;
697
45d76888 698 /*
862f2618
MD
699 * The loop must be entered with one critical section held. The thread
700 * is created with TDF_MPSAFE so the MP lock is not held on start.
45d76888
MD
701 */
702 crit_enter_gd(gd);
862f2618 703 mpheld = 0;
ef0fdad1 704
ef0fdad1 705 for (;;) {
862f2618
MD
706 /*
707 * The chain is only considered MPSAFE if all its interrupt handlers
708 * are MPSAFE. However, if intr_mpsafe has been turned off we
709 * always operate with the BGL.
710 */
0e6beaa3 711#ifdef SMP
862f2618
MD
712 if (intr_mpsafe == 0) {
713 if (mpheld == 0) {
714 get_mplock();
715 mpheld = 1;
716 }
717 } else if (info->i_mplock_required != mpheld) {
718 if (info->i_mplock_required) {
719 KKASSERT(mpheld == 0);
720 get_mplock();
721 mpheld = 1;
722 } else {
723 KKASSERT(mpheld != 0);
724 rel_mplock();
725 mpheld = 0;
726 }
727 }
0e6beaa3 728#endif
862f2618 729
93781523 730 /*
f33e9c1c
MD
731 * If an interrupt is pending, clear i_running and execute the
732 * handlers. Note that certain types of interrupts can re-trigger
733 * and set i_running again.
45d76888 734 *
f33e9c1c 735 * Each handler is run in a critical section. Note that we run both
862f2618 736 * FAST and SLOW designated service routines.
93781523 737 */
f33e9c1c
MD
738 if (info->i_running) {
739 ++ill_count;
740 info->i_running = 0;
9d522d14 741
f33e9c1c
MD
742 for (rec = *list; rec; rec = nrec) {
743 nrec = rec->next;
744 if (rec->serializer) {
745 lwkt_serialize_handler_call(rec->serializer, rec->handler,
746 rec->argument, NULL);
747 } else {
748 rec->handler(rec->argument, NULL);
749 }
477d3c1c 750 }
ef0fdad1 751 }
37d44089
MD
752
753 /*
754 * This is our interrupt hook to add rate randomness to the random
755 * number generator.
756 */
477d3c1c 757 if (info->i_random.sc_enabled)
96728c05 758 add_interrupt_randomness(intr);
37d44089
MD
759
760 /*
f33e9c1c
MD
761 * Unmask the interrupt to allow it to trigger again. This only
762 * applies to certain types of interrupts (typ level interrupts).
763 * This can result in the interrupt retriggering, but the retrigger
764 * will not be processed until we cycle our critical section.
363d922a
MD
765 *
766 * Only unmask interrupts while handlers are installed. It is
767 * possible to hit a situation where no handlers are installed
768 * due to a device driver livelocking and then tearing down its
769 * interrupt on close (the parallel bus being a good example).
37d44089 770 */
363d922a 771 if (*list)
37e7efec 772 machintr_intren(intr);
f33e9c1c
MD
773
774 /*
775 * Do a quick exit/enter to catch any higher-priority interrupt
776 * sources, such as the statclock, so thread time accounting
777 * will still work. This may also cause an interrupt to re-trigger.
778 */
779 crit_exit_gd(gd);
780 crit_enter_gd(gd);
781
782 /*
783 * LIVELOCK STATE MACHINE
784 */
785 switch(info->i_state) {
786 case ISTATE_NORMAL:
787 /*
788 * Calculate a running average every tick.
789 */
790 if (lticks != ticks) {
791 lticks = ticks;
792 ill_count -= ill_count / hz;
793 }
794
795 /*
796 * If we did not exceed the frequency limit, we are done.
797 * If the interrupt has not retriggered we deschedule ourselves.
798 */
799 if (ill_count <= livelock_limit) {
800 if (info->i_running == 0) {
801 lwkt_deschedule_self(gd->gd_curthread);
802 lwkt_switch();
803 }
37d44089 804 break;
f33e9c1c
MD
805 }
806
807 /*
808 * Otherwise we are livelocked. Set up a periodic systimer
809 * to wake the thread up at the limit frequency.
810 */
811 printf("intr %d at %d > %d hz, livelocked limit engaged!\n",
812 intr, livelock_limit, ill_count);
813 info->i_state = ISTATE_LIVELOCKED;
814 if ((use_limit = livelock_limit) < 100)
815 use_limit = 100;
816 else if (use_limit > 500000)
817 use_limit = 500000;
818 systimer_init_periodic(&ill_timer, ithread_livelock_wakeup,
819 (void *)intr, use_limit);
820 lcount = 0;
37d44089 821 /* fall through */
f33e9c1c 822 case ISTATE_LIVELOCKED:
37d44089 823 /*
f33e9c1c
MD
824 * Wait for our periodic timer to go off. Since the interrupt
825 * has re-armed it can still set i_running, but it will not
826 * reschedule us while we are in a livelocked state.
37d44089 827 */
f33e9c1c 828 lwkt_deschedule_self(gd->gd_curthread);
37d44089 829 lwkt_switch();
93781523 830
37d44089 831 /*
f33e9c1c
MD
832 * Check to see if the livelock condition no longer applies.
833 * The interrupt must be able to operate normally for one
834 * full second before we restore normal operation.
37d44089 835 */
f33e9c1c
MD
836 if (lticks != ticks) {
837 lticks = ticks;
838 if (ill_count < livelock_lowater) {
839 if (++lcount >= hz) {
840 info->i_state = ISTATE_NORMAL;
841 systimer_del(&ill_timer);
842 printf("intr %d at %d < %d hz, livelock removed\n",
843 intr, ill_count, livelock_lowater);
844 }
845 } else {
846 lcount = 0;
847 }
848 ill_count -= ill_count / hz;
37d44089
MD
849 }
850 break;
851 }
ef0fdad1 852 }
e43a034f 853 /* not reached */
ef0fdad1
MD
854}
855
a9d00ec1
MD
856/*
857 * Emergency interrupt polling thread. The thread begins execution
858 * outside a critical section with the BGL held.
859 *
860 * If emergency interrupt polling is enabled, this thread will
861 * execute all system interrupts not marked INTR_NOPOLL at the
862 * specified polling frequency.
863 *
864 * WARNING! This thread runs *ALL* interrupt service routines that
865 * are not marked INTR_NOPOLL, which basically means everything except
866 * the 8254 clock interrupt and the ATA interrupt. It has very high
867 * overhead and should only be used in situations where the machine
868 * cannot otherwise be made to work. Due to the severe performance
869 * degredation, it should not be enabled on production machines.
870 */
871static void
872ithread_emergency(void *arg __unused)
873{
874 struct intr_info *info;
875 intrec_t rec, nrec;
876 int intr;
877
878 for (;;) {
5f456c40 879 for (intr = 0; intr < max_installed_hard_intr; ++intr) {
a9d00ec1
MD
880 info = &intr_info_ary[intr];
881 for (rec = info->i_reclist; rec; rec = nrec) {
882 if ((rec->intr_flags & INTR_NOPOLL) == 0) {
883 if (rec->serializer) {
884 lwkt_serialize_handler_call(rec->serializer,
885 rec->handler, rec->argument, NULL);
886 } else {
887 rec->handler(rec->argument, NULL);
888 }
889 }
890 nrec = rec->next;
891 }
892 }
893 lwkt_deschedule_self(curthread);
894 lwkt_switch();
895 }
896}
897
898/*
899 * Systimer callback - schedule the emergency interrupt poll thread
900 * if emergency polling is enabled.
901 */
902static
903void
904emergency_intr_timer_callback(systimer_t info, struct intrframe *frame __unused)
905{
906 if (emergency_intr_enable)
907 lwkt_schedule(info->data);
908}
909
984263bc
MD
910/*
911 * Sysctls used by systat and others: hw.intrnames and hw.intrcnt.
912 * The data for this machine dependent, and the declarations are in machine
913 * dependent code. The layout of intrnames and intrcnt however is machine
914 * independent.
915 *
916 * We do not know the length of intrcnt and intrnames at compile time, so
917 * calculate things at run time.
918 */
477d3c1c 919
984263bc
MD
920static int
921sysctl_intrnames(SYSCTL_HANDLER_ARGS)
922{
477d3c1c
MD
923 struct intr_info *info;
924 intrec_t rec;
925 int error = 0;
926 int len;
927 int intr;
928 char buf[64];
929
5f456c40 930 for (intr = 0; error == 0 && intr < MAX_INTS; ++intr) {
477d3c1c
MD
931 info = &intr_info_ary[intr];
932
933 len = 0;
934 buf[0] = 0;
935 for (rec = info->i_reclist; rec; rec = rec->next) {
936 snprintf(buf + len, sizeof(buf) - len, "%s%s",
937 (len ? "/" : ""), rec->name);
938 len += strlen(buf + len);
939 }
940 if (len == 0) {
941 snprintf(buf, sizeof(buf), "irq%d", intr);
942 len = strlen(buf);
943 }
944 error = SYSCTL_OUT(req, buf, len + 1);
945 }
946 return (error);
984263bc
MD
947}
948
477d3c1c 949
984263bc
MD
950SYSCTL_PROC(_hw, OID_AUTO, intrnames, CTLTYPE_OPAQUE | CTLFLAG_RD,
951 NULL, 0, sysctl_intrnames, "", "Interrupt Names");
952
953static int
954sysctl_intrcnt(SYSCTL_HANDLER_ARGS)
955{
477d3c1c
MD
956 struct intr_info *info;
957 int error = 0;
958 int intr;
959
5f456c40 960 for (intr = 0; intr < max_installed_hard_intr; ++intr) {
477d3c1c
MD
961 info = &intr_info_ary[intr];
962
963 error = SYSCTL_OUT(req, &info->i_count, sizeof(info->i_count));
964 if (error)
5f456c40
MD
965 goto failed;
966 }
967 for (intr = FIRST_SOFTINT; intr < max_installed_soft_intr; ++intr) {
968 info = &intr_info_ary[intr];
969
970 error = SYSCTL_OUT(req, &info->i_count, sizeof(info->i_count));
971 if (error)
972 goto failed;
477d3c1c 973 }
5f456c40 974failed:
477d3c1c 975 return(error);
984263bc
MD
976}
977
978SYSCTL_PROC(_hw, OID_AUTO, intrcnt, CTLTYPE_OPAQUE | CTLFLAG_RD,
979 NULL, 0, sysctl_intrcnt, "", "Interrupt Counts");
477d3c1c 980