bge: Reduce the number of dropped frames when flow-control is enabled
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
011c0f93 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
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34 */
35
36/*
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
41 */
42
43/*
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
54 * into the driver.
55 *
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58 *
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
62 *
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
65 *
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
70 * ring.
71 */
72
315fe0ee 73#include "opt_polling.h"
a7db2caa 74
984263bc 75#include <sys/param.h>
62be1357 76#include <sys/bus.h>
20c9a969 77#include <sys/endian.h>
62be1357 78#include <sys/kernel.h>
6b880771 79#include <sys/ktr.h>
9db4b353 80#include <sys/interrupt.h>
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81#include <sys/mbuf.h>
82#include <sys/malloc.h>
984263bc 83#include <sys/queue.h>
62be1357 84#include <sys/rman.h>
16dca0df 85#include <sys/serialize.h>
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86#include <sys/socket.h>
87#include <sys/sockio.h>
055d06f0 88#include <sys/sysctl.h>
984263bc 89
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90#include <net/bpf.h>
91#include <net/ethernet.h>
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92#include <net/if.h>
93#include <net/if_arp.h>
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94#include <net/if_dl.h>
95#include <net/if_media.h>
984263bc 96#include <net/if_types.h>
62be1357 97#include <net/ifq_var.h>
1f2de5d4 98#include <net/vlan/if_vlan_var.h>
b637f170 99#include <net/vlan/if_vlan_ether.h>
984263bc 100
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101#include <dev/netif/mii_layer/mii.h>
102#include <dev/netif/mii_layer/miivar.h>
1f2de5d4 103#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 104
f952ab63 105#include <bus/pci/pcidevs.h>
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106#include <bus/pci/pcireg.h>
107#include <bus/pci/pcivar.h>
984263bc 108
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109#include <dev/netif/bge/if_bgereg.h>
110
111/* "device miibus" required. See GENERIC if you get errors here. */
112#include "miibus_if.h"
984263bc 113
3daed3db 114#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
cb623c48 115#define BGE_MIN_FRAME 60
984263bc 116
d265721a 117static const struct bge_type bge_devs[] = {
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118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119 "3COM 3C996 Gigabit Ethernet" },
120
f952ab63 121 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
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122 "Alteon BCM5700 Gigabit Ethernet" },
123 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124 "Alteon BCM5701 Gigabit Ethernet" },
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125
126 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127 "Altima AC1000 Gigabit Ethernet" },
128 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129 "Altima AC1002 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131 "Altima AC9100 Gigabit Ethernet" },
132
133 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134 "Apple BCM5701 Gigabit Ethernet" },
135
f952ab63 136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
984263bc 137 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
984263bc 139 "Broadcom BCM5701 Gigabit Ethernet" },
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140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141 "Broadcom BCM5702 Gigabit Ethernet" },
f952ab63 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
984263bc 143 "Broadcom BCM5702X Gigabit Ethernet" },
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144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145 "Broadcom BCM5702 Gigabit Ethernet" },
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146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147 "Broadcom BCM5703 Gigabit Ethernet" },
f952ab63
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148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149 "Broadcom BCM5703X Gigabit Ethernet" },
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150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151 "Broadcom BCM5703 Gigabit Ethernet" },
f952ab63 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
984263bc 153 "Broadcom BCM5704C Dual Gigabit Ethernet" },
f952ab63 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
984263bc 155 "Broadcom BCM5704S Dual Gigabit Ethernet" },
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156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157 "Broadcom BCM5704S Dual Gigabit Ethernet" },
f952ab63 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
7e40b8c5 159 "Broadcom BCM5705 Gigabit Ethernet" },
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160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161 "Broadcom BCM5705F Gigabit Ethernet" },
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162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163 "Broadcom BCM5705K Gigabit Ethernet" },
f952ab63 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
7e40b8c5 165 "Broadcom BCM5705M Gigabit Ethernet" },
9a6ee7e2 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
7e40b8c5 167 "Broadcom BCM5705M Gigabit Ethernet" },
92decf65 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
9a6ee7e2 169 "Broadcom BCM5714C Gigabit Ethernet" },
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170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171 "Broadcom BCM5714S Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173 "Broadcom BCM5715 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175 "Broadcom BCM5715S Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177 "Broadcom BCM5720 Gigabit Ethernet" },
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178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179 "Broadcom BCM5721 Gigabit Ethernet" },
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180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181 "Broadcom BCM5722 Gigabit Ethernet" },
f47afe1a
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182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183 "Broadcom BCM5723 Gigabit Ethernet" },
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184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185 "Broadcom BCM5750 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187 "Broadcom BCM5750M Gigabit Ethernet" },
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188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189 "Broadcom BCM5751 Gigabit Ethernet" },
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190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191 "Broadcom BCM5751F Gigabit Ethernet" },
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192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193 "Broadcom BCM5751M Gigabit Ethernet" },
bae5fe9a
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194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195 "Broadcom BCM5752 Gigabit Ethernet" },
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196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197 "Broadcom BCM5752M Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199 "Broadcom BCM5753 Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201 "Broadcom BCM5753F Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203 "Broadcom BCM5753M Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205 "Broadcom BCM5754 Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207 "Broadcom BCM5754M Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209 "Broadcom BCM5755 Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211 "Broadcom BCM5755M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213 "Broadcom BCM5756 Gigabit Ethernet" },
f47afe1a
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214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215 "Broadcom BCM5761 Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217 "Broadcom BCM5761E Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219 "Broadcom BCM5761S Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221 "Broadcom BCM5761SE Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223 "Broadcom BCM5764 Gigabit Ethernet" },
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224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225 "Broadcom BCM5780 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227 "Broadcom BCM5780S Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229 "Broadcom BCM5781 Gigabit Ethernet" },
f952ab63 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
7e40b8c5 231 "Broadcom BCM5782 Gigabit Ethernet" },
f47afe1a
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232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233 "Broadcom BCM5784 Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235 "Broadcom BCM5785F Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237 "Broadcom BCM5785G Gigabit Ethernet" },
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238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239 "Broadcom BCM5786 Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241 "Broadcom BCM5787 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243 "Broadcom BCM5787F Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245 "Broadcom BCM5787M Gigabit Ethernet" },
9a6ee7e2 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
f952ab63 247 "Broadcom BCM5788 Gigabit Ethernet" },
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248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249 "Broadcom BCM5789 Gigabit Ethernet" },
f952ab63
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250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251 "Broadcom BCM5901 Fast Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253 "Broadcom BCM5901A2 Fast Ethernet" },
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254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255 "Broadcom BCM5903M Fast Ethernet" },
591dfc77
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256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257 "Broadcom BCM5906 Fast Ethernet"},
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259 "Broadcom BCM5906M Fast Ethernet"},
f47afe1a
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260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261 "Broadcom BCM57760 Gigabit Ethernet"},
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263 "Broadcom BCM57780 Gigabit Ethernet"},
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265 "Broadcom BCM57788 Gigabit Ethernet"},
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267 "Broadcom BCM57790 Gigabit Ethernet"},
f952ab63 268 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
984263bc 269 "SysKonnect Gigabit Ethernet" },
0ecb11d7 270
984263bc
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271 { 0, 0, NULL }
272};
273
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274#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
275#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
f47afe1a 279#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
0ecb11d7 280
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281typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
282
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283static int bge_probe(device_t);
284static int bge_attach(device_t);
285static int bge_detach(device_t);
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286static void bge_txeof(struct bge_softc *);
287static void bge_rxeof(struct bge_softc *);
288
289static void bge_tick(void *);
290static void bge_stats_update(struct bge_softc *);
291static void bge_stats_update_regs(struct bge_softc *);
4a607ed6 292static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
33c39a69 293
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294#ifdef DEVICE_POLLING
295static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
296#endif
33c39a69 297static void bge_intr(void *);
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298static void bge_enable_intr(struct bge_softc *);
299static void bge_disable_intr(struct bge_softc *);
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300static void bge_start(struct ifnet *);
301static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
302static void bge_init(void *);
303static void bge_stop(struct bge_softc *);
304static void bge_watchdog(struct ifnet *);
305static void bge_shutdown(device_t);
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306static int bge_suspend(device_t);
307static int bge_resume(device_t);
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308static int bge_ifmedia_upd(struct ifnet *);
309static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
310
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311static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
312static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
313
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314static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
315static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
316
33c39a69 317static void bge_setmulti(struct bge_softc *);
6439b28a 318static void bge_setpromisc(struct bge_softc *);
33c39a69 319
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320static int bge_alloc_jumbo_mem(struct bge_softc *);
321static void bge_free_jumbo_mem(struct bge_softc *);
2aa9b12f
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322static struct bge_jslot
323 *bge_jalloc(struct bge_softc *);
324static void bge_jfree(void *);
325static void bge_jref(void *);
1436f9a0
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326static int bge_newbuf_std(struct bge_softc *, int, int);
327static int bge_newbuf_jumbo(struct bge_softc *, int, int);
328static void bge_setup_rxdesc_std(struct bge_softc *, int);
329static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
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330static int bge_init_rx_ring_std(struct bge_softc *);
331static void bge_free_rx_ring_std(struct bge_softc *);
332static int bge_init_rx_ring_jumbo(struct bge_softc *);
333static void bge_free_rx_ring_jumbo(struct bge_softc *);
334static void bge_free_tx_ring(struct bge_softc *);
335static int bge_init_tx_ring(struct bge_softc *);
336
337static int bge_chipinit(struct bge_softc *);
338static int bge_blockinit(struct bge_softc *);
984263bc 339
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340static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
341static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
984263bc 342#ifdef notdef
33c39a69 343static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
984263bc 344#endif
33c39a69 345static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
0ecb11d7 346static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
591dfc77 347static void bge_writembx(struct bge_softc *, int, int);
984263bc 348
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349static int bge_miibus_readreg(device_t, int, int);
350static int bge_miibus_writereg(device_t, int, int, int);
351static void bge_miibus_statchg(device_t);
db861466
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352static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
353static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
354static void bge_copper_link_upd(struct bge_softc *, uint32_t);
984263bc 355
33c39a69 356static void bge_reset(struct bge_softc *);
984263bc 357
20c9a969
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358static int bge_dma_alloc(struct bge_softc *);
359static void bge_dma_free(struct bge_softc *);
360static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
361 bus_dma_tag_t *, bus_dmamap_t *,
362 void **, bus_addr_t *);
363static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
364
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365static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
366static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
367static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
368static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
369
055d06f0
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370static void bge_coal_change(struct bge_softc *);
371static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
372static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
373static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
374static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
375static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
376
5c56d5d8
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377/*
378 * Set following tunable to 1 for some IBM blade servers with the DNLK
379 * switch module. Auto negotiation is broken for those configurations.
380 */
381static int bge_fake_autoneg = 0;
382TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
383
055d06f0 384/* Interrupt moderation control variables. */
61b4fa0a 385static int bge_rx_coal_ticks = 100; /* usec */
83015dae 386static int bge_tx_coal_ticks = 1023; /* usec */
b02a2d90 387static int bge_rx_max_coal_bds = 80;
77dee542 388static int bge_tx_max_coal_bds = 128;
055d06f0
SZ
389
390TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
391TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
392TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
393TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
394
6b880771
SZ
395#if !defined(KTR_IF_BGE)
396#define KTR_IF_BGE KTR_ALL
397#endif
398KTR_INFO_MASTER(if_bge);
5bf48697
AE
399KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
400KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
401KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
6b880771
SZ
402#define logif(name) KTR_LOG(if_bge_ ## name)
403
984263bc
MD
404static device_method_t bge_methods[] = {
405 /* Device interface */
406 DEVMETHOD(device_probe, bge_probe),
407 DEVMETHOD(device_attach, bge_attach),
408 DEVMETHOD(device_detach, bge_detach),
409 DEVMETHOD(device_shutdown, bge_shutdown),
aa65409c
SZ
410 DEVMETHOD(device_suspend, bge_suspend),
411 DEVMETHOD(device_resume, bge_resume),
984263bc
MD
412
413 /* bus interface */
414 DEVMETHOD(bus_print_child, bus_generic_print_child),
415 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
416
417 /* MII interface */
418 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
419 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
420 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
421
422 { 0, 0 }
423};
424
33c39a69 425static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
984263bc
MD
426static devclass_t bge_devclass;
427
32832096 428DECLARE_DUMMY_MODULE(if_bge);
aa2b9d05
SW
429DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
430DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
984263bc 431
33c39a69
JS
432static uint32_t
433bge_readmem_ind(struct bge_softc *sc, uint32_t off)
984263bc 434{
33c39a69 435 device_t dev = sc->bge_dev;
0ecb11d7 436 uint32_t val;
984263bc
MD
437
438 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
0ecb11d7
SZ
439 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441 return (val);
984263bc
MD
442}
443
444static void
33c39a69 445bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 446{
33c39a69 447 device_t dev = sc->bge_dev;
984263bc
MD
448
449 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
450 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
0ecb11d7 451 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
984263bc
MD
452}
453
454#ifdef notdef
33c39a69
JS
455static uint32_t
456bge_readreg_ind(struct bge_softc *sc, uin32_t off)
984263bc 457{
33c39a69 458 device_t dev = sc->bge_dev;
984263bc
MD
459
460 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
462}
463#endif
464
465static void
33c39a69 466bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 467{
33c39a69 468 device_t dev = sc->bge_dev;
984263bc
MD
469
470 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
471 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
984263bc
MD
472}
473
0ecb11d7
SZ
474static void
475bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
476{
477 CSR_WRITE_4(sc, off, val);
478}
479
591dfc77
SZ
480static void
481bge_writembx(struct bge_softc *sc, int off, int val)
482{
483 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
484 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
485
486 CSR_WRITE_4(sc, off, val);
487}
488
489static uint8_t
490bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
491{
492 uint32_t access, byte = 0;
493 int i;
494
495 /* Lock. */
496 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
497 for (i = 0; i < 8000; i++) {
498 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
499 break;
500 DELAY(20);
501 }
502 if (i == 8000)
503 return (1);
504
505 /* Enable access. */
506 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
507 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
508
509 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
510 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
511 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
512 DELAY(10);
513 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
514 DELAY(10);
515 break;
516 }
517 }
518
519 if (i == BGE_TIMEOUT * 10) {
520 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
521 return (1);
522 }
523
524 /* Get result. */
525 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
526
527 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
528
529 /* Disable access. */
530 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
531
532 /* Unlock. */
533 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
534 CSR_READ_4(sc, BGE_NVRAM_SWARB);
535
536 return (0);
537}
538
539/*
540 * Read a sequence of bytes from NVRAM.
541 */
542static int
543bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
544{
545 int err = 0, i;
546 uint8_t byte = 0;
547
548 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
549 return (1);
550
551 for (i = 0; i < cnt; i++) {
552 err = bge_nvram_getbyte(sc, off + i, &byte);
553 if (err)
554 break;
555 *(dest + i) = byte;
556 }
557
558 return (err ? 1 : 0);
559}
560
984263bc
MD
561/*
562 * Read a byte of data stored in the EEPROM at address 'addr.' The
563 * BCM570x supports both the traditional bitbang interface and an
564 * auto access interface for reading the EEPROM. We use the auto
565 * access method.
566 */
33c39a69
JS
567static uint8_t
568bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
984263bc
MD
569{
570 int i;
33c39a69 571 uint32_t byte = 0;
984263bc
MD
572
573 /*
574 * Enable use of auto EEPROM access so we can avoid
575 * having to use the bitbang method.
576 */
577 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
578
579 /* Reset the EEPROM, load the clock period. */
580 CSR_WRITE_4(sc, BGE_EE_ADDR,
581 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
582 DELAY(20);
583
584 /* Issue the read EEPROM command. */
585 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
586
587 /* Wait for completion */
588 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
589 DELAY(10);
590 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
591 break;
592 }
593
594 if (i == BGE_TIMEOUT) {
c6fd6f3b 595 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
7b47d9c2 596 return(1);
984263bc
MD
597 }
598
599 /* Get result. */
600 byte = CSR_READ_4(sc, BGE_EE_DATA);
601
602 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
603
604 return(0);
605}
606
607/*
608 * Read a sequence of bytes from the EEPROM.
609 */
610static int
33c39a69 611bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
984263bc 612{
33c39a69
JS
613 size_t i;
614 int err;
615 uint8_t byte;
984263bc 616
33c39a69 617 for (byte = 0, err = 0, i = 0; i < len; i++) {
984263bc
MD
618 err = bge_eeprom_getbyte(sc, off + i, &byte);
619 if (err)
620 break;
621 *(dest + i) = byte;
622 }
623
624 return(err ? 1 : 0);
625}
626
627static int
33c39a69 628bge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 629{
f7a1f3ba
SZ
630 struct bge_softc *sc = device_get_softc(dev);
631 struct ifnet *ifp = &sc->arpcom.ac_if;
33c39a69 632 uint32_t val, autopoll;
984263bc
MD
633 int i;
634
7e40b8c5
HP
635 /*
636 * Broadcom's own driver always assumes the internal
637 * PHY is at GMII address 1. On some chips, the PHY responds
638 * to accesses at all addresses, which could cause us to
639 * bogusly attach the PHY 32 times at probe type. Always
640 * restricting the lookup to address 1 is simpler than
641 * trying to figure out which chips revisions should be
642 * special-cased.
643 */
984263bc 644 if (phy != 1)
7e40b8c5 645 return(0);
984263bc
MD
646
647 /* Reading with autopolling on may trigger PCI errors */
648 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
649 if (autopoll & BGE_MIMODE_AUTOPOLL) {
650 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
651 DELAY(40);
652 }
653
654 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
655 BGE_MIPHY(phy)|BGE_MIREG(reg));
656
657 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba 658 DELAY(10);
984263bc
MD
659 val = CSR_READ_4(sc, BGE_MI_COMM);
660 if (!(val & BGE_MICOMM_BUSY))
661 break;
662 }
663
664 if (i == BGE_TIMEOUT) {
f7a1f3ba
SZ
665 if_printf(ifp, "PHY read timed out "
666 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
984263bc
MD
667 val = 0;
668 goto done;
669 }
670
f7a1f3ba 671 DELAY(5);
984263bc
MD
672 val = CSR_READ_4(sc, BGE_MI_COMM);
673
674done:
675 if (autopoll & BGE_MIMODE_AUTOPOLL) {
676 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
677 DELAY(40);
678 }
679
680 if (val & BGE_MICOMM_READFAIL)
681 return(0);
682
683 return(val & 0xFFFF);
684}
685
686static int
33c39a69 687bge_miibus_writereg(device_t dev, int phy, int reg, int val)
984263bc 688{
f7a1f3ba 689 struct bge_softc *sc = device_get_softc(dev);
33c39a69 690 uint32_t autopoll;
984263bc
MD
691 int i;
692
f7a1f3ba
SZ
693 /*
694 * See the related comment in bge_miibus_readreg()
695 */
696 if (phy != 1)
697 return(0);
984263bc 698
591dfc77
SZ
699 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701 return(0);
702
984263bc
MD
703 /* Reading with autopolling on may trigger PCI errors */
704 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
705 if (autopoll & BGE_MIMODE_AUTOPOLL) {
706 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
707 DELAY(40);
708 }
709
710 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
711 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
712
713 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba
SZ
714 DELAY(10);
715 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716 DELAY(5);
717 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
984263bc 718 break;
f7a1f3ba 719 }
984263bc
MD
720 }
721
722 if (autopoll & BGE_MIMODE_AUTOPOLL) {
723 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
724 DELAY(40);
725 }
726
727 if (i == BGE_TIMEOUT) {
f7a1f3ba
SZ
728 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
729 "(phy %d, reg %d, val %d)\n", phy, reg, val);
984263bc
MD
730 return(0);
731 }
732
733 return(0);
734}
735
736static void
33c39a69 737bge_miibus_statchg(device_t dev)
984263bc
MD
738{
739 struct bge_softc *sc;
740 struct mii_data *mii;
741
742 sc = device_get_softc(dev);
743 mii = device_get_softc(sc->bge_miibus);
744
745 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
4d38e186
SZ
746 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
747 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
984263bc
MD
748 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
749 } else {
750 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
751 }
752
753 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
754 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
755 } else {
756 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
757 }
984263bc
MD
758}
759
760/*
984263bc
MD
761 * Memory management for jumbo frames.
762 */
984263bc 763static int
33c39a69 764bge_alloc_jumbo_mem(struct bge_softc *sc)
984263bc 765{
20c9a969 766 struct ifnet *ifp = &sc->arpcom.ac_if;
2aa9b12f 767 struct bge_jslot *entry;
20c9a969
SZ
768 uint8_t *ptr;
769 bus_addr_t paddr;
770 int i, error;
984263bc 771
20c9a969
SZ
772 /*
773 * Create tag for jumbo mbufs.
774 * This is really a bit of a kludge. We allocate a special
775 * jumbo buffer pool which (thanks to the way our DMA
776 * memory allocation works) will consist of contiguous
777 * pages. This means that even though a jumbo buffer might
778 * be larger than a page size, we don't really need to
779 * map it into more than one DMA segment. However, the
780 * default mbuf tag will result in multi-segment mappings,
781 * so we have to create a special jumbo mbuf tag that
782 * lets us get away with mapping the jumbo buffers as
783 * a single segment. I think eventually the driver should
784 * be changed so that it uses ordinary mbufs and cluster
785 * buffers, i.e. jumbo frames can span multiple DMA
786 * descriptors. But that's a project for another day.
787 */
984263bc 788
20c9a969
SZ
789 /*
790 * Create DMA stuffs for jumbo RX ring.
791 */
792 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
793 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
794 &sc->bge_cdata.bge_rx_jumbo_ring_map,
da44240f 795 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
20c9a969
SZ
796 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
797 if (error) {
798 if_printf(ifp, "could not create jumbo RX ring\n");
799 return error;
800 }
801
802 /*
803 * Create DMA stuffs for jumbo buffer block.
804 */
805 error = bge_dma_block_alloc(sc, BGE_JMEM,
806 &sc->bge_cdata.bge_jumbo_tag,
807 &sc->bge_cdata.bge_jumbo_map,
808 (void **)&sc->bge_ldata.bge_jumbo_buf,
809 &paddr);
810 if (error) {
811 if_printf(ifp, "could not create jumbo buffer\n");
812 return error;
984263bc
MD
813 }
814
815 SLIST_INIT(&sc->bge_jfree_listhead);
984263bc
MD
816
817 /*
818 * Now divide it up into 9K pieces and save the addresses
819 * in an array. Note that we play an evil trick here by using
820 * the first few bytes in the buffer to hold the the address
821 * of the softc structure for this interface. This is because
822 * bge_jfree() needs it, but it is called by the mbuf management
823 * code which will not pass it to us explicitly.
824 */
20c9a969 825 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
2aa9b12f
JS
826 entry = &sc->bge_cdata.bge_jslots[i];
827 entry->bge_sc = sc;
828 entry->bge_buf = ptr;
20c9a969 829 entry->bge_paddr = paddr;
2aa9b12f
JS
830 entry->bge_inuse = 0;
831 entry->bge_slot = i;
832 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
20c9a969 833
2aa9b12f 834 ptr += BGE_JLEN;
20c9a969 835 paddr += BGE_JLEN;
984263bc 836 }
20c9a969 837 return 0;
984263bc
MD
838}
839
840static void
33c39a69 841bge_free_jumbo_mem(struct bge_softc *sc)
984263bc 842{
20c9a969
SZ
843 /* Destroy jumbo RX ring. */
844 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
845 sc->bge_cdata.bge_rx_jumbo_ring_map,
846 sc->bge_ldata.bge_rx_jumbo_ring);
847
848 /* Destroy jumbo buffer block. */
849 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
850 sc->bge_cdata.bge_jumbo_map,
851 sc->bge_ldata.bge_jumbo_buf);
984263bc
MD
852}
853
854/*
855 * Allocate a jumbo buffer.
856 */
2aa9b12f 857static struct bge_jslot *
33c39a69 858bge_jalloc(struct bge_softc *sc)
984263bc 859{
2aa9b12f 860 struct bge_jslot *entry;
33c39a69 861
16dca0df 862 lwkt_serialize_enter(&sc->bge_jslot_serializer);
984263bc 863 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
16dca0df
MD
864 if (entry) {
865 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
866 entry->bge_inuse = 1;
867 } else {
c6fd6f3b 868 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
984263bc 869 }
16dca0df 870 lwkt_serialize_exit(&sc->bge_jslot_serializer);
2aa9b12f 871 return(entry);
984263bc
MD
872}
873
874/*
875 * Adjust usage count on a jumbo buffer.
876 */
877static void
2aa9b12f 878bge_jref(void *arg)
984263bc 879{
2aa9b12f
JS
880 struct bge_jslot *entry = (struct bge_jslot *)arg;
881 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
882
883 if (sc == NULL)
884 panic("bge_jref: can't find softc pointer!");
885
16dca0df 886 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc
MD
887 panic("bge_jref: asked to reference buffer "
888 "that we don't manage!");
16dca0df 889 } else if (entry->bge_inuse == 0) {
984263bc 890 panic("bge_jref: buffer already free!");
16dca0df
MD
891 } else {
892 atomic_add_int(&entry->bge_inuse, 1);
893 }
984263bc
MD
894}
895
896/*
897 * Release a jumbo buffer.
898 */
899static void
2aa9b12f 900bge_jfree(void *arg)
984263bc 901{
2aa9b12f
JS
902 struct bge_jslot *entry = (struct bge_jslot *)arg;
903 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
904
905 if (sc == NULL)
906 panic("bge_jfree: can't find softc pointer!");
907
16dca0df 908 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc 909 panic("bge_jfree: asked to free buffer that we don't manage!");
16dca0df 910 } else if (entry->bge_inuse == 0) {
984263bc 911 panic("bge_jfree: buffer already free!");
16dca0df
MD
912 } else {
913 /*
914 * Possible MP race to 0, use the serializer. The atomic insn
915 * is still needed for races against bge_jref().
916 */
917 lwkt_serialize_enter(&sc->bge_jslot_serializer);
918 atomic_subtract_int(&entry->bge_inuse, 1);
919 if (entry->bge_inuse == 0) {
920 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
921 entry, jslot_link);
922 }
923 lwkt_serialize_exit(&sc->bge_jslot_serializer);
924 }
984263bc
MD
925}
926
927
928/*
929 * Intialize a standard receive ring descriptor.
930 */
931static int
1436f9a0 932bge_newbuf_std(struct bge_softc *sc, int i, int init)
984263bc 933{
33c39a69 934 struct mbuf *m_new = NULL;
20c9a969 935 bus_dma_segment_t seg;
1436f9a0 936 bus_dmamap_t map;
2de621e9 937 int error, nsegs;
984263bc 938
1436f9a0
SZ
939 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
940 if (m_new == NULL)
941 return ENOBUFS;
20c9a969 942 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
984263bc 943
0ecb11d7 944 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
984263bc 945 m_adj(m_new, ETHER_ALIGN);
20c9a969 946
2de621e9
SZ
947 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
948 sc->bge_cdata.bge_rx_tmpmap, m_new,
949 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
950 if (error) {
1436f9a0 951 m_freem(m_new);
2de621e9 952 return error;
20c9a969
SZ
953 }
954
1436f9a0
SZ
955 if (!init) {
956 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
957 sc->bge_cdata.bge_rx_std_dmamap[i],
958 BUS_DMASYNC_POSTREAD);
959 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
960 sc->bge_cdata.bge_rx_std_dmamap[i]);
961 }
20c9a969 962
1436f9a0
SZ
963 map = sc->bge_cdata.bge_rx_tmpmap;
964 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
965 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
966
967 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
2de621e9 968 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1436f9a0
SZ
969
970 bge_setup_rxdesc_std(sc, i);
20c9a969 971 return 0;
984263bc
MD
972}
973
1436f9a0
SZ
974static void
975bge_setup_rxdesc_std(struct bge_softc *sc, int i)
976{
977 struct bge_rxchain *rc;
978 struct bge_rx_bd *r;
979
980 rc = &sc->bge_cdata.bge_rx_std_chain[i];
981 r = &sc->bge_ldata.bge_rx_std_ring[i];
982
983 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
984 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
985 r->bge_len = rc->bge_mbuf->m_len;
986 r->bge_idx = i;
987 r->bge_flags = BGE_RXBDFLAG_END;
988}
989
984263bc
MD
990/*
991 * Initialize a jumbo receive ring descriptor. This allocates
992 * a jumbo buffer from the pool managed internally by the driver.
993 */
994static int
1436f9a0 995bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
984263bc
MD
996{
997 struct mbuf *m_new = NULL;
20c9a969 998 struct bge_jslot *buf;
20c9a969 999 bus_addr_t paddr;
984263bc 1000
1436f9a0
SZ
1001 /* Allocate the mbuf. */
1002 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1003 if (m_new == NULL)
1004 return ENOBUFS;
2aa9b12f 1005
1436f9a0
SZ
1006 /* Allocate the jumbo buffer */
1007 buf = bge_jalloc(sc);
1008 if (buf == NULL) {
1009 m_freem(m_new);
1010 return ENOBUFS;
984263bc 1011 }
1436f9a0
SZ
1012
1013 /* Attach the buffer to the mbuf. */
1014 m_new->m_ext.ext_arg = buf;
1015 m_new->m_ext.ext_buf = buf->bge_buf;
1016 m_new->m_ext.ext_free = bge_jfree;
1017 m_new->m_ext.ext_ref = bge_jref;
1018 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1019
1020 m_new->m_flags |= M_EXT;
1021
20c9a969
SZ
1022 m_new->m_data = m_new->m_ext.ext_buf;
1023 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc 1024
20c9a969 1025 paddr = buf->bge_paddr;
0ecb11d7 1026 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
984263bc 1027 m_adj(m_new, ETHER_ALIGN);
20c9a969
SZ
1028 paddr += ETHER_ALIGN;
1029 }
1030
1436f9a0
SZ
1031 /* Save necessary information */
1032 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1033 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1034
984263bc 1035 /* Set up the descriptor. */
1436f9a0
SZ
1036 bge_setup_rxdesc_jumbo(sc, i);
1037 return 0;
1038}
1039
1040static void
1041bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1042{
1043 struct bge_rx_bd *r;
1044 struct bge_rxchain *rc;
20c9a969
SZ
1045
1046 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1436f9a0 1047 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
984263bc 1048
1436f9a0
SZ
1049 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1050 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1051 r->bge_len = rc->bge_mbuf->m_len;
1052 r->bge_idx = i;
1053 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
984263bc
MD
1054}
1055
984263bc 1056static int
33c39a69 1057bge_init_rx_ring_std(struct bge_softc *sc)
984263bc 1058{
1436f9a0 1059 int i, error;
984263bc 1060
1436f9a0
SZ
1061 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1062 error = bge_newbuf_std(sc, i, 1);
1063 if (error)
1064 return error;
984263bc
MD
1065 };
1066
1436f9a0 1067 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
591dfc77 1068 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc
MD
1069
1070 return(0);
1071}
1072
1073static void
33c39a69 1074bge_free_rx_ring_std(struct bge_softc *sc)
984263bc
MD
1075{
1076 int i;
1077
1078 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1436f9a0
SZ
1079 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1080
1081 if (rc->bge_mbuf != NULL) {
ddca511d 1082 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
20c9a969 1083 sc->bge_cdata.bge_rx_std_dmamap[i]);
1436f9a0
SZ
1084 m_freem(rc->bge_mbuf);
1085 rc->bge_mbuf = NULL;
984263bc 1086 }
20c9a969 1087 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
984263bc
MD
1088 sizeof(struct bge_rx_bd));
1089 }
984263bc
MD
1090}
1091
1092static int
33c39a69 1093bge_init_rx_ring_jumbo(struct bge_softc *sc)
984263bc 1094{
984263bc 1095 struct bge_rcb *rcb;
1436f9a0 1096 int i, error;
984263bc
MD
1097
1098 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1099 error = bge_newbuf_jumbo(sc, i, 1);
1100 if (error)
1101 return error;
984263bc
MD
1102 };
1103
1436f9a0 1104 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
984263bc 1105
20c9a969 1106 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
984263bc
MD
1107 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1108 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1109
591dfc77 1110 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
1111
1112 return(0);
1113}
1114
1115static void
33c39a69 1116bge_free_rx_ring_jumbo(struct bge_softc *sc)
984263bc
MD
1117{
1118 int i;
1119
1120 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1121 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1122
1123 if (rc->bge_mbuf != NULL) {
1124 m_freem(rc->bge_mbuf);
1125 rc->bge_mbuf = NULL;
984263bc 1126 }
20c9a969 1127 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
984263bc
MD
1128 sizeof(struct bge_rx_bd));
1129 }
984263bc
MD
1130}
1131
1132static void
33c39a69 1133bge_free_tx_ring(struct bge_softc *sc)
984263bc
MD
1134{
1135 int i;
1136
984263bc
MD
1137 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1138 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
ddca511d 1139 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 1140 sc->bge_cdata.bge_tx_dmamap[i]);
984263bc
MD
1141 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1142 sc->bge_cdata.bge_tx_chain[i] = NULL;
1143 }
20c9a969 1144 bzero(&sc->bge_ldata.bge_tx_ring[i],
984263bc
MD
1145 sizeof(struct bge_tx_bd));
1146 }
984263bc
MD
1147}
1148
1149static int
33c39a69 1150bge_init_tx_ring(struct bge_softc *sc)
984263bc
MD
1151{
1152 sc->bge_txcnt = 0;
1153 sc->bge_tx_saved_considx = 0;
94db8384
SZ
1154 sc->bge_tx_prodidx = 0;
1155
1156 /* Initialize transmit producer index for host-memory send ring. */
591dfc77 1157 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1158
984263bc
MD
1159 /* 5700 b2 errata */
1160 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1161 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1162
591dfc77 1163 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1164 /* 5700 b2 errata */
1165 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1166 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1167
1168 return(0);
1169}
1170
984263bc 1171static void
33c39a69 1172bge_setmulti(struct bge_softc *sc)
984263bc
MD
1173{
1174 struct ifnet *ifp;
1175 struct ifmultiaddr *ifma;
33c39a69 1176 uint32_t hashes[4] = { 0, 0, 0, 0 };
984263bc
MD
1177 int h, i;
1178
1179 ifp = &sc->arpcom.ac_if;
1180
1181 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1182 for (i = 0; i < 4; i++)
1183 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1184 return;
1185 }
1186
1187 /* First, zot all the existing filters. */
1188 for (i = 0; i < 4; i++)
1189 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1190
1191 /* Now program new ones. */
441d34b2 1192 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1193 if (ifma->ifma_addr->sa_family != AF_LINK)
1194 continue;
3b4ec5b8
JS
1195 h = ether_crc32_le(
1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1197 ETHER_ADDR_LEN) & 0x7f;
984263bc
MD
1198 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1199 }
1200
1201 for (i = 0; i < 4; i++)
1202 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
984263bc
MD
1203}
1204
1205/*
1206 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1207 * self-test results.
1208 */
1209static int
33c39a69 1210bge_chipinit(struct bge_softc *sc)
984263bc 1211{
33c39a69
JS
1212 int i;
1213 uint32_t dma_rw_ctl;
c5a5f269 1214 uint16_t val;
984263bc 1215
20c9a969
SZ
1216 /* Set endian type before we access any non-PCI registers. */
1217 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
984263bc 1218
984263bc
MD
1219 /* Clear the MAC control register */
1220 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1221
1222 /*
1223 * Clear the MAC statistics block in the NIC's
1224 * internal memory.
1225 */
1226 for (i = BGE_STATS_BLOCK;
33c39a69 1227 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1228 BGE_MEMWIN_WRITE(sc, i, 0);
1229
1230 for (i = BGE_STATUS_BLOCK;
33c39a69 1231 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1232 BGE_MEMWIN_WRITE(sc, i, 0);
1233
c5a5f269
SZ
1234 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1235 /*
1236 * Fix data corruption caused by non-qword write with WB.
1237 * Fix master abort in PCI mode.
1238 * Fix PCI latency timer.
1239 */
1240 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1241 val |= (1 << 10) | (1 << 12) | (1 << 13);
1242 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1243 }
1244
984263bc 1245 /* Set up the PCI DMA control register. */
0ecb11d7 1246 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
1247 /* PCI Express */
1248 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1249 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1250 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1251 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
984263bc 1252 /* PCI-X bus */
0ecb11d7
SZ
1253 if (BGE_IS_5714_FAMILY(sc)) {
1254 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1255 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1256 /* XXX magic values, Broadcom-supplied Linux driver */
1257 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1258 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1259 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1260 } else {
1261 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1262 }
33af0f18
SZ
1263 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1264 /*
1265 * In the BCM5703, the DMA read watermark should
1266 * be set to less than or equal to the maximum
1267 * memory read byte count of the PCI-X command
1268 * register.
1269 */
1270 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1271 (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1272 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7
SZ
1273 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1274 /*
1275 * The 5704 uses a different encoding of read/write
1276 * watermarks.
1277 */
984263bc
MD
1278 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1279 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1280 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1281 } else {
984263bc
MD
1282 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1283 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1284 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1285 (0x0F);
0ecb11d7 1286 }
984263bc
MD
1287
1288 /*
1289 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1290 * for hardware bugs.
1291 */
1292 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1293 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
33c39a69 1294 uint32_t tmp;
984263bc
MD
1295
1296 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1297 if (tmp == 0x6 || tmp == 0x7)
1298 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1299 }
0ecb11d7
SZ
1300 } else {
1301 /* Conventional PCI bus */
1302 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1303 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1304 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1305 (0x0F);
984263bc
MD
1306 }
1307
1308 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
7e40b8c5 1309 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
0ecb11d7 1310 sc->bge_asicrev == BGE_ASICREV_BCM5705)
984263bc
MD
1311 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1312 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1313
1314 /*
1315 * Set up general mode register.
1316 */
20c9a969 1317 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
984263bc 1318 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
bf29e666 1319 BGE_MODECTL_TX_NO_PHDR_CSUM);
984263bc
MD
1320
1321 /*
33dd4678
SZ
1322 * BCM5701 B5 have a bug causing data corruption when using
1323 * 64-bit DMA reads, which can be terminated early and then
1324 * completed later as 32-bit accesses, in combination with
1325 * certain bridges.
1326 */
1327 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1328 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1329 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1330
1331 /*
984263bc
MD
1332 * Disable memory write invalidate. Apparently it is not supported
1333 * properly by these devices.
1334 */
1335 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1336
984263bc
MD
1337 /* Set the timer prescaler (always 66Mhz) */
1338 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1339
591dfc77
SZ
1340 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1341 DELAY(40); /* XXX */
1342
1343 /* Put PHY into ready state */
1344 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1345 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1346 DELAY(40);
1347 }
1348
984263bc
MD
1349 return(0);
1350}
1351
1352static int
33c39a69 1353bge_blockinit(struct bge_softc *sc)
984263bc
MD
1354{
1355 struct bge_rcb *rcb;
20c9a969
SZ
1356 bus_size_t vrcb;
1357 bge_hostaddr taddr;
0ecb11d7 1358 uint32_t val;
984263bc
MD
1359 int i;
1360
1361 /*
1362 * Initialize the memory window pointer register so that
1363 * we can access the first 32K of internal NIC RAM. This will
1364 * allow us to set up the TX send ring RCBs and the RX return
1365 * ring RCBs, plus other things which live in NIC memory.
1366 */
1367 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1368
7e40b8c5
HP
1369 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1370
0ecb11d7 1371 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5 1372 /* Configure mbuf memory pool */
0ecb11d7
SZ
1373 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1374 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1375 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1376 else
1377 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
984263bc 1378
7e40b8c5
HP
1379 /* Configure DMA resource pool */
1380 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1381 BGE_DMA_DESCRIPTORS);
1382 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1383 }
984263bc
MD
1384
1385 /* Configure mbuf pool watermarks */
591dfc77 1386 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1387 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1388 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
591dfc77
SZ
1389 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1390 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1391 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1392 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1394 } else {
1395 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1396 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
7e40b8c5 1398 }
984263bc
MD
1399
1400 /* Configure DMA resource watermarks */
1401 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1402 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1403
1404 /* Enable buffer manager */
0ecb11d7 1405 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1406 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1407 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
984263bc 1408
7e40b8c5
HP
1409 /* Poll for buffer manager start indication */
1410 for (i = 0; i < BGE_TIMEOUT; i++) {
1411 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1412 break;
1413 DELAY(10);
1414 }
984263bc 1415
7e40b8c5 1416 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1417 if_printf(&sc->arpcom.ac_if,
1418 "buffer manager failed to start\n");
7e40b8c5
HP
1419 return(ENXIO);
1420 }
984263bc
MD
1421 }
1422
1423 /* Enable flow-through queues */
1424 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1425 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1426
1427 /* Wait until queue initialization is complete */
1428 for (i = 0; i < BGE_TIMEOUT; i++) {
1429 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1430 break;
1431 DELAY(10);
1432 }
1433
1434 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1435 if_printf(&sc->arpcom.ac_if,
1436 "flow-through queue init failed\n");
984263bc
MD
1437 return(ENXIO);
1438 }
1439
1440 /* Initialize the standard RX ring control block */
20c9a969
SZ
1441 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1442 rcb->bge_hostaddr.bge_addr_lo =
1443 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1444 rcb->bge_hostaddr.bge_addr_hi =
1445 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
0ecb11d7 1446 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
1447 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1448 else
1449 rcb->bge_maxlen_flags =
1450 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
0ecb11d7 1451 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
984263bc
MD
1452 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1453 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1454 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1455 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1456
1457 /*
1458 * Initialize the jumbo RX ring control block
1459 * We set the 'ring disabled' bit in the flags
1460 * field until we're actually ready to start
1461 * using this ring (i.e. once we set the MTU
1462 * high enough to require it).
1463 */
0ecb11d7 1464 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969
SZ
1465 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1466
1467 rcb->bge_hostaddr.bge_addr_lo =
1468 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1469 rcb->bge_hostaddr.bge_addr_hi =
1470 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
7e40b8c5
HP
1471 rcb->bge_maxlen_flags =
1472 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1473 BGE_RCB_FLAG_RING_DISABLED);
0ecb11d7 1474 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
7e40b8c5
HP
1475 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1476 rcb->bge_hostaddr.bge_addr_hi);
1477 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1478 rcb->bge_hostaddr.bge_addr_lo);
1479 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1480 rcb->bge_maxlen_flags);
1481 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1482
1483 /* Set up dummy disabled mini ring RCB */
20c9a969 1484 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
7e40b8c5
HP
1485 rcb->bge_maxlen_flags =
1486 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1487 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1488 rcb->bge_maxlen_flags);
1489 }
984263bc
MD
1490
1491 /*
1492 * Set the BD ring replentish thresholds. The recommended
1493 * values are 1/8th the number of descriptors allocated to
1494 * each ring.
1495 */
0ecb11d7
SZ
1496 if (BGE_IS_5705_PLUS(sc))
1497 val = 8;
1498 else
1499 val = BGE_STD_RX_RING_CNT / 8;
1500 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
127003d4
SZ
1501 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1502 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1503 BGE_JUMBO_RX_RING_CNT/8);
1504 }
984263bc
MD
1505
1506 /*
1507 * Disable all unused send rings by setting the 'ring disabled'
1508 * bit in the flags field of all the TX send ring control blocks.
1509 * These are located in NIC memory.
1510 */
20c9a969 1511 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
984263bc 1512 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
20c9a969
SZ
1513 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1514 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1515 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1516 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1517 }
1518
1519 /* Configure TX RCB 0 (we use only the first ring) */
20c9a969
SZ
1520 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1521 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1522 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1523 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1524 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1525 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
0ecb11d7 1526 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1527 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1528 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1529 }
984263bc
MD
1530
1531 /* Disable all unused RX return rings */
20c9a969 1532 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
984263bc 1533 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
20c9a969
SZ
1534 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1535 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1536 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
7e40b8c5 1537 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
20c9a969
SZ
1538 BGE_RCB_FLAG_RING_DISABLED));
1539 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
591dfc77 1540 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
33c39a69 1541 (i * (sizeof(uint64_t))), 0);
20c9a969 1542 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1543 }
1544
1545 /* Initialize RX ring indexes */
591dfc77 1546 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
127003d4
SZ
1547 if (BGE_IS_JUMBO_CAPABLE(sc))
1548 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
591dfc77 1549 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
984263bc
MD
1550
1551 /*
1552 * Set up RX return ring 0
1553 * Note that the NIC address for RX return rings is 0x00000000.
1554 * The return rings live entirely within the host, so the
1555 * nicaddr field in the RCB isn't used.
1556 */
20c9a969
SZ
1557 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1558 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1559 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1560 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1561 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1562 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1563 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
984263bc
MD
1564
1565 /* Set random backoff seed for TX */
1566 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1567 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1568 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1569 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1570 BGE_TX_BACKOFF_SEED_MASK);
1571
1572 /* Set inter-packet gap */
1573 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1574
1575 /*
1576 * Specify which ring to use for packets that don't match
1577 * any RX rules.
1578 */
1579 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1580
1581 /*
1582 * Configure number of RX lists. One interrupt distribution
1583 * list, sixteen active lists, one bad frames class.
1584 */
1585 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1586
1587 /* Inialize RX list placement stats mask. */
1588 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1589 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1590
1591 /* Disable host coalescing until we get it set up */
1592 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1593
1594 /* Poll to make sure it's shut down. */
1595 for (i = 0; i < BGE_TIMEOUT; i++) {
1596 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1597 break;
1598 DELAY(10);
1599 }
1600
1601 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1602 if_printf(&sc->arpcom.ac_if,
1603 "host coalescing engine failed to idle\n");
984263bc
MD
1604 return(ENXIO);
1605 }
1606
1607 /* Set up host coalescing defaults */
1608 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1609 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1610 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1611 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
0ecb11d7 1612 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1613 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1614 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1615 }
ba39cc82
SZ
1616 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1617 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
984263bc
MD
1618
1619 /* Set up address of statistics block */
0ecb11d7 1620 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1621 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1622 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
7e40b8c5 1623 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
20c9a969 1624 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
7e40b8c5
HP
1625
1626 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1627 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1628 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1629 }
984263bc
MD
1630
1631 /* Set up address of status block */
a1620bc8 1632 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
20c9a969
SZ
1633 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1634 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
984263bc 1635 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
20c9a969 1636 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
984263bc 1637
8b1932b2
SZ
1638 /*
1639 * Set up status block partail update size.
1640 *
1641 * Because only single TX ring, RX produce ring and Rx return ring
1642 * are used, ask device to update only minimum part of status block
1643 * except for BCM5700 AX/BX, whose status block partial update size
1644 * can't be configured.
1645 */
1646 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1647 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1648 /* XXX Actually reserved on BCM5700 AX/BX */
1649 val = BGE_STATBLKSZ_FULL;
1650 } else {
1651 val = BGE_STATBLKSZ_32BYTE;
1652 }
1653
984263bc 1654 /* Turn on host coalescing state machine */
8b1932b2 1655 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
984263bc
MD
1656
1657 /* Turn on RX BD completion state machine and enable attentions */
1658 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1659 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1660
1661 /* Turn on RX list placement state machine */
1662 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1663
1664 /* Turn on RX list selector state machine. */
0ecb11d7 1665 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1666 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc 1667
4d38e186
SZ
1668 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1669 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1670 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1671 BGE_MACMODE_FRMHDR_DMA_ENB;
1672
1673 if (sc->bge_flags & BGE_FLAG_TBI)
1674 val |= BGE_PORTMODE_TBI;
1675 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1676 val |= BGE_PORTMODE_GMII;
1677 else
1678 val |= BGE_PORTMODE_MII;
1679
984263bc 1680 /* Turn on DMA, clear stats */
4d38e186 1681 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
984263bc
MD
1682
1683 /* Set misc. local control, enable interrupts on attentions */
1684 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1685
1686#ifdef notdef
1687 /* Assert GPIO pins for PHY reset */
1688 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1689 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1690 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1691 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1692#endif
1693
1694 /* Turn on DMA completion state machine */
0ecb11d7 1695 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1696 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
1697
1698 /* Turn on write DMA state machine */
0ecb11d7 1699 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
832863d2
SZ
1700 if (BGE_IS_5755_PLUS(sc)) {
1701 /* Enable host coalescing bug fix. */
1702 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1703 }
0ecb11d7 1704 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
671bd7ed
SZ
1705 DELAY(40);
1706
984263bc 1707 /* Turn on read DMA state machine */
671bd7ed 1708 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
f47afe1a
MN
1709 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1710 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1711 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1712 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1713 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1714 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
671bd7ed
SZ
1715 if (sc->bge_flags & BGE_FLAG_PCIE)
1716 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1717 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1718 DELAY(40);
984263bc
MD
1719
1720 /* Turn on RX data completion state machine */
1721 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1722
1723 /* Turn on RX BD initiator state machine */
1724 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1725
1726 /* Turn on RX data and RX BD initiator state machine */
1727 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1728
1729 /* Turn on Mbuf cluster free state machine */
0ecb11d7 1730 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1731 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
1732
1733 /* Turn on send BD completion state machine */
1734 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1735
1736 /* Turn on send data completion state machine */
f47afe1a
MN
1737 val = BGE_SDCMODE_ENABLE;
1738 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1739 val |= BGE_SDCMODE_CDELAY;
1740 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
984263bc
MD
1741
1742 /* Turn on send data initiator state machine */
1743 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1744
1745 /* Turn on send BD initiator state machine */
1746 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1747
1748 /* Turn on send BD selector state machine */
1749 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1750
1751 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1752 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1753 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1754
1755 /* ack/clear link change events */
1756 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
1757 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1758 BGE_MACSTAT_LINK_CHANGED);
20c9a969 1759 CSR_WRITE_4(sc, BGE_MI_STS, 0);
984263bc
MD
1760
1761 /* Enable PHY auto polling (for MII/GMII only) */
0ecb11d7 1762 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
1763 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1764 } else {
1765 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
db861466
SZ
1766 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1767 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
984263bc
MD
1768 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1769 BGE_EVTENB_MI_INTERRUPT);
db861466 1770 }
984263bc
MD
1771 }
1772
db861466
SZ
1773 /*
1774 * Clear any pending link state attention.
1775 * Otherwise some link state change events may be lost until attention
1776 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1777 * It's not necessary on newer BCM chips - perhaps enabling link
1778 * state change attentions implies clearing pending attention.
1779 */
1780 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1781 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1782 BGE_MACSTAT_LINK_CHANGED);
1783
984263bc
MD
1784 /* Enable link state change attentions. */
1785 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1786
1787 return(0);
1788}
1789
1790/*
1791 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1792 * against our list and return its name if we find a match. Note
1793 * that since the Broadcom controller contains VPD support, we
1794 * can get the device name string from the controller itself instead
1795 * of the compiled-in string. This is a little slow, but it guarantees
1796 * we'll always announce the right product name.
1797 */
1798static int
33c39a69 1799bge_probe(device_t dev)
984263bc 1800{
d265721a 1801 const struct bge_type *t;
33c39a69
JS
1802 uint16_t product, vendor;
1803
1804 product = pci_get_device(dev);
1805 vendor = pci_get_vendor(dev);
1806
1807 for (t = bge_devs; t->bge_name != NULL; t++) {
1808 if (vendor == t->bge_vid && product == t->bge_did)
1809 break;
1810 }
33c39a69
JS
1811 if (t->bge_name == NULL)
1812 return(ENXIO);
984263bc 1813
d265721a
SZ
1814 device_set_desc(dev, t->bge_name);
1815 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1816 struct bge_softc *sc = device_get_softc(dev);
0ecb11d7 1817 sc->bge_flags |= BGE_FLAG_NO_3LED;
d265721a 1818 }
33c39a69 1819 return(0);
984263bc
MD
1820}
1821
1822static int
33c39a69 1823bge_attach(device_t dev)
984263bc 1824{
984263bc
MD
1825 struct ifnet *ifp;
1826 struct bge_softc *sc;
33c39a69 1827 uint32_t hwcfg = 0;
c6fd6f3b 1828 int error = 0, rid;
0a8b5977 1829 uint8_t ether_addr[ETHER_ADDR_LEN];
984263bc 1830
984263bc 1831 sc = device_get_softc(dev);
984263bc 1832 sc->bge_dev = dev;
263489fb 1833 callout_init(&sc->bge_stat_timer);
16dca0df 1834 lwkt_serialize_init(&sc->bge_jslot_serializer);
984263bc 1835
591dfc77
SZ
1836#ifndef BURN_BRIDGES
1837 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1838 uint32_t irq, mem;
1839
1840 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1841 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1842
1843 device_printf(dev, "chip is in D%d power mode "
1844 "-- setting to D0\n", pci_get_powerstate(dev));
1845
1846 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1847
1848 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1849 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1850 }
1851#endif /* !BURN_BRIDGE */
1852
984263bc
MD
1853 /*
1854 * Map control/status registers.
1855 */
cc8ddf9e 1856 pci_enable_busmaster(dev);
984263bc
MD
1857
1858 rid = BGE_PCI_BAR0;
cc8ddf9e
JS
1859 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1860 RF_ACTIVE);
984263bc
MD
1861
1862 if (sc->bge_res == NULL) {
c6fd6f3b 1863 device_printf(dev, "couldn't map memory\n");
baf731bb 1864 return ENXIO;
984263bc
MD
1865 }
1866
1867 sc->bge_btag = rman_get_bustag(sc->bge_res);
1868 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
984263bc 1869
d265721a 1870 /* Save various chip information */
9a6ee7e2 1871 sc->bge_chipid =
f47afe1a
MN
1872 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1873 BGE_PCIMISCCTL_ASICREV_SHIFT;
1874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1875 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
9a6ee7e2
JS
1876 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1877 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1878
0ecb11d7
SZ
1879 /* Save chipset family. */
1880 switch (sc->bge_asicrev) {
f47afe1a
MN
1881 case BGE_ASICREV_BCM5755:
1882 case BGE_ASICREV_BCM5761:
1883 case BGE_ASICREV_BCM5784:
1884 case BGE_ASICREV_BCM5785:
1885 case BGE_ASICREV_BCM5787:
1886 case BGE_ASICREV_BCM57780:
1887 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1888 BGE_FLAG_5705_PLUS;
1889 break;
1890
0ecb11d7
SZ
1891 case BGE_ASICREV_BCM5700:
1892 case BGE_ASICREV_BCM5701:
1893 case BGE_ASICREV_BCM5703:
1894 case BGE_ASICREV_BCM5704:
1895 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1896 break;
1897
1898 case BGE_ASICREV_BCM5714_A0:
1899 case BGE_ASICREV_BCM5780:
1900 case BGE_ASICREV_BCM5714:
1901 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1902 /* Fall through */
1903
1904 case BGE_ASICREV_BCM5750:
1905 case BGE_ASICREV_BCM5752:
591dfc77 1906 case BGE_ASICREV_BCM5906:
0ecb11d7
SZ
1907 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1908 /* Fall through */
1909
1910 case BGE_ASICREV_BCM5705:
1911 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1912 break;
1913 }
9a6ee7e2 1914
591dfc77
SZ
1915 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1916 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1917
9a6ee7e2 1918 /*
0ecb11d7 1919 * Set various quirk flags.
9a6ee7e2 1920 */
9a6ee7e2 1921
0ecb11d7
SZ
1922 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1923 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1924 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1925 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1926 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1927 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1928 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1929
1930 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1931 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1932 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1933
1934 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1935 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1936 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1937
1938 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1939 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1940
2d79280f 1941 if (BGE_IS_5705_PLUS(sc)) {
0ecb11d7 1942 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
f47afe1a
MN
1943 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1944 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
0ecb11d7 1945 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2d79280f
SZ
1946 uint32_t product = pci_get_device(dev);
1947
1948 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1949 product != PCI_PRODUCT_BROADCOM_BCM5756)
1950 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1951 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1952 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
0ecb11d7
SZ
1953 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1954 sc->bge_flags |= BGE_FLAG_BER_BUG;
9a6ee7e2
JS
1955 }
1956 }
1957
0ecb11d7
SZ
1958 /* Allocate interrupt */
1959 rid = 0;
1960
1961 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1962 RF_SHAREABLE | RF_ACTIVE);
1963
1964 if (sc->bge_irq == NULL) {
1965 device_printf(dev, "couldn't map interrupt\n");
1966 error = ENXIO;
1967 goto fail;
1968 }
1969
1970 /*
1971 * Check if this is a PCI-X or PCI Express device.
1972 */
1973 if (BGE_IS_5705_PLUS(sc)) {
32159cc2 1974 if (pci_is_pcie(dev)) {
0ecb11d7 1975 sc->bge_flags |= BGE_FLAG_PCIE;
01c9014b 1976 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
671bd7ed 1977 }
0ecb11d7
SZ
1978 } else {
1979 /*
1980 * Check if the device is in PCI-X Mode.
1981 * (This bit is not valid on PCI Express controllers.)
1982 */
1983 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
ab8c1124 1984 BGE_PCISTATE_PCI_BUSMODE) == 0) {
0ecb11d7 1985 sc->bge_flags |= BGE_FLAG_PCIX;
ab8c1124
SZ
1986 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
1987 }
0ecb11d7
SZ
1988 }
1989
d265721a
SZ
1990 device_printf(dev, "CHIP ID 0x%08x; "
1991 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1992 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1993 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1994 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1995 "PCI-E" : "PCI"));
b197e64e 1996
d723dbb5
SZ
1997 /*
1998 * All controllers that are not 5755 or higher have 4GB
1999 * boundary DMA bug.
2000 * Whenever an address crosses a multiple of the 4GB boundary
2001 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2002 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2003 * state machine will lockup and cause the device to hang.
2004 */
2005 if (BGE_IS_5755_PLUS(sc) == 0)
2006 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
2007
2008 /*
2009 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2010 * not actually a MAC controller bug but an issue with the embedded
2011 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2012 */
2013 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2014 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2015
c6fd6f3b
JS
2016 ifp = &sc->arpcom.ac_if;
2017 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
2018
2019 /* Try to reset the chip. */
2020 bge_reset(sc);
2021
2022 if (bge_chipinit(sc)) {
c6fd6f3b 2023 device_printf(dev, "chip initialization failed\n");
984263bc
MD
2024 error = ENXIO;
2025 goto fail;
2026 }
2027
2028 /*
591dfc77 2029 * Get station address
984263bc 2030 */
591dfc77
SZ
2031 error = bge_get_eaddr(sc, ether_addr);
2032 if (error) {
c6fd6f3b 2033 device_printf(dev, "failed to read station address\n");
984263bc
MD
2034 goto fail;
2035 }
2036
20c9a969 2037 /* 5705/5750 limits RX return ring to 512 entries. */
0ecb11d7 2038 if (BGE_IS_5705_PLUS(sc))
20c9a969
SZ
2039 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2040 else
2041 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
984263bc 2042
20c9a969
SZ
2043 error = bge_dma_alloc(sc);
2044 if (error)
984263bc 2045 goto fail;
984263bc
MD
2046
2047 /* Set default tuneable values. */
2048 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
055d06f0
SZ
2049 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2050 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2051 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2052 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
984263bc
MD
2053
2054 /* Set up ifnet structure */
984263bc 2055 ifp->if_softc = sc;
984263bc
MD
2056 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2057 ifp->if_ioctl = bge_ioctl;
984263bc 2058 ifp->if_start = bge_start;
315fe0ee
MD
2059#ifdef DEVICE_POLLING
2060 ifp->if_poll = bge_poll;
2061#endif
984263bc
MD
2062 ifp->if_watchdog = bge_watchdog;
2063 ifp->if_init = bge_init;
2064 ifp->if_mtu = ETHERMTU;
cb623c48 2065 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
936ff230
JS
2066 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2067 ifq_set_ready(&ifp->if_snd);
cb623c48
SZ
2068
2069 /*
2070 * 5700 B0 chips do not support checksumming correctly due
2071 * to hardware bugs.
2072 */
2073 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2074 ifp->if_capabilities |= IFCAP_HWCSUM;
2075 ifp->if_hwassist = BGE_CSUM_FEATURES;
2076 }
984263bc
MD
2077 ifp->if_capenable = ifp->if_capabilities;
2078
984263bc
MD
2079 /*
2080 * Figure out what sort of media we have by checking the
2081 * hardware config word in the first 32k of NIC internal memory,
2082 * or fall back to examining the EEPROM if necessary.
2083 * Note: on some BCM5700 cards, this value appears to be unset.
2084 * If that's the case, we have to rely on identifying the NIC
2085 * by its PCI subsystem ID, as we do below for the SysKonnect
2086 * SK-9D41.
2087 */
2088 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2089 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2090 else {
7b47d9c2
SZ
2091 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2092 sizeof(hwcfg))) {
2093 device_printf(dev, "failed to read EEPROM\n");
2094 error = ENXIO;
2095 goto fail;
2096 }
984263bc
MD
2097 hwcfg = ntohl(hwcfg);
2098 }
2099
984263bc 2100 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
4d38e186
SZ
2101 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2102 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2103 if (BGE_IS_5714_FAMILY(sc))
2104 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2105 else
2106 sc->bge_flags |= BGE_FLAG_TBI;
2107 }
984263bc 2108
0ecb11d7 2109 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
2110 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2111 bge_ifmedia_upd, bge_ifmedia_sts);
2112 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2113 ifmedia_add(&sc->bge_ifmedia,
2114 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2115 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2116 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
70059b3c 2117 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
984263bc
MD
2118 } else {
2119 /*
2120 * Do transceiver setup.
2121 */
2122 if (mii_phy_probe(dev, &sc->bge_miibus,
2123 bge_ifmedia_upd, bge_ifmedia_sts)) {
c6fd6f3b 2124 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
2125 error = ENXIO;
2126 goto fail;
2127 }
2128 }
2129
2130 /*
2131 * When using the BCM5701 in PCI-X mode, data corruption has
2132 * been observed in the first few bytes of some received packets.
2133 * Aligning the packet buffer in memory eliminates the corruption.
2134 * Unfortunately, this misaligns the packet payloads. On platforms
2135 * which do not support unaligned accesses, we will realign the
2136 * payloads by copying the received packets.
2137 */
0ecb11d7
SZ
2138 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2139 (sc->bge_flags & BGE_FLAG_PCIX))
2140 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
984263bc 2141
db861466
SZ
2142 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2143 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2144 sc->bge_link_upd = bge_bcm5700_link_upd;
2145 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
0ecb11d7 2146 } else if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2147 sc->bge_link_upd = bge_tbi_link_upd;
2148 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2149 } else {
2150 sc->bge_link_upd = bge_copper_link_upd;
2151 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2152 }
2153
984263bc 2154 /*
055d06f0
SZ
2155 * Create sysctl nodes.
2156 */
2157 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2158 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2159 SYSCTL_STATIC_CHILDREN(_hw),
2160 OID_AUTO,
2161 device_get_nameunit(dev),
2162 CTLFLAG_RD, 0, "");
2163 if (sc->bge_sysctl_tree == NULL) {
2164 device_printf(dev, "can't add sysctl node\n");
2165 error = ENXIO;
2166 goto fail;
2167 }
2168
2169 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2170 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2171 OID_AUTO, "rx_coal_ticks",
2172 CTLTYPE_INT | CTLFLAG_RW,
2173 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2174 "Receive coalescing ticks (usec).");
2175 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2176 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2177 OID_AUTO, "tx_coal_ticks",
2178 CTLTYPE_INT | CTLFLAG_RW,
2179 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2180 "Transmit coalescing ticks (usec).");
2181 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2182 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2183 OID_AUTO, "rx_max_coal_bds",
2184 CTLTYPE_INT | CTLFLAG_RW,
2185 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2186 "Receive max coalesced BD count.");
2187 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2188 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2189 OID_AUTO, "tx_max_coal_bds",
2190 CTLTYPE_INT | CTLFLAG_RW,
2191 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2192 "Transmit max coalesced BD count.");
2193
c728ae98
SZ
2194 if (sc->bge_flags & BGE_FLAG_PCIE) {
2195 /*
2196 * A common design characteristic for many Broadcom
2197 * client controllers is that they only support a
2198 * single outstanding DMA read operation on the PCIe
2199 * bus. This means that it will take twice as long to
2200 * fetch a TX frame that is split into header and
2201 * payload buffers as it does to fetch a single,
2202 * contiguous TX frame (2 reads vs. 1 read). For these
2203 * controllers, coalescing buffers to reduce the number
2204 * of memory reads is effective way to get maximum
2205 * performance(about 940Mbps). Without collapsing TX
2206 * buffers the maximum TCP bulk transfer performance
2207 * is about 850Mbps. However forcing coalescing mbufs
2208 * consumes a lot of CPU cycles, so leave it off by
2209 * default.
2210 */
2211 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2212 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2213 OID_AUTO, "force_defrag", CTLFLAG_RW,
2214 &sc->bge_force_defrag, 0,
2215 "Force defragment on TX path");
2216 }
2217
055d06f0 2218 /*
984263bc
MD
2219 * Call MI attach routine.
2220 */
78195a76 2221 ether_ifattach(ifp, ether_addr, NULL);
984263bc 2222
95893fe4 2223 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
78195a76
MD
2224 bge_intr, sc, &sc->bge_intrhand,
2225 ifp->if_serializer);
9a717c15
JS
2226 if (error) {
2227 ether_ifdetach(ifp);
2228 device_printf(dev, "couldn't set up irq\n");
2229 goto fail;
2230 }
9db4b353 2231
28e81a28 2232 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
9db4b353
SZ
2233 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2234
9a717c15 2235 return(0);
984263bc 2236fail:
9a717c15 2237 bge_detach(dev);
984263bc
MD
2238 return(error);
2239}
2240
2241static int
33c39a69 2242bge_detach(device_t dev)
984263bc 2243{
9a717c15 2244 struct bge_softc *sc = device_get_softc(dev);
984263bc 2245
9a717c15 2246 if (device_is_attached(dev)) {
baf731bb
SZ
2247 struct ifnet *ifp = &sc->arpcom.ac_if;
2248
cdf89432 2249 lwkt_serialize_enter(ifp->if_serializer);
9a717c15
JS
2250 bge_stop(sc);
2251 bge_reset(sc);
cdf89432
SZ
2252 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2253 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2254
cdf89432
SZ
2255 ether_ifdetach(ifp);
2256 }
baf731bb 2257
0ecb11d7 2258 if (sc->bge_flags & BGE_FLAG_TBI)
984263bc 2259 ifmedia_removeall(&sc->bge_ifmedia);
cbf32d7e 2260 if (sc->bge_miibus)
984263bc 2261 device_delete_child(dev, sc->bge_miibus);
9a717c15 2262 bus_generic_detach(dev);
984263bc 2263
984263bc
MD
2264 if (sc->bge_irq != NULL)
2265 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2266
2267 if (sc->bge_res != NULL)
2268 bus_release_resource(dev, SYS_RES_MEMORY,
2269 BGE_PCI_BAR0, sc->bge_res);
baf731bb 2270
055d06f0
SZ
2271 if (sc->bge_sysctl_tree != NULL)
2272 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2273
baf731bb
SZ
2274 bge_dma_free(sc);
2275
2276 return 0;
984263bc
MD
2277}
2278
2279static void
33c39a69 2280bge_reset(struct bge_softc *sc)
984263bc
MD
2281{
2282 device_t dev;
9a6ee7e2 2283 uint32_t cachesize, command, pcistate, reset;
0ecb11d7 2284 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
984263bc
MD
2285 int i, val = 0;
2286
2287 dev = sc->bge_dev;
2288
591dfc77
SZ
2289 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2290 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
0ecb11d7
SZ
2291 if (sc->bge_flags & BGE_FLAG_PCIE)
2292 write_op = bge_writemem_direct;
2293 else
2294 write_op = bge_writemem_ind;
2295 } else {
2296 write_op = bge_writereg_ind;
2297 }
2298
984263bc
MD
2299 /* Save some important PCI state. */
2300 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2301 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2302 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2303
2304 pci_write_config(dev, BGE_PCI_MISC_CTL,
2305 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 2306 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc 2307
0ecb11d7
SZ
2308 /* Disable fastboot on controllers that support it. */
2309 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
832863d2 2310 BGE_IS_5755_PLUS(sc)) {
0ecb11d7
SZ
2311 if (bootverbose)
2312 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2313 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2314 }
2315
2316 /*
2317 * Write the magic number to SRAM at offset 0xB50.
2318 * When firmware finishes its initialization it will
2319 * write ~BGE_MAGIC_NUMBER to the same location.
2320 */
2321 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2322
9a6ee7e2
JS
2323 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2324
2325 /* XXX: Broadcom Linux driver. */
0ecb11d7 2326 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2327 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2328 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2329 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2330 /* Prevent PCIE link training during global reset */
2331 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2332 reset |= (1<<29);
2333 }
2334 }
2335
0ecb11d7
SZ
2336 /*
2337 * Set GPHY Power Down Override to leave GPHY
2338 * powered up in D0 uninitialized.
2339 */
2340 if (BGE_IS_5705_PLUS(sc))
2330cf73 2341 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
0ecb11d7 2342
984263bc 2343 /* Issue global reset */
0ecb11d7 2344 write_op(sc, BGE_MISC_CFG, reset);
984263bc 2345
591dfc77
SZ
2346 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2347 uint32_t status, ctrl;
2348
2349 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2350 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2351 status | BGE_VCPU_STATUS_DRV_RESET);
2352 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2353 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2354 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2355 }
2356
984263bc
MD
2357 DELAY(1000);
2358
9a6ee7e2 2359 /* XXX: Broadcom Linux driver. */
0ecb11d7 2360 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2361 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2362 uint32_t v;
2363
2364 DELAY(500000); /* wait for link training to complete */
2365 v = pci_read_config(dev, 0xc4, 4);
2366 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2367 }
0ecb11d7
SZ
2368 /*
2369 * Set PCIE max payload size to 128 bytes and
2370 * clear error status.
2371 */
9a6ee7e2
JS
2372 pci_write_config(dev, 0xd8, 0xf5000, 4);
2373 }
2374
984263bc
MD
2375 /* Reset some of the PCI state that got zapped by reset */
2376 pci_write_config(dev, BGE_PCI_MISC_CTL,
2377 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 2378 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc
MD
2379 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2380 pci_write_config(dev, BGE_PCI_CMD, command, 4);
0ecb11d7 2381 write_op(sc, BGE_MISC_CFG, (65 << 1));
984263bc 2382
ab8c1124
SZ
2383 /*
2384 * Disable PCI-X relaxed ordering to ensure status block update
2385 * comes first then packet buffer DMA. Otherwise driver may
2386 * read stale status block.
2387 */
2388 if (sc->bge_flags & BGE_FLAG_PCIX) {
2389 uint16_t devctl;
2390
2391 devctl = pci_read_config(dev,
2392 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2393 devctl &= ~PCIXM_COMMAND_ERO;
2394 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2395 devctl &= ~PCIXM_COMMAND_MAX_READ;
2396 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2397 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2398 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2399 PCIXM_COMMAND_MAX_READ);
2400 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2401 }
2402 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2403 devctl, 2);
2404 }
2405
a313b56f 2406 /* Enable memory arbiter. */
0ecb11d7
SZ
2407 if (BGE_IS_5714_FAMILY(sc)) {
2408 uint32_t val;
2409
2410 val = CSR_READ_4(sc, BGE_MARB_MODE);
2411 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2412 } else {
a313b56f 2413 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
0ecb11d7 2414 }
a313b56f 2415
591dfc77
SZ
2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2417 for (i = 0; i < BGE_TIMEOUT; i++) {
2418 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2419 if (val & BGE_VCPU_STATUS_INIT_DONE)
2420 break;
2421 DELAY(100);
2422 }
2423 if (i == BGE_TIMEOUT) {
2424 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2425 return;
2426 }
2427 } else {
2428 /*
2429 * Poll until we see the 1's complement of the magic number.
2430 * This indicates that the firmware initialization
2431 * is complete.
2432 */
d880f7b3 2433 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
591dfc77
SZ
2434 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2435 if (val == ~BGE_MAGIC_NUMBER)
2436 break;
2437 DELAY(10);
2438 }
d880f7b3 2439 if (i == BGE_FIRMWARE_TIMEOUT) {
591dfc77
SZ
2440 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2441 "timed out, found 0x%08x\n", val);
2442 return;
2443 }
984263bc
MD
2444 }
2445
2446 /*
2447 * XXX Wait for the value of the PCISTATE register to
2448 * return to its original pre-reset state. This is a
2449 * fairly good indicator of reset completion. If we don't
2450 * wait for the reset to fully complete, trying to read
2451 * from the device's non-PCI registers may yield garbage
2452 * results.
2453 */
2454 for (i = 0; i < BGE_TIMEOUT; i++) {
2455 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2456 break;
2457 DELAY(10);
2458 }
2459
984263bc 2460 /* Fix up byte swapping */
20c9a969 2461 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
984263bc
MD
2462 BGE_MODECTL_BYTESWAP_DATA);
2463
2464 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2465
70059b3c
JS
2466 /*
2467 * The 5704 in TBI mode apparently needs some special
2468 * adjustment to insure the SERDES drive level is set
2469 * to 1.2V.
2470 */
0ecb11d7
SZ
2471 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2472 (sc->bge_flags & BGE_FLAG_TBI)) {
70059b3c
JS
2473 uint32_t serdescfg;
2474
2475 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2476 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2477 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2478 }
2479
9a6ee7e2 2480 /* XXX: Broadcom Linux driver. */
0ecb11d7 2481 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
3dfc12af
SZ
2482 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2483 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
9a6ee7e2 2484 uint32_t v;
984263bc 2485
3dfc12af 2486 /* Enable Data FIFO protection. */
9a6ee7e2
JS
2487 v = CSR_READ_4(sc, 0x7c00);
2488 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2489 }
2490
2491 DELAY(10000);
984263bc
MD
2492}
2493
2494/*
2495 * Frame reception handling. This is called if there's a frame
2496 * on the receive return list.
2497 *
2498 * Note: we have to be able to handle two possibilities here:
2499 * 1) the frame is from the jumbo recieve ring
2500 * 2) the frame is from the standard receive ring
2501 */
2502
2503static void
33c39a69 2504bge_rxeof(struct bge_softc *sc)
984263bc
MD
2505{
2506 struct ifnet *ifp;
2507 int stdcnt = 0, jumbocnt = 0;
2508
449e06cc 2509 if (sc->bge_rx_saved_considx ==
20c9a969 2510 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
449e06cc
SZ
2511 return;
2512
984263bc
MD
2513 ifp = &sc->arpcom.ac_if;
2514
20c9a969
SZ
2515 while (sc->bge_rx_saved_considx !=
2516 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
984263bc 2517 struct bge_rx_bd *cur_rx;
33c39a69 2518 uint32_t rxidx;
984263bc 2519 struct mbuf *m = NULL;
33c39a69 2520 uint16_t vlan_tag = 0;
984263bc
MD
2521 int have_tag = 0;
2522
2523 cur_rx =
20c9a969 2524 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
984263bc
MD
2525
2526 rxidx = cur_rx->bge_idx;
7e40b8c5 2527 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
6b880771 2528 logif(rx_pkt);
984263bc
MD
2529
2530 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2531 have_tag = 1;
2532 vlan_tag = cur_rx->bge_vlan_tag;
2533 }
2534
2535 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2536 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
984263bc 2537 jumbocnt++;
1436f9a0
SZ
2538
2539 if (rxidx != sc->bge_jumbo) {
2540 ifp->if_ierrors++;
2541 if_printf(ifp, "sw jumbo index(%d) "
2542 "and hw jumbo index(%d) mismatch, drop!\n",
2543 sc->bge_jumbo, rxidx);
2544 bge_setup_rxdesc_jumbo(sc, rxidx);
2545 continue;
2546 }
2547
2548 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
984263bc
MD
2549 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2550 ifp->if_ierrors++;
1436f9a0 2551 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2552 continue;
2553 }
1436f9a0 2554 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
984263bc 2555 ifp->if_ierrors++;
1436f9a0 2556 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2557 continue;
2558 }
2559 } else {
2560 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
984263bc 2561 stdcnt++;
1436f9a0
SZ
2562
2563 if (rxidx != sc->bge_std) {
2564 ifp->if_ierrors++;
2565 if_printf(ifp, "sw std index(%d) "
2566 "and hw std index(%d) mismatch, drop!\n",
2567 sc->bge_std, rxidx);
2568 bge_setup_rxdesc_std(sc, rxidx);
2569 continue;
2570 }
2571
2572 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
984263bc
MD
2573 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2574 ifp->if_ierrors++;
1436f9a0 2575 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2576 continue;
2577 }
1436f9a0 2578 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
984263bc 2579 ifp->if_ierrors++;
1436f9a0 2580 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2581 continue;
2582 }
2583 }
2584
2585 ifp->if_ipackets++;
061def6f 2586#if !defined(__i386__) && !defined(__x86_64__)
984263bc 2587 /*
061def6f 2588 * The x86 allows unaligned accesses, but for other
984263bc
MD
2589 * platforms we must make sure the payload is aligned.
2590 */
0ecb11d7 2591 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
984263bc
MD
2592 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2593 cur_rx->bge_len);
2594 m->m_data += ETHER_ALIGN;
2595 }
2596#endif
160185fa 2597 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
984263bc
MD
2598 m->m_pkthdr.rcvif = ifp;
2599
cb623c48
SZ
2600 if (ifp->if_capenable & IFCAP_RXCSUM) {
2601 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2602 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2603 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2604 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2605 }
17240569 2606 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
cb623c48 2607 m->m_pkthdr.len >= BGE_MIN_FRAME) {
984263bc 2608 m->m_pkthdr.csum_data =
17240569 2609 cur_rx->bge_tcp_udp_csum;
bf29e666
SZ
2610 m->m_pkthdr.csum_flags |=
2611 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
984263bc
MD
2612 }
2613 }
984263bc
MD
2614
2615 /*
2616 * If we received a packet with a vlan tag, pass it
2617 * to vlan_input() instead of ether_input().
2618 */
2619 if (have_tag) {
e6b5847c
SZ
2620 m->m_flags |= M_VLANTAG;
2621 m->m_pkthdr.ether_vlantag = vlan_tag;
984263bc 2622 have_tag = vlan_tag = 0;
984263bc 2623 }
eda7db08 2624 ifp->if_input(ifp, m);
984263bc
MD
2625 }
2626
591dfc77 2627 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
984263bc 2628 if (stdcnt)
591dfc77 2629 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc 2630 if (jumbocnt)
591dfc77 2631 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
2632}
2633
2634static void
33c39a69 2635bge_txeof(struct bge_softc *sc)
984263bc
MD
2636{
2637 struct bge_tx_bd *cur_tx = NULL;
2638 struct ifnet *ifp;
2639
449e06cc 2640 if (sc->bge_tx_saved_considx ==
20c9a969 2641 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
449e06cc
SZ
2642 return;
2643
984263bc
MD
2644 ifp = &sc->arpcom.ac_if;
2645
2646 /*
2647 * Go through our tx ring and free mbufs for those
2648 * frames that have been sent.
2649 */
2650 while (sc->bge_tx_saved_considx !=
20c9a969
SZ
2651 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2652 uint32_t idx = 0;
984263bc
MD
2653
2654 idx = sc->bge_tx_saved_considx;
20c9a969 2655 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
984263bc
MD
2656 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2657 ifp->if_opackets++;
2658 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
ddca511d 2659 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 2660 sc->bge_cdata.bge_tx_dmamap[idx]);
984263bc
MD
2661 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2662 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2663 }
2664 sc->bge_txcnt--;
2665 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
6b880771 2666 logif(tx_pkt);
984263bc
MD
2667 }
2668
20c9a969
SZ
2669 if (cur_tx != NULL &&
2670 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2671 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
984263bc 2672 ifp->if_flags &= ~IFF_OACTIVE;
20c9a969 2673
142ca760
SZ
2674 if (sc->bge_txcnt == 0)
2675 ifp->if_timer = 0;
2676
20c9a969 2677 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2678 if_devstart(ifp);
984263bc
MD
2679}
2680
315fe0ee
MD
2681#ifdef DEVICE_POLLING
2682
2683static void
2684bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2685{
2686 struct bge_softc *sc = ifp->if_softc;
2687 uint32_t status;
2688
2689 switch(cmd) {
2690 case POLL_REGISTER:
ba39cc82 2691 bge_disable_intr(sc);
315fe0ee
MD
2692 break;
2693 case POLL_DEREGISTER:
ba39cc82 2694 bge_enable_intr(sc);
315fe0ee
MD
2695 break;
2696 case POLL_AND_CHECK_STATUS:
315fe0ee
MD
2697 /*
2698 * Process link state changes.
2699 */
2700 status = CSR_READ_4(sc, BGE_MAC_STS);
2701 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2702 sc->bge_link_evt = 0;
2703 sc->bge_link_upd(sc, status);
2704 }
2705 /* fall through */
2706 case POLL_ONLY:
2707 if (ifp->if_flags & IFF_RUNNING) {
2708 bge_rxeof(sc);
2709 bge_txeof(sc);
2710 }
2711 break;
2712 }
2713}
2714
2715#endif
2716
984263bc 2717static void
33c39a69 2718bge_intr(void *xsc)
984263bc 2719{
bf522c7f 2720 struct bge_softc *sc = xsc;
33c39a69 2721 struct ifnet *ifp = &sc->arpcom.ac_if;
6b880771
SZ
2722 uint32_t status;
2723
2724 logif(intr);
0029ccf6 2725
142ca760
SZ
2726 /*
2727 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2728 * disable interrupts by writing nonzero like we used to, since with
2729 * our current organization this just gives complications and
2730 * pessimizations for re-enabling interrupts. We used to have races
2731 * instead of the necessary complications. Disabling interrupts
2732 * would just reduce the chance of a status update while we are
2733 * running (by switching to the interrupt-mode coalescence
2734 * parameters), but this chance is already very low so it is more
2735 * efficient to get another interrupt than prevent it.
2736 *
2737 * We do the ack first to ensure another interrupt if there is a
2738 * status update after the ack. We don't check for the status
2739 * changing later because it is more efficient to get another
2740 * interrupt than prevent it, not quite as above (not checking is
2741 * a smaller optimization than not toggling the interrupt enable,
2742 * since checking doesn't involve PCI accesses and toggling require
2743 * the status check). So toggling would probably be a pessimization
2744 * even with MSI. It would only be needed for using a task queue.
2745 */
591dfc77 2746 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
142ca760 2747
984263bc
MD
2748 /*
2749 * Process link state changes.
984263bc 2750 */
db861466
SZ
2751 status = CSR_READ_4(sc, BGE_MAC_STS);
2752 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2753 sc->bge_link_evt = 0;
2754 sc->bge_link_upd(sc, status);
984263bc
MD
2755 }
2756
2757 if (ifp->if_flags & IFF_RUNNING) {
2758 /* Check RX return ring producer/consumer */
2759 bge_rxeof(sc);
2760
2761 /* Check TX ring producer/consumer */
2762 bge_txeof(sc);
2763 }
055d06f0
SZ
2764
2765 if (sc->bge_coal_chg)
2766 bge_coal_change(sc);
984263bc
MD
2767}
2768
2769static void
33c39a69 2770bge_tick(void *xsc)
984263bc 2771{
33c39a69
JS
2772 struct bge_softc *sc = xsc;
2773 struct ifnet *ifp = &sc->arpcom.ac_if;
78195a76
MD
2774
2775 lwkt_serialize_enter(ifp->if_serializer);
984263bc 2776
0ecb11d7 2777 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
2778 bge_stats_update_regs(sc);
2779 else
2780 bge_stats_update(sc);
9a717c15 2781
0ecb11d7 2782 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2783 /*
2784 * Since in TBI mode auto-polling can't be used we should poll
2785 * link status manually. Here we register pending link event
2786 * and trigger interrupt.
2787 */
2788 sc->bge_link_evt++;
2789 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3f82ed83 2790 } else if (!sc->bge_link) {
db861466 2791 mii_tick(device_get_softc(sc->bge_miibus));
984263bc
MD
2792 }
2793
db861466
SZ
2794 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2795
2796 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2797}
2798
2799static void
33c39a69 2800bge_stats_update_regs(struct bge_softc *sc)
7e40b8c5 2801{
33c39a69 2802 struct ifnet *ifp = &sc->arpcom.ac_if;
7e40b8c5 2803 struct bge_mac_stats_regs stats;
33c39a69 2804 uint32_t *s;
7e40b8c5
HP
2805 int i;
2806
33c39a69 2807 s = (uint32_t *)&stats;
7e40b8c5
HP
2808 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2809 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2810 s++;
2811 }
2812
2813 ifp->if_collisions +=
2814 (stats.dot3StatsSingleCollisionFrames +
2815 stats.dot3StatsMultipleCollisionFrames +
2816 stats.dot3StatsExcessiveCollisions +
2817 stats.dot3StatsLateCollisions) -
2818 ifp->if_collisions;
7e40b8c5
HP
2819}
2820
2821static void
33c39a69 2822bge_stats_update(struct bge_softc *sc)
984263bc 2823{
33c39a69 2824 struct ifnet *ifp = &sc->arpcom.ac_if;
20c9a969
SZ
2825 bus_size_t stats;
2826
2827 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
984263bc 2828
20c9a969
SZ
2829#define READ_STAT(sc, stats, stat) \
2830 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
984263bc
MD
2831
2832 ifp->if_collisions +=
20c9a969
SZ
2833 (READ_STAT(sc, stats,
2834 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2835 READ_STAT(sc, stats,
2836 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2837 READ_STAT(sc, stats,
2838 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2839 READ_STAT(sc, stats,
2840 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
984263bc
MD
2841 ifp->if_collisions;
2842
20c9a969
SZ
2843#undef READ_STAT
2844
984263bc
MD
2845#ifdef notdef
2846 ifp->if_collisions +=
2847 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2848 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2849 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2850 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2851 ifp->if_collisions;
2852#endif
984263bc
MD
2853}
2854
2855/*
2856 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2857 * pointers to descriptors.
2858 */
2859static int
4a607ed6 2860bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
984263bc 2861{
20c9a969 2862 struct bge_tx_bd *d = NULL;
33c39a69 2863 uint16_t csum_flags = 0;
20c9a969
SZ
2864 bus_dma_segment_t segs[BGE_NSEG_NEW];
2865 bus_dmamap_t map;
2de621e9 2866 int error, maxsegs, nsegs, idx, i;
4a607ed6 2867 struct mbuf *m_head = *m_head0;
984263bc 2868
984263bc
MD
2869 if (m_head->m_pkthdr.csum_flags) {
2870 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2871 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2872 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2873 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2874 if (m_head->m_flags & M_LASTFRAG)
2875 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2876 else if (m_head->m_flags & M_FRAG)
2877 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2878 }
20c9a969
SZ
2879
2880 idx = *txidx;
2881 map = sc->bge_cdata.bge_tx_dmamap[idx];
2882
2883 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2884 KASSERT(maxsegs >= BGE_NSEG_SPARE,
ed20d0e3 2885 ("not enough segments %d", maxsegs));
20c9a969
SZ
2886
2887 if (maxsegs > BGE_NSEG_NEW)
2888 maxsegs = BGE_NSEG_NEW;
2889
cb623c48
SZ
2890 /*
2891 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2892 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2893 * but when such padded frames employ the bge IP/TCP checksum
2894 * offload, the hardware checksum assist gives incorrect results
2895 * (possibly from incorporating its own padding into the UDP/TCP
2896 * checksum; who knows). If we pad such runts with zeros, the
2679514c 2897 * onboard checksum comes out correct.
cb623c48
SZ
2898 */
2899 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2900 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
cf12ba3c 2901 error = m_devpad(m_head, BGE_MIN_FRAME);
2679514c
SZ
2902 if (error)
2903 goto back;
cb623c48 2904 }
2679514c 2905
c728ae98
SZ
2906 if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
2907 m_head->m_next != NULL) {
2908 struct mbuf *m_new;
2909
2910 /*
2911 * Forcefully defragment mbuf chain to overcome hardware
2912 * limitation which only support a single outstanding
2913 * DMA read operation. If it fails, keep moving on using
2914 * the original mbuf chain.
2915 */
2916 m_new = m_defrag(m_head, MB_DONTWAIT);
2917 if (m_new != NULL)
2918 *m_head0 = m_head = m_new;
2919 }
2920
2de621e9
SZ
2921 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2922 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2923 if (error)
20c9a969 2924 goto back;
984263bc 2925
2de621e9 2926 m_head = *m_head0;
ddca511d 2927 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
984263bc 2928
20c9a969
SZ
2929 for (i = 0; ; i++) {
2930 d = &sc->bge_ldata.bge_tx_ring[idx];
984263bc 2931
2de621e9
SZ
2932 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2933 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
20c9a969
SZ
2934 d->bge_len = segs[i].ds_len;
2935 d->bge_flags = csum_flags;
984263bc 2936
2de621e9 2937 if (i == nsegs - 1)
20c9a969
SZ
2938 break;
2939 BGE_INC(idx, BGE_TX_RING_CNT);
2940 }
2941 /* Mark the last segment as end of packet... */
2942 d->bge_flags |= BGE_TXBDFLAG_END;
984263bc 2943
20c9a969
SZ
2944 /* Set vlan tag to the first segment of the packet. */
2945 d = &sc->bge_ldata.bge_tx_ring[*txidx];
83790f85 2946 if (m_head->m_flags & M_VLANTAG) {
20c9a969 2947 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
83790f85 2948 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
20c9a969
SZ
2949 } else {
2950 d->bge_vlan_tag = 0;
2951 }
2952
2953 /*
2954 * Insure that the map for this transmission is placed at
2955 * the array index of the last descriptor in this chain.
2956 */
2957 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2958 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2959 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2de621e9 2960 sc->bge_txcnt += nsegs;
20c9a969
SZ
2961
2962 BGE_INC(idx, BGE_TX_RING_CNT);
2963 *txidx = idx;
2964back:
4a607ed6 2965 if (error) {
2de621e9 2966 m_freem(*m_head0);
4a607ed6
SZ
2967 *m_head0 = NULL;
2968 }
20c9a969 2969 return error;
984263bc
MD
2970}
2971
2972/*
2973 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2974 * to the mbuf data regions directly in the transmit descriptors.
2975 */
2976static void
33c39a69 2977bge_start(struct ifnet *ifp)
984263bc 2978{
20c9a969 2979 struct bge_softc *sc = ifp->if_softc;
984263bc 2980 struct mbuf *m_head = NULL;
20c9a969 2981 uint32_t prodidx;
2f54d1d2 2982 int need_trans;
984263bc 2983
d47d96f2 2984 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
984263bc
MD
2985 return;
2986
94db8384 2987 prodidx = sc->bge_tx_prodidx;
984263bc 2988
2f54d1d2 2989 need_trans = 0;
75544bcd 2990 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
9db4b353 2991 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
2992 if (m_head == NULL)
2993 break;
2994
2995 /*
2996 * XXX
cb623c48
SZ
2997 * The code inside the if() block is never reached since we
2998 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2999 * requests to checksum TCP/UDP in a fragmented packet.
3000 *
3001 * XXX
984263bc
MD
3002 * safety overkill. If this is a fragmented packet chain
3003 * with delayed TCP/UDP checksums, then only encapsulate
3004 * it if we have enough descriptors to handle the entire
3005 * chain at once.
3006 * (paranoia -- may not actually be needed)
3007 */
9db4b353
SZ
3008 if ((m_head->m_flags & M_FIRSTFRAG) &&
3009 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
984263bc 3010 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
9db4b353 3011 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
984263bc 3012 ifp->if_flags |= IFF_OACTIVE;
9db4b353 3013 ifq_prepend(&ifp->if_snd, m_head);
984263bc
MD
3014 break;
3015 }
3016 }
3017
3018 /*
20c9a969
SZ
3019 * Sanity check: avoid coming within BGE_NSEG_RSVD
3020 * descriptors of the end of the ring. Also make
3021 * sure there are BGE_NSEG_SPARE descriptors for
3022 * jumbo buffers' defragmentation.
3023 */
3024 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3025 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3026 ifp->if_flags |= IFF_OACTIVE;
9db4b353 3027 ifq_prepend(&ifp->if_snd, m_head);
20c9a969
SZ
3028 break;
3029 }
3030
3031 /*
984263bc
MD
3032 * Pack the data into the transmit ring. If we
3033 * don't have room, set the OACTIVE flag and wait
3034 * for the NIC to drain the ring.
3035 */
4a607ed6 3036 if (bge_encap(sc, &m_head, &prodidx)) {
984263bc 3037 ifp->if_flags |= IFF_OACTIVE;
2679514c 3038 ifp->if_oerrors++;
984263bc
MD
3039 break;
3040 }
2f54d1d2 3041 need_trans = 1;
984263bc 3042
b637f170 3043 ETHER_BPF_MTAP(ifp, m_head);
984263bc
MD
3044 }
3045
2f54d1d2
SZ
3046 if (!need_trans)
3047 return;
3048
984263bc 3049 /* Transmit */
591dfc77 3050 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
984263bc
MD
3051 /* 5700 b2 errata */
3052 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 3053 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
984263bc 3054
94db8384
SZ
3055 sc->bge_tx_prodidx = prodidx;
3056
984263bc
MD
3057 /*
3058 * Set a timeout in case the chip goes out to lunch.
3059 */
3060 ifp->if_timer = 5;
984263bc
MD
3061}
3062
3063static void
33c39a69 3064bge_init(void *xsc)
984263bc
MD
3065{
3066 struct bge_softc *sc = xsc;
33c39a69
JS
3067 struct ifnet *ifp = &sc->arpcom.ac_if;
3068 uint16_t *m;
984263bc 3069
aa65409c
SZ
3070 ASSERT_SERIALIZED(ifp->if_serializer);
3071
3072 if (ifp->if_flags & IFF_RUNNING)
984263bc 3073 return;
984263bc
MD
3074
3075 /* Cancel pending I/O and flush buffers. */
3076 bge_stop(sc);
3077 bge_reset(sc);
3078 bge_chipinit(sc);
3079
3080 /*
3081 * Init the various state machines, ring
3082 * control blocks and firmware.
3083 */
3084 if (bge_blockinit(sc)) {
c6fd6f3b 3085 if_printf(ifp, "initialization failure\n");
1436f9a0 3086 bge_stop(sc);
984263bc
MD
3087 return;
3088 }
3089
984263bc
MD
3090 /* Specify MTU. */
3091 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
011c0f93 3092 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
984263bc
MD
3093
3094 /* Load our MAC address. */
33c39a69 3095 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
984263bc
MD
3096 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3097 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3098
3099 /* Enable or disable promiscuous mode as needed. */
6439b28a 3100 bge_setpromisc(sc);
984263bc
MD
3101
3102 /* Program multicast filter. */
3103 bge_setmulti(sc);
3104
3105 /* Init RX ring. */
1436f9a0
SZ
3106 if (bge_init_rx_ring_std(sc)) {
3107 if_printf(ifp, "RX ring initialization failed\n");
3108 bge_stop(sc);
3109 return;
3110 }
984263bc 3111
7e40b8c5
HP
3112 /*
3113 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3114 * memory to insure that the chip has in fact read the first
3115 * entry of the ring.
3116 */
3117 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
33c39a69 3118 uint32_t v, i;
7e40b8c5
HP
3119 for (i = 0; i < 10; i++) {
3120 DELAY(20);
3121 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3122 if (v == (MCLBYTES - ETHER_ALIGN))
3123 break;
3124 }
3125 if (i == 10)
c6fd6f3b 3126 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
7e40b8c5
HP
3127 }
3128
984263bc 3129 /* Init jumbo RX ring. */
1436f9a0
SZ
3130 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3131 if (bge_init_rx_ring_jumbo(sc)) {
3132 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3133 bge_stop(sc);
3134 return;
3135 }
3136 }
984263bc
MD
3137
3138 /* Init our RX return ring index */
3139 sc->bge_rx_saved_considx = 0;
3140
3141 /* Init TX ring. */
3142 bge_init_tx_ring(sc);
3143
3144 /* Turn on transmitter */
3145 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3146
3147 /* Turn on receiver */
3148 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3149
5fe22f8b
SZ
3150 /*
3151 * Set the number of good frames to receive after RX MBUF
3152 * Low Watermark has been reached. After the RX MAC receives
3153 * this number of frames, it will drop subsequent incoming
3154 * frames until the MBUF High Watermark is reached.
3155 */
3156 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3157
984263bc
MD
3158 /* Tell firmware we're alive. */
3159 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3160
ba39cc82 3161 /* Enable host interrupts if polling(4) is not enabled. */
984263bc 3162 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
315fe0ee 3163#ifdef DEVICE_POLLING
ba39cc82
SZ
3164 if (ifp->if_flags & IFF_POLLING)
3165 bge_disable_intr(sc);
3166 else
315fe0ee 3167#endif
ba39cc82 3168 bge_enable_intr(sc);
984263bc
MD
3169
3170 bge_ifmedia_upd(ifp);
3171
3172 ifp->if_flags |= IFF_RUNNING;
3173 ifp->if_flags &= ~IFF_OACTIVE;
3174
263489fb 3175 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
984263bc
MD
3176}
3177
3178/*
3179 * Set media options.
3180 */
3181static int
33c39a69 3182bge_ifmedia_upd(struct ifnet *ifp)
984263bc 3183{
33c39a69 3184 struct bge_softc *sc = ifp->if_softc;
984263bc
MD
3185
3186 /* If this is a 1000baseX NIC, enable the TBI port. */
0ecb11d7 3187 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
3188 struct ifmedia *ifm = &sc->bge_ifmedia;
3189
984263bc
MD
3190 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3191 return(EINVAL);
db861466 3192
984263bc
MD
3193 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3194 case IFM_AUTO:
70059b3c
JS
3195 /*
3196 * The BCM5704 ASIC appears to have a special
3197 * mechanism for programming the autoneg
3198 * advertisement registers in TBI mode.
3199 */
5c56d5d8
SZ
3200 if (!bge_fake_autoneg &&
3201 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
70059b3c
JS
3202 uint32_t sgdig;
3203
3204 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3205 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3206 sgdig |= BGE_SGDIGCFG_AUTO |
3207 BGE_SGDIGCFG_PAUSE_CAP |
3208 BGE_SGDIGCFG_ASYM_PAUSE;
3209 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3210 sgdig | BGE_SGDIGCFG_SEND);
3211 DELAY(5);
3212 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3213 }
984263bc
MD
3214 break;
3215 case IFM_1000_SX:
3216 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3217 BGE_CLRBIT(sc, BGE_MAC_MODE,
3218 BGE_MACMODE_HALF_DUPLEX);
3219 } else {
3220 BGE_SETBIT(sc, BGE_MAC_MODE,
3221 BGE_MACMODE_HALF_DUPLEX);
3222 }
3223 break;
3224 default:
3225 return(EINVAL);
3226 }
db861466
SZ
3227 } else {
3228 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 3229
db861466 3230 sc->bge_link_evt++;
3f82ed83 3231 sc->bge_link = 0;
db861466
SZ
3232 if (mii->mii_instance) {
3233 struct mii_softc *miisc;
984263bc 3234
db861466
SZ
3235 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3236 mii_phy_reset(miisc);
3237 }
3238 mii_mediachg(mii);
3239 }
984263bc
MD
3240 return(0);
3241}
3242
3243/*
3244 * Report current media status.
3245 */
3246static void
33c39a69 3247bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 3248{
33c39a69 3249 struct bge_softc *sc = ifp->if_softc;
984263bc 3250
0ecb11d7 3251 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
3252 ifmr->ifm_status = IFM_AVALID;
3253 ifmr->ifm_active = IFM_ETHER;
3254 if (CSR_READ_4(sc, BGE_MAC_STS) &
db861466 3255 BGE_MACSTAT_TBI_PCS_SYNCHED) {
984263bc 3256 ifmr->ifm_status |= IFM_ACTIVE;
db861466
SZ
3257 } else {
3258 ifmr->ifm_active |= IFM_NONE;
3259 return;
3260 }
3261
984263bc
MD
3262 ifmr->ifm_active |= IFM_1000_SX;
3263 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3264 ifmr->ifm_active |= IFM_HDX;
3265 else
3266 ifmr->ifm_active |= IFM_FDX;
db861466
SZ
3267 } else {
3268 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 3269
db861466
SZ
3270 mii_pollstat(mii);
3271 ifmr->ifm_active = mii->mii_media_active;
3272 ifmr->ifm_status = mii->mii_media_status;
3273 }
984263bc
MD
3274}
3275
3276static int
33c39a69 3277bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
3278{
3279 struct bge_softc *sc = ifp->if_softc;
98dabdac 3280 struct ifreq *ifr = (struct ifreq *)data;
9a717c15 3281 int mask, error = 0;
984263bc 3282
aa65409c
SZ
3283 ASSERT_SERIALIZED(ifp->if_serializer);
3284
98dabdac 3285 switch (command) {
984263bc 3286 case SIOCSIFMTU:
0ecb11d7
SZ
3287 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3288 (BGE_IS_JUMBO_CAPABLE(sc) &&
3289 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
984263bc 3290 error = EINVAL;
0ecb11d7 3291 } else if (ifp->if_mtu != ifr->ifr_mtu) {
984263bc
MD
3292 ifp->if_mtu = ifr->ifr_mtu;
3293 ifp->if_flags &= ~IFF_RUNNING;
3294 bge_init(sc);
3295 }
3296 break;
3297 case SIOCSIFFLAGS:
3298 if (ifp->if_flags & IFF_UP) {
6439b28a 3299 if (ifp->if_flags & IFF_RUNNING) {
98dabdac 3300 mask = ifp->if_flags ^ sc->bge_if_flags;
6439b28a
SZ
3301
3302 /*
3303 * If only the state of the PROMISC flag
3304 * changed, then just use the 'set promisc
3305 * mode' command instead of reinitializing
3306 * the entire NIC. Doing a full re-init
3307 * means reloading the firmware and waiting
3308 * for it to start up, which may take a
3309 * second or two. Similarly for ALLMULTI.
3310 */
98dabdac 3311 if (mask & IFF_PROMISC)
6439b28a 3312 bge_setpromisc(sc);
98dabdac 3313 if (mask & IFF_ALLMULTI)
6439b28a
SZ
3314 bge_setmulti(sc);
3315 } else {
984263bc 3316 bge_init(sc);
6439b28a 3317 }
984263bc 3318 } else {
aa65409c 3319 if (ifp->if_flags & IFF_RUNNING)
984263bc 3320 bge_stop(sc);
984263bc
MD
3321 }
3322 sc->bge_if_flags = ifp->if_flags;
984263bc
MD
3323 break;
3324 case SIOCADDMULTI: