igb: Initialize if_name so functions used on if_init could use if_printf
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
CommitLineData
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1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "opt_polling.h"
8d6600da 33#include "opt_igb.h"
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34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/interrupt.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/serialize2.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <sys/sysctl.h>
49#include <sys/systm.h>
50
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/ifq_var.h>
58#include <net/toeplitz.h>
59#include <net/toeplitz2.h>
60#include <net/vlan/if_vlan_var.h>
61#include <net/vlan/if_vlan_ether.h>
62#include <net/if_poll.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <bus/pci/pcivar.h>
71#include <bus/pci/pcireg.h>
72
73#include <dev/netif/ig_hal/e1000_api.h>
74#include <dev/netif/ig_hal/e1000_82575.h>
75#include <dev/netif/igb/if_igb.h>
76
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77#ifdef IGB_RSS_DEBUG
78#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79do { \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82} while (0)
83#else /* !IGB_RSS_DEBUG */
84#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85#endif /* IGB_RSS_DEBUG */
86
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87#define IGB_NAME "Intel(R) PRO/1000 "
88#define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90#define IGB_DEVICE_NULL { 0, 0, NULL }
91
92static struct igb_device {
93 uint16_t vid;
94 uint16_t did;
95 const char *desc;
96} igb_devices[] = {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
123 IGB_DEVICE(I350_VF),
124
125 /* required last entry */
126 IGB_DEVICE_NULL
127};
128
129static int igb_probe(device_t);
130static int igb_attach(device_t);
131static int igb_detach(device_t);
132static int igb_shutdown(device_t);
133static int igb_suspend(device_t);
134static int igb_resume(device_t);
135
136static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137static void igb_setup_ifp(struct igb_softc *);
48faa653 138static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
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139static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
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141static void igb_add_sysctl(struct igb_softc *);
142static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
9c0ecdcc 143static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
b6220144 144static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
9c0ecdcc 145static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
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146
147static void igb_vf_init_stats(struct igb_softc *);
148static void igb_reset(struct igb_softc *);
149static void igb_update_stats_counters(struct igb_softc *);
150static void igb_update_vf_stats_counters(struct igb_softc *);
151static void igb_update_link_status(struct igb_softc *);
152static void igb_init_tx_unit(struct igb_softc *);
153static void igb_init_rx_unit(struct igb_softc *);
154
155static void igb_set_vlan(struct igb_softc *);
156static void igb_set_multi(struct igb_softc *);
157static void igb_set_promisc(struct igb_softc *);
158static void igb_disable_promisc(struct igb_softc *);
159
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160static int igb_alloc_rings(struct igb_softc *);
161static void igb_free_rings(struct igb_softc *);
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162static int igb_create_tx_ring(struct igb_tx_ring *);
163static int igb_create_rx_ring(struct igb_rx_ring *);
164static void igb_free_tx_ring(struct igb_tx_ring *);
165static void igb_free_rx_ring(struct igb_rx_ring *);
166static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
167static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
168static void igb_init_tx_ring(struct igb_tx_ring *);
169static int igb_init_rx_ring(struct igb_rx_ring *);
170static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
171static int igb_encap(struct igb_tx_ring *, struct mbuf **);
172
173static void igb_stop(struct igb_softc *);
174static void igb_init(void *);
175static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
176static void igb_media_status(struct ifnet *, struct ifmediareq *);
177static int igb_media_change(struct ifnet *);
178static void igb_timer(void *);
179static void igb_watchdog(struct ifnet *);
180static void igb_start(struct ifnet *);
181#ifdef DEVICE_POLLING
182static void igb_poll(struct ifnet *, enum poll_cmd, int);
183#endif
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184static void igb_serialize(struct ifnet *, enum ifnet_serialize);
185static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
186static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
187#ifdef INVARIANTS
188static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
189 boolean_t);
190#endif
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191
192static void igb_intr(void *);
9c0ecdcc 193static void igb_intr_shared(void *);
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194static void igb_rxeof(struct igb_rx_ring *, int);
195static void igb_txeof(struct igb_tx_ring *);
9c0ecdcc 196static void igb_set_eitr(struct igb_softc *, int, int);
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197static void igb_enable_intr(struct igb_softc *);
198static void igb_disable_intr(struct igb_softc *);
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199static void igb_init_unshared_intr(struct igb_softc *);
200static void igb_init_intr(struct igb_softc *);
201static int igb_setup_intr(struct igb_softc *);
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202static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
203static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
be922da6 204static void igb_set_intr_mask(struct igb_softc *);
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205static int igb_alloc_intr(struct igb_softc *);
206static void igb_free_intr(struct igb_softc *);
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207static void igb_teardown_intr(struct igb_softc *);
208static void igb_msix_try_alloc(struct igb_softc *);
209static void igb_msix_free(struct igb_softc *, boolean_t);
210static int igb_msix_setup(struct igb_softc *);
211static void igb_msix_teardown(struct igb_softc *, int);
212static void igb_msix_rx(void *);
213static void igb_msix_tx(void *);
214static void igb_msix_status(void *);
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215
216/* Management and WOL Support */
217static void igb_get_mgmt(struct igb_softc *);
218static void igb_rel_mgmt(struct igb_softc *);
219static void igb_get_hw_control(struct igb_softc *);
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220static void igb_rel_hw_control(struct igb_softc *);
221static void igb_enable_wol(device_t);
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222
223static device_method_t igb_methods[] = {
224 /* Device interface */
225 DEVMETHOD(device_probe, igb_probe),
226 DEVMETHOD(device_attach, igb_attach),
227 DEVMETHOD(device_detach, igb_detach),
228 DEVMETHOD(device_shutdown, igb_shutdown),
229 DEVMETHOD(device_suspend, igb_suspend),
230 DEVMETHOD(device_resume, igb_resume),
231 { 0, 0 }
232};
233
234static driver_t igb_driver = {
235 "igb",
236 igb_methods,
237 sizeof(struct igb_softc),
238};
239
240static devclass_t igb_devclass;
241
242DECLARE_DUMMY_MODULE(if_igb);
243MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
244DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
245
246static int igb_rxd = IGB_DEFAULT_RXD;
247static int igb_txd = IGB_DEFAULT_TXD;
8d6600da 248static int igb_rxr = 0;
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249static int igb_msi_enable = 1;
250static int igb_msix_enable = 1;
251static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
252static int igb_fc_setting = e1000_fc_full;
253
254/*
255 * DMA Coalescing, only for i350 - default to off,
256 * this feature is for power savings
257 */
258static int igb_dma_coalesce = 0;
259
260TUNABLE_INT("hw.igb.rxd", &igb_rxd);
261TUNABLE_INT("hw.igb.txd", &igb_txd);
8d6600da 262TUNABLE_INT("hw.igb.rxr", &igb_rxr);
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263TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
264TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
265TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
266
267/* i350 specific */
268TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
269TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
270
271static __inline void
272igb_rxcsum(uint32_t staterr, struct mbuf *mp)
273{
274 /* Ignore Checksum bit is set */
275 if (staterr & E1000_RXD_STAT_IXSM)
276 return;
277
278 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
279 E1000_RXD_STAT_IPCS)
280 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
281
282 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
283 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
284 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
285 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
286 mp->m_pkthdr.csum_data = htons(0xffff);
287 }
288 }
289}
290
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291static __inline struct pktinfo *
292igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
293 uint32_t hash, uint32_t hashtype, uint32_t staterr)
294{
295 switch (hashtype) {
296 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
297 pi->pi_netisr = NETISR_IP;
298 pi->pi_flags = 0;
299 pi->pi_l3proto = IPPROTO_TCP;
300 break;
301
302 case E1000_RXDADV_RSSTYPE_IPV4:
303 if (staterr & E1000_RXD_STAT_IXSM)
304 return NULL;
305
306 if ((staterr &
307 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
308 E1000_RXD_STAT_TCPCS) {
309 pi->pi_netisr = NETISR_IP;
310 pi->pi_flags = 0;
311 pi->pi_l3proto = IPPROTO_UDP;
312 break;
313 }
314 /* FALL THROUGH */
315 default:
316 return NULL;
317 }
318
319 m->m_flags |= M_HASH;
320 m->m_pkthdr.hash = toeplitz_hash(hash);
321 return pi;
322}
323
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324static int
325igb_probe(device_t dev)
326{
327 const struct igb_device *d;
328 uint16_t vid, did;
329
330 vid = pci_get_vendor(dev);
331 did = pci_get_device(dev);
332
333 for (d = igb_devices; d->desc != NULL; ++d) {
334 if (vid == d->vid && did == d->did) {
335 device_set_desc(dev, d->desc);
336 return 0;
337 }
338 }
339 return ENXIO;
340}
341
342static int
343igb_attach(device_t dev)
344{
345 struct igb_softc *sc = device_get_softc(dev);
1f7e3916 346 uint16_t eeprom_data;
8d6600da 347 int error = 0, i, j, ring_max;
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348
349#ifdef notyet
350 /* SYSCTL stuff */
351 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
352 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
353 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
354 igb_sysctl_nvm_info, "I", "NVM Information");
355
356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
358 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
359 &igb_enable_aim, 1, "Interrupt Moderation");
360
361 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
362 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
363 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
364 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
365#endif
366
367 callout_init_mp(&sc->timer);
9c0ecdcc 368 lwkt_serialize_init(&sc->main_serialize);
1f7e3916 369
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370 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
371 device_get_unit(dev));
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372 sc->dev = sc->osdep.dev = dev;
373
374 /*
375 * Determine hardware and mac type
376 */
377 sc->hw.vendor_id = pci_get_vendor(dev);
378 sc->hw.device_id = pci_get_device(dev);
379 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
380 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
381 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
382
383 if (e1000_set_mac_type(&sc->hw))
384 return ENXIO;
385
386 /* Are we a VF device? */
387 if (sc->hw.mac.type == e1000_vfadapt ||
388 sc->hw.mac.type == e1000_vfadapt_i350)
389 sc->vf_ifp = 1;
390 else
391 sc->vf_ifp = 0;
392
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393 /*
394 * Configure total supported RX/TX ring count
395 */
396 switch (sc->hw.mac.type) {
397 case e1000_82575:
398 ring_max = IGB_MAX_RING_82575;
399 break;
400 case e1000_82580:
401 ring_max = IGB_MAX_RING_82580;
402 break;
403 case e1000_i350:
404 ring_max = IGB_MAX_RING_I350;
405 break;
406 case e1000_82576:
407 ring_max = IGB_MAX_RING_82576;
408 break;
409 default:
410 ring_max = IGB_MIN_RING;
411 break;
412 }
413 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
414 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
415#ifdef IGB_RSS_DEBUG
416 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
417#endif
418 sc->rx_ring_inuse = sc->rx_ring_cnt;
419 sc->tx_ring_cnt = 1; /* XXX */
420
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421 if (sc->hw.mac.type == e1000_82575)
422 sc->flags |= IGB_FLAG_TSO_IPLEN0;
423
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424 /* Enable bus mastering */
425 pci_enable_busmaster(dev);
426
427 /*
428 * Allocate IO memory
429 */
430 sc->mem_rid = PCIR_BAR(0);
431 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
432 RF_ACTIVE);
433 if (sc->mem_res == NULL) {
434 device_printf(dev, "Unable to allocate bus resource: memory\n");
435 error = ENXIO;
436 goto failed;
437 }
438 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
439 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
440
441 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
442
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443 /* Save PCI command register for Shared Code */
444 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
445 sc->hw.back = &sc->osdep;
446
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447 /* Do Shared Code initialization */
448 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
449 device_printf(dev, "Setup of Shared code failed\n");
450 error = ENXIO;
451 goto failed;
452 }
453
454 e1000_get_bus_info(&sc->hw);
455
456 sc->hw.mac.autoneg = DO_AUTO_NEG;
457 sc->hw.phy.autoneg_wait_to_complete = FALSE;
458 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
459
460 /* Copper options */
461 if (sc->hw.phy.media_type == e1000_media_type_copper) {
462 sc->hw.phy.mdix = AUTO_ALL_MODES;
463 sc->hw.phy.disable_polarity_correction = FALSE;
464 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
465 }
466
467 /* Set the frame limits assuming standard ethernet sized frames. */
468 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
1f7e3916 469
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470 /* Allocate RX/TX rings */
471 error = igb_alloc_rings(sc);
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472 if (error)
473 goto failed;
474
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475 /* Allocate interrupt */
476 error = igb_alloc_intr(sc);
477 if (error)
a1647e40 478 goto failed;
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479
480 /*
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481 * Setup serializers
482 */
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483 i = 0;
484 sc->serializes[i++] = &sc->main_serialize;
485
486 sc->tx_serialize = i;
487 for (j = 0; j < sc->tx_ring_cnt; ++j)
488 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
489
490 sc->rx_serialize = i;
491 for (j = 0; j < sc->rx_ring_cnt; ++j)
492 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
493
494 sc->serialize_cnt = i;
495 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
496
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497 /* Allocate the appropriate stats memory */
498 if (sc->vf_ifp) {
499 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
500 M_WAITOK | M_ZERO);
501 igb_vf_init_stats(sc);
502 } else {
503 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
504 M_WAITOK | M_ZERO);
505 }
506
507 /* Allocate multicast array memory. */
508 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
509 M_DEVBUF, M_WAITOK);
510
511 /* Some adapter-specific advanced features */
512 if (sc->hw.mac.type >= e1000_i350) {
513#ifdef notyet
514 igb_set_sysctl_value(adapter, "dma_coalesce",
515 "configure dma coalesce",
516 &adapter->dma_coalesce, igb_dma_coalesce);
517 igb_set_sysctl_value(adapter, "eee_disabled",
518 "enable Energy Efficient Ethernet",
519 &adapter->hw.dev_spec._82575.eee_disable,
520 igb_eee_disabled);
521#else
522 sc->dma_coalesce = igb_dma_coalesce;
523 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
524#endif
525 e1000_set_eee_i350(&sc->hw);
526 }
527
528 /*
529 * Start from a known state, this is important in reading the nvm and
530 * mac from that.
531 */
532 e1000_reset_hw(&sc->hw);
533
534 /* Make sure we have a good EEPROM before we read from it */
535 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
536 /*
537 * Some PCI-E parts fail the first check due to
538 * the link being in sleep state, call it again,
539 * if it fails a second time its a real issue.
540 */
541 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
542 device_printf(dev,
543 "The EEPROM Checksum Is Not Valid\n");
544 error = EIO;
545 goto failed;
546 }
547 }
548
549 /* Copy the permanent MAC address out of the EEPROM */
550 if (e1000_read_mac_addr(&sc->hw) < 0) {
551 device_printf(dev, "EEPROM read error while reading MAC"
552 " address\n");
553 error = EIO;
554 goto failed;
555 }
556 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
557 device_printf(dev, "Invalid MAC address\n");
558 error = EIO;
559 goto failed;
560 }
561
562#ifdef notyet
563 /*
564 ** Configure Interrupts
565 */
566 if ((adapter->msix > 1) && (igb_enable_msix))
567 error = igb_allocate_msix(adapter);
568 else /* MSI or Legacy */
569 error = igb_allocate_legacy(adapter);
570 if (error)
571 goto err_late;
572#endif
573
574 /* Setup OS specific network interface */
575 igb_setup_ifp(sc);
576
577 /* Add sysctl tree, must after igb_setup_ifp() */
578 igb_add_sysctl(sc);
579
580 /* Now get a good starting state */
581 igb_reset(sc);
582
583 /* Initialize statistics */
584 igb_update_stats_counters(sc);
585
586 sc->hw.mac.get_link_status = 1;
587 igb_update_link_status(sc);
588
589 /* Indicate SOL/IDER usage */
590 if (e1000_check_reset_block(&sc->hw)) {
591 device_printf(dev,
592 "PHY reset is blocked due to SOL/IDER session.\n");
593 }
594
595 /* Determine if we have to control management hardware */
396b7048
SZ
596 if (e1000_enable_mng_pass_thru(&sc->hw))
597 sc->flags |= IGB_FLAG_HAS_MGMT;
1f7e3916
SZ
598
599 /*
600 * Setup Wake-on-Lan
601 */
602 /* APME bit in EEPROM is mapped to WUC.APME */
603 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
604 if (eeprom_data)
605 sc->wol = E1000_WUFC_MAG;
606 /* XXX disable WOL */
607 sc->wol = 0;
608
609#ifdef notyet
610 /* Register for VLAN events */
611 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
612 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
613 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
614 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
615#endif
616
617#ifdef notyet
618 igb_add_hw_stats(adapter);
619#endif
620
f6167a56 621 error = igb_setup_intr(sc);
1f7e3916 622 if (error) {
1f7e3916
SZ
623 ether_ifdetach(&sc->arpcom.ac_if);
624 goto failed;
625 }
1f7e3916
SZ
626 return 0;
627
628failed:
629 igb_detach(dev);
630 return error;
631}
632
633static int
634igb_detach(device_t dev)
635{
636 struct igb_softc *sc = device_get_softc(dev);
637
638 if (device_is_attached(dev)) {
639 struct ifnet *ifp = &sc->arpcom.ac_if;
640
641 ifnet_serialize_all(ifp);
642
643 igb_stop(sc);
644
645 e1000_phy_hw_reset(&sc->hw);
646
647 /* Give control back to firmware */
648 igb_rel_mgmt(sc);
649 igb_rel_hw_control(sc);
650
651 if (sc->wol) {
652 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
653 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
654 igb_enable_wol(dev);
655 }
656
9c0ecdcc 657 igb_teardown_intr(sc);
1f7e3916
SZ
658
659 ifnet_deserialize_all(ifp);
660
661 ether_ifdetach(ifp);
662 } else if (sc->mem_res != NULL) {
663 igb_rel_hw_control(sc);
664 }
665 bus_generic_detach(dev);
666
9c0ecdcc
SZ
667 if (sc->sysctl_tree != NULL)
668 sysctl_ctx_free(&sc->sysctl_ctx);
669
3c7cc5e2 670 igb_free_intr(sc);
1f7e3916 671
9c0ecdcc
SZ
672 if (sc->msix_mem_res != NULL) {
673 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
674 sc->msix_mem_res);
675 }
1f7e3916
SZ
676 if (sc->mem_res != NULL) {
677 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
678 sc->mem_res);
679 }
680
a619b256 681 igb_free_rings(sc);
1f7e3916
SZ
682
683 if (sc->mta != NULL)
684 kfree(sc->mta, M_DEVBUF);
685 if (sc->stats != NULL)
686 kfree(sc->stats, M_DEVBUF);
687
1f7e3916
SZ
688 return 0;
689}
690
691static int
692igb_shutdown(device_t dev)
693{
694 return igb_suspend(dev);
695}
696
697static int
698igb_suspend(device_t dev)
699{
700 struct igb_softc *sc = device_get_softc(dev);
701 struct ifnet *ifp = &sc->arpcom.ac_if;
702
703 ifnet_serialize_all(ifp);
704
705 igb_stop(sc);
706
707 igb_rel_mgmt(sc);
708 igb_rel_hw_control(sc);
709
710 if (sc->wol) {
711 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
712 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
713 igb_enable_wol(dev);
714 }
715
716 ifnet_deserialize_all(ifp);
717
718 return bus_generic_suspend(dev);
719}
720
721static int
722igb_resume(device_t dev)
723{
724 struct igb_softc *sc = device_get_softc(dev);
725 struct ifnet *ifp = &sc->arpcom.ac_if;
726
727 ifnet_serialize_all(ifp);
728
729 igb_init(sc);
730 igb_get_mgmt(sc);
731
732 if_devstart(ifp);
733
734 ifnet_deserialize_all(ifp);
735
736 return bus_generic_resume(dev);
737}
738
739static int
740igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
741{
742 struct igb_softc *sc = ifp->if_softc;
743 struct ifreq *ifr = (struct ifreq *)data;
744 int max_frame_size, mask, reinit;
745 int error = 0;
746
747 ASSERT_IFNET_SERIALIZED_ALL(ifp);
748
749 switch (command) {
750 case SIOCSIFMTU:
751 max_frame_size = 9234;
752 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
753 ETHER_CRC_LEN) {
754 error = EINVAL;
755 break;
756 }
757
758 ifp->if_mtu = ifr->ifr_mtu;
759 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
760 ETHER_CRC_LEN;
761
762 if (ifp->if_flags & IFF_RUNNING)
763 igb_init(sc);
764 break;
765
766 case SIOCSIFFLAGS:
767 if (ifp->if_flags & IFF_UP) {
768 if (ifp->if_flags & IFF_RUNNING) {
769 if ((ifp->if_flags ^ sc->if_flags) &
770 (IFF_PROMISC | IFF_ALLMULTI)) {
771 igb_disable_promisc(sc);
772 igb_set_promisc(sc);
773 }
774 } else {
775 igb_init(sc);
776 }
777 } else if (ifp->if_flags & IFF_RUNNING) {
778 igb_stop(sc);
779 }
780 sc->if_flags = ifp->if_flags;
781 break;
782
783 case SIOCADDMULTI:
784 case SIOCDELMULTI:
785 if (ifp->if_flags & IFF_RUNNING) {
786 igb_disable_intr(sc);
787 igb_set_multi(sc);
788#ifdef DEVICE_POLLING
789 if (!(ifp->if_flags & IFF_POLLING))
790#endif
791 igb_enable_intr(sc);
792 }
793 break;
794
795 case SIOCSIFMEDIA:
796 /*
797 * As the speed/duplex settings are being
798 * changed, we need toreset the PHY.
799 */
800 sc->hw.phy.reset_disable = FALSE;
801
802 /* Check SOL/IDER usage */
803 if (e1000_check_reset_block(&sc->hw)) {
804 if_printf(ifp, "Media change is "
805 "blocked due to SOL/IDER session.\n");
806 break;
807 }
808 /* FALL THROUGH */
809
810 case SIOCGIFMEDIA:
811 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
812 break;
813
814 case SIOCSIFCAP:
815 reinit = 0;
816 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
77d8cab9
SZ
817 if (mask & IFCAP_RXCSUM) {
818 ifp->if_capenable ^= IFCAP_RXCSUM;
1f7e3916
SZ
819 reinit = 1;
820 }
821 if (mask & IFCAP_VLAN_HWTAGGING) {
822 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
823 reinit = 1;
824 }
77d8cab9
SZ
825 if (mask & IFCAP_TXCSUM) {
826 ifp->if_capenable ^= IFCAP_TXCSUM;
827 if (ifp->if_capenable & IFCAP_TXCSUM)
828 ifp->if_hwassist |= IGB_CSUM_FEATURES;
829 else
830 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
831 }
23f6ffe4
SZ
832 if (mask & IFCAP_TSO) {
833 ifp->if_capenable ^= IFCAP_TSO;
834 if (ifp->if_capenable & IFCAP_TSO)
835 ifp->if_hwassist |= CSUM_TSO;
836 else
837 ifp->if_hwassist &= ~CSUM_TSO;
838 }
8d6600da
SZ
839 if (mask & IFCAP_RSS)
840 ifp->if_capenable ^= IFCAP_RSS;
1f7e3916
SZ
841 if (reinit && (ifp->if_flags & IFF_RUNNING))
842 igb_init(sc);
843 break;
844
845 default:
846 error = ether_ioctl(ifp, command, data);
847 break;
848 }
849 return error;
850}
851
852static void
853igb_init(void *xsc)
854{
855 struct igb_softc *sc = xsc;
856 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 857 boolean_t polling;
1f7e3916
SZ
858 int i;
859
860 ASSERT_IFNET_SERIALIZED_ALL(ifp);
861
862 igb_stop(sc);
863
864 /* Get the latest mac address, User can use a LAA */
865 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
866
867 /* Put the address into the Receive Address Array */
868 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
869
870 igb_reset(sc);
871 igb_update_link_status(sc);
872
873 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
874
1f7e3916
SZ
875 /* Configure for OS presence */
876 igb_get_mgmt(sc);
877
9c0ecdcc 878 polling = FALSE;
be922da6 879#ifdef DEVICE_POLLING
9c0ecdcc
SZ
880 if (ifp->if_flags & IFF_POLLING)
881 polling = TRUE;
be922da6 882#endif
9c0ecdcc
SZ
883
884 /* Configured used RX/TX rings */
885 igb_set_ring_inuse(sc, polling);
886
887 /* Initialize interrupt */
888 igb_init_intr(sc);
be922da6 889
1f7e3916 890 /* Prepare transmit descriptors and buffers */
27866bf1 891 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916
SZ
892 igb_init_tx_ring(&sc->tx_rings[i]);
893 igb_init_tx_unit(sc);
894
895 /* Setup Multicast table */
896 igb_set_multi(sc);
897
898#if 0
899 /*
900 * Figure out the desired mbuf pool
901 * for doing jumbo/packetsplit
902 */
903 if (adapter->max_frame_size <= 2048)
904 adapter->rx_mbuf_sz = MCLBYTES;
905 else if (adapter->max_frame_size <= 4096)
906 adapter->rx_mbuf_sz = MJUMPAGESIZE;
907 else
908 adapter->rx_mbuf_sz = MJUM9BYTES;
1f7e3916
SZ
909#endif
910
911 /* Prepare receive descriptors and buffers */
be922da6 912 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
913 int error;
914
915 error = igb_init_rx_ring(&sc->rx_rings[i]);
916 if (error) {
917 if_printf(ifp, "Could not setup receive structures\n");
918 igb_stop(sc);
919 return;
920 }
921 }
922 igb_init_rx_unit(sc);
923
924 /* Enable VLAN support */
925 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
926 igb_set_vlan(sc);
927
928 /* Don't lose promiscuous settings */
929 igb_set_promisc(sc);
930
1f7e3916
SZ
931 ifp->if_flags |= IFF_RUNNING;
932 ifp->if_flags &= ~IFF_OACTIVE;
933
934 callout_reset(&sc->timer, hz, igb_timer, sc);
935 e1000_clear_hw_cntrs_base_generic(&sc->hw);
936
9c0ecdcc 937 /* This clears any pending interrupts */
1f7e3916 938 E1000_READ_REG(&sc->hw, E1000_ICR);
9c0ecdcc 939
1f7e3916
SZ
940 /*
941 * Only enable interrupts if we are not polling, make sure
942 * they are off otherwise.
943 */
9c0ecdcc 944 if (polling) {
1f7e3916 945 igb_disable_intr(sc);
9c0ecdcc 946 } else {
1f7e3916
SZ
947 igb_enable_intr(sc);
948 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
949 }
950
951 /* Set Energy Efficient Ethernet */
952 e1000_set_eee_i350(&sc->hw);
953
954 /* Don't reset the phy next time init gets called */
955 sc->hw.phy.reset_disable = TRUE;
956}
957
958static void
959igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
960{
961 struct igb_softc *sc = ifp->if_softc;
962 u_char fiber_type = IFM_1000_SX;
963
964 ASSERT_IFNET_SERIALIZED_ALL(ifp);
965
966 igb_update_link_status(sc);
967
968 ifmr->ifm_status = IFM_AVALID;
969 ifmr->ifm_active = IFM_ETHER;
970
971 if (!sc->link_active)
972 return;
973
974 ifmr->ifm_status |= IFM_ACTIVE;
975
976 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
977 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
978 ifmr->ifm_active |= fiber_type | IFM_FDX;
979 } else {
980 switch (sc->link_speed) {
981 case 10:
982 ifmr->ifm_active |= IFM_10_T;
983 break;
984
985 case 100:
986 ifmr->ifm_active |= IFM_100_TX;
987 break;
988
989 case 1000:
990 ifmr->ifm_active |= IFM_1000_T;
991 break;
992 }
993 if (sc->link_duplex == FULL_DUPLEX)
994 ifmr->ifm_active |= IFM_FDX;
995 else
996 ifmr->ifm_active |= IFM_HDX;
997 }
998}
999
1000static int
1001igb_media_change(struct ifnet *ifp)
1002{
1003 struct igb_softc *sc = ifp->if_softc;
1004 struct ifmedia *ifm = &sc->media;
1005
1006 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1007
1008 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1009 return EINVAL;
1010
1011 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1012 case IFM_AUTO:
1013 sc->hw.mac.autoneg = DO_AUTO_NEG;
1014 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1015 break;
1016
1017 case IFM_1000_LX:
1018 case IFM_1000_SX:
1019 case IFM_1000_T:
1020 sc->hw.mac.autoneg = DO_AUTO_NEG;
1021 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1022 break;
1023
1024 case IFM_100_TX:
1025 sc->hw.mac.autoneg = FALSE;
1026 sc->hw.phy.autoneg_advertised = 0;
1027 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1028 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1029 else
1030 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1031 break;
1032
1033 case IFM_10_T:
1034 sc->hw.mac.autoneg = FALSE;
1035 sc->hw.phy.autoneg_advertised = 0;
1036 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1037 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1038 else
1039 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1040 break;
1041
1042 default:
1043 if_printf(ifp, "Unsupported media type\n");
1044 break;
1045 }
1046
1047 igb_init(sc);
1048
1049 return 0;
1050}
1051
1052static void
1053igb_set_promisc(struct igb_softc *sc)
1054{
1055 struct ifnet *ifp = &sc->arpcom.ac_if;
1056 struct e1000_hw *hw = &sc->hw;
1057 uint32_t reg;
1058
1059 if (sc->vf_ifp) {
1060 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1061 return;
1062 }
1063
1064 reg = E1000_READ_REG(hw, E1000_RCTL);
1065 if (ifp->if_flags & IFF_PROMISC) {
1066 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1067 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1068 } else if (ifp->if_flags & IFF_ALLMULTI) {
1069 reg |= E1000_RCTL_MPE;
1070 reg &= ~E1000_RCTL_UPE;
1071 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1072 }
1073}
1074
1075static void
1076igb_disable_promisc(struct igb_softc *sc)
1077{
1078 struct e1000_hw *hw = &sc->hw;
1079 uint32_t reg;
1080
1081 if (sc->vf_ifp) {
1082 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1083 return;
1084 }
1085 reg = E1000_READ_REG(hw, E1000_RCTL);
1086 reg &= ~E1000_RCTL_UPE;
1087 reg &= ~E1000_RCTL_MPE;
1088 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1089}
1090
1091static void
1092igb_set_multi(struct igb_softc *sc)
1093{
1094 struct ifnet *ifp = &sc->arpcom.ac_if;
1095 struct ifmultiaddr *ifma;
1096 uint32_t reg_rctl = 0;
1097 uint8_t *mta;
1098 int mcnt = 0;
1099
1100 mta = sc->mta;
1101 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1102
1103 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1104 if (ifma->ifma_addr->sa_family != AF_LINK)
1105 continue;
1106
1107 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1108 break;
1109
1110 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1111 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1112 mcnt++;
1113 }
1114
1115 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1116 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1117 reg_rctl |= E1000_RCTL_MPE;
1118 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1119 } else {
1120 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1121 }
1122}
1123
1124static void
1125igb_timer(void *xsc)
1126{
1127 struct igb_softc *sc = xsc;
1f7e3916 1128
27dd00d6 1129 lwkt_serialize_enter(&sc->main_serialize);
1f7e3916
SZ
1130
1131 igb_update_link_status(sc);
1132 igb_update_stats_counters(sc);
1133
1134 callout_reset(&sc->timer, hz, igb_timer, sc);
1135
27dd00d6 1136 lwkt_serialize_exit(&sc->main_serialize);
1f7e3916
SZ
1137}
1138
1139static void
1140igb_update_link_status(struct igb_softc *sc)
1141{
1142 struct ifnet *ifp = &sc->arpcom.ac_if;
1143 struct e1000_hw *hw = &sc->hw;
1144 uint32_t link_check, thstat, ctrl;
1145
1146 link_check = thstat = ctrl = 0;
1147
1148 /* Get the cached link value or read for real */
1149 switch (hw->phy.media_type) {
1150 case e1000_media_type_copper:
1151 if (hw->mac.get_link_status) {
1152 /* Do the work to read phy */
1153 e1000_check_for_link(hw);
1154 link_check = !hw->mac.get_link_status;
1155 } else {
1156 link_check = TRUE;
1157 }
1158 break;
1159
1160 case e1000_media_type_fiber:
1161 e1000_check_for_link(hw);
1162 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1163 break;
1164
1165 case e1000_media_type_internal_serdes:
1166 e1000_check_for_link(hw);
1167 link_check = hw->mac.serdes_has_link;
1168 break;
1169
1170 /* VF device is type_unknown */
1171 case e1000_media_type_unknown:
1172 e1000_check_for_link(hw);
1173 link_check = !hw->mac.get_link_status;
1174 /* Fall thru */
1175 default:
1176 break;
1177 }
1178
1179 /* Check for thermal downshift or shutdown */
1180 if (hw->mac.type == e1000_i350) {
1181 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1182 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1183 }
1184
1185 /* Now we check if a transition has happened */
1186 if (link_check && sc->link_active == 0) {
1187 e1000_get_speed_and_duplex(hw,
1188 &sc->link_speed, &sc->link_duplex);
1189 if (bootverbose) {
1190 if_printf(ifp, "Link is up %d Mbps %s\n",
1191 sc->link_speed,
1192 sc->link_duplex == FULL_DUPLEX ?
1193 "Full Duplex" : "Half Duplex");
1194 }
1195 sc->link_active = 1;
1196
1197 ifp->if_baudrate = sc->link_speed * 1000000;
1198 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1199 (thstat & E1000_THSTAT_LINK_THROTTLE))
1200 if_printf(ifp, "Link: thermal downshift\n");
1201 /* This can sleep */
1202 ifp->if_link_state = LINK_STATE_UP;
1203 if_link_state_change(ifp);
1204 } else if (!link_check && sc->link_active == 1) {
1205 ifp->if_baudrate = sc->link_speed = 0;
1206 sc->link_duplex = 0;
1207 if (bootverbose)
1208 if_printf(ifp, "Link is Down\n");
1209 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1210 (thstat & E1000_THSTAT_PWR_DOWN))
1211 if_printf(ifp, "Link: thermal shutdown\n");
1212 sc->link_active = 0;
1213 /* This can sleep */
1214 ifp->if_link_state = LINK_STATE_DOWN;
1215 if_link_state_change(ifp);
1216 }
1217}
1218
1219static void
1220igb_stop(struct igb_softc *sc)
1221{
1222 struct ifnet *ifp = &sc->arpcom.ac_if;
1223 int i;
1224
1225 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1226
1227 igb_disable_intr(sc);
1228
1229 callout_stop(&sc->timer);
1230
1231 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1232 ifp->if_timer = 0;
1233
1234 e1000_reset_hw(&sc->hw);
1235 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1236
1237 e1000_led_off(&sc->hw);
1238 e1000_cleanup_led(&sc->hw);
1239
27866bf1 1240 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916 1241 igb_free_tx_ring(&sc->tx_rings[i]);
27866bf1 1242 for (i = 0; i < sc->rx_ring_cnt; ++i)
1f7e3916
SZ
1243 igb_free_rx_ring(&sc->rx_rings[i]);
1244}
1245
1246static void
1247igb_reset(struct igb_softc *sc)
1248{
1249 struct ifnet *ifp = &sc->arpcom.ac_if;
1250 struct e1000_hw *hw = &sc->hw;
1251 struct e1000_fc_info *fc = &hw->fc;
1252 uint32_t pba = 0;
1253 uint16_t hwm;
1254
1255 /* Let the firmware know the OS is in control */
1256 igb_get_hw_control(sc);
1257
1258 /*
1259 * Packet Buffer Allocation (PBA)
1260 * Writing PBA sets the receive portion of the buffer
1261 * the remainder is used for the transmit buffer.
1262 */
1263 switch (hw->mac.type) {
1264 case e1000_82575:
1265 pba = E1000_PBA_32K;
1266 break;
1267
1268 case e1000_82576:
1269 case e1000_vfadapt:
1270 pba = E1000_READ_REG(hw, E1000_RXPBS);
1271 pba &= E1000_RXPBS_SIZE_MASK_82576;
1272 break;
1273
1274 case e1000_82580:
1275 case e1000_i350:
1276 case e1000_vfadapt_i350:
1277 pba = E1000_READ_REG(hw, E1000_RXPBS);
1278 pba = e1000_rxpbs_adjust_82580(pba);
1279 break;
1280 /* XXX pba = E1000_PBA_35K; */
1281
1282 default:
1283 break;
1284 }
1285
1286 /* Special needs in case of Jumbo frames */
1287 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1288 uint32_t tx_space, min_tx, min_rx;
1289
1290 pba = E1000_READ_REG(hw, E1000_PBA);
1291 tx_space = pba >> 16;
1292 pba &= 0xffff;
1293
1294 min_tx = (sc->max_frame_size +
1295 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1296 min_tx = roundup2(min_tx, 1024);
1297 min_tx >>= 10;
1298 min_rx = sc->max_frame_size;
1299 min_rx = roundup2(min_rx, 1024);
1300 min_rx >>= 10;
1301 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1302 pba = pba - (min_tx - tx_space);
1303 /*
1304 * if short on rx space, rx wins
1305 * and must trump tx adjustment
1306 */
1307 if (pba < min_rx)
1308 pba = min_rx;
1309 }
1310 E1000_WRITE_REG(hw, E1000_PBA, pba);
1311 }
1312
1313 /*
1314 * These parameters control the automatic generation (Tx) and
1315 * response (Rx) to Ethernet PAUSE frames.
1316 * - High water mark should allow for at least two frames to be
1317 * received after sending an XOFF.
1318 * - Low water mark works best when it is very near the high water mark.
1319 * This allows the receiver to restart by sending XON when it has
1320 * drained a bit.
1321 */
1322 hwm = min(((pba << 10) * 9 / 10),
1323 ((pba << 10) - 2 * sc->max_frame_size));
1324
1325 if (hw->mac.type < e1000_82576) {
1326 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1327 fc->low_water = fc->high_water - 8;
1328 } else {
1329 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1330 fc->low_water = fc->high_water - 16;
1331 }
1332 fc->pause_time = IGB_FC_PAUSE_TIME;
1333 fc->send_xon = TRUE;
1334
1335 /* Issue a global reset */
1336 e1000_reset_hw(hw);
1337 E1000_WRITE_REG(hw, E1000_WUC, 0);
1338
1339 if (e1000_init_hw(hw) < 0)
1340 if_printf(ifp, "Hardware Initialization Failed\n");
1341
1342 /* Setup DMA Coalescing */
1343 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1344 uint32_t reg;
1345
1346 hwm = (pba - 4) << 10;
1347 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1348 & E1000_DMACR_DMACTHR_MASK;
1349
1350 /* transition to L0x or L1 if available..*/
1351 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1352
1353 /* timer = +-1000 usec in 32usec intervals */
1354 reg |= (1000 >> 5);
1355 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1356
1357 /* No lower threshold */
1358 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1359
1360 /* set hwm to PBA - 2 * max frame size */
1361 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1362
1363 /* Set the interval before transition */
1364 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1365 reg |= 0x800000FF; /* 255 usec */
1366 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1367
1368 /* free space in tx packet buffer to wake from DMA coal */
1369 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1370 (20480 - (2 * sc->max_frame_size)) >> 6);
1371
1372 /* make low power state decision controlled by DMA coal */
1373 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1374 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1375 reg | E1000_PCIEMISC_LX_DECISION);
1376 if_printf(ifp, "DMA Coalescing enabled\n");
1377 }
1378
1379 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1380 e1000_get_phy_info(hw);
1381 e1000_check_for_link(hw);
1382}
1383
1384static void
1385igb_setup_ifp(struct igb_softc *sc)
1386{
1387 struct ifnet *ifp = &sc->arpcom.ac_if;
1388
1f7e3916
SZ
1389 ifp->if_softc = sc;
1390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c0ecdcc 1391 ifp->if_init = igb_init;
1f7e3916
SZ
1392 ifp->if_ioctl = igb_ioctl;
1393 ifp->if_start = igb_start;
7d235eb5
SZ
1394 ifp->if_serialize = igb_serialize;
1395 ifp->if_deserialize = igb_deserialize;
1396 ifp->if_tryserialize = igb_tryserialize;
1397#ifdef INVARIANTS
1398 ifp->if_serialize_assert = igb_serialize_assert;
1399#endif
1f7e3916
SZ
1400#ifdef DEVICE_POLLING
1401 ifp->if_poll = igb_poll;
1402#endif
1403 ifp->if_watchdog = igb_watchdog;
1404
91b8700a 1405 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1f7e3916
SZ
1406 ifq_set_ready(&ifp->if_snd);
1407
1408 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1409
1410 ifp->if_capabilities =
23f6ffe4 1411 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
8d6600da
SZ
1412 if (IGB_ENABLE_HWRSS(sc))
1413 ifp->if_capabilities |= IFCAP_RSS;
1f7e3916 1414 ifp->if_capenable = ifp->if_capabilities;
23f6ffe4 1415 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1f7e3916
SZ
1416
1417 /*
1418 * Tell the upper layer(s) we support long frames
1419 */
1420 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1421
1422 /*
1423 * Specify the media types supported by this adapter and register
1424 * callbacks to update media and link information
1425 */
1426 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1427 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1428 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1429 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1430 0, NULL);
1431 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1432 } else {
1433 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1434 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1435 0, NULL);
1436 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1437 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1438 0, NULL);
1439 if (sc->hw.phy.type != e1000_phy_ife) {
1440 ifmedia_add(&sc->media,
1441 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1442 ifmedia_add(&sc->media,
1443 IFM_ETHER | IFM_1000_T, 0, NULL);
1444 }
1445 }
1446 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1447 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1448}
1449
1450static void
1451igb_add_sysctl(struct igb_softc *sc)
1452{
9c0ecdcc 1453 char node[32];
8d6600da 1454 int i;
8d6600da 1455
1f7e3916
SZ
1456 sysctl_ctx_init(&sc->sysctl_ctx);
1457 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1458 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1459 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1460 if (sc->sysctl_tree == NULL) {
1461 device_printf(sc->dev, "can't add sysctl node\n");
1462 return;
1463 }
1464
1465 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1466 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1467 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
be922da6
SZ
1468 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1469 "# of RX rings used");
1470 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1471 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1472 "# of RX descs");
1f7e3916 1473 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1474 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1475 "# of TX descs");
1f7e3916 1476
9c0ecdcc
SZ
1477 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1478 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1479 SYSCTL_CHILDREN(sc->sysctl_tree),
1480 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1481 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1482 } else {
1483 for (i = 0; i < sc->msix_cnt; ++i) {
1484 struct igb_msix_data *msix = &sc->msix_data[i];
1485
1486 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1487 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1488 SYSCTL_CHILDREN(sc->sysctl_tree),
1489 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1490 msix, 0, igb_sysctl_msix_rate, "I",
1491 msix->msix_rate_desc);
1492 }
1493 }
b6220144
SZ
1494
1495 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1496 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1497 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
8d6600da
SZ
1498 "# of segments per TX interrupt");
1499
1500#ifdef IGB_RSS_DEBUG
1501 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1502 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1503 "RSS debug level");
1504 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9c0ecdcc 1505 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
8d6600da 1506 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
9c0ecdcc 1507 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
8d6600da
SZ
1508 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1509 }
1510#endif
1f7e3916
SZ
1511}
1512
1513static int
a619b256 1514igb_alloc_rings(struct igb_softc *sc)
1f7e3916
SZ
1515{
1516 int error, i;
1517
1f7e3916
SZ
1518 /*
1519 * Create top level busdma tag
1520 */
1521 error = bus_dma_tag_create(NULL, 1, 0,
1522 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1523 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1524 &sc->parent_tag);
1525 if (error) {
1526 device_printf(sc->dev, "could not create top level DMA tag\n");
1527 return error;
1528 }
1529
1530 /*
1531 * Allocate TX descriptor rings and buffers
1532 */
27866bf1 1533 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1f7e3916 1534 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1535 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1536 struct igb_tx_ring *txr = &sc->tx_rings[i];
1537
1538 /* Set up some basics */
1539 txr->sc = sc;
1540 txr->me = i;
7d235eb5 1541 lwkt_serialize_init(&txr->tx_serialize);
1f7e3916
SZ
1542
1543 error = igb_create_tx_ring(txr);
1544 if (error)
1545 return error;
1546 }
1547
1548 /*
1549 * Allocate RX descriptor rings and buffers
1550 */
27866bf1 1551 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1f7e3916 1552 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1553 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1f7e3916
SZ
1554 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1555
1556 /* Set up some basics */
1557 rxr->sc = sc;
1558 rxr->me = i;
7d235eb5 1559 lwkt_serialize_init(&rxr->rx_serialize);
1f7e3916
SZ
1560
1561 error = igb_create_rx_ring(rxr);
1562 if (error)
1563 return error;
1564 }
1565
1f7e3916
SZ
1566 return 0;
1567}
1568
1569static void
a619b256 1570igb_free_rings(struct igb_softc *sc)
1f7e3916
SZ
1571{
1572 int i;
1573
1f7e3916 1574 if (sc->tx_rings != NULL) {
91b8700a
SZ
1575 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1576 struct igb_tx_ring *txr = &sc->tx_rings[i];
1577
1578 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1579 }
1f7e3916
SZ
1580 kfree(sc->tx_rings, M_DEVBUF);
1581 }
1582
1583 if (sc->rx_rings != NULL) {
91b8700a
SZ
1584 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1585 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1586
1587 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1588 }
1f7e3916
SZ
1589 kfree(sc->rx_rings, M_DEVBUF);
1590 }
1591}
1592
1593static int
1594igb_create_tx_ring(struct igb_tx_ring *txr)
1595{
1596 int tsize, error, i;
1597
1598 /*
1599 * Validate number of transmit descriptors. It must not exceed
1600 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1601 */
1602 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1603 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1604 device_printf(txr->sc->dev,
1605 "Using %d TX descriptors instead of %d!\n",
1606 IGB_DEFAULT_TXD, igb_txd);
91b8700a 1607 txr->num_tx_desc = IGB_DEFAULT_TXD;
1f7e3916 1608 } else {
91b8700a 1609 txr->num_tx_desc = igb_txd;
1f7e3916
SZ
1610 }
1611
1612 /*
1613 * Allocate TX descriptor ring
1614 */
91b8700a 1615 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1f7e3916
SZ
1616 IGB_DBA_ALIGN);
1617 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1618 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1619 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1620 if (txr->txdma.dma_vaddr == NULL) {
1621 device_printf(txr->sc->dev,
1622 "Unable to allocate TX Descriptor memory\n");
1623 return ENOMEM;
1624 }
1625 txr->tx_base = txr->txdma.dma_vaddr;
1626 bzero(txr->tx_base, tsize);
1627
91b8700a 1628 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1f7e3916
SZ
1629 M_DEVBUF, M_WAITOK | M_ZERO);
1630
1631 /*
b6220144
SZ
1632 * Allocate TX head write-back buffer
1633 */
1634 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1635 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1636 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1637 if (txr->tx_hdr == NULL) {
1638 device_printf(txr->sc->dev,
1639 "Unable to allocate TX head write-back buffer\n");
1640 return ENOMEM;
1641 }
1642
1643 /*
1f7e3916
SZ
1644 * Create DMA tag for TX buffers
1645 */
1646 error = bus_dma_tag_create(txr->sc->parent_tag,
1647 1, 0, /* alignment, bounds */
1648 BUS_SPACE_MAXADDR, /* lowaddr */
1649 BUS_SPACE_MAXADDR, /* highaddr */
1650 NULL, NULL, /* filter, filterarg */
1651 IGB_TSO_SIZE, /* maxsize */
1652 IGB_MAX_SCATTER, /* nsegments */
1653 PAGE_SIZE, /* maxsegsize */
1654 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1655 BUS_DMA_ONEBPAGE, /* flags */
1656 &txr->tx_tag);
1657 if (error) {
1658 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1659 kfree(txr->tx_buf, M_DEVBUF);
1660 txr->tx_buf = NULL;
1661 return error;
1662 }
1663
1664 /*
1665 * Create DMA maps for TX buffers
1666 */
91b8700a 1667 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1668 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1669
1670 error = bus_dmamap_create(txr->tx_tag,
1671 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1672 if (error) {
1673 device_printf(txr->sc->dev,
1674 "Unable to create TX DMA map\n");
1675 igb_destroy_tx_ring(txr, i);
1676 return error;
1677 }
1678 }
b6220144
SZ
1679
1680 /*
1681 * Initialize various watermark
1682 */
1683 txr->spare_desc = IGB_TX_SPARE;
91b8700a
SZ
1684 txr->intr_nsegs = txr->num_tx_desc / 16;
1685 txr->oact_hi_desc = txr->num_tx_desc / 2;
1686 txr->oact_lo_desc = txr->num_tx_desc / 8;
b6220144
SZ
1687 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1688 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1689 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1690 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1691
1f7e3916
SZ
1692 return 0;
1693}
1694
1695static void
1696igb_free_tx_ring(struct igb_tx_ring *txr)
1697{
1698 int i;
1699
91b8700a 1700 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1701 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1702
1703 if (txbuf->m_head != NULL) {
1704 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1705 m_freem(txbuf->m_head);
1706 txbuf->m_head = NULL;
1707 }
1708 }
1709}
1710
1711static void
1712igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1713{
1714 int i;
1715
1716 if (txr->txdma.dma_vaddr != NULL) {
1717 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1718 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1719 txr->txdma.dma_map);
1720 bus_dma_tag_destroy(txr->txdma.dma_tag);
1721 txr->txdma.dma_vaddr = NULL;
1722 }
1723
b6220144
SZ
1724 if (txr->tx_hdr != NULL) {
1725 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1726 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1727 txr->tx_hdr_dmap);
1728 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1729 txr->tx_hdr = NULL;
1730 }
1731
1f7e3916
SZ
1732 if (txr->tx_buf == NULL)
1733 return;
1734
1735 for (i = 0; i < ndesc; ++i) {
1736 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1737
1738 KKASSERT(txbuf->m_head == NULL);
1739 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1740 }
1741 bus_dma_tag_destroy(txr->tx_tag);
1742
1743 kfree(txr->tx_buf, M_DEVBUF);
1744 txr->tx_buf = NULL;
1745}
1746
1747static void
1748igb_init_tx_ring(struct igb_tx_ring *txr)
1749{
1f7e3916
SZ
1750 /* Clear the old descriptor contents */
1751 bzero(txr->tx_base,
91b8700a 1752 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1f7e3916 1753
b6220144
SZ
1754 /* Clear TX head write-back buffer */
1755 *(txr->tx_hdr) = 0;
1756
1f7e3916
SZ
1757 /* Reset indices */
1758 txr->next_avail_desc = 0;
1759 txr->next_to_clean = 0;
b6220144 1760 txr->tx_nsegs = 0;
1f7e3916
SZ
1761
1762 /* Set number of descriptors available */
91b8700a 1763 txr->tx_avail = txr->num_tx_desc;
1f7e3916
SZ
1764}
1765
1766static void
1767igb_init_tx_unit(struct igb_softc *sc)
1768{
1769 struct e1000_hw *hw = &sc->hw;
1770 uint32_t tctl;
1771 int i;
1772
1773 /* Setup the Tx Descriptor Rings */
27866bf1 1774 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1775 struct igb_tx_ring *txr = &sc->tx_rings[i];
1776 uint64_t bus_addr = txr->txdma.dma_paddr;
c3162c4e 1777 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1f7e3916 1778 uint32_t txdctl = 0;
b6220144 1779 uint32_t dca_txctrl;
1f7e3916
SZ
1780
1781 E1000_WRITE_REG(hw, E1000_TDLEN(i),
91b8700a 1782 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1f7e3916
SZ
1783 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1784 (uint32_t)(bus_addr >> 32));
1785 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1786 (uint32_t)bus_addr);
1787
1788 /* Setup the HW Tx Head and Tail descriptor pointers */
1789 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1790 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1791
54691ff1
SZ
1792 /*
1793 * WTHRESH is ignored by the hardware, since header
1794 * write back mode is used.
1795 */
1f7e3916
SZ
1796 txdctl |= IGB_TX_PTHRESH;
1797 txdctl |= IGB_TX_HTHRESH << 8;
1798 txdctl |= IGB_TX_WTHRESH << 16;
1799 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1800 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
b6220144
SZ
1801
1802 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1803 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1804 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1805
54691ff1
SZ
1806 /*
1807 * Don't set WB_on_EITR:
1808 * - 82575 does not have it
1809 * - It almost has no effect on 82576, see:
1810 * 82576 specification update errata #26
1811 * - It causes unnecessary bus traffic
1812 */
b6220144 1813 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
c3162c4e 1814 (uint32_t)(hdr_paddr >> 32));
b6220144 1815 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
c3162c4e 1816 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1f7e3916
SZ
1817 }
1818
1819 if (sc->vf_ifp)
1820 return;
1821
1822 e1000_config_collision_dist(hw);
1823
1824 /* Program the Transmit Control Register */
1825 tctl = E1000_READ_REG(hw, E1000_TCTL);
1826 tctl &= ~E1000_TCTL_CT;
1827 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1828 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1829
1830 /* This write will effectively turn on the transmit unit. */
1831 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1832}
1833
1834static boolean_t
48faa653 1835igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1f7e3916
SZ
1836{
1837 struct e1000_adv_tx_context_desc *TXD;
1f7e3916 1838 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1f7e3916 1839 int ehdrlen, ctxd, ip_hlen = 0;
1f7e3916
SZ
1840 boolean_t offload = TRUE;
1841
1842 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1843 offload = FALSE;
1844
1845 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
48faa653 1846
1f7e3916 1847 ctxd = txr->next_avail_desc;
1f7e3916
SZ
1848 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1849
1850 /*
1851 * In advanced descriptors the vlan tag must
1852 * be placed into the context descriptor, thus
1853 * we need to be here just for that setup.
1854 */
1855 if (mp->m_flags & M_VLANTAG) {
23f6ffe4
SZ
1856 uint16_t vlantag;
1857
1f7e3916
SZ
1858 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1859 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1860 } else if (!offload) {
1861 return FALSE;
1862 }
1863
48faa653
SZ
1864 ehdrlen = mp->m_pkthdr.csum_lhlen;
1865 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1f7e3916
SZ
1866
1867 /* Set the ether header length */
1868 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
48faa653
SZ
1869 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1870 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1871 ip_hlen = mp->m_pkthdr.csum_iphlen;
1872 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1f7e3916 1873 }
1f7e3916 1874 vlan_macip_lens |= ip_hlen;
1f7e3916 1875
23f6ffe4 1876 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1f7e3916
SZ
1877 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1878 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1879 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1880 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1881
1882 /* 82575 needs the queue index added */
1883 if (txr->sc->hw.mac.type == e1000_82575)
1884 mss_l4len_idx = txr->me << 4;
1885
1886 /* Now copy bits into descriptor */
1887 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1888 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1889 TXD->seqnum_seed = htole32(0);
1890 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1891
1f7e3916 1892 /* We've consumed the first desc, adjust counters */
91b8700a 1893 if (++ctxd == txr->num_tx_desc)
1f7e3916
SZ
1894 ctxd = 0;
1895 txr->next_avail_desc = ctxd;
1896 --txr->tx_avail;
1897
1898 return offload;
1899}
1900
1901static void
1902igb_txeof(struct igb_tx_ring *txr)
1903{
1904 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
b6220144 1905 int first, hdr, avail;
1f7e3916 1906
91b8700a 1907 if (txr->tx_avail == txr->num_tx_desc)
1f7e3916
SZ
1908 return;
1909
1910 first = txr->next_to_clean;
b6220144 1911 hdr = *(txr->tx_hdr);
1f7e3916 1912
b6220144
SZ
1913 if (first == hdr)
1914 return;
1f7e3916 1915
b6220144
SZ
1916 avail = txr->tx_avail;
1917 while (first != hdr) {
1918 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1f7e3916 1919
b6220144
SZ
1920 ++avail;
1921 if (txbuf->m_head) {
1922 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1923 m_freem(txbuf->m_head);
1924 txbuf->m_head = NULL;
1925 ++ifp->if_opackets;
1f7e3916 1926 }
91b8700a 1927 if (++first == txr->num_tx_desc)
b6220144 1928 first = 0;
1f7e3916
SZ
1929 }
1930 txr->next_to_clean = first;
b6220144 1931 txr->tx_avail = avail;
1f7e3916
SZ
1932
1933 /*
1934 * If we have a minimum free, clear IFF_OACTIVE
1935 * to tell the stack that it is OK to send packets.
1936 */
b6220144 1937 if (IGB_IS_NOT_OACTIVE(txr)) {
1f7e3916
SZ
1938 ifp->if_flags &= ~IFF_OACTIVE;
1939
1f7e3916
SZ
1940 /*
1941 * We have enough TX descriptors, turn off
b6220144
SZ
1942 * the watchdog. We allow small amount of
1943 * packets (roughly intr_nsegs) pending on
1944 * the transmit ring.
1f7e3916
SZ
1945 */
1946 ifp->if_timer = 0;
1f7e3916
SZ
1947 }
1948}
1949
1950static int
1951igb_create_rx_ring(struct igb_rx_ring *rxr)
1952{
1953 int rsize, i, error;
1954
1955 /*
1956 * Validate number of receive descriptors. It must not exceed
1957 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1958 */
1959 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1960 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1961 device_printf(rxr->sc->dev,
1962 "Using %d RX descriptors instead of %d!\n",
1963 IGB_DEFAULT_RXD, igb_rxd);
91b8700a 1964 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1f7e3916 1965 } else {
91b8700a 1966 rxr->num_rx_desc = igb_rxd;
1f7e3916
SZ
1967 }
1968
1969 /*
1970 * Allocate RX descriptor ring
1971 */
91b8700a 1972 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1f7e3916
SZ
1973 IGB_DBA_ALIGN);
1974 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1975 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1976 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1977 &rxr->rxdma.dma_paddr);
1978 if (rxr->rxdma.dma_vaddr == NULL) {
1979 device_printf(rxr->sc->dev,
1980 "Unable to allocate RxDescriptor memory\n");
1981 return ENOMEM;
1982 }
1983 rxr->rx_base = rxr->rxdma.dma_vaddr;
1984 bzero(rxr->rx_base, rsize);
1985
91b8700a 1986 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1f7e3916
SZ
1987 M_DEVBUF, M_WAITOK | M_ZERO);
1988
1989 /*
1990 * Create DMA tag for RX buffers
1991 */
1992 error = bus_dma_tag_create(rxr->sc->parent_tag,
1993 1, 0, /* alignment, bounds */
1994 BUS_SPACE_MAXADDR, /* lowaddr */
1995 BUS_SPACE_MAXADDR, /* highaddr */
1996 NULL, NULL, /* filter, filterarg */
1997 MCLBYTES, /* maxsize */
1998 1, /* nsegments */
1999 MCLBYTES, /* maxsegsize */
2000 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2001 &rxr->rx_tag);
2002 if (error) {
2003 device_printf(rxr->sc->dev,
2004 "Unable to create RX payload DMA tag\n");
2005 kfree(rxr->rx_buf, M_DEVBUF);
2006 rxr->rx_buf = NULL;
2007 return error;
2008 }
2009
2010 /*
2011 * Create spare DMA map for RX buffers
2012 */
2013 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2014 &rxr->rx_sparemap);
2015 if (error) {
2016 device_printf(rxr->sc->dev,
2017 "Unable to create spare RX DMA maps\n");
2018 bus_dma_tag_destroy(rxr->rx_tag);
2019 kfree(rxr->rx_buf, M_DEVBUF);
2020 rxr->rx_buf = NULL;
2021 return error;
2022 }
2023
2024 /*
2025 * Create DMA maps for RX buffers
2026 */
91b8700a 2027 for (i = 0; i < rxr->num_rx_desc; i++) {
1f7e3916
SZ
2028 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2029
2030 error = bus_dmamap_create(rxr->rx_tag,
2031 BUS_DMA_WAITOK, &rxbuf->map);
2032 if (error) {
2033 device_printf(rxr->sc->dev,
2034 "Unable to create RX DMA maps\n");
2035 igb_destroy_rx_ring(rxr, i);
2036 return error;
2037 }
2038 }
2039 return 0;
2040}
2041
2042static void
2043igb_free_rx_ring(struct igb_rx_ring *rxr)
2044{
2045 int i;
2046
91b8700a 2047 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2048 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2049
2050 if (rxbuf->m_head != NULL) {
2051 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2052 m_freem(rxbuf->m_head);
2053 rxbuf->m_head = NULL;
2054 }
2055 }
2056
2057 if (rxr->fmp != NULL)
2058 m_freem(rxr->fmp);
2059 rxr->fmp = NULL;
2060 rxr->lmp = NULL;
2061}
2062
2063static void
2064igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2065{
2066 int i;
2067
2068 if (rxr->rxdma.dma_vaddr != NULL) {
2069 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2070 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2071 rxr->rxdma.dma_map);
2072 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2073 rxr->rxdma.dma_vaddr = NULL;
2074 }
2075
2076 if (rxr->rx_buf == NULL)
2077 return;
2078
2079 for (i = 0; i < ndesc; ++i) {
2080 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2081
2082 KKASSERT(rxbuf->m_head == NULL);
2083 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2084 }
2085 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2086 bus_dma_tag_destroy(rxr->rx_tag);
2087
2088 kfree(rxr->rx_buf, M_DEVBUF);
2089 rxr->rx_buf = NULL;
2090}
2091
2092static void
2093igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2094{
2095 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2096 rxd->wb.upper.status_error = 0;
2097}
2098
2099static int
2100igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2101{
2102 struct mbuf *m;
2103 bus_dma_segment_t seg;
2104 bus_dmamap_t map;
2105 struct igb_rx_buf *rxbuf;
2106 int error, nseg;
2107
2108 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2109 if (m == NULL) {
2110 if (wait) {
2111 if_printf(&rxr->sc->arpcom.ac_if,
2112 "Unable to allocate RX mbuf\n");
2113 }
2114 return ENOBUFS;
2115 }
2116 m->m_len = m->m_pkthdr.len = MCLBYTES;
2117
2118 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2119 m_adj(m, ETHER_ALIGN);
2120
2121 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2122 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2123 if (error) {
2124 m_freem(m);
2125 if (wait) {
2126 if_printf(&rxr->sc->arpcom.ac_if,
2127 "Unable to load RX mbuf\n");
2128 }
2129 return error;
2130 }
2131
2132 rxbuf = &rxr->rx_buf[i];
2133 if (rxbuf->m_head != NULL)
2134 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2135
2136 map = rxbuf->map;
2137 rxbuf->map = rxr->rx_sparemap;
2138 rxr->rx_sparemap = map;
2139
2140 rxbuf->m_head = m;
2141 rxbuf->paddr = seg.ds_addr;
2142
2143 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2144 return 0;
2145}
2146
2147static int
2148igb_init_rx_ring(struct igb_rx_ring *rxr)
2149{
2150 int i;
2151
2152 /* Clear the ring contents */
2153 bzero(rxr->rx_base,
91b8700a 2154 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
1f7e3916
SZ
2155
2156 /* Now replenish the ring mbufs */
91b8700a 2157 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2158 int error;
2159
2160 error = igb_newbuf(rxr, i, TRUE);
2161 if (error)
2162 return error;
2163 }
2164
2165 /* Setup our descriptor indices */
2166 rxr->next_to_check = 0;
2167
2168 rxr->fmp = NULL;
2169 rxr->lmp = NULL;
2170 rxr->discard = FALSE;
2171
2172 return 0;
2173}
2174
2175static void
2176igb_init_rx_unit(struct igb_softc *sc)
2177{
2178 struct ifnet *ifp = &sc->arpcom.ac_if;
2179 struct e1000_hw *hw = &sc->hw;
2180 uint32_t rctl, rxcsum, srrctl = 0;
2181 int i;
2182
2183 /*
2184 * Make sure receives are disabled while setting
2185 * up the descriptor ring
2186 */
2187 rctl = E1000_READ_REG(hw, E1000_RCTL);
2188 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2189
2190#if 0
2191 /*
2192 ** Set up for header split
2193 */
2194 if (igb_header_split) {
2195 /* Use a standard mbuf for the header */
2196 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2197 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2198 } else
2199#endif
2200 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2201
2202 /*
2203 ** Set up for jumbo frames
2204 */
2205 if (ifp->if_mtu > ETHERMTU) {
2206 rctl |= E1000_RCTL_LPE;
2207#if 0
2208 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2209 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2210 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2211 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2212 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2213 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2214 }
2215 /* Set maximum packet len */
2216 psize = adapter->max_frame_size;
2217 /* are we on a vlan? */
2218 if (adapter->ifp->if_vlantrunk != NULL)
2219 psize += VLAN_TAG_SIZE;
2220 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2221#else
2222 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2223 rctl |= E1000_RCTL_SZ_2048;
2224#endif
2225 } else {
2226 rctl &= ~E1000_RCTL_LPE;
2227 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2228 rctl |= E1000_RCTL_SZ_2048;
2229 }
2230
2231 /* Setup the Base and Length of the Rx Descriptor Rings */
be922da6 2232 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2233 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2234 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2235 uint32_t rxdctl;
2236
2237 E1000_WRITE_REG(hw, E1000_RDLEN(i),
91b8700a 2238 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
1f7e3916
SZ
2239 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2240 (uint32_t)(bus_addr >> 32));
2241 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2242 (uint32_t)bus_addr);
2243 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2244 /* Enable this Queue */
2245 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2246 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2247 rxdctl &= 0xFFF00000;
2248 rxdctl |= IGB_RX_PTHRESH;
2249 rxdctl |= IGB_RX_HTHRESH << 8;
54691ff1
SZ
2250 /*
2251 * Don't set WTHRESH to a value above 1 on 82576, see:
2252 * 82576 specification update errata #26
2253 */
1f7e3916
SZ
2254 rxdctl |= IGB_RX_WTHRESH << 16;
2255 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2256 }
2257
8d6600da
SZ
2258 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2259 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2260
1f7e3916 2261 /*
8d6600da
SZ
2262 * Receive Checksum Offload for TCP and UDP
2263 *
2264 * Checksum offloading is also enabled if multiple receive
2265 * queue is to be supported, since we need it to figure out
2266 * fragments.
1f7e3916 2267 */
8d6600da
SZ
2268 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2269 /*
2270 * NOTE:
2271 * PCSD must be enabled to enable multiple
2272 * receive queues.
2273 */
2274 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2275 E1000_RXCSUM_PCSD;
2276 } else {
2277 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2278 E1000_RXCSUM_PCSD);
2279 }
2280 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2281
2282 if (IGB_ENABLE_HWRSS(sc)) {
2283 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
d1218435
SZ
2284 uint32_t reta_shift;
2285 int j, r;
8d6600da
SZ
2286
2287 /*
2288 * NOTE:
2289 * When we reach here, RSS has already been disabled
2290 * in igb_stop(), so we could safely configure RSS key
2291 * and redirect table.
2292 */
2293
2294 /*
2295 * Configure RSS key
2296 */
2297 toeplitz_get_key(key, sizeof(key));
2298 for (i = 0; i < IGB_NRSSRK; ++i) {
2299 uint32_t rssrk;
2300
2301 rssrk = IGB_RSSRK_VAL(key, i);
2302 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2303
2304 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
1f7e3916 2305 }
1f7e3916
SZ
2306
2307 /*
8d6600da
SZ
2308 * Configure RSS redirect table in following fashion:
2309 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2310 */
2311 reta_shift = IGB_RETA_SHIFT;
2312 if (hw->mac.type == e1000_82575)
2313 reta_shift = IGB_RETA_SHIFT_82575;
8d6600da 2314
d1218435
SZ
2315 r = 0;
2316 for (j = 0; j < IGB_NRETA; ++j) {
2317 uint32_t reta = 0;
8d6600da 2318
d1218435
SZ
2319 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2320 uint32_t q;
2321
be922da6 2322 q = (r % sc->rx_ring_inuse) << reta_shift;
d1218435
SZ
2323 reta |= q << (8 * i);
2324 ++r;
2325 }
2326 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2327 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2328 }
8d6600da
SZ
2329
2330 /*
2331 * Enable multiple receive queues.
2332 * Enable IPv4 RSS standard hash functions.
2333 * Disable RSS interrupt on 82575
2334 */
2335 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2336 E1000_MRQC_ENABLE_RSS_4Q |
2337 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2338 E1000_MRQC_RSS_FIELD_IPV4);
1f7e3916 2339 }
1f7e3916
SZ
2340
2341 /* Setup the Receive Control Register */
2342 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2343 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2344 E1000_RCTL_RDMTS_HALF |
2345 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2346 /* Strip CRC bytes. */
2347 rctl |= E1000_RCTL_SECRC;
2348 /* Make sure VLAN Filters are off */
2349 rctl &= ~E1000_RCTL_VFE;
2350 /* Don't store bad packets */
2351 rctl &= ~E1000_RCTL_SBP;
2352
2353 /* Enable Receives */
2354 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2355
2356 /*
2357 * Setup the HW Rx Head and Tail Descriptor Pointers
2358 * - needs to be after enable
2359 */
be922da6 2360 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2361 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2362
2363 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
91b8700a 2364 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
1f7e3916
SZ
2365 }
2366}
2367
2368static void
2369igb_rxeof(struct igb_rx_ring *rxr, int count)
2370{
2371 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2372 union e1000_adv_rx_desc *cur;
2373 uint32_t staterr;
2374 int i;
2375
2376 i = rxr->next_to_check;
2377 cur = &rxr->rx_base[i];
2378 staterr = le32toh(cur->wb.upper.status_error);
2379
2380 if ((staterr & E1000_RXD_STAT_DD) == 0)
2381 return;
2382
2383 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
8d6600da 2384 struct pktinfo *pi = NULL, pi0;
1f7e3916
SZ
2385 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2386 struct mbuf *m = NULL;
2387 boolean_t eop;
2388
2389 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2390 if (eop)
2391 --count;
2392
2393 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2394 !rxr->discard) {
2395 struct mbuf *mp = rxbuf->m_head;
8d6600da 2396 uint32_t hash, hashtype;
1f7e3916
SZ
2397 uint16_t vlan;
2398 int len;
2399
2400 len = le16toh(cur->wb.upper.length);
2401 if (rxr->sc->hw.mac.type == e1000_i350 &&
2402 (staterr & E1000_RXDEXT_STATERR_LB))
2403 vlan = be16toh(cur->wb.upper.vlan);
2404 else
2405 vlan = le16toh(cur->wb.upper.vlan);
2406
8d6600da
SZ
2407 hash = le32toh(cur->wb.lower.hi_dword.rss);
2408 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2409 E1000_RXDADV_RSSTYPE_MASK;
2410
2411 IGB_RSS_DPRINTF(rxr->sc, 10,
2412 "ring%d, hash 0x%08x, hashtype %u\n",
2413 rxr->me, hash, hashtype);
2414
1f7e3916
SZ
2415 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2416 BUS_DMASYNC_POSTREAD);
2417
2418 if (igb_newbuf(rxr, i, FALSE) != 0) {
2419 ifp->if_iqdrops++;
2420 goto discard;
2421 }
2422
2423 mp->m_len = len;
2424 if (rxr->fmp == NULL) {
2425 mp->m_pkthdr.len = len;
2426 rxr->fmp = mp;
2427 rxr->lmp = mp;
2428 } else {
2429 rxr->lmp->m_next = mp;
2430 rxr->lmp = rxr->lmp->m_next;
2431 rxr->fmp->m_pkthdr.len += len;
2432 }
2433
2434 if (eop) {
2435 m = rxr->fmp;
2436 rxr->fmp = NULL;
2437 rxr->lmp = NULL;
2438
2439 m->m_pkthdr.rcvif = ifp;
2440 ifp->if_ipackets++;
2441
2442 if (ifp->if_capenable & IFCAP_RXCSUM)
2443 igb_rxcsum(staterr, m);
2444
2445 if (staterr & E1000_RXD_STAT_VP) {
2446 m->m_pkthdr.ether_vlantag = vlan;
2447 m->m_flags |= M_VLANTAG;
2448 }
2449
1f7e3916 2450 if (ifp->if_capenable & IFCAP_RSS) {
8d6600da
SZ
2451 pi = igb_rssinfo(m, &pi0,
2452 hash, hashtype, staterr);
1f7e3916 2453 }
8d6600da
SZ
2454#ifdef IGB_RSS_DEBUG
2455 rxr->rx_packets++;
1f7e3916
SZ
2456#endif
2457 }
2458 } else {
2459 ifp->if_ierrors++;
2460discard:
2461 igb_setup_rxdesc(cur, rxbuf);
2462 if (!eop)
2463 rxr->discard = TRUE;
2464 else
2465 rxr->discard = FALSE;
2466 if (rxr->fmp != NULL) {
2467 m_freem(rxr->fmp);
2468 rxr->fmp = NULL;
2469 rxr->lmp = NULL;
2470 }
2471 m = NULL;
2472 }
2473
2474 if (m != NULL)
8d6600da 2475 ether_input_pkt(ifp, m, pi);
1f7e3916
SZ
2476
2477 /* Advance our pointers to the next descriptor. */
91b8700a 2478 if (++i == rxr->num_rx_desc)
1f7e3916
SZ
2479 i = 0;
2480
2481 cur = &rxr->rx_base[i];
2482 staterr = le32toh(cur->wb.upper.status_error);
2483 }
2484 rxr->next_to_check = i;
2485
2486 if (--i < 0)
91b8700a 2487 i = rxr->num_rx_desc - 1;
1f7e3916
SZ
2488 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2489}
2490
2491
2492static void
2493igb_set_vlan(struct igb_softc *sc)
2494{
2495 struct e1000_hw *hw = &sc->hw;
2496 uint32_t reg;
2497#if 0
2498 struct ifnet *ifp = sc->arpcom.ac_if;
2499#endif
2500
2501 if (sc->vf_ifp) {
2502 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2503 return;
2504 }
2505
2506 reg = E1000_READ_REG(hw, E1000_CTRL);
2507 reg |= E1000_CTRL_VME;
2508 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2509
2510#if 0
2511 /* Enable the Filter Table */
2512 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2513 reg = E1000_READ_REG(hw, E1000_RCTL);
2514 reg &= ~E1000_RCTL_CFIEN;
2515 reg |= E1000_RCTL_VFE;
2516 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2517 }
2518#endif
2519
2520 /* Update the frame size */
2521 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2522 sc->max_frame_size + VLAN_TAG_SIZE);
2523
2524#if 0
2525 /* Don't bother with table if no vlans */
2526 if ((adapter->num_vlans == 0) ||
2527 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2528 return;
2529 /*
2530 ** A soft reset zero's out the VFTA, so
2531 ** we need to repopulate it now.
2532 */
2533 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2534 if (adapter->shadow_vfta[i] != 0) {
2535 if (adapter->vf_ifp)
2536 e1000_vfta_set_vf(hw,
2537 adapter->shadow_vfta[i], TRUE);
2538 else
2539 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2540 i, adapter->shadow_vfta[i]);
2541 }
2542#endif
2543}
2544
2545static void
2546igb_enable_intr(struct igb_softc *sc)
2547{
9c0ecdcc
SZ
2548 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2549 lwkt_serialize_handler_enable(&sc->main_serialize);
2550 } else {
2551 int i;
2552
2553 for (i = 0; i < sc->msix_cnt; ++i) {
2554 lwkt_serialize_handler_enable(
2555 sc->msix_data[i].msix_serialize);
2556 }
2557 }
1f7e3916 2558
f6167a56 2559 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
9c0ecdcc
SZ
2560 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2561 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2562 else
2563 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56
SZ
2564 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2565 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
1f7e3916
SZ
2566 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2567 } else {
2568 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2569 }
2570 E1000_WRITE_FLUSH(&sc->hw);
2571}
2572
2573static void
2574igb_disable_intr(struct igb_softc *sc)
2575{
f6167a56 2576 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
1f7e3916
SZ
2577 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2578 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56 2579 }
1f7e3916
SZ
2580 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2581 E1000_WRITE_FLUSH(&sc->hw);
2582
9c0ecdcc
SZ
2583 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2584 lwkt_serialize_handler_disable(&sc->main_serialize);
2585 } else {
2586 int i;
2587
2588 for (i = 0; i < sc->msix_cnt; ++i) {
2589 lwkt_serialize_handler_disable(
2590 sc->msix_data[i].msix_serialize);
2591 }
2592 }
1f7e3916
SZ
2593}
2594
2595/*
2596 * Bit of a misnomer, what this really means is
2597 * to enable OS management of the system... aka
2598 * to disable special hardware management features
2599 */
2600static void
2601igb_get_mgmt(struct igb_softc *sc)
2602{
396b7048 2603 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2604 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2605 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2606
2607 /* disable hardware interception of ARP */
2608 manc &= ~E1000_MANC_ARP_EN;
2609
2610 /* enable receiving management packets to the host */
2611 manc |= E1000_MANC_EN_MNG2HOST;
2612 manc2h |= 1 << 5; /* Mng Port 623 */
2613 manc2h |= 1 << 6; /* Mng Port 664 */
2614 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2615 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2616 }
2617}
2618
2619/*
2620 * Give control back to hardware management controller
2621 * if there is one.
2622 */
2623static void
2624igb_rel_mgmt(struct igb_softc *sc)
2625{
396b7048 2626 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2627 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2628
2629 /* Re-enable hardware interception of ARP */
2630 manc |= E1000_MANC_ARP_EN;
2631 manc &= ~E1000_MANC_EN_MNG2HOST;
2632
2633 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2634 }
2635}
2636
2637/*
2638 * Sets CTRL_EXT:DRV_LOAD bit.
2639 *
2640 * For ASF and Pass Through versions of f/w this means that
2641 * the driver is loaded.
2642 */
2643static void
2644igb_get_hw_control(struct igb_softc *sc)
2645{
2646 uint32_t ctrl_ext;
2647
2648 if (sc->vf_ifp)
2649 return;
2650
2651 /* Let firmware know the driver has taken over */
2652 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2653 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2654 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2655}
2656
2657/*
2658 * Resets CTRL_EXT:DRV_LOAD bit.
2659 *
2660 * For ASF and Pass Through versions of f/w this means that the
2661 * driver is no longer loaded.
2662 */
2663static void
2664igb_rel_hw_control(struct igb_softc *sc)
2665{
2666 uint32_t ctrl_ext;
2667
2668 if (sc->vf_ifp)
2669 return;
2670
2671 /* Let firmware taken over control of h/w */
2672 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2673 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2674 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2675}
2676
2677static int
2678igb_is_valid_ether_addr(const uint8_t *addr)
2679{
2680 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2681
2682 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2683 return FALSE;
2684 return TRUE;
2685}
2686
2687/*
2688 * Enable PCI Wake On Lan capability
2689 */
2690static void
2691igb_enable_wol(device_t dev)
2692{
2693 uint16_t cap, status;
2694 uint8_t id;
2695
2696 /* First find the capabilities pointer*/
2697 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2698
2699 /* Read the PM Capabilities */
2700 id = pci_read_config(dev, cap, 1);
2701 if (id != PCIY_PMG) /* Something wrong */
2702 return;
2703
2704 /*
2705 * OK, we have the power capabilities,
2706 * so now get the status register
2707 */
2708 cap += PCIR_POWER_STATUS;
2709 status = pci_read_config(dev, cap, 2);
2710 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2711 pci_write_config(dev, cap, status, 2);
2712}
2713
2714static void
2715igb_update_stats_counters(struct igb_softc *sc)
2716{
2717 struct e1000_hw *hw = &sc->hw;
2718 struct e1000_hw_stats *stats;
2719 struct ifnet *ifp = &sc->arpcom.ac_if;
2720
2721 /*
2722 * The virtual function adapter has only a
2723 * small controlled set of stats, do only
2724 * those and return.
2725 */
2726 if (sc->vf_ifp) {
2727 igb_update_vf_stats_counters(sc);
2728 return;
2729 }
2730 stats = sc->stats;
2731
2732 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2733 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2734 stats->symerrs +=
2735 E1000_READ_REG(hw,E1000_SYMERRS);
2736 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2737 }
2738
2739 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2740 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2741 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2742 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2743
2744 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2745 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2746 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2747 stats->dc += E1000_READ_REG(hw, E1000_DC);
2748 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2749 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2750 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2751
2752 /*
2753 * For watchdog management we need to know if we have been
2754 * paused during the last interval, so capture that here.
2755 */
2756 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2757 stats->xoffrxc += sc->pause_frames;
2758 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2759 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2760 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2761 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2762 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2763 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2764 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2765 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2766 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2767 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2768 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2769 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2770
2771 /* For the 64-bit byte counters the low dword must be read first. */
2772 /* Both registers clear on the read of the high dword */
2773
2774 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2775 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2776 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2777 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2778
2779 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2780 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2781 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2782 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2783 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2784
2785 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2786 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2787
2788 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2789 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2790 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2791 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2792 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2793 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2794 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2795 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2796 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2797 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2798
2799 /* Interrupt Counts */
2800
2801 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2802 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2803 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2804 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2805 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2806 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2807 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2808 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2809 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2810
2811 /* Host to Card Statistics */
2812
2813 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2814 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2815 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2816 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2817 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2818 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2819 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2820 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2821 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2822 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2823 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2824 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2825 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2826 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2827
2828 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2829 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2830 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2831 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2832 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2833 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2834
2835 ifp->if_collisions = stats->colc;
2836
2837 /* Rx Errors */
2838 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2839 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2840
2841 /* Tx Errors */
2842 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2843
2844 /* Driver specific counters */
2845 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2846 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2847 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2848 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2849 sc->packet_buf_alloc_tx =
2850 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2851 sc->packet_buf_alloc_rx =
2852 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2853}
2854
2855static void
2856igb_vf_init_stats(struct igb_softc *sc)
2857{
2858 struct e1000_hw *hw = &sc->hw;
2859 struct e1000_vf_stats *stats;
2860
2861 stats = sc->stats;
2862 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2863 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2864 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2865 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2866 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2867}
2868
2869static void
2870igb_update_vf_stats_counters(struct igb_softc *sc)
2871{
2872 struct e1000_hw *hw = &sc->hw;
2873 struct e1000_vf_stats *stats;
2874
2875 if (sc->link_speed == 0)
2876 return;
2877
2878 stats = sc->stats;
2879 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2880 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2881 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2882 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2883 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2884}
2885
2886#ifdef DEVICE_POLLING
2887
2888static void
2889igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2890{
2891 struct igb_softc *sc = ifp->if_softc;
2892 uint32_t reg_icr;
2893
1f7e3916
SZ
2894 switch (cmd) {
2895 case POLL_REGISTER:
1f7e3916 2896 case POLL_DEREGISTER:
9c0ecdcc
SZ
2897 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2898 igb_init(sc);
1f7e3916
SZ
2899 break;
2900
2901 case POLL_AND_CHECK_STATUS:
9c0ecdcc 2902 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2903 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2904 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2905 sc->hw.mac.get_link_status = 1;
2906 igb_update_link_status(sc);
2907 }
2908 /* FALL THROUGH */
2909 case POLL_ONLY:
9c0ecdcc 2910 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916 2911 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2912 struct igb_tx_ring *txr;
2913 int i;
2914
be922da6 2915 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2916 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2917
2918 lwkt_serialize_enter(&rxr->rx_serialize);
2919 igb_rxeof(rxr, count);
2920 lwkt_serialize_exit(&rxr->rx_serialize);
2921 }
1f7e3916 2922
7d235eb5
SZ
2923 txr = &sc->tx_rings[0];
2924 lwkt_serialize_enter(&txr->tx_serialize);
2925 igb_txeof(txr);
1f7e3916
SZ
2926 if (!ifq_is_empty(&ifp->if_snd))
2927 if_devstart(ifp);
7d235eb5 2928 lwkt_serialize_exit(&txr->tx_serialize);
1f7e3916
SZ
2929 }
2930 break;
2931 }
2932}
2933
2934#endif /* DEVICE_POLLING */
2935
2936static void
2937igb_intr(void *xsc)
2938{
2939 struct igb_softc *sc = xsc;
2940 struct ifnet *ifp = &sc->arpcom.ac_if;
f6167a56
SZ
2941 uint32_t eicr;
2942
7d235eb5 2943 ASSERT_SERIALIZED(&sc->main_serialize);
f6167a56
SZ
2944
2945 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2946
2947 if (eicr == 0)
2948 return;
2949
2950 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2951 struct igb_tx_ring *txr;
2952 int i;
f6167a56 2953
be922da6 2954 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2955 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2956
2957 if (eicr & rxr->rx_intr_mask) {
2958 lwkt_serialize_enter(&rxr->rx_serialize);
2959 igb_rxeof(rxr, -1);
2960 lwkt_serialize_exit(&rxr->rx_serialize);
2961 }
2962 }
2963
2964 txr = &sc->tx_rings[0];
2965 if (eicr & txr->tx_intr_mask) {
2966 lwkt_serialize_enter(&txr->tx_serialize);
2967 igb_txeof(txr);
f6167a56
SZ
2968 if (!ifq_is_empty(&ifp->if_snd))
2969 if_devstart(ifp);
7d235eb5 2970 lwkt_serialize_exit(&txr->tx_serialize);
f6167a56
SZ
2971 }
2972 }
2973
2974 if (eicr & E1000_EICR_OTHER) {
2975 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2976
2977 /* Link status change */
2978 if (icr & E1000_ICR_LSC) {
2979 sc->hw.mac.get_link_status = 1;
2980 igb_update_link_status(sc);
2981 }
2982 }
2983
2984 /*
2985 * Reading EICR has the side effect to clear interrupt mask,
2986 * so all interrupts need to be enabled here.
2987 */
2988 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2989}
2990
2991static void
9c0ecdcc 2992igb_intr_shared(void *xsc)
f6167a56
SZ
2993{
2994 struct igb_softc *sc = xsc;
2995 struct ifnet *ifp = &sc->arpcom.ac_if;
1f7e3916
SZ
2996 uint32_t reg_icr;
2997
7d235eb5 2998 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2999
3000 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3001
3002 /* Hot eject? */
3003 if (reg_icr == 0xffffffff)
3004 return;
3005
3006 /* Definitely not our interrupt. */
3007 if (reg_icr == 0x0)
3008 return;
3009
3010 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3011 return;
3012
3013 if (ifp->if_flags & IFF_RUNNING) {
71b8b086
SZ
3014 if (reg_icr &
3015 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3016 int i;
7d235eb5 3017
71b8b086
SZ
3018 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3019 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1f7e3916 3020
71b8b086
SZ
3021 lwkt_serialize_enter(&rxr->rx_serialize);
3022 igb_rxeof(rxr, -1);
3023 lwkt_serialize_exit(&rxr->rx_serialize);
3024 }
7d235eb5
SZ
3025 }
3026
71b8b086
SZ
3027 if (reg_icr & E1000_ICR_TXDW) {
3028 struct igb_tx_ring *txr = &sc->tx_rings[0];
3029
3030 lwkt_serialize_enter(&txr->tx_serialize);
3031 igb_txeof(txr);
3032 if (!ifq_is_empty(&ifp->if_snd))
3033 if_devstart(ifp);
3034 lwkt_serialize_exit(&txr->tx_serialize);
3035 }
1f7e3916
SZ
3036 }
3037
3038 /* Link status change */
3039 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3040 sc->hw.mac.get_link_status = 1;
3041 igb_update_link_status(sc);
3042 }
3043
3044 if (reg_icr & E1000_ICR_RXO)
3045 sc->rx_overruns++;
3046}
3047
3048static int
1f7e3916
SZ
3049igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3050{
3051 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3052 bus_dmamap_t map;
3053 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3054 union e1000_adv_tx_desc *txd = NULL;
3055 struct mbuf *m_head = *m_headp;
b6220144
SZ
3056 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3057 int maxsegs, nsegs, i, j, error, last = 0;
1f7e3916
SZ
3058 uint32_t hdrlen = 0;
3059
23f6ffe4
SZ
3060 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3061 error = igb_tso_pullup(txr, m_headp);
3062 if (error)
3063 return error;
3064 m_head = *m_headp;
3065 }
3066
1f7e3916
SZ
3067 /* Set basic descriptor constants */
3068 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3069 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3070 if (m_head->m_flags & M_VLANTAG)
3071 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3072
3073 /*
3074 * Map the packet for DMA.
1f7e3916 3075 */
b6220144 3076 tx_buf = &txr->tx_buf[txr->next_avail_desc];
1f7e3916
SZ
3077 tx_buf_mapped = tx_buf;
3078 map = tx_buf->map;
3079
b6220144
SZ
3080 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3081 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
1f7e3916
SZ
3082 if (maxsegs > IGB_MAX_SCATTER)
3083 maxsegs = IGB_MAX_SCATTER;
3084
3085 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3086 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3087 if (error) {
3088 if (error == ENOBUFS)
3089 txr->sc->mbuf_defrag_failed++;
3090 else
3091 txr->sc->no_tx_dma_setup++;
3092
3093 m_freem(*m_headp);
3094 *m_headp = NULL;
3095 return error;
3096 }
3097 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3098
3099 m_head = *m_headp;
3100
1f7e3916 3101 /*
66c68b4b
SZ
3102 * Set up the TX context descriptor, if any hardware offloading is
3103 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3104 * TX descriptor.
3105 *
3106 * Unlike these chips' predecessors (em/emx), TX context descriptor
3107 * will _not_ interfere TX data fetching pipelining.
1f7e3916
SZ
3108 */
3109 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
23f6ffe4
SZ
3110 igb_tso_ctx(txr, m_head, &hdrlen);
3111 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3112 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3113 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3114 txr->tx_nsegs++;
3115 } else if (igb_txcsum_ctx(txr, m_head)) {
48faa653
SZ
3116 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3117 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
1f7e3916
SZ
3118 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3119 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
b6220144 3120 txr->tx_nsegs++;
1f7e3916 3121 }
1f7e3916 3122
b6220144
SZ
3123 txr->tx_nsegs += nsegs;
3124 if (txr->tx_nsegs >= txr->intr_nsegs) {
3125 /*
3126 * Report Status (RS) is turned on every intr_nsegs
3127 * descriptors (roughly).
3128 */
3129 txr->tx_nsegs = 0;
3130 cmd_rs = E1000_ADVTXD_DCMD_RS;
3131 }
3132
1f7e3916
SZ
3133 /* Calculate payload length */
3134 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3135 << E1000_ADVTXD_PAYLEN_SHIFT);
3136
3137 /* 82575 needs the queue index added */
3138 if (txr->sc->hw.mac.type == e1000_82575)
3139 olinfo_status |= txr->me << 4;
3140
3141 /* Set up our transmit descriptors */
3142 i = txr->next_avail_desc;
3143 for (j = 0; j < nsegs; j++) {
3144 bus_size_t seg_len;
3145 bus_addr_t seg_addr;
3146
3147 tx_buf = &txr->tx_buf[i];
3148 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3149 seg_addr = segs[j].ds_addr;
3150 seg_len = segs[j].ds_len;
3151
3152 txd->read.buffer_addr = htole64(seg_addr);
3153 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3154 txd->read.olinfo_status = htole32(olinfo_status);
3155 last = i;
91b8700a 3156 if (++i == txr->num_tx_desc)
1f7e3916
SZ
3157 i = 0;
3158 tx_buf->m_head = NULL;
1f7e3916
SZ
3159 }
3160
3161 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3162 txr->next_avail_desc = i;
3163 txr->tx_avail -= nsegs;
3164
3165 tx_buf->m_head = m_head;
3166 tx_buf_mapped->map = tx_buf->map;
3167 tx_buf->map = map;
3168
3169 /*
b6220144 3170 * Last Descriptor of Packet needs End Of Packet (EOP)
1f7e3916 3171 */
b6220144 3172 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
1f7e3916
SZ
3173
3174 /*
3175 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3176 * that this frame is available to transmit.
3177 */
3178 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3179 ++txr->tx_packets;
3180
3181 return 0;
3182}
3183
3184static void
3185igb_start(struct ifnet *ifp)
3186{
3187 struct igb_softc *sc = ifp->if_softc;
27866bf1 3188 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3189 struct mbuf *m_head;
3190
7d235eb5 3191 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3192
9c0ecdcc 3193 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1f7e3916
SZ
3194 return;
3195
3196 if (!sc->link_active) {
3197 ifq_purge(&ifp->if_snd);
3198 return;
3199 }
3200
b6220144 3201 if (!IGB_IS_NOT_OACTIVE(txr))
1f7e3916
SZ
3202 igb_txeof(txr);
3203
3204 while (!ifq_is_empty(&ifp->if_snd)) {
b6220144 3205 if (IGB_IS_OACTIVE(txr)) {
1f7e3916
SZ
3206 ifp->if_flags |= IFF_OACTIVE;
3207 /* Set watchdog on */
3208 ifp->if_timer = 5;
3209 break;
3210 }
3211
3212 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3213 if (m_head == NULL)
3214 break;
3215
3216 if (igb_encap(txr, &m_head)) {
3217 ifp->if_oerrors++;
3218 continue;
3219 }
3220
3221 /* Send a copy of the frame to the BPF listener */
3222 ETHER_BPF_MTAP(ifp, m_head);
3223 }
3224}
3225
3226static void
3227igb_watchdog(struct ifnet *ifp)
3228{
3229 struct igb_softc *sc = ifp->if_softc;
27866bf1 3230 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3231
3232 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3233
3234 /*
3235 * If flow control has paused us since last checking
3236 * it invalidates the watchdog timing, so dont run it.
3237 */
3238 if (sc->pause_frames) {
3239 sc->pause_frames = 0;
3240 ifp->if_timer = 5;
3241 return;
3242 }
3243
3244 if_printf(ifp, "Watchdog timeout -- resetting\n");
3245 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3246 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3247 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3248 if_printf(ifp, "TX(%d) desc avail = %d, "
3249 "Next TX to Clean = %d\n",
3250 txr->me, txr->tx_avail, txr->next_to_clean);
3251
3252 ifp->if_oerrors++;
3253 sc->watchdog_events++;
3254
3255 igb_init(sc);
3256 if (!ifq_is_empty(&ifp->if_snd))
3257 if_devstart(ifp);
3258}
3259
3260static void
9c0ecdcc 3261igb_set_eitr(struct igb_softc *sc, int idx, int rate)
1f7e3916 3262{
9c0ecdcc 3263 uint32_t eitr = 0;
1f7e3916 3264
9c0ecdcc 3265 if (rate > 0) {
1f7e3916 3266 if (sc->hw.mac.type == e1000_82575) {
9c0ecdcc 3267 eitr = 1000000000 / 256 / rate;
1f7e3916
SZ
3268 /*
3269 * NOTE:
3270 * Document is wrong on the 2 bits left shift
3271 */
3272 } else {
9c0ecdcc 3273 eitr = 1000000 / rate;
d4beffa9
SZ
3274 eitr <<= IGB_EITR_INTVL_SHIFT;
3275 }
3276
3277 if (eitr == 0) {
3278 /* Don't disable it */
3279 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3280 } else if (eitr > IGB_EITR_INTVL_MASK) {
3281 /* Don't allow it to be too large */
3282 eitr = IGB_EITR_INTVL_MASK;
1f7e3916 3283 }
1f7e3916
SZ
3284 }
3285 if (sc->hw.mac.type == e1000_82575)
9c0ecdcc 3286 eitr |= eitr << 16;
1f7e3916 3287 else
9c0ecdcc
SZ
3288 eitr |= E1000_EITR_CNT_IGNR;
3289 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
1f7e3916
SZ
3290}
3291
3292static int
3293igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3294{
3295 struct igb_softc *sc = (void *)arg1;
3296 struct ifnet *ifp = &sc->arpcom.ac_if;
3297 int error, intr_rate;
3298
3299 intr_rate = sc->intr_rate;
3300 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3301 if (error || req->newptr == NULL)
3302 return error;
3303 if (intr_rate < 0)
3304 return EINVAL;
3305
3306 ifnet_serialize_all(ifp);
3307
3308 sc->intr_rate = intr_rate;
3309 if (ifp->if_flags & IFF_RUNNING)
9c0ecdcc
SZ
3310 igb_set_eitr(sc, 0, sc->intr_rate);
3311
3312 if (bootverbose)
3313 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
1f7e3916
SZ
3314
3315 ifnet_deserialize_all(ifp);
3316
9c0ecdcc
SZ
3317 return 0;
3318}
3319
3320static int
3321igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3322{
3323 struct igb_msix_data *msix = (void *)arg1;
3324 struct igb_softc *sc = msix->msix_sc;
3325 struct ifnet *ifp = &sc->arpcom.ac_if;
3326 int error, msix_rate;
3327
3328 msix_rate = msix->msix_rate;
3329 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3330 if (error || req->newptr == NULL)
3331 return error;
3332 if (msix_rate < 0)
3333 return EINVAL;
3334
3335 lwkt_serialize_enter(msix->msix_serialize);
3336
3337 msix->msix_rate = msix_rate;
3338 if (ifp->if_flags & IFF_RUNNING)
3339 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3340
3341 if (bootverbose) {
3342 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3343 msix->msix_rate);
3344 }
3345
3346 lwkt_serialize_exit(msix->msix_serialize);
3347
1f7e3916
SZ
3348 return 0;
3349}
b6220144
SZ
3350
3351static int
3352igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3353{
3354 struct igb_softc *sc = (void *)arg1;
3355 struct ifnet *ifp = &sc->arpcom.ac_if;
27866bf1 3356 struct igb_tx_ring *txr = &sc->tx_rings[0];
b6220144
SZ
3357 int error, nsegs;
3358
3359 nsegs = txr->intr_nsegs;
3360 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3361 if (error || req->newptr == NULL)
3362 return error;
3363 if (nsegs <= 0)
3364 return EINVAL;
3365
3366 ifnet_serialize_all(ifp);
3367
91b8700a 3368 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
b6220144
SZ
3369 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3370 error = EINVAL;
3371 } else {
3372 error = 0;
3373 txr->intr_nsegs = nsegs;
3374 }
3375
3376 ifnet_deserialize_all(ifp);
3377
3378 return error;
3379}
f6167a56
SZ
3380
3381static void
3382igb_init_intr(struct igb_softc *sc)
3383{
be922da6 3384 igb_set_intr_mask(sc);
9c0ecdcc
SZ
3385
3386 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
f6167a56 3387 igb_init_unshared_intr(sc);
9c0ecdcc
SZ
3388
3389 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3390 igb_set_eitr(sc, 0, sc->intr_rate);
3391 } else {
3392 int i;
3393
3394 for (i = 0; i < sc->msix_cnt; ++i)
3395 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3396 }
f6167a56
SZ
3397}
3398
3399static void
3400igb_init_unshared_intr(struct igb_softc *sc)
3401{
3402 struct e1000_hw *hw = &sc->hw;
3403 const struct igb_rx_ring *rxr;
3404 const struct igb_tx_ring *txr;
3405 uint32_t ivar, index;
3406 int i;
3407
3408 /*
3409 * Enable extended mode
3410 */
3411 if (sc->hw.mac.type != e1000_82575) {
9c0ecdcc
SZ
3412 uint32_t gpie;
3413 int ivar_max;
3414
3415 gpie = E1000_GPIE_NSICR;
3416 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3417 gpie |= E1000_GPIE_MSIX_MODE |
3418 E1000_GPIE_EIAME |
3419 E1000_GPIE_PBA;
3420 }
3421 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3422
3423 /*
3424 * Clear IVARs
3425 */
3426 switch (sc->hw.mac.type) {
3427 case e1000_82580:
3428 ivar_max = IGB_MAX_IVAR_82580;
3429 break;
3430
3431 case e1000_i350:
3432 ivar_max = IGB_MAX_IVAR_I350;
3433 break;
3434
3435 case e1000_vfadapt:
3436 case e1000_vfadapt_i350:
3437 ivar_max = IGB_MAX_IVAR_VF;
3438 break;
3439
3440 case e1000_82576:
3441 ivar_max = IGB_MAX_IVAR_82576;
3442 break;
3443
3444 default:
3445 panic("unknown mac type %d\n", sc->hw.mac.type);
3446 }
3447 for (i = 0; i < ivar_max; ++i)
3448 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3449 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
f6167a56
SZ
3450 } else {
3451 uint32_t tmp;
3452
9c0ecdcc
SZ
3453 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3454 ("82575 w/ MSI-X"));
f6167a56
SZ
3455 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3456 tmp |= E1000_CTRL_EXT_IRCA;
3457 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3458 }
3459
3460 /*
3461 * Map TX/RX interrupts to EICR
3462 */
3463 switch (sc->hw.mac.type) {
3464 case e1000_82580:
3465 case e1000_i350:
3466 case e1000_vfadapt:
3467 case e1000_vfadapt_i350:
3468 /* RX entries */
be922da6 3469 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3470 rxr = &sc->rx_rings[i];
3471
3472 index = i >> 1;
3473 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3474
3475 if (i & 1) {
3476 ivar &= 0xff00ffff;
3477 ivar |=
3478 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3479 } else {
3480 ivar &= 0xffffff00;
3481 ivar |=
3482 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3483 }
3484 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3485 }
3486 /* TX entries */
27866bf1 3487 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3488 txr = &sc->tx_rings[i];
3489
3490 index = i >> 1;
3491 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3492
3493 if (i & 1) {
3494 ivar &= 0x00ffffff;
3495 ivar |=
3496 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3497 } else {
3498 ivar &= 0xffff00ff;
3499 ivar |=
3500 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3501 }
3502 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3503 }
9c0ecdcc
SZ
3504 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3505 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3506 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3507 }
f6167a56
SZ
3508 break;
3509
3510 case e1000_82576:
3511 /* RX entries */
be922da6 3512 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3513 rxr = &sc->rx_rings[i];
3514
3515 index = i & 0x7; /* Each IVAR has two entries */
3516 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3517
3518 if (i < 8) {
3519 ivar &= 0xffffff00;
3520 ivar |=
3521 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3522 } else {
3523 ivar &= 0xff00ffff;
3524 ivar |=
3525 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3526 }
3527 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3528 }
3529 /* TX entries */
27866bf1 3530 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3531 txr = &sc->tx_rings[i];
3532
3533 index = i & 0x7; /* Each IVAR has two entries */
3534 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3535
3536 if (i < 8) {
3537 ivar &= 0xffff00ff;
3538 ivar |=
3539 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3540 } else {
3541 ivar &= 0x00ffffff;
3542 ivar |=
3543 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3544 }
3545 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3546 }
9c0ecdcc
SZ
3547 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3548 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3549 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3550 }
f6167a56
SZ
3551 break;
3552
3553 case e1000_82575:
3554 /*
3555 * Enable necessary interrupt bits.
3556 *
3557 * The name of the register is confusing; in addition to
3558 * configuring the first vector of MSI-X, it also configures
3559 * which bits of EICR could be set by the hardware even when
3560 * MSI or line interrupt is used; it thus controls interrupt
3561 * generation. It MUST be configured explicitly; the default
3562 * value mentioned in the datasheet is wrong: RX queue0 and
3563 * TX queue0 are NOT enabled by default.
3564 */
3565 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3566 break;
3567
3568 default:
9c0ecdcc 3569 panic("unknown mac type %d\n", sc->hw.mac.type);
f6167a56 3570 }
f6167a56
SZ
3571}
3572
3573static int
3574igb_setup_intr(struct igb_softc *sc)
3575{
3576 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 3577 int error;
f6167a56 3578
9c0ecdcc
SZ
3579 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3580 return igb_msix_setup(sc);
f6167a56 3581
f6167a56 3582 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
9c0ecdcc 3583 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
7d235eb5 3584 sc, &sc->intr_tag, &sc->main_serialize);
f6167a56
SZ
3585 if (error) {
3586 device_printf(sc->dev, "Failed to register interrupt handler");
3587 return error;
3588 }
3589
3590 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3591 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3592
3593 return 0;
3594}
3595
3596static void
9c0ecdcc 3597igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3598{
3599 if (txr->sc->hw.mac.type == e1000_82575) {
3600 txr->tx_intr_bit = 0; /* unused */
3601 switch (txr->me) {
3602 case 0:
3603 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3604 break;
3605 case 1:
3606 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3607 break;
3608 case 2:
3609 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3610 break;
3611 case 3:
3612 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3613 break;
3614 default:
3615 panic("unsupported # of TX ring, %d\n", txr->me);
3616 }
3617 } else {
8d6600da
SZ
3618 int intr_bit = *intr_bit0;
3619
3620 txr->tx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3621 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
8d6600da
SZ
3622
3623 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3624 }
3625}
3626
3627static void
9c0ecdcc 3628igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3629{
3630 if (rxr->sc->hw.mac.type == e1000_82575) {
3631 rxr->rx_intr_bit = 0; /* unused */
3632 switch (rxr->me) {
3633 case 0:
3634 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3635 break;
3636 case 1:
3637 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3638 break;
3639 case 2:
3640 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3641 break;
3642 case 3:
3643 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3644 break;
3645 default:
3646 panic("unsupported # of RX ring, %d\n", rxr->me);
3647 }
3648 } else {
8d6600da
SZ
3649 int intr_bit = *intr_bit0;
3650
3651 rxr->rx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3652 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
8d6600da
SZ
3653
3654 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3655 }
3656}
7d235eb5
SZ
3657
3658static void
3659igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3660{
3661 struct igb_softc *sc = ifp->if_softc;
3662
3663 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3664 sc->tx_serialize, sc->rx_serialize, slz);
3665}
3666
3667static void
3668igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3669{
3670 struct igb_softc *sc = ifp->if_softc;
3671
3672 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3673 sc->tx_serialize, sc->rx_serialize, slz);
3674}
3675
3676static int
3677igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3678{
3679 struct igb_softc *sc = ifp->if_softc;
3680
3681 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3682 sc->tx_serialize, sc->rx_serialize, slz);
3683}
3684
7d235eb5
SZ
3685#ifdef INVARIANTS
3686
3687static void
3688igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3689 boolean_t serialized)
3690{
3691 struct igb_softc *sc = ifp->if_softc;
3692
3693 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3694 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3695}
3696
3697#endif /* INVARIANTS */
be922da6
SZ
3698
3699static void
3700igb_set_intr_mask(struct igb_softc *sc)
3701{
3702 int i;
3703
9c0ecdcc 3704 sc->intr_mask = sc->sts_intr_mask;
be922da6
SZ
3705 for (i = 0; i < sc->rx_ring_inuse; ++i)
3706 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3707 for (i = 0; i < sc->tx_ring_cnt; ++i)
3708 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
62be5890
SZ
3709 if (bootverbose) {
3710 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3711 sc->intr_mask);
3712 }
be922da6 3713}
3c7cc5e2
SZ
3714
3715static int
3716igb_alloc_intr(struct igb_softc *sc)
3717{
9c0ecdcc 3718 int i, intr_bit, intr_bitmax;
3c7cc5e2
SZ
3719 u_int intr_flags;
3720
9c0ecdcc
SZ
3721 igb_msix_try_alloc(sc);
3722 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3723 goto done;
3724
3725 /*
3726 * Allocate MSI/legacy interrupt resource
3727 */
3c7cc5e2
SZ
3728 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3729 &sc->intr_rid, &intr_flags);
3730
677d7b99
SZ
3731 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3732 int unshared;
3733
3734 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3735 if (!unshared) {
3736 sc->flags |= IGB_FLAG_SHARED_INTR;
3737 if (bootverbose)
3738 device_printf(sc->dev, "IRQ shared\n");
3739 } else {
3740 intr_flags &= ~RF_SHAREABLE;
3741 if (bootverbose)
3742 device_printf(sc->dev, "IRQ unshared\n");
3743 }
3744 }
3745
3c7cc5e2
SZ
3746 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3747 &sc->intr_rid, intr_flags);
3748 if (sc->intr_res == NULL) {
3749 device_printf(sc->dev, "Unable to allocate bus resource: "
3750 "interrupt\n");
3751 return ENXIO;
3752 }
9c0ecdcc
SZ
3753
3754 /*
3755 * Setup MSI/legacy interrupt mask
3756 */
3757 switch (sc->hw.mac.type) {
3758 case e1000_82575:
3759 intr_bitmax = IGB_MAX_TXRXINT_82575;
3760 break;
3761 case e1000_82580:
3762 intr_bitmax = IGB_MAX_TXRXINT_82580;
3763 break;
3764 case e1000_i350:
3765 intr_bitmax = IGB_MAX_TXRXINT_I350;
3766 break;
3767 case e1000_82576:
3768 intr_bitmax = IGB_MAX_TXRXINT_82576;
3769 break;
3770 default:
3771 intr_bitmax = IGB_MIN_TXRXINT;
3772 break;
3773 }
3774 intr_bit = 0;
3775 for (i = 0; i < sc->tx_ring_cnt; ++i)
3776 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3777 for (i = 0; i < sc->rx_ring_cnt; ++i)
3778 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3779 sc->sts_intr_bit = 0;
3780 sc->sts_intr_mask = E1000_EICR_OTHER;
3781
3782 /* Initialize interrupt rate */
3783 sc->intr_rate = IGB_INTR_RATE;
3784done:
3785 igb_set_ring_inuse(sc, FALSE);
3786 igb_set_intr_mask(sc);
3c7cc5e2
SZ
3787 return 0;
3788}
3789
3790static void
3791igb_free_intr(struct igb_softc *sc)
3792{
9c0ecdcc
SZ
3793 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3794 if (sc->intr_res != NULL) {
3795 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3796 sc->intr_res);
3797 }
3798 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3799 pci_release_msi(sc->dev);
3800 } else {
3801 igb_msix_free(sc, TRUE);
3802 }
3803}
3804
3805static void
3806igb_teardown_intr(struct igb_softc *sc)
3807{
3808 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3809 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3810 else
3811 igb_msix_teardown(sc, sc->msix_cnt);
3812}
3813
3814static void
3815igb_msix_try_alloc(struct igb_softc *sc)
3816{
3817 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3818 int i, x, error;
3819 struct igb_msix_data *msix;
3820 boolean_t aggregate, setup = FALSE;
3821
3822 /*
fea3f48a
SZ
3823 * Don't enable MSI-X on 82575, see:
3824 * 82575 specification update errata #25
9c0ecdcc
SZ
3825 */
3826 if (sc->hw.mac.type == e1000_82575)
3827 return;
3828
3829 /* Don't enable MSI-X on VF */
3830 if (sc->vf_ifp)
3831 return;
3832
3833 msix_enable = device_getenv_int(sc->dev, "msix.enable",
3834 igb_msix_enable);
3835 if (!msix_enable)
3836 return;
3837
3838 msix_cnt = pci_msix_count(sc->dev);
3839#ifdef IGB_MSIX_DEBUG
3840 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3841#endif
3842 if (msix_cnt <= 1) {
3843 /* One MSI-X model does not make sense */
3844 return;
3845 }
3846
3847 i = 0;
3848 while ((1 << (i + 1)) <= msix_cnt)
3849 ++i;
3850 msix_cnt2 = 1 << i;
3851
3852 if (bootverbose) {
3853 device_printf(sc->dev, "MSI-X count %d/%d\n",
3854 msix_cnt2, msix_cnt);
3855 }
3856
3857 KKASSERT(msix_cnt2 <= msix_cnt);
3858 if (msix_cnt == msix_cnt2) {
3859 /* We need at least one MSI-X for link status */
3860 msix_cnt2 >>= 1;
3861 if (msix_cnt2 <= 1) {
3862 /* One MSI-X for RX/TX does not make sense */
3863 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3864 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3865 return;
3866 }
3867 KKASSERT(msix_cnt > msix_cnt2);
3868