pci: Bring back 3f607eb6e6bf8981c33dc29fd477005f364fa9ce
[dragonfly.git] / sys / bus / pci / pcivar.h
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4d28e78f 1/*-
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2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
4d28e78f 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
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27 *
28 */
29
30#ifndef _PCIVAR_H_
4d28e78f 31#define _PCIVAR_H_
984263bc 32
984263bc 33#include <sys/queue.h>
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34#include <bus/pci/pcireg.h>
35extern const char *pcib_owner; /* arbitrate who owns the pci device arch */
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36
37/* some PCI bus constants */
38
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39#define PCI_DOMAINMAX 65535 /* highest supported domain number */
40#define PCI_BUSMAX 255 /* highest supported bus number */
41#define PCI_SLOTMAX 31 /* highest supported slot number */
42#define PCI_FUNCMAX 7 /* highest supported function number */
43#define PCI_REGMAX 255 /* highest supported config register addr. */
984263bc 44
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45#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
46#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
47#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
984263bc 48
4d28e78f 49typedef uint64_t pci_addr_t;
984263bc 50
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51/* Interesting values for PCI power management */
52struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* config space address of PCI power status reg */
55 uint8_t pp_pmcsr; /* config space address of PMCSR reg */
56 uint8_t pp_data; /* config space address of PCI power data reg */
1f7d9fe0 57};
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58
59struct vpd_readonly {
60 char keyword[2];
61 char *value;
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62};
63
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64struct vpd_write {
65 char keyword[2];
66 char *value;
67 int start;
68 int len;
69};
638744c5 70
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71struct pcicfg_vpd {
72 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
73 char vpd_cached;
74 char *vpd_ident; /* string identifier */
75 int vpd_rocnt;
76 struct vpd_readonly *vpd_ros;
77 int vpd_wcnt;
78 struct vpd_write *vpd_w;
79};
984263bc 80
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81/* Interesting values for PCI MSI */
82struct pcicfg_msi {
83 uint16_t msi_ctrl; /* Message Control */
84 uint8_t msi_location; /* Offset of MSI capability registers. */
85 uint8_t msi_msgnum; /* Number of messages */
86 int msi_alloc; /* Number of allocated messages. */
87 uint64_t msi_addr; /* Contents of address register. */
88 uint16_t msi_data; /* Contents of data register. */
89 u_int msi_handlers;
90};
984263bc 91
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92/* Interesting values for PCI MSI-X */
93struct msix_vector {
94 uint64_t mv_address; /* Contents of address register. */
95 uint32_t mv_data; /* Contents of data register. */
96 int mv_irq;
97};
984263bc 98
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99struct msix_table_entry {
100 u_int mte_vector; /* 1-based index into msix_vectors array. */
101 u_int mte_handlers;
102};
984263bc 103
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104struct pcicfg_msix {
105 uint16_t msix_ctrl; /* Message Control */
106 uint16_t msix_msgnum; /* Number of messages */
107 uint8_t msix_location; /* Offset of MSI-X capability registers. */
108 uint8_t msix_table_bar; /* BAR containing vector table. */
109 uint8_t msix_pba_bar; /* BAR containing PBA. */
110 uint32_t msix_table_offset;
111 uint32_t msix_pba_offset;
112 int msix_alloc; /* Number of allocated vectors. */
113 int msix_table_len; /* Length of virtual table. */
114 struct msix_table_entry *msix_table; /* Virtual table. */
115 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
116 struct resource *msix_table_res; /* Resource containing vector table. */
117 struct resource *msix_pba_res; /* Resource containing PBA. */
118};
984263bc 119
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120/* Interesting values for HyperTransport */
121struct pcicfg_ht {
122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
123 uint16_t ht_msictrl; /* MSI mapping control */
124 uint64_t ht_msiaddr; /* MSI mapping base address */
125};
984263bc 126
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127/* config header information common to all header types */
128typedef struct pcicfg {
129 struct device *dev; /* device which owns this */
984263bc 130
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131 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
132 uint32_t bios; /* BIOS mapping */
984263bc 133
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134 uint16_t subvendor; /* card vendor ID */
135 uint16_t subdevice; /* card device ID, assigned by card vendor */
136 uint16_t vendor; /* chip vendor ID */
137 uint16_t device; /* chip device ID, assigned by chip vendor */
138
139 uint16_t cmdreg; /* disable/enable chip and PCI options */
140 uint16_t statreg; /* supported PCI features and error state */
141
142 uint8_t baseclass; /* chip PCI class */
143 uint8_t subclass; /* chip PCI subclass */
144 uint8_t progif; /* chip PCI programming interface */
145 uint8_t revid; /* chip revision ID */
146
147 uint8_t hdrtype; /* chip config header type */
148 uint8_t cachelnsz; /* cache line size in 4byte units */
149 uint8_t intpin; /* PCI interrupt pin */
150 uint8_t intline; /* interrupt line (IRQ for PC arch) */
151
152 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
153 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
154 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
155
156 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
157 uint8_t nummaps; /* actual number of PCI maps used */
158
159 uint32_t domain; /* PCI domain */
160 uint8_t bus; /* config space bus address */
161 uint8_t slot; /* config space slot address */
162 uint8_t func; /* config space function number */
163
164 struct pcicfg_pp pp; /* pci power management */
165 struct pcicfg_vpd vpd; /* pci vital product data */
166 struct pcicfg_msi msi; /* pci msi */
167 struct pcicfg_msix msix; /* pci msi-x */
168 struct pcicfg_ht ht; /* HyperTransport */
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169} pcicfgregs;
170
171/* additional type 1 device config header information (PCI to PCI bridge) */
172
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173#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
174#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
175#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
176#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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177
178typedef struct {
179 pci_addr_t pmembase; /* base address of prefetchable memory */
180 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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181 uint32_t membase; /* base address of memory window */
182 uint32_t memlimit; /* topmost address of memory window */
183 uint32_t iobase; /* base address of port window */
184 uint32_t iolimit; /* topmost address of port window */
185 uint16_t secstat; /* secondary bus status register */
186 uint16_t bridgectl; /* bridge control register */
187 uint8_t seclat; /* CardBus latency timer */
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188} pcih1cfgregs;
189
190/* additional type 2 device config header information (CardBus bridge) */
191
192typedef struct {
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193 uint32_t membase0; /* base address of memory window */
194 uint32_t memlimit0; /* topmost address of memory window */
195 uint32_t membase1; /* base address of memory window */
196 uint32_t memlimit1; /* topmost address of memory window */
197 uint32_t iobase0; /* base address of port window */
198 uint32_t iolimit0; /* topmost address of port window */
199 uint32_t iobase1; /* base address of port window */
200 uint32_t iolimit1; /* topmost address of port window */
201 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
202 uint16_t secstat; /* secondary bus status register */
203 uint16_t bridgectl; /* bridge control register */
204 uint8_t seclat; /* CardBus latency timer */
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205} pcih2cfgregs;
206
4d28e78f 207extern uint32_t pci_numdevs;
984263bc 208
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209/* Only if the prerequisites are present */
210#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
211struct pci_devinfo {
212 STAILQ_ENTRY(pci_devinfo) pci_links;
213 struct resource_list resources;
214 pcicfgregs cfg;
215 struct pci_conf conf;
216};
217#endif
984263bc 218
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219#ifdef _SYS_BUS_H_
220
221#include "pci_if.h"
222
223/*
224 * Define pci-specific resource flags for accessing memory via dense
225 * or bwx memory spaces. These flags are ignored on i386.
226 */
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227#define PCI_RF_DENSE 0x10000
228#define PCI_RF_BWX 0x20000
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229
230enum pci_device_ivars {
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231 PCI_IVAR_SUBVENDOR,
232 PCI_IVAR_SUBDEVICE,
233 PCI_IVAR_VENDOR,
234 PCI_IVAR_DEVICE,
235 PCI_IVAR_DEVID,
236 PCI_IVAR_CLASS,
237 PCI_IVAR_SUBCLASS,
238 PCI_IVAR_PROGIF,
239 PCI_IVAR_REVID,
240 PCI_IVAR_INTPIN,
241 PCI_IVAR_IRQ,
242 PCI_IVAR_DOMAIN,
243 PCI_IVAR_BUS,
244 PCI_IVAR_SLOT,
245 PCI_IVAR_FUNCTION,
246 PCI_IVAR_ETHADDR,
247 PCI_IVAR_CMDREG,
248 PCI_IVAR_CACHELNSZ,
249 PCI_IVAR_MINGNT,
250 PCI_IVAR_MAXLAT,
251 PCI_IVAR_LATTIMER,
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252};
253
254/*
255 * Simplified accessors for pci devices
256 */
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257#define PCI_ACCESSOR(var, ivar, type) \
258 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
259
260PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
261PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
262PCI_ACCESSOR(vendor, VENDOR, uint16_t)
263PCI_ACCESSOR(device, DEVICE, uint16_t)
264PCI_ACCESSOR(devid, DEVID, uint32_t)
265PCI_ACCESSOR(class, CLASS, uint8_t)
266PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
267PCI_ACCESSOR(progif, PROGIF, uint8_t)
268PCI_ACCESSOR(revid, REVID, uint8_t)
269PCI_ACCESSOR(intpin, INTPIN, uint8_t)
270PCI_ACCESSOR(irq, IRQ, uint8_t)
271PCI_ACCESSOR(domain, DOMAIN, uint32_t)
272PCI_ACCESSOR(bus, BUS, uint8_t)
273PCI_ACCESSOR(slot, SLOT, uint8_t)
274PCI_ACCESSOR(function, FUNCTION, uint8_t)
f72d3d23 275PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
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276PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
277PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
278PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
279PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
280PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
984263bc 281
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282#undef PCI_ACCESSOR
283
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284/*
285 * Operations on configuration space.
286 */
287static __inline uint32_t
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288pci_read_config(device_t dev, int reg, int width)
289{
290 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
291}
292
293static __inline void
4d28e78f 294pci_write_config(device_t dev, int reg, uint32_t val, int width)
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295{
296 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
297}
298
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299/*
300 * Ivars for pci bridges.
301 */
302
303/*typedef enum pci_device_ivars pcib_device_ivars;*/
304enum pcib_device_ivars {
305 PCIB_IVAR_DOMAIN,
306 PCIB_IVAR_BUS
307};
308
309#define PCIB_ACCESSOR(var, ivar, type) \
310 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
311
312PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
313PCIB_ACCESSOR(bus, BUS, uint32_t)
314
315#undef PCIB_ACCESSOR
316
317/*
318 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
319 * on i386 or other platforms should be mapped out in the MD pcireadconf
320 * code and not here, since the only MI invalid IRQ is 255.
321 */
322#define PCI_INVALID_IRQ 255
323#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
324
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325/*
326 * Convenience functions.
327 *
328 * These should be used in preference to manually manipulating
329 * configuration space.
330 */
4d28e78f 331static __inline int
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332pci_enable_busmaster(device_t dev)
333{
4d28e78f 334 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
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335}
336
4d28e78f 337static __inline int
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338pci_disable_busmaster(device_t dev)
339{
4d28e78f 340 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
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341}
342
4d28e78f 343static __inline int
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344pci_enable_io(device_t dev, int space)
345{
4d28e78f 346 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
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347}
348
4d28e78f 349static __inline int
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350pci_disable_io(device_t dev, int space)
351{
4d28e78f 352 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
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353}
354
c7e4e7eb 355static __inline int
4d28e78f 356pci_get_vpd_ident(device_t dev, const char **identptr)
c7e4e7eb 357{
4d28e78f 358 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
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359}
360
361static __inline int
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362pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
363{
364 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
365}
366
367/*
368 * Check if the address range falls within the VGA defined address range(s)
369 */
370static __inline int
371pci_is_vga_ioport_range(u_long start, u_long end)
372{
373
374 return (((start >= 0x3b0 && end <= 0x3bb) ||
375 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
376}
377
378static __inline int
379pci_is_vga_memory_range(u_long start, u_long end)
c7e4e7eb 380{
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381
382 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
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383}
384
4d28e78f 385void pcie_set_max_readrq(device_t, uint16_t);
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386/*
387 * PCI power states are as defined by ACPI:
388 *
389 * D0 State in which device is on and running. It is receiving full
390 * power from the system and delivering full functionality to the user.
391 * D1 Class-specific low-power state in which device context may or may not
392 * be lost. Buses in D1 cannot do anything to the bus that would force
4d28e78f 393 * devices on that bus to lose context.
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394 * D2 Class-specific low-power state in which device context may or may
395 * not be lost. Attains greater power savings than D1. Buses in D2
4d28e78f 396 * can cause devices on that bus to lose some context. Devices in D2
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397 * must be prepared for the bus to be in D2 or higher.
398 * D3 State in which the device is off and not running. Device context is
399 * lost. Power can be removed from the device.
400 */
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401#define PCI_POWERSTATE_D0 0
402#define PCI_POWERSTATE_D1 1
403#define PCI_POWERSTATE_D2 2
404#define PCI_POWERSTATE_D3 3
405#define PCI_POWERSTATE_UNKNOWN -1
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406
407static __inline int
408pci_set_powerstate(device_t dev, int state)
409{
410 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
411}
412
413static __inline int
414pci_get_powerstate(device_t dev)
415{
416 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
417}
418
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419static __inline int
420pci_find_extcap(device_t dev, int capability, int *capreg)
421{
422 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
423}
424
425static __inline int
426pci_is_pcie(device_t dev)
427{
428 int reg;
429 return (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0);
430}
984263bc 431
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432static __inline int
433pci_is_pcix(device_t dev)
434{
435 int reg;
436 return (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0);
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437}
438
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439#warning "this code is probably incorrect"
440static __inline int*
441pci_get_vpdcap_ptr(device_t dev)
442{
443 int *reg;
444 pci_find_extcap(dev, PCIY_VPD, reg);
445 return reg;
446}
984263bc 447
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448static __inline int*
449pci_get_pciecap_ptr(device_t dev)
450{
451 int *reg;
452 pci_find_extcap(dev, PCIY_EXPRESS, reg);
453 return reg;
454}
27c23c6b 455
984263bc 456
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457static __inline int*
458pci_get_pcixcap_ptr(device_t dev)
459{
460 int *reg;
461 pci_find_extcap(dev, PCIY_PCIX, reg);
462 return reg;
463}
dc5a7bd2 464
984263bc 465
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466static __inline int
467pci_alloc_msi(device_t dev, int *count)
468{
469 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
470}
471
472static __inline int
473pci_alloc_msix(device_t dev, int *count)
474{
475 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
476}
984263bc 477
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478static __inline int
479pci_remap_msix(device_t dev, int count, const u_int *vectors)
480{
481 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
482}
984263bc 483
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484static __inline int
485pci_release_msi(device_t dev)
486{
487 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
488}
984263bc 489
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490static __inline int
491pci_msi_count(device_t dev)
492{
493 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
494}
984263bc 495
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496static __inline int
497pci_msix_count(device_t dev)
498{
499 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
500}
984263bc 501
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502device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
503device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
504device_t pci_find_device(uint16_t, uint16_t);
505
506/*
507 * Can be used by MD code to request the PCI bus to re-map an MSI or
508 * MSI-X message.
509 */
510int pci_remap_msi_irq(device_t dev, u_int irq);
511
512/* Can be used by drivers to manage the MSI-X table. */
513int pci_pending_msix(device_t dev, u_int index);
514
515int pci_msi_device_blacklisted(device_t dev);
516
517void pci_ht_map_msi(device_t dev, uint64_t addr);
518
519#endif /* _SYS_BUS_H_ */
520
521/*
522 * cdev switch for control device, initialised in generic PCI code
523 */
524extern struct cdevsw pcicdev;
525
526/*
527 * List of all PCI devices, generation count for the list.
528 */
529STAILQ_HEAD(devlist, pci_devinfo);
530
531extern struct devlist pci_devq;
532extern uint32_t pci_generation;
984263bc 533
984263bc 534#endif /* _PCIVAR_H_ */