emx: Utilize mbuf's header lengthes
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
8434a83b 68#include "opt_rss.h"
e6cde6e6 69#include "opt_emx.h"
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70
71#include <sys/param.h>
72#include <sys/bus.h>
73#include <sys/endian.h>
74#include <sys/interrupt.h>
75#include <sys/kernel.h>
76#include <sys/ktr.h>
77#include <sys/malloc.h>
78#include <sys/mbuf.h>
79#include <sys/proc.h>
80#include <sys/rman.h>
81#include <sys/serialize.h>
bc197380 82#include <sys/serialize2.h>
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83#include <sys/socket.h>
84#include <sys/sockio.h>
85#include <sys/sysctl.h>
86#include <sys/systm.h>
87
88#include <net/bpf.h>
89#include <net/ethernet.h>
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/if_dl.h>
93#include <net/if_media.h>
94#include <net/ifq_var.h>
89d8e73d 95#include <net/toeplitz.h>
9cc86e17 96#include <net/toeplitz2.h>
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97#include <net/vlan/if_vlan_var.h>
98#include <net/vlan/if_vlan_ether.h>
b3a7093f 99#include <net/if_poll.h>
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100
101#include <netinet/in_systm.h>
102#include <netinet/in.h>
103#include <netinet/ip.h>
104#include <netinet/tcp.h>
105#include <netinet/udp.h>
106
107#include <bus/pci/pcivar.h>
108#include <bus/pci/pcireg.h>
109
110#include <dev/netif/ig_hal/e1000_api.h>
111#include <dev/netif/ig_hal/e1000_82571.h>
112#include <dev/netif/emx/if_emx.h>
113
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114#ifdef EMX_RSS_DEBUG
115#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116do { \
89d8e73d 117 if (sc->rss_debug >= lvl) \
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118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119} while (0)
120#else /* !EMX_RSS_DEBUG */
121#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122#endif /* EMX_RSS_DEBUG */
123
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124#define EMX_TX_SERIALIZE 1
125#define EMX_RX_SERIALIZE 2
126
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127#define EMX_NAME "Intel(R) PRO/1000 "
128
129#define EMX_DEVICE(id) \
130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
131#define EMX_DEVICE_NULL { 0, 0, NULL }
132
133static const struct emx_device {
134 uint16_t vid;
135 uint16_t did;
136 const char *desc;
137} emx_devices[] = {
138 EMX_DEVICE(82571EB_COPPER),
139 EMX_DEVICE(82571EB_FIBER),
140 EMX_DEVICE(82571EB_SERDES),
141 EMX_DEVICE(82571EB_SERDES_DUAL),
142 EMX_DEVICE(82571EB_SERDES_QUAD),
143 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 144 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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145 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
146 EMX_DEVICE(82571EB_QUAD_FIBER),
147 EMX_DEVICE(82571PT_QUAD_COPPER),
148
149 EMX_DEVICE(82572EI_COPPER),
150 EMX_DEVICE(82572EI_FIBER),
151 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82572EI),
153
154 EMX_DEVICE(82573E),
155 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(82573L),
157
158 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
160 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
161 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
162
163 EMX_DEVICE(82574L),
2d0e5700 164 EMX_DEVICE(82574LA),
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165
166 /* required last entry */
167 EMX_DEVICE_NULL
168};
169
170static int emx_probe(device_t);
171static int emx_attach(device_t);
172static int emx_detach(device_t);
173static int emx_shutdown(device_t);
174static int emx_suspend(device_t);
175static int emx_resume(device_t);
176
177static void emx_init(void *);
178static void emx_stop(struct emx_softc *);
179static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180static void emx_start(struct ifnet *);
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181#ifdef IFPOLL_ENABLE
182static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
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183#endif
184static void emx_watchdog(struct ifnet *);
185static void emx_media_status(struct ifnet *, struct ifmediareq *);
186static int emx_media_change(struct ifnet *);
187static void emx_timer(void *);
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188static void emx_serialize(struct ifnet *, enum ifnet_serialize);
189static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
190static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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191#ifdef INVARIANTS
192static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 boolean_t);
194#endif
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195
196static void emx_intr(void *);
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197static void emx_intr_mask(void *);
198static void emx_intr_body(struct emx_softc *, boolean_t);
c39e3a1f 199static void emx_rxeof(struct emx_softc *, int, int);
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200static void emx_txeof(struct emx_softc *);
201static void emx_tx_collect(struct emx_softc *);
202static void emx_tx_purge(struct emx_softc *);
203static void emx_enable_intr(struct emx_softc *);
204static void emx_disable_intr(struct emx_softc *);
205
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206static int emx_dma_alloc(struct emx_softc *);
207static void emx_dma_free(struct emx_softc *);
5330213c 208static void emx_init_tx_ring(struct emx_softc *);
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209static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
210static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 211static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 212static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 213static void emx_destroy_tx_ring(struct emx_softc *, int);
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214static void emx_destroy_rx_ring(struct emx_softc *,
215 struct emx_rxdata *, int);
216static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 217static int emx_encap(struct emx_softc *, struct mbuf **);
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218static int emx_txcsum(struct emx_softc *, struct mbuf *,
219 uint32_t *, uint32_t *);
220
221static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 222static int emx_reset(struct emx_softc *);
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223static void emx_setup_ifp(struct emx_softc *);
224static void emx_init_tx_unit(struct emx_softc *);
225static void emx_init_rx_unit(struct emx_softc *);
226static void emx_update_stats(struct emx_softc *);
227static void emx_set_promisc(struct emx_softc *);
228static void emx_disable_promisc(struct emx_softc *);
229static void emx_set_multi(struct emx_softc *);
230static void emx_update_link_status(struct emx_softc *);
231static void emx_smartspeed(struct emx_softc *);
2d0e5700 232static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 233static void emx_disable_aspm(struct emx_softc *);
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234
235static void emx_print_debug_info(struct emx_softc *);
236static void emx_print_nvm_info(struct emx_softc *);
237static void emx_print_hw_stats(struct emx_softc *);
238
239static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
240static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
241static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
242static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
243static void emx_add_sysctl(struct emx_softc *);
244
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245static void emx_serialize_skipmain(struct emx_softc *);
246static void emx_deserialize_skipmain(struct emx_softc *);
247
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248/* Management and WOL Support */
249static void emx_get_mgmt(struct emx_softc *);
250static void emx_rel_mgmt(struct emx_softc *);
251static void emx_get_hw_control(struct emx_softc *);
252static void emx_rel_hw_control(struct emx_softc *);
253static void emx_enable_wol(device_t);
254
255static device_method_t emx_methods[] = {
256 /* Device interface */
257 DEVMETHOD(device_probe, emx_probe),
258 DEVMETHOD(device_attach, emx_attach),
259 DEVMETHOD(device_detach, emx_detach),
260 DEVMETHOD(device_shutdown, emx_shutdown),
261 DEVMETHOD(device_suspend, emx_suspend),
262 DEVMETHOD(device_resume, emx_resume),
263 { 0, 0 }
264};
265
266static driver_t emx_driver = {
267 "emx",
268 emx_methods,
269 sizeof(struct emx_softc),
270};
271
272static devclass_t emx_devclass;
273
274DECLARE_DUMMY_MODULE(if_emx);
275MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 276DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
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277
278/*
279 * Tunables
280 */
281static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
282static int emx_rxd = EMX_DEFAULT_RXD;
283static int emx_txd = EMX_DEFAULT_TXD;
704b6287 284static int emx_smart_pwr_down = 0;
724cbff8 285static int emx_rxr = 0;
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286
287/* Controls whether promiscuous also shows bad packets */
b4d8c36b 288static int emx_debug_sbp = 0;
5330213c 289
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290static int emx_82573_workaround = 1;
291static int emx_msi_enable = 1;
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292
293TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
294TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 295TUNABLE_INT("hw.emx.rxr", &emx_rxr);
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296TUNABLE_INT("hw.emx.txd", &emx_txd);
297TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
298TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
299TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 300TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
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301
302/* Global used in WOL setup with multiport cards */
303static int emx_global_quad_port_a = 0;
304
305/* Set this to one to display debug statistics */
306static int emx_display_debug_stats = 0;
307
308#if !defined(KTR_IF_EMX)
309#define KTR_IF_EMX KTR_ALL
310#endif
311KTR_INFO_MASTER(if_emx);
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312KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
313KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
314KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
315KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
316KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
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317#define logif(name) KTR_LOG(if_emx_ ## name)
318
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319static __inline void
320emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
321{
322 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 323 /* DD bit must be cleared */
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324 rxd->rxd_staterr = 0;
325}
326
327static __inline void
328emx_rxcsum(uint32_t staterr, struct mbuf *mp)
329{
330 /* Ignore Checksum bit is set */
331 if (staterr & E1000_RXD_STAT_IXSM)
332 return;
333
334 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
335 E1000_RXD_STAT_IPCS)
336 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
337
338 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
339 E1000_RXD_STAT_TCPCS) {
340 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
341 CSUM_PSEUDO_HDR |
342 CSUM_FRAG_NOT_CHECKED;
343 mp->m_pkthdr.csum_data = htons(0xffff);
344 }
345}
346
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347static __inline struct pktinfo *
348emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
349 uint32_t mrq, uint32_t hash, uint32_t staterr)
350{
351 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
352 case EMX_RXDMRQ_IPV4_TCP:
353 pi->pi_netisr = NETISR_IP;
354 pi->pi_flags = 0;
355 pi->pi_l3proto = IPPROTO_TCP;
356 break;
357
358 case EMX_RXDMRQ_IPV6_TCP:
359 pi->pi_netisr = NETISR_IPV6;
360 pi->pi_flags = 0;
361 pi->pi_l3proto = IPPROTO_TCP;
362 break;
363
364 case EMX_RXDMRQ_IPV4:
365 if (staterr & E1000_RXD_STAT_IXSM)
366 return NULL;
367
368 if ((staterr &
369 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
370 E1000_RXD_STAT_TCPCS) {
371 pi->pi_netisr = NETISR_IP;
372 pi->pi_flags = 0;
373 pi->pi_l3proto = IPPROTO_UDP;
374 break;
375 }
376 /* FALL THROUGH */
377 default:
378 return NULL;
379 }
380
381 m->m_flags |= M_HASH;
382 m->m_pkthdr.hash = toeplitz_hash(hash);
383 return pi;
384}
385
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386static int
387emx_probe(device_t dev)
388{
389 const struct emx_device *d;
390 uint16_t vid, did;
391
392 vid = pci_get_vendor(dev);
393 did = pci_get_device(dev);
394
395 for (d = emx_devices; d->desc != NULL; ++d) {
396 if (vid == d->vid && did == d->did) {
397 device_set_desc(dev, d->desc);
398 device_set_async_attach(dev, TRUE);
399 return 0;
400 }
401 }
402 return ENXIO;
403}
404
405static int
406emx_attach(device_t dev)
407{
408 struct emx_softc *sc = device_get_softc(dev);
409 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 410 int error = 0, i, throttle, msi_enable;
704b6287 411 u_int intr_flags;
2d0e5700 412 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 413 driver_intr_t *intr_func;
5330213c 414
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415 lwkt_serialize_init(&sc->main_serialize);
416 lwkt_serialize_init(&sc->tx_serialize);
417 for (i = 0; i < EMX_NRX_RING; ++i)
418 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
419
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420 i = 0;
421 sc->serializes[i++] = &sc->main_serialize;
422 sc->serializes[i++] = &sc->tx_serialize;
423 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
424 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
425 KKASSERT(i == EMX_NSERIALIZE);
426
c2022416 427 callout_init_mp(&sc->timer);
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428
429 sc->dev = sc->osdep.dev = dev;
430
431 /*
432 * Determine hardware and mac type
433 */
434 sc->hw.vendor_id = pci_get_vendor(dev);
435 sc->hw.device_id = pci_get_device(dev);
436 sc->hw.revision_id = pci_get_revid(dev);
437 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
438 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
439
440 if (e1000_set_mac_type(&sc->hw))
441 return ENXIO;
442
443 /* Enable bus mastering */
444 pci_enable_busmaster(dev);
445
446 /*
447 * Allocate IO memory
448 */
449 sc->memory_rid = EMX_BAR_MEM;
450 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
451 &sc->memory_rid, RF_ACTIVE);
452 if (sc->memory == NULL) {
453 device_printf(dev, "Unable to allocate bus resource: memory\n");
454 error = ENXIO;
455 goto fail;
456 }
457 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
458 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
459
460 /* XXX This is quite goofy, it is not actually used */
461 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
462
463 /*
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464 * Don't enable MSI-X on 82574, see:
465 * 82574 specification update errata #15
466 *
d01335e8 467 * Don't enable MSI on 82571/82572, see:
a835687d 468 * 82571/82572 specification update errata #63
d01335e8
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469 */
470 msi_enable = emx_msi_enable;
471 if (msi_enable &&
472 (sc->hw.mac.type == e1000_82571 ||
473 sc->hw.mac.type == e1000_82572))
474 msi_enable = 0;
475
476 /*
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477 * Allocate interrupt
478 */
d01335e8 479 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 480 &sc->intr_rid, &intr_flags);
704b6287 481
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482 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
483 int unshared;
484
485 unshared = device_getenv_int(dev, "irq.unshared", 0);
486 if (!unshared) {
487 sc->flags |= EMX_FLAG_SHARED_INTR;
488 if (bootverbose)
489 device_printf(dev, "IRQ shared\n");
490 } else {
491 intr_flags &= ~RF_SHAREABLE;
492 if (bootverbose)
493 device_printf(dev, "IRQ unshared\n");
494 }
495 }
496
5330213c 497 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 498 intr_flags);
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499 if (sc->intr_res == NULL) {
500 device_printf(dev, "Unable to allocate bus resource: "
501 "interrupt\n");
502 error = ENXIO;
503 goto fail;
504 }
505
506 /* Save PCI command register for Shared Code */
507 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
508 sc->hw.back = &sc->osdep;
509
510 /* Do Shared Code initialization */
511 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
512 device_printf(dev, "Setup of Shared code failed\n");
513 error = ENXIO;
514 goto fail;
515 }
516 e1000_get_bus_info(&sc->hw);
517
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518 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
519 sc->hw.phy.autoneg_wait_to_complete = FALSE;
520 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
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521
522 /*
523 * Interrupt throttle rate
524 */
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525 throttle = device_getenv_int(dev, "int_throttle_ceil",
526 emx_int_throttle_ceil);
527 if (throttle == 0) {
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528 sc->int_throttle_ceil = 0;
529 } else {
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530 if (throttle < 0)
531 throttle = EMX_DEFAULT_ITR;
532
533 /* Recalculate the tunable value to get the exact frequency. */
534 throttle = 1000000000 / 256 / throttle;
535
536 /* Upper 16bits of ITR is reserved and should be zero */
537 if (throttle & 0xffff0000)
538 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
539
540 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
541 }
542
543 e1000_init_script_state_82541(&sc->hw, TRUE);
544 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
545
546 /* Copper options */
547 if (sc->hw.phy.media_type == e1000_media_type_copper) {
548 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
549 sc->hw.phy.disable_polarity_correction = FALSE;
550 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
551 }
552
553 /* Set the frame limits assuming standard ethernet sized frames. */
554 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
555 sc->min_frame_size = ETHER_MIN_LEN;
556
557 /* This controls when hardware reports transmit completion status. */
558 sc->hw.mac.report_tx_early = 1;
559
65c7a6af 560 /* Calculate # of RX rings */
724cbff8 561 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 562 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 563
071699f8
SZ
564 /* Allocate RX/TX rings' busdma(9) stuffs */
565 error = emx_dma_alloc(sc);
566 if (error)
e5b3bcc4 567 goto fail;
e5b3bcc4 568
2d0e5700
SZ
569 /* Allocate multicast array memory. */
570 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
571 M_DEVBUF, M_WAITOK);
572
573 /* Indicate SOL/IDER usage */
574 if (e1000_check_reset_block(&sc->hw)) {
575 device_printf(dev,
576 "PHY reset is blocked due to SOL/IDER session.\n");
577 }
578
579 /*
580 * Start from a known state, this is important in reading the
581 * nvm and mac from that.
582 */
583 e1000_reset_hw(&sc->hw);
584
5330213c
SZ
585 /* Make sure we have a good EEPROM before we read from it */
586 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
587 /*
588 * Some PCI-E parts fail the first check due to
589 * the link being in sleep state, call it again,
590 * if it fails a second time its a real issue.
591 */
592 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
593 device_printf(dev,
594 "The EEPROM Checksum Is Not Valid\n");
595 error = EIO;
596 goto fail;
597 }
598 }
599
5330213c
SZ
600 /* Copy the permanent MAC address out of the EEPROM */
601 if (e1000_read_mac_addr(&sc->hw) < 0) {
602 device_printf(dev, "EEPROM read error while reading MAC"
603 " address\n");
604 error = EIO;
605 goto fail;
606 }
607 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
608 device_printf(dev, "Invalid MAC address\n");
609 error = EIO;
610 goto fail;
611 }
612
5330213c
SZ
613 /* Determine if we have to control management hardware */
614 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
615
616 /*
617 * Setup Wake-on-Lan
618 */
2d0e5700
SZ
619 apme_mask = EMX_EEPROM_APME;
620 eeprom_data = 0;
5330213c 621 switch (sc->hw.mac.type) {
2d0e5700
SZ
622 case e1000_82573:
623 sc->has_amt = 1;
624 /* FALL THROUGH */
625
5330213c 626 case e1000_82571:
2d0e5700 627 case e1000_82572:
5330213c
SZ
628 case e1000_80003es2lan:
629 if (sc->hw.bus.func == 1) {
630 e1000_read_nvm(&sc->hw,
631 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
632 } else {
633 e1000_read_nvm(&sc->hw,
634 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
635 }
5330213c
SZ
636 break;
637
638 default:
2d0e5700
SZ
639 e1000_read_nvm(&sc->hw,
640 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ
641 break;
642 }
2d0e5700
SZ
643 if (eeprom_data & apme_mask)
644 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
645
5330213c
SZ
646 /*
647 * We have the eeprom settings, now apply the special cases
648 * where the eeprom may be wrong or the board won't support
649 * wake on lan on a particular port
650 */
651 device_id = pci_get_device(dev);
652 switch (device_id) {
653 case E1000_DEV_ID_82571EB_FIBER:
654 /*
655 * Wake events only supported on port A for dual fiber
656 * regardless of eeprom setting
657 */
658 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
659 E1000_STATUS_FUNC_1)
660 sc->wol = 0;
661 break;
662
663 case E1000_DEV_ID_82571EB_QUAD_COPPER:
664 case E1000_DEV_ID_82571EB_QUAD_FIBER:
665 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
666 /* if quad port sc, disable WoL on all but port A */
667 if (emx_global_quad_port_a != 0)
668 sc->wol = 0;
669 /* Reset for multiple quad port adapters */
670 if (++emx_global_quad_port_a == 4)
671 emx_global_quad_port_a = 0;
672 break;
673 }
674
675 /* XXX disable wol */
676 sc->wol = 0;
677
2d0e5700
SZ
678 /* Setup OS specific network interface */
679 emx_setup_ifp(sc);
680
681 /* Add sysctl tree, must after em_setup_ifp() */
682 emx_add_sysctl(sc);
683
684 /* Reset the hardware */
685 error = emx_reset(sc);
686 if (error) {
687 device_printf(dev, "Unable to reset the hardware\n");
688 goto fail;
689 }
690
691 /* Initialize statistics */
692 emx_update_stats(sc);
693
694 sc->hw.mac.get_link_status = 1;
695 emx_update_link_status(sc);
696
5330213c
SZ
697 sc->spare_tx_desc = EMX_TX_SPARE;
698
699 /*
700 * Keep following relationship between spare_tx_desc, oact_tx_desc
701 * and tx_int_nsegs:
702 * (spare_tx_desc + EMX_TX_RESERVED) <=
703 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
704 */
705 sc->oact_tx_desc = sc->num_tx_desc / 8;
706 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
707 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
708 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
709 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
710
711 sc->tx_int_nsegs = sc->num_tx_desc / 16;
712 if (sc->tx_int_nsegs < sc->oact_tx_desc)
713 sc->tx_int_nsegs = sc->oact_tx_desc;
714
2d0e5700
SZ
715 /* Non-AMT based hardware can now take control from firmware */
716 if (sc->has_manage && !sc->has_amt)
717 emx_get_hw_control(sc);
718
4cb541ae
SZ
719 /*
720 * Missing Interrupt Following ICR read:
721 *
a835687d
SZ
722 * 82571/82572 specification update errata #76
723 * 82573 specification update errata #31
724 * 82574 specification update errata #12
4cb541ae
SZ
725 */
726 intr_func = emx_intr;
727 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
728 (sc->hw.mac.type == e1000_82571 ||
729 sc->hw.mac.type == e1000_82572 ||
730 sc->hw.mac.type == e1000_82573 ||
731 sc->hw.mac.type == e1000_82574))
732 intr_func = emx_intr_mask;
733
734 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 735 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
736 if (error) {
737 device_printf(dev, "Failed to register interrupt handler");
738 ether_ifdetach(&sc->arpcom.ac_if);
739 goto fail;
740 }
741
704b6287 742 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ
743 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
744 return (0);
745fail:
746 emx_detach(dev);
747 return (error);
748}
749
750static int
751emx_detach(device_t dev)
752{
753 struct emx_softc *sc = device_get_softc(dev);
754
755 if (device_is_attached(dev)) {
756 struct ifnet *ifp = &sc->arpcom.ac_if;
757
6d435846 758 ifnet_serialize_all(ifp);
5330213c
SZ
759
760 emx_stop(sc);
761
762 e1000_phy_hw_reset(&sc->hw);
763
764 emx_rel_mgmt(sc);
2d0e5700 765 emx_rel_hw_control(sc);
5330213c
SZ
766
767 if (sc->wol) {
768 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
769 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
770 emx_enable_wol(dev);
771 }
772
773 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
774
6d435846 775 ifnet_deserialize_all(ifp);
5330213c
SZ
776
777 ether_ifdetach(ifp);
2d0e5700
SZ
778 } else {
779 emx_rel_hw_control(sc);
5330213c
SZ
780 }
781 bus_generic_detach(dev);
782
783 if (sc->intr_res != NULL) {
784 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
785 sc->intr_res);
786 }
787
7fb43956 788 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ
789 pci_release_msi(dev);
790
5330213c
SZ
791 if (sc->memory != NULL) {
792 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
793 sc->memory);
794 }
795
071699f8 796 emx_dma_free(sc);
5330213c
SZ
797
798 /* Free sysctl tree */
799 if (sc->sysctl_tree != NULL)
800 sysctl_ctx_free(&sc->sysctl_ctx);
801
802 return (0);
803}
804
805static int
806emx_shutdown(device_t dev)
807{
808 return emx_suspend(dev);
809}
810
811static int
812emx_suspend(device_t dev)
813{
814 struct emx_softc *sc = device_get_softc(dev);
815 struct ifnet *ifp = &sc->arpcom.ac_if;
816
6d435846 817 ifnet_serialize_all(ifp);
5330213c
SZ
818
819 emx_stop(sc);
820
821 emx_rel_mgmt(sc);
2d0e5700 822 emx_rel_hw_control(sc);
5330213c 823
2d0e5700 824 if (sc->wol) {
5330213c
SZ
825 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
826 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
827 emx_enable_wol(dev);
2d0e5700 828 }
5330213c 829
6d435846 830 ifnet_deserialize_all(ifp);
5330213c
SZ
831
832 return bus_generic_suspend(dev);
833}
834
835static int
836emx_resume(device_t dev)
837{
838 struct emx_softc *sc = device_get_softc(dev);
839 struct ifnet *ifp = &sc->arpcom.ac_if;
840
6d435846 841 ifnet_serialize_all(ifp);
5330213c
SZ
842
843 emx_init(sc);
844 emx_get_mgmt(sc);
845 if_devstart(ifp);
846
6d435846 847 ifnet_deserialize_all(ifp);
5330213c
SZ
848
849 return bus_generic_resume(dev);
850}
851
852static void
853emx_start(struct ifnet *ifp)
854{
855 struct emx_softc *sc = ifp->if_softc;
856 struct mbuf *m_head;
857
6d435846 858 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
859
860 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
861 return;
862
863 if (!sc->link_active) {
864 ifq_purge(&ifp->if_snd);
865 return;
866 }
867
868 while (!ifq_is_empty(&ifp->if_snd)) {
869 /* Now do we at least have a minimal? */
870 if (EMX_IS_OACTIVE(sc)) {
871 emx_tx_collect(sc);
872 if (EMX_IS_OACTIVE(sc)) {
873 ifp->if_flags |= IFF_OACTIVE;
874 sc->no_tx_desc_avail1++;
875 break;
876 }
877 }
878
879 logif(pkt_txqueue);
880 m_head = ifq_dequeue(&ifp->if_snd, NULL);
881 if (m_head == NULL)
882 break;
883
884 if (emx_encap(sc, &m_head)) {
885 ifp->if_oerrors++;
886 emx_tx_collect(sc);
887 continue;
888 }
889
890 /* Send a copy of the frame to the BPF listener */
891 ETHER_BPF_MTAP(ifp, m_head);
892
893 /* Set timeout in case hardware has problems transmitting. */
894 ifp->if_timer = EMX_TX_TIMEOUT;
895 }
896}
897
898static int
899emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
900{
901 struct emx_softc *sc = ifp->if_softc;
902 struct ifreq *ifr = (struct ifreq *)data;
903 uint16_t eeprom_data = 0;
904 int max_frame_size, mask, reinit;
905 int error = 0;
906
2c9effcf 907 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
908
909 switch (command) {
910 case SIOCSIFMTU:
911 switch (sc->hw.mac.type) {
912 case e1000_82573:
913 /*
914 * 82573 only supports jumbo frames
915 * if ASPM is disabled.
916 */
917 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
918 &eeprom_data);
919 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
920 max_frame_size = ETHER_MAX_LEN;
921 break;
922 }
923 /* FALL THROUGH */
924
925 /* Limit Jumbo Frame size */
926 case e1000_82571:
927 case e1000_82572:
928 case e1000_82574:
929 case e1000_80003es2lan:
930 max_frame_size = 9234;
931 break;
932
933 default:
934 max_frame_size = MAX_JUMBO_FRAME_SIZE;
935 break;
936 }
937 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
938 ETHER_CRC_LEN) {
939 error = EINVAL;
940 break;
941 }
942
943 ifp->if_mtu = ifr->ifr_mtu;
944 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
945 ETHER_CRC_LEN;
946
947 if (ifp->if_flags & IFF_RUNNING)
948 emx_init(sc);
949 break;
950
951 case SIOCSIFFLAGS:
952 if (ifp->if_flags & IFF_UP) {
953 if ((ifp->if_flags & IFF_RUNNING)) {
954 if ((ifp->if_flags ^ sc->if_flags) &
955 (IFF_PROMISC | IFF_ALLMULTI)) {
956 emx_disable_promisc(sc);
957 emx_set_promisc(sc);
958 }
959 } else {
960 emx_init(sc);
961 }
962 } else if (ifp->if_flags & IFF_RUNNING) {
963 emx_stop(sc);
964 }
965 sc->if_flags = ifp->if_flags;
966 break;
967
968 case SIOCADDMULTI:
969 case SIOCDELMULTI:
970 if (ifp->if_flags & IFF_RUNNING) {
971 emx_disable_intr(sc);
972 emx_set_multi(sc);
b3a7093f
SZ
973#ifdef IFPOLL_ENABLE
974 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
975#endif
976 emx_enable_intr(sc);
977 }
978 break;
979
980 case SIOCSIFMEDIA:
981 /* Check SOL/IDER usage */
982 if (e1000_check_reset_block(&sc->hw)) {
983 device_printf(sc->dev, "Media change is"
984 " blocked due to SOL/IDER session.\n");
985 break;
986 }
987 /* FALL THROUGH */
988
989 case SIOCGIFMEDIA:
990 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
991 break;
992
993 case SIOCSIFCAP:
994 reinit = 0;
995 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
996 if (mask & IFCAP_HWCSUM) {
997 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
998 reinit = 1;
999 }
1000 if (mask & IFCAP_VLAN_HWTAGGING) {
1001 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1002 reinit = 1;
1003 }
13890b61 1004 if (mask & IFCAP_RSS)
8434a83b 1005 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ
1006 if (reinit && (ifp->if_flags & IFF_RUNNING))
1007 emx_init(sc);
1008 break;
1009
1010 default:
1011 error = ether_ioctl(ifp, command, data);
1012 break;
1013 }
1014 return (error);
1015}
1016
1017static void
1018emx_watchdog(struct ifnet *ifp)
1019{
1020 struct emx_softc *sc = ifp->if_softc;
1021
2c9effcf 1022 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1023
1024 /*
1025 * The timer is set to 5 every time start queues a packet.
1026 * Then txeof keeps resetting it as long as it cleans at
1027 * least one descriptor.
1028 * Finally, anytime all descriptors are clean the timer is
1029 * set to 0.
1030 */
1031
1032 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1033 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1034 /*
1035 * If we reach here, all TX jobs are completed and
1036 * the TX engine should have been idled for some time.
1037 * We don't need to call if_devstart() here.
1038 */
1039 ifp->if_flags &= ~IFF_OACTIVE;
1040 ifp->if_timer = 0;
1041 return;
1042 }
1043
1044 /*
1045 * If we are in this routine because of pause frames, then
1046 * don't reset the hardware.
1047 */
1048 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1049 ifp->if_timer = EMX_TX_TIMEOUT;
1050 return;
1051 }
1052
1053 if (e1000_check_for_link(&sc->hw) == 0)
1054 if_printf(ifp, "watchdog timeout -- resetting\n");
1055
1056 ifp->if_oerrors++;
1057 sc->watchdog_events++;
1058
1059 emx_init(sc);
1060
1061 if (!ifq_is_empty(&ifp->if_snd))
1062 if_devstart(ifp);
1063}
1064
1065static void
1066emx_init(void *xsc)
1067{
1068 struct emx_softc *sc = xsc;
1069 struct ifnet *ifp = &sc->arpcom.ac_if;
1070 device_t dev = sc->dev;
1071 uint32_t pba;
3f939c23 1072 int i;
5330213c 1073
2c9effcf 1074 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1075
1076 emx_stop(sc);
1077
1078 /*
1079 * Packet Buffer Allocation (PBA)
1080 * Writing PBA sets the receive portion of the buffer
1081 * the remainder is used for the transmit buffer.
1082 */
1083 switch (sc->hw.mac.type) {
1084 /* Total Packet Buffer on these is 48K */
1085 case e1000_82571:
1086 case e1000_82572:
1087 case e1000_80003es2lan:
1088 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1089 break;
1090
1091 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1092 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1093 break;
1094
1095 case e1000_82574:
1096 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1097 break;
1098
1099 default:
1100 /* Devices before 82547 had a Packet Buffer of 64K. */
1101 if (sc->max_frame_size > 8192)
1102 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1103 else
1104 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1105 }
1106 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1107
1108 /* Get the latest mac address, User can use a LAA */
1109 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1110
1111 /* Put the address into the Receive Address Array */
1112 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1113
1114 /*
1115 * With the 82571 sc, RAR[0] may be overwritten
1116 * when the other port is reset, we make a duplicate
1117 * in RAR[14] for that eventuality, this assures
1118 * the interface continues to function.
1119 */
1120 if (sc->hw.mac.type == e1000_82571) {
1121 e1000_set_laa_state_82571(&sc->hw, TRUE);
1122 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1123 E1000_RAR_ENTRIES - 1);
1124 }
1125
1126 /* Initialize the hardware */
2d0e5700
SZ
1127 if (emx_reset(sc)) {
1128 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ
1129 /* XXX emx_stop()? */
1130 return;
1131 }
1132 emx_update_link_status(sc);
1133
1134 /* Setup VLAN support, basic and offload if available */
1135 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1136
1137 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1138 uint32_t ctrl;
1139
1140 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1141 ctrl |= E1000_CTRL_VME;
1142 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1143 }
1144
1145 /* Set hardware offload abilities */
1146 if (ifp->if_capenable & IFCAP_TXCSUM)
1147 ifp->if_hwassist = EMX_CSUM_FEATURES;
1148 else
1149 ifp->if_hwassist = 0;
1150
1151 /* Configure for OS presence */
1152 emx_get_mgmt(sc);
1153
1154 /* Prepare transmit descriptors and buffers */
1155 emx_init_tx_ring(sc);
1156 emx_init_tx_unit(sc);
1157
1158 /* Setup Multicast table */
1159 emx_set_multi(sc);
1160
1161 /* Prepare receive descriptors and buffers */
13890b61 1162 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
1163 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1164 device_printf(dev,
1165 "Could not setup receive structures\n");
1166 emx_stop(sc);
1167 return;
1168 }
5330213c
SZ
1169 }
1170 emx_init_rx_unit(sc);
1171
1172 /* Don't lose promiscuous settings */
1173 emx_set_promisc(sc);
1174
1175 ifp->if_flags |= IFF_RUNNING;
1176 ifp->if_flags &= ~IFF_OACTIVE;
1177
1178 callout_reset(&sc->timer, hz, emx_timer, sc);
1179 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1180
1181 /* MSI/X configuration for 82574 */
1182 if (sc->hw.mac.type == e1000_82574) {
1183 int tmp;
1184
1185 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1186 tmp |= E1000_CTRL_EXT_PBA_CLR;
1187 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1188 /*
2d0e5700 1189 * XXX MSIX
5330213c
SZ
1190 * Set the IVAR - interrupt vector routing.
1191 * Each nibble represents a vector, high bit
1192 * is enable, other 3 bits are the MSIX table
1193 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1194 * Link (other) to 2, hence the magic number.
1195 */
1196 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1197 }
1198
b3a7093f 1199#ifdef IFPOLL_ENABLE
5330213c
SZ
1200 /*
1201 * Only enable interrupts if we are not polling, make sure
1202 * they are off otherwise.
1203 */
b3a7093f 1204 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1205 emx_disable_intr(sc);
1206 else
b3a7093f 1207#endif /* IFPOLL_ENABLE */
5330213c
SZ
1208 emx_enable_intr(sc);
1209
2d0e5700
SZ
1210 /* AMT based hardware can now take control from firmware */
1211 if (sc->has_manage && sc->has_amt)
1212 emx_get_hw_control(sc);
1213
5330213c
SZ
1214 /* Don't reset the phy next time init gets called */
1215 sc->hw.phy.reset_disable = TRUE;
1216}
1217
5330213c
SZ
1218static void
1219emx_intr(void *xsc)
1220{
4cb541ae
SZ
1221 emx_intr_body(xsc, TRUE);
1222}
1223
1224static void
1225emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1226{
5330213c
SZ
1227 struct ifnet *ifp = &sc->arpcom.ac_if;
1228 uint32_t reg_icr;
1229
1230 logif(intr_beg);
6d435846 1231 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1232
1233 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1234
4cb541ae 1235 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ
1236 logif(intr_end);
1237 return;
1238 }
1239
1240 /*
1241 * XXX: some laptops trigger several spurious interrupts
df50f778 1242 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1243 * reports all-ones value in this case. Processing such
1244 * interrupts would lead to a freeze. I don't know why.
1245 */
1246 if (reg_icr == 0xffffffff) {
1247 logif(intr_end);
1248 return;
1249 }
1250
1251 if (ifp->if_flags & IFF_RUNNING) {
1252 if (reg_icr &
3f939c23
SZ
1253 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1254 int i;
1255
13890b61 1256 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ
1257 lwkt_serialize_enter(
1258 &sc->rx_data[i].rx_serialize);
3f939c23 1259 emx_rxeof(sc, i, -1);
6d435846
SZ
1260 lwkt_serialize_exit(
1261 &sc->rx_data[i].rx_serialize);
1262 }
3f939c23 1263 }
6446af7b 1264 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1265 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1266 emx_txeof(sc);
1267 if (!ifq_is_empty(&ifp->if_snd))
1268 if_devstart(ifp);
6d435846 1269 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1270 }
1271 }
1272
1273 /* Link status change */
1274 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1275 emx_serialize_skipmain(sc);
6d435846 1276
5330213c
SZ
1277 callout_stop(&sc->timer);
1278 sc->hw.mac.get_link_status = 1;
1279 emx_update_link_status(sc);
1280
1281 /* Deal with TX cruft when link lost */
1282 emx_tx_purge(sc);
1283
1284 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1285
bca7c435 1286 emx_deserialize_skipmain(sc);
5330213c
SZ
1287 }
1288
1289 if (reg_icr & E1000_ICR_RXO)
1290 sc->rx_overruns++;
1291
1292 logif(intr_end);
1293}
1294
1295static void
4cb541ae
SZ
1296emx_intr_mask(void *xsc)
1297{
1298 struct emx_softc *sc = xsc;
1299
1300 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1301 /*
1302 * NOTE:
1303 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1304 * so don't check it.
1305 */
1306 emx_intr_body(sc, FALSE);
1307 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1308}
1309
1310static void
5330213c
SZ
1311emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1312{
1313 struct emx_softc *sc = ifp->if_softc;
1314
2c9effcf 1315 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1316
1317 emx_update_link_status(sc);
1318
1319 ifmr->ifm_status = IFM_AVALID;
1320 ifmr->ifm_active = IFM_ETHER;
1321
1322 if (!sc->link_active)
1323 return;
1324
1325 ifmr->ifm_status |= IFM_ACTIVE;
1326
1327 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1328 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1329 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1330 } else {
1331 switch (sc->link_speed) {
1332 case 10:
1333 ifmr->ifm_active |= IFM_10_T;
1334 break;
1335 case 100:
1336 ifmr->ifm_active |= IFM_100_TX;
1337 break;
1338
1339 case 1000:
1340 ifmr->ifm_active |= IFM_1000_T;
1341 break;
1342 }
1343 if (sc->link_duplex == FULL_DUPLEX)
1344 ifmr->ifm_active |= IFM_FDX;
1345 else
1346 ifmr->ifm_active |= IFM_HDX;
1347 }
1348}
1349
1350static int
1351emx_media_change(struct ifnet *ifp)
1352{
1353 struct emx_softc *sc = ifp->if_softc;
1354 struct ifmedia *ifm = &sc->media;
1355
2c9effcf 1356 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1357
1358 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1359 return (EINVAL);
1360
1361 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1362 case IFM_AUTO:
1363 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1364 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1365 break;
1366
1367 case IFM_1000_LX:
1368 case IFM_1000_SX:
1369 case IFM_1000_T:
1370 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1371 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1372 break;
1373
1374 case IFM_100_TX:
1375 sc->hw.mac.autoneg = FALSE;
1376 sc->hw.phy.autoneg_advertised = 0;
1377 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1378 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1379 else
1380 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1381 break;
1382
1383 case IFM_10_T:
1384 sc->hw.mac.autoneg = FALSE;
1385 sc->hw.phy.autoneg_advertised = 0;
1386 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1387 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1388 else
1389 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1390 break;
1391
1392 default:
1393 if_printf(ifp, "Unsupported media type\n");
1394 break;
1395 }
1396
1397 /*
1398 * As the speed/duplex settings my have changed we need to
1399 * reset the PHY.
1400 */
1401 sc->hw.phy.reset_disable = FALSE;
1402
1403 emx_init(sc);
1404
1405 return (0);
1406}
1407
1408static int
1409emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1410{
1411 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1412 bus_dmamap_t map;
323e5ecd 1413 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ
1414 struct e1000_tx_desc *ctxd = NULL;
1415 struct mbuf *m_head = *m_headp;
1416 uint32_t txd_upper, txd_lower, cmd = 0;
1417 int maxsegs, nsegs, i, j, first, last = 0, error;
1418
5330213c
SZ
1419 txd_upper = txd_lower = 0;
1420
1421 /*
1422 * Capture the first descriptor index, this descriptor
1423 * will have the index of the EOP which is the only one
1424 * that now gets a DONE bit writeback.
1425 */
1426 first = sc->next_avail_tx_desc;
323e5ecd 1427 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1428 tx_buffer_mapped = tx_buffer;
1429 map = tx_buffer->map;
1430
1431 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1432 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ
1433 if (maxsegs > EMX_MAX_SCATTER)
1434 maxsegs = EMX_MAX_SCATTER;
1435
1436 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1437 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1438 if (error) {
1439 if (error == ENOBUFS)
1440 sc->mbuf_alloc_failed++;
1441 else
1442 sc->no_tx_dma_setup++;
1443
1444 m_freem(*m_headp);
1445 *m_headp = NULL;
1446 return error;
1447 }
1448 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1449
1450 m_head = *m_headp;
1451 sc->tx_nsegs += nsegs;
1452
1453 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1454 /* TX csum offloading will consume one TX desc */
1455 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1456 }
1457 i = sc->next_avail_tx_desc;
1458
1459 /* Set up our transmit descriptors */
1460 for (j = 0; j < nsegs; j++) {
323e5ecd 1461 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1462 ctxd = &sc->tx_desc_base[i];
1463
1464 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1465 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1466 txd_lower | segs[j].ds_len);
1467 ctxd->upper.data = htole32(txd_upper);
1468
1469 last = i;
1470 if (++i == sc->num_tx_desc)
1471 i = 0;
5330213c
SZ
1472 }
1473
1474 sc->next_avail_tx_desc = i;
1475
1476 KKASSERT(sc->num_tx_desc_avail > nsegs);
1477 sc->num_tx_desc_avail -= nsegs;
1478
1479 /* Handle VLAN tag */
1480 if (m_head->m_flags & M_VLANTAG) {
1481 /* Set the vlan id. */
1482 ctxd->upper.fields.special =
1483 htole16(m_head->m_pkthdr.ether_vlantag);
1484
1485 /* Tell hardware to add tag */
1486 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1487 }
1488
1489 tx_buffer->m_head = m_head;
1490 tx_buffer_mapped->map = tx_buffer->map;
1491 tx_buffer->map = map;
1492
1493 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1494 sc->tx_nsegs = 0;
4e4e8481
SZ
1495
1496 /*
1497 * Report Status (RS) is turned on
1498 * every tx_int_nsegs descriptors.
1499 */
5330213c
SZ
1500 cmd = E1000_TXD_CMD_RS;
1501
b4b0a2b4
SZ
1502 /*
1503 * Keep track of the descriptor, which will
1504 * be written back by hardware.
1505 */
5330213c
SZ
1506 sc->tx_dd[sc->tx_dd_tail] = last;
1507 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1508 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1509 }
1510
1511 /*
1512 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1513 */
1514 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1515
1516 /*
5330213c
SZ
1517 * Advance the Transmit Descriptor Tail (TDT), this tells
1518 * the E1000 that this frame is available to transmit.
1519 */
1520 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1521
1522 return (0);
1523}
1524
1525static void
1526emx_set_promisc(struct emx_softc *sc)
1527{
1528 struct ifnet *ifp = &sc->arpcom.ac_if;
1529 uint32_t reg_rctl;
1530
1531 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1532
1533 if (ifp->if_flags & IFF_PROMISC) {
1534 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1535 /* Turn this on if you want to see bad packets */
1536 if (emx_debug_sbp)
1537 reg_rctl |= E1000_RCTL_SBP;
1538 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1539 } else if (ifp->if_flags & IFF_ALLMULTI) {
1540 reg_rctl |= E1000_RCTL_MPE;
1541 reg_rctl &= ~E1000_RCTL_UPE;
1542 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1543 }
1544}
1545
1546static void
1547emx_disable_promisc(struct emx_softc *sc)
1548{
1549 uint32_t reg_rctl;
1550
1551 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1552
1553 reg_rctl &= ~E1000_RCTL_UPE;
1554 reg_rctl &= ~E1000_RCTL_MPE;
1555 reg_rctl &= ~E1000_RCTL_SBP;
1556 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1557}
1558
1559static void
1560emx_set_multi(struct emx_softc *sc)
1561{
1562 struct ifnet *ifp = &sc->arpcom.ac_if;
1563 struct ifmultiaddr *ifma;
1564 uint32_t reg_rctl = 0;
2d0e5700 1565 uint8_t *mta;
5330213c
SZ
1566 int mcnt = 0;
1567
2d0e5700
SZ
1568 mta = sc->mta;
1569 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1570
441d34b2 1571 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ
1572 if (ifma->ifma_addr->sa_family != AF_LINK)
1573 continue;
1574
1575 if (mcnt == EMX_MCAST_ADDR_MAX)
1576 break;
1577
1578 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1579 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1580 mcnt++;
1581 }
1582
1583 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1584 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1585 reg_rctl |= E1000_RCTL_MPE;
1586 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1587 } else {
6a5a645e 1588 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ
1589 }
1590}
1591
1592/*
1593 * This routine checks for link status and updates statistics.
1594 */
1595static void
1596emx_timer(void *xsc)
1597{
1598 struct emx_softc *sc = xsc;
1599 struct ifnet *ifp = &sc->arpcom.ac_if;
1600
6d435846 1601 ifnet_serialize_all(ifp);
5330213c
SZ
1602
1603 emx_update_link_status(sc);
1604 emx_update_stats(sc);
1605
1606 /* Reset LAA into RAR[0] on 82571 */
1607 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1608 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1609
1610 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1611 emx_print_hw_stats(sc);
1612
1613 emx_smartspeed(sc);
1614
1615 callout_reset(&sc->timer, hz, emx_timer, sc);
1616
6d435846 1617 ifnet_deserialize_all(ifp);
5330213c
SZ
1618}
1619
1620static void
1621emx_update_link_status(struct emx_softc *sc)
1622{
1623 struct e1000_hw *hw = &sc->hw;
1624 struct ifnet *ifp = &sc->arpcom.ac_if;
1625 device_t dev = sc->dev;
1626 uint32_t link_check = 0;
1627
1628 /* Get the cached link value or read phy for real */
1629 switch (hw->phy.media_type) {
1630 case e1000_media_type_copper:
1631 if (hw->mac.get_link_status) {
1632 /* Do the work to read phy */
1633 e1000_check_for_link(hw);
1634 link_check = !hw->mac.get_link_status;
1635 if (link_check) /* ESB2 fix */
1636 e1000_cfg_on_link_up(hw);
1637 } else {
1638 link_check = TRUE;
1639 }
1640 break;
1641
1642 case e1000_media_type_fiber:
1643 e1000_check_for_link(hw);
1644 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1645 break;
1646
1647 case e1000_media_type_internal_serdes:
1648 e1000_check_for_link(hw);
1649 link_check = sc->hw.mac.serdes_has_link;
1650 break;
1651
1652 case e1000_media_type_unknown:
1653 default:
1654 break;
1655 }
1656
1657 /* Now check for a transition */
1658 if (link_check && sc->link_active == 0) {
1659 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1660 &sc->link_duplex);
1661
1662 /*
1663 * Check if we should enable/disable SPEED_MODE bit on
1664 * 82571EB/82572EI
1665 */
2d0e5700
SZ
1666 if (sc->link_speed != SPEED_1000 &&
1667 (hw->mac.type == e1000_82571 ||
1668 hw->mac.type == e1000_82572)) {
5330213c
SZ
1669 int tarc0;
1670
1671 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1672 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ
1673 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1674 }
1675 if (bootverbose) {
1676 device_printf(dev, "Link is up %d Mbps %s\n",
1677 sc->link_speed,
1678 ((sc->link_duplex == FULL_DUPLEX) ?
1679 "Full Duplex" : "Half Duplex"));
1680 }
1681 sc->link_active = 1;
1682 sc->smartspeed = 0;
1683 ifp->if_baudrate = sc->link_speed * 1000000;
1684 ifp->if_link_state = LINK_STATE_UP;
1685 if_link_state_change(ifp);
1686 } else if (!link_check && sc->link_active == 1) {
1687 ifp->if_baudrate = sc->link_speed = 0;
1688 sc->link_duplex = 0;
1689 if (bootverbose)
1690 device_printf(dev, "Link is Down\n");
1691 sc->link_active = 0;
1692#if 0
1693 /* Link down, disable watchdog */
1694 if->if_timer = 0;
1695#endif
1696 ifp->if_link_state = LINK_STATE_DOWN;
1697 if_link_state_change(ifp);
1698 }
1699}
1700
1701static void
1702emx_stop(struct emx_softc *sc)
1703{
1704 struct ifnet *ifp = &sc->arpcom.ac_if;
1705 int i;
1706
2c9effcf 1707 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1708
1709 emx_disable_intr(sc);
1710
1711 callout_stop(&sc->timer);
1712
1713 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1714 ifp->if_timer = 0;
1715
3f939c23
SZ
1716 /*
1717 * Disable multiple receive queues.
1718 *
1719 * NOTE:
1720 * We should disable multiple receive queues before
1721 * resetting the hardware.
1722 */
1723 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1724
5330213c
SZ
1725 e1000_reset_hw(&sc->hw);
1726 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1727
1728 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1729 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1730
1731 if (tx_buffer->m_head != NULL) {
1732 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1733 m_freem(tx_buffer->m_head);
1734 tx_buffer->m_head = NULL;
1735 }
1736 }
1737
13890b61 1738 for (i = 0; i < sc->rx_ring_cnt; ++i)
3f939c23 1739 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ
1740
1741 sc->csum_flags = 0;
1742 sc->csum_ehlen = 0;
1743 sc->csum_iphlen = 0;
1744
1745 sc->tx_dd_head = 0;
1746 sc->tx_dd_tail = 0;
1747 sc->tx_nsegs = 0;
1748}
1749
1750static int
2d0e5700 1751emx_reset(struct emx_softc *sc)
5330213c
SZ
1752{
1753 device_t dev = sc->dev;
1754 uint16_t rx_buffer_size;
1755
5330213c
SZ
1756 /* Set up smart power down as default off on newer adapters. */
1757 if (!emx_smart_pwr_down &&
1758 (sc->hw.mac.type == e1000_82571 ||
1759 sc->hw.mac.type == e1000_82572)) {
1760 uint16_t phy_tmp = 0;
1761
1762 /* Speed up time to link by disabling smart power down. */
1763 e1000_read_phy_reg(&sc->hw,
1764 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1765 phy_tmp &= ~IGP02E1000_PM_SPD;
1766 e1000_write_phy_reg(&sc->hw,
1767 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1768 }
1769
1770 /*
1771 * These parameters control the automatic generation (Tx) and
1772 * response (Rx) to Ethernet PAUSE frames.
1773 * - High water mark should allow for at least two frames to be
1774 * received after sending an XOFF.
1775 * - Low water mark works best when it is very near the high water mark.
1776 * This allows the receiver to restart by sending XON when it has
1777 * drained a bit. Here we use an arbitary value of 1500 which will
1778 * restart after one full frame is pulled from the buffer. There
1779 * could be several smaller frames in the buffer and if so they will
1780 * not trigger the XON until their total number reduces the buffer
1781 * by 1500.
1782 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1783 */
1784 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1785
1786 sc->hw.fc.high_water = rx_buffer_size -
1787 roundup2(sc->max_frame_size, 1024);
1788 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1789
1790 if (sc->hw.mac.type == e1000_80003es2lan)
1791 sc->hw.fc.pause_time = 0xFFFF;
1792 else
1793 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1794 sc->hw.fc.send_xon = TRUE;
1795 sc->hw.fc.requested_mode = e1000_fc_full;
1796
2d0e5700
SZ
1797 /* Issue a global reset */
1798 e1000_reset_hw(&sc->hw);
1799 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1800 emx_disable_aspm(sc);
2d0e5700 1801
5330213c
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1802 if (e1000_init_hw(&sc->hw) < 0) {
1803 device_printf(dev, "Hardware Initialization Failed\n");
1804 return (EIO);
1805 }
1806
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SZ
1807 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1808 e1000_get_phy_info(&sc->hw);
5330213c
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1809 e1000_check_for_link(&sc->hw);
1810
1811 return (0);
1812}
1813
1814static void
1815emx_setup_ifp(struct emx_softc *sc)
1816{
1817 struct ifnet *ifp = &sc->arpcom.ac_if;
1818
1819 if_initname(ifp, device_get_name(sc->dev),
1820 device_get_unit(sc->dev));
1821 ifp->if_softc = sc;
1822 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1823 ifp->if_init = emx_init;
1824 ifp->if_ioctl = emx_ioctl;
1825 ifp->if_start = emx_start;
b3a7093f
SZ
1826#ifdef IFPOLL_ENABLE
1827 ifp->if_qpoll = emx_qpoll;
5330213c
SZ
1828#endif
1829 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1830 ifp->if_serialize = emx_serialize;
1831 ifp->if_deserialize = emx_deserialize;
1832 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1833#ifdef INVARIANTS
1834 ifp->if_serialize_assert = emx_serialize_assert;
1835#endif
5330213c
SZ
1836 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1837 ifq_set_ready(&ifp->if_snd);
1838
ae474cfa 1839 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ
1840
1841 ifp->if_capabilities = IFCAP_HWCSUM |
1842 IFCAP_VLAN_HWTAGGING |
1843 IFCAP_VLAN_MTU;
8434a83b
SZ
1844 if (sc->rx_ring_cnt > 1)
1845 ifp->if_capabilities |= IFCAP_RSS;
5330213c
SZ
1846 ifp->if_capenable = ifp->if_capabilities;
1847 ifp->if_hwassist = EMX_CSUM_FEATURES;
1848
1849 /*
1850 * Tell the upper layer(s) we support long frames.
1851 */
1852 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1853
1854 /*
1855 * Specify the media types supported by this sc and register
1856 * callbacks to update media and link information
1857 */
1858 ifmedia_init(&sc->media, IFM_IMASK,
1859 emx_media_change, emx_media_status);
1860 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1861 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1862 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1863 0, NULL);
1864 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1865 } else {
1866 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1867 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1868 0, NULL);
1869 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1870 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1871 0, NULL);
1872 if (sc->hw.phy.type != e1000_phy_ife) {
1873 ifmedia_add(&sc->media,
1874 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1875 ifmedia_add(&sc->media,
1876 IFM_ETHER | IFM_1000_T, 0, NULL);
1877 }
1878 }
1879 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1880 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1881}
1882
1883/*
1884 * Workaround for SmartSpeed on 82541 and 82547 controllers
1885 */
1886static void
1887emx_smartspeed(struct emx_softc *sc)
1888{
1889 uint16_t phy_tmp;
1890
1891 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1892 sc->hw.mac.autoneg == 0 ||
1893 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1894 return;
1895
1896 if (sc->smartspeed == 0) {
1897 /*
1898 * If Master/Slave config fault is asserted twice,
1899 * we assume back-to-back
1900 */
1901 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1902 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1903 return;
1904 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1905 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1906 e1000_read_phy_reg(&sc->hw,
1907 PHY_1000T_CTRL, &phy_tmp);
1908 if (phy_tmp & CR_1000T_MS_ENABLE) {
1909 phy_tmp &= ~CR_1000T_MS_ENABLE;
1910 e1000_write_phy_reg(&sc->hw,
1911 PHY_1000T_CTRL, phy_tmp);
1912 sc->smartspeed++;
1913 if (sc->hw.mac.autoneg &&
1914 !e1000_phy_setup_autoneg(&sc->hw) &&
1915 !e1000_read_phy_reg(&sc->hw,
1916 PHY_CONTROL, &phy_tmp)) {
1917 phy_tmp |= MII_CR_AUTO_NEG_EN |
1918 MII_CR_RESTART_AUTO_NEG;
1919 e1000_write_phy_reg(&sc->hw,
1920 PHY_CONTROL, phy_tmp);
1921 }
1922 }
1923 }
1924 return;
1925 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1926 /* If still no link, perhaps using 2/3 pair cable */
1927 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1928 phy_tmp |= CR_1000T_MS_ENABLE;
1929 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1930 if (sc->hw.mac.autoneg &&
1931 !e1000_phy_setup_autoneg(&sc->hw) &&
1932 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1933 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1934 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1935 }
1936 }
1937
1938 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1939 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1940 sc->smartspeed = 0;
1941}
1942
1943static int
5330213c
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1944emx_create_tx_ring(struct emx_softc *sc)
1945{
1946 device_t dev = sc->dev;
323e5ecd 1947 struct emx_txbuf *tx_buffer;
b4d8c36b 1948 int error, i, tsize, ntxd;
bdca134f
SZ
1949
1950 /*
1951 * Validate number of transmit descriptors. It must not exceed
1952 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1953 */
b4d8c36b
SZ
1954 ntxd = device_getenv_int(dev, "txd", emx_txd);
1955 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1956 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 1957 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 1958 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ
1959 sc->num_tx_desc = EMX_DEFAULT_TXD;
1960 } else {
b4d8c36b 1961 sc->num_tx_desc = ntxd;
bdca134f
SZ
1962 }
1963
1964 /*
1965 * Allocate Transmit Descriptor ring
1966 */
1967 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1968 EMX_DBA_ALIGN);
a596084c
SZ
1969 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1970 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1971 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1972 &sc->tx_desc_paddr);
1973 if (sc->tx_desc_base == NULL) {
bdca134f 1974 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 1975 return ENOMEM;
bdca134f 1976 }
5330213c 1977
323e5ecd
SZ
1978 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1979 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
1980
1981 /*
1982 * Create DMA tags for tx buffers
1983 */
1984 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1985 1, 0, /* alignment, bounds */
1986 BUS_SPACE_MAXADDR, /* lowaddr */
1987 BUS_SPACE_MAXADDR, /* highaddr */
1988 NULL, NULL, /* filter, filterarg */
1989 EMX_TSO_SIZE, /* maxsize */
1990 EMX_MAX_SCATTER, /* nsegments */
1991 EMX_MAX_SEGSIZE, /* maxsegsize */
1992 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1993 BUS_DMA_ONEBPAGE, /* flags */
1994 &sc->txtag);
1995 if (error) {
1996 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ
1997 kfree(sc->tx_buf, M_DEVBUF);
1998 sc->tx_buf = NULL;
5330213c
SZ
1999 return error;
2000 }
2001
2002 /*
2003 * Create DMA maps for tx buffers
2004 */
2005 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2006 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2007
2008 error = bus_dmamap_create(sc->txtag,
2009 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2010 &tx_buffer->map);
2011 if (error) {
2012 device_printf(dev, "Unable to create TX DMA map\n");
2013 emx_destroy_tx_ring(sc, i);
2014 return error;
2015 }
2016 }
2017 return (0);
2018}
2019
2020static void
2021emx_init_tx_ring(struct emx_softc *sc)
2022{
2023 /* Clear the old ring contents */
2024 bzero(sc->tx_desc_base,
2025 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2026
2027 /* Reset state */
2028 sc->next_avail_tx_desc = 0;
2029 sc->next_tx_to_clean = 0;
2030 sc->num_tx_desc_avail = sc->num_tx_desc;
2031}
2032
2033static void
2034emx_init_tx_unit(struct emx_softc *sc)
2035{
2036 uint32_t tctl, tarc, tipg = 0;
2037 uint64_t bus_addr;
2038
2039 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2040 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
2041 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2042 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2043 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2044 (uint32_t)(bus_addr >> 32));
2045 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2046 (uint32_t)bus_addr);
2047 /* Setup the HW Tx Head and Tail descriptor pointers */
2048 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2049 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2050
2051 /* Set the default values for the Tx Inter Packet Gap timer */
2052 switch (sc->hw.mac.type) {
2053 case e1000_80003es2lan:
2054 tipg = DEFAULT_82543_TIPG_IPGR1;
2055 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2056 E1000_TIPG_IPGR2_SHIFT;
2057 break;
2058
2059 default:
2060 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2061 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2062 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2063 else
2064 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2065 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2066 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2067 break;
2068 }
2069
2070 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2071
2072 /* NOTE: 0 is not allowed for TIDV */
2073 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2074 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2075
2076 if (sc->hw.mac.type == e1000_82571 ||
2077 sc->hw.mac.type == e1000_82572) {
2078 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2079 tarc |= EMX_TARC_SPEED_MODE;
2080 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2081 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2082 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2083 tarc |= 1;
2084 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2085 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2086 tarc |= 1;
2087 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2088 }
2089
2090 /* Program the Transmit Control Register */
2091 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2092 tctl &= ~E1000_TCTL_CT;
2093 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2094 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2095 tctl |= E1000_TCTL_MULR;
2096
2097 /* This write will effectively turn on the transmit unit. */
2098 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2099}
2100
2101static void
2102emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2103{
323e5ecd 2104 struct emx_txbuf *tx_buffer;
5330213c
SZ
2105 int i;
2106
bdca134f 2107 /* Free Transmit Descriptor ring */
a596084c
SZ
2108 if (sc->tx_desc_base) {
2109 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2110 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2111 sc->tx_desc_dmap);
2112 bus_dma_tag_destroy(sc->tx_desc_dtag);
2113
2114 sc->tx_desc_base = NULL;
2115 }
bdca134f 2116
323e5ecd 2117 if (sc->tx_buf == NULL)
5330213c
SZ
2118 return;
2119
2120 for (i = 0; i < ndesc; i++) {
323e5ecd 2121 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2122
2123 KKASSERT(tx_buffer->m_head == NULL);
2124 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2125 }
2126 bus_dma_tag_destroy(sc->txtag);
2127
323e5ecd
SZ
2128 kfree(sc->tx_buf, M_DEVBUF);
2129 sc->tx_buf = NULL;
5330213c
SZ
2130}
2131
2132/*
2133 * The offload context needs to be set when we transfer the first
2134 * packet of a particular protocol (TCP/UDP). This routine has been
2135 * enhanced to deal with inserted VLAN headers.
2136 *
2137 * If the new packet's ether header length, ip header length and
2138 * csum offloading type are same as the previous packet, we should
2139 * avoid allocating a new csum context descriptor; mainly to take
2140 * advantage of the pipeline effect of the TX data read request.
2141 *
2142 * This function returns number of TX descrptors allocated for
2143 * csum context.
2144 */
2145static int
2146emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2147 uint32_t *txd_upper, uint32_t *txd_lower)
2148{
2149 struct e1000_context_desc *TXD;
323e5ecd 2150 struct emx_txbuf *tx_buffer;
5330213c
SZ
2151 int curr_txd, ehdrlen, csum_flags;
2152 uint32_t cmd, hdr_len, ip_hlen;
5330213c
SZ
2153
2154 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
68447568
SZ
2155 ip_hlen = mp->m_pkthdr.csum_iphlen;
2156 ehdrlen = mp->m_pkthdr.csum_lhlen;
5330213c
SZ
2157
2158 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2159 sc->csum_flags == csum_flags) {
2160 /*
2161 * Same csum offload context as the previous packets;
2162 * just return.
2163 */
2164 *txd_upper = sc->csum_txd_upper;
2165 *txd_lower = sc->csum_txd_lower;
2166 return 0;
2167 }
2168
2169 /*
2170 * Setup a new csum offload context.
2171 */
2172
2173 curr_txd = sc->next_avail_tx_desc;
323e5ecd 2174 tx_buffer = &sc->tx_buf[curr_txd];
5330213c
SZ
2175 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2176
2177 cmd = 0;
2178
2179 /* Setup of IP header checksum. */
2180 if (csum_flags & CSUM_IP) {
2181 /*
2182 * Start offset for header checksum calculation.
2183 * End offset for header checksum calculation.
2184 * Offset of place to put the checksum.
2185 */
2186 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2187 TXD->lower_setup.ip_fields.ipcse =
2188 htole16(ehdrlen + ip_hlen - 1);
2189 TXD->lower_setup.ip_fields.ipcso =
2190 ehdrlen + offsetof(struct ip, ip_sum);
2191 cmd |= E1000_TXD_CMD_IP;
2192 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2193 }
2194 hdr_len = ehdrlen + ip_hlen;
2195
2196 if (csum_flags & CSUM_TCP) {
2197 /*
2198 * Start offset for payload checksum calculation.
2199 * End offset for payload checksum calculation.
2200 * Offset of place to put the checksum.
2201 */
2202 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2203 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2204 TXD->upper_setup.tcp_fields.tucso =
2205 hdr_len + offsetof(struct tcphdr, th_sum);
2206 cmd |= E1000_TXD_CMD_TCP;
2207 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2208 } else if (csum_flags & CSUM_UDP) {
2209 /*
2210 * Start offset for header checksum calculation.
2211 * End offset for header checksum calculation.
2212 * Offset of place to put the checksum.
2213 */
2214 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2215 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2216 TXD->upper_setup.tcp_fields.tucso =
2217 hdr_len + offsetof(struct udphdr, uh_sum);
2218 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2219 }
2220
2221 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2222 E1000_TXD_DTYP_D; /* Data descr */
2223
2224 /* Save the information for this csum offloading context */
2225 sc->csum_ehlen = ehdrlen;
2226 sc->csum_iphlen = ip_hlen;
2227 sc->csum_flags = csum_flags;
2228 sc->csum_txd_upper = *txd_upper;
2229 sc->csum_txd_lower = *txd_lower;
2230
2231 TXD->tcp_seg_setup.data = htole32(0);
2232 TXD->cmd_and_length =
2233 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2234
2235 if (++curr_txd == sc->num_tx_desc)
2236 curr_txd = 0;
2237
2238 KKASSERT(sc->num_tx_desc_avail > 0);
2239 sc->num_tx_desc_avail--;
2240
2241 sc->next_avail_tx_desc = curr_txd;
2242 return 1;
2243}
2244
5330213c
SZ
2245static void
2246emx_txeof(struct emx_softc *sc)
2247{
2248 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2249 struct emx_txbuf *tx_buffer;
5330213c
SZ
2250 int first, num_avail;
2251
2252 if (sc->tx_dd_head == sc->tx_dd_tail)
2253 return;
2254
2255 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2256 return;
2257
2258 num_avail = sc->num_tx_desc_avail;
2259 first = sc->next_tx_to_clean;
2260
2261 while (sc->tx_dd_head != sc->tx_dd_tail) {
2262 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2263 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2264
2265 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2266 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2267 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2268
2269 if (++dd_idx == sc->num_tx_desc)
2270 dd_idx = 0;
2271
2272 while (first != dd_idx) {
2273 logif(pkt_txclean);
2274
5330213c
SZ
2275 num_avail++;
2276
323e5ecd 2277 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2278 if (tx_buffer->m_head) {
2279 ifp->if_opackets++;
2280 bus_dmamap_unload(sc->txtag,
2281 tx_buffer->map);
2282 m_freem(tx_buffer->m_head);
2283 tx_buffer->m_head = NULL;
2284 }
2285
2286 if (++first == sc->num_tx_desc)
2287 first = 0;
2288 }
2289 } else {
2290 break;
2291 }
2292 }
2293 sc->next_tx_to_clean = first;
2294 sc->num_tx_desc_avail = num_avail;
2295
2296 if (sc->tx_dd_head == sc->tx_dd_tail) {
2297 sc->tx_dd_head = 0;
2298 sc->tx_dd_tail = 0;
2299 }
2300
2301 if (!EMX_IS_OACTIVE(sc)) {
2302 ifp->if_flags &= ~IFF_OACTIVE;
2303
2304 /* All clean, turn off the timer */
2305 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2306 ifp->if_timer = 0;
2307 }
2308}
2309
2310static void
2311emx_tx_collect(struct emx_softc *sc)
2312{
2313 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2314 struct emx_txbuf *tx_buffer;
5330213c
SZ
2315 int tdh, first, num_avail, dd_idx = -1;
2316
2317 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2318 return;
2319
2320 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2321 if (tdh == sc->next_tx_to_clean)
2322 return;
2323
2324 if (sc->tx_dd_head != sc->tx_dd_tail)
2325 dd_idx = sc->tx_dd[sc->tx_dd_head];
2326
2327 num_avail = sc->num_tx_desc_avail;
2328 first = sc->next_tx_to_clean;
2329
2330 while (first != tdh) {
2331 logif(pkt_txclean);
2332
5330213c
SZ
2333 num_avail++;
2334
323e5ecd 2335 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2336 if (tx_buffer->m_head) {
2337 ifp->if_opackets++;
2338 bus_dmamap_unload(sc->txtag,
2339 tx_buffer->map);
2340 m_freem(tx_buffer->m_head);
2341 tx_buffer->m_head = NULL;
2342 }
2343
2344 if (first == dd_idx) {
2345 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2346 if (sc->tx_dd_head == sc->tx_dd_tail) {
2347 sc->tx_dd_head = 0;
2348 sc->tx_dd_tail = 0;
2349 dd_idx = -1;
2350 } else {
2351 dd_idx = sc->tx_dd[sc->tx_dd_head];
2352 }
2353 }
2354
2355 if (++first == sc->num_tx_desc)
2356 first = 0;
2357 }
2358 sc->next_tx_to_clean = first;
2359 sc->num_tx_desc_avail = num_avail;
2360
2361 if (!EMX_IS_OACTIVE(sc)) {
2362 ifp->if_flags &= ~IFF_OACTIVE;
2363
2364 /* All clean, turn off the timer */
2365 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2366 ifp->if_timer = 0;
2367 }
2368}
2369
2370/*
2371 * When Link is lost sometimes there is work still in the TX ring
2372 * which will result in a watchdog, rather than allow that do an
2373 * attempted cleanup and then reinit here. Note that this has been
2374 * seens mostly with fiber adapters.
2375 */
2376static void
2377emx_tx_purge(struct emx_softc *sc)
2378{
2379 struct ifnet *ifp = &sc->arpcom.ac_if;
2380
2381 if (!sc->link_active && ifp->if_timer) {
2382 emx_tx_collect(sc);
2383 if (ifp->if_timer) {
2384 if_printf(ifp, "Link lost, TX pending, reinit\n");
2385 ifp->if_timer = 0;
2386 emx_init(sc);
2387 }
2388 }
2389}
2390
2391static int
c39e3a1f 2392emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2393{
2394 struct mbuf *m;
2395 bus_dma_segment_t seg;
2396 bus_dmamap_t map;
323e5ecd 2397 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2398 int error, nseg;
2399
2400 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2401 if (m == NULL) {
c39e3a1f 2402 rdata->mbuf_cluster_failed++;
5330213c
SZ
2403 if (init) {
2404 if_printf(&sc->arpcom.ac_if,
2405 "Unable to allocate RX mbuf\n");
2406 }
2407 return (ENOBUFS);
2408 }
2409 m->m_len = m->m_pkthdr.len = MCLBYTES;
2410
2411 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2412 m_adj(m, ETHER_ALIGN);
2413
c39e3a1f
SZ
2414 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2415 rdata->rx_sparemap, m,
5330213c
SZ
2416 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2417 if (error) {
2418 m_freem(m);
2419 if (init) {
2420 if_printf(&sc->arpcom.ac_if,
2421 "Unable to load RX mbuf\n");
2422 }
2423 return (error);
2424 }
2425
323e5ecd 2426 rx_buffer = &rdata->rx_buf[i];
5330213c 2427 if (rx_buffer->m_head != NULL)
c39e3a1f 2428 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2429
2430 map = rx_buffer->map;
c39e3a1f
SZ
2431 rx_buffer->map = rdata->rx_sparemap;
2432 rdata->rx_sparemap = map;
5330213c
SZ
2433
2434 rx_buffer->m_head = m;
235b9d30 2435 rx_buffer->paddr = seg.ds_addr;
5330213c 2436
235b9d30 2437 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2438 return (0);
2439}
2440
2441static int
c39e3a1f 2442emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2443{
2444 device_t dev = sc->dev;
323e5ecd 2445 struct emx_rxbuf *rx_buffer;
b4d8c36b 2446 int i, error, rsize, nrxd;
bdca134f
SZ
2447
2448 /*
2449 * Validate number of receive descriptors. It must not exceed
2450 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2451 */
b4d8c36b
SZ
2452 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2453 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2454 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2455 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2456 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2457 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2458 } else {
b4d8c36b 2459 rdata->num_rx_desc = nrxd;
bdca134f
SZ
2460 }
2461
2462 /*
2463 * Allocate Receive Descriptor ring
2464 */
235b9d30 2465 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2466 EMX_DBA_ALIGN);
235b9d30 2467 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2468 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2469 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2470 &rdata->rx_desc_paddr);
235b9d30 2471 if (rdata->rx_desc == NULL) {
bdca134f 2472 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2473 return ENOMEM;
bdca134f 2474 }
5330213c 2475
323e5ecd
SZ
2476 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2477 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2478
2479 /*
2480 * Create DMA tag for rx buffers
2481 */
2482 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2483 1, 0, /* alignment, bounds */
2484 BUS_SPACE_MAXADDR, /* lowaddr */
2485 BUS_SPACE_MAXADDR, /* highaddr */
2486 NULL, NULL, /* filter, filterarg */
2487 MCLBYTES, /* maxsize */
2488 1, /* nsegments */
2489 MCLBYTES, /* maxsegsize */
2490 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2491 &rdata->rxtag);
5330213c
SZ
2492 if (error) {
2493 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2494 kfree(rdata->rx_buf, M_DEVBUF);
2495 rdata->rx_buf = NULL;
5330213c
SZ
2496 return error;
2497 }
2498
2499 /*
2500 * Create spare DMA map for rx buffers
2501 */
c39e3a1f
SZ
2502 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2503 &rdata->rx_sparemap);
5330213c
SZ
2504 if (error) {
2505 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2506 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2507 kfree(rdata->rx_buf, M_DEVBUF);
2508 rdata->rx_buf = NULL;
5330213c
SZ
2509 return error;
2510 }
2511
2512 /*
2513 * Create DMA maps for rx buffers
2514 */
c39e3a1f 2515 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2516 rx_buffer = &rdata->rx_buf[i];
5330213c 2517
c39e3a1f 2518 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2519 &rx_buffer->map);
2520 if (error) {
2521 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2522 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ
2523 return error;
2524 }
2525 }
2526 return (0);
2527}
2528
c39e3a1f
SZ
2529static void
2530emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2531{
2532 int i;
2533
2534 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2535 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2536
2537 if (rx_buffer->m_head != NULL) {
2538 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2539 m_freem(rx_buffer->m_head);
2540 rx_buffer->m_head = NULL;
2541 }
2542 }
2543
2544 if (rdata->fmp != NULL)
2545 m_freem(rdata->fmp);
2546 rdata->fmp = NULL;
2547 rdata->lmp = NULL;
2548}
2549
5330213c 2550static int
c39e3a1f 2551emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2552{
2553 int i, error;
2554
2555 /* Reset descriptor ring */
235b9d30 2556 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2557
2558 /* Allocate new ones. */
c39e3a1f
SZ
2559 for (i = 0; i < rdata->num_rx_desc; i++) {
2560 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ
2561 if (error)
2562 return (error);
2563 }
2564
2565 /* Setup our descriptor pointers */
c39e3a1f 2566 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2567
2568 return (0);
2569}
2570
2571static void
2572emx_init_rx_unit(struct emx_softc *sc)
2573{
2574 struct ifnet *ifp = &sc->arpcom.ac_if;
2575 uint64_t bus_addr;
2d0e5700 2576 uint32_t rctl, itr, rfctl;
3f939c23 2577 int i;
5330213c
SZ
2578
2579 /*
2580 * Make sure receives are disabled while setting
2581 * up the descriptor ring
2582 */
2583 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2584 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2585
2586 /*
2587 * Set the interrupt throttling rate. Value is calculated
2588 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2589 */
2d0e5700
SZ
2590 if (sc->int_throttle_ceil)
2591 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2592 else
2593 itr = 0;
2594 emx_set_itr(sc, itr);
5330213c 2595
235b9d30
SZ
2596 /* Use extended RX descriptor */
2597 rfctl = E1000_RFCTL_EXTEN;
2598
5330213c 2599 /* Disable accelerated ackknowledge */
235b9d30
SZ
2600 if (sc->hw.mac.type == e1000_82574)
2601 rfctl |= E1000_RFCTL_ACK_DIS;
2602
2603 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2604
65c7a6af
SZ
2605 /*
2606 * Receive Checksum Offload for TCP and UDP
2607 *
2608 * Checksum offloading is also enabled if multiple receive
2609 * queue is to be supported, since we need it to figure out
2610 * packet type.
2611 */
13890b61
SZ
2612 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2613 sc->rx_ring_cnt > 1) {
2d0e5700
SZ
2614 uint32_t rxcsum;
2615
5330213c 2616 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2617
2618 /*
2619 * NOTE:
2620 * PCSD must be enabled to enable multiple
2621 * receive queues.
2622 */
2623 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2624 E1000_RXCSUM_PCSD;
5330213c
SZ
2625 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2626 }
2627
2628 /*
65c7a6af 2629 * Configure multiple receive queue (RSS)
3f939c23 2630 */
13890b61 2631 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ
2632 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2633 uint32_t reta;
2634
13890b61
SZ
2635 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2636 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2637
65c7a6af
SZ
2638 /*
2639 * NOTE:
2640 * When we reach here, RSS has already been disabled
2641 * in emx_stop(), so we could safely configure RSS key
2642 * and redirect table.
2643 */
3f939c23 2644
65c7a6af
SZ
2645 /*
2646 * Configure RSS key
2647 */
89d8e73d
SZ
2648 toeplitz_get_key(key, sizeof(key));
2649 for (i = 0; i < EMX_NRSSRK; ++i) {
2650 uint32_t rssrk;
2651
2652 rssrk = EMX_RSSRK_VAL(key, i);
2653 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2654
2655 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2656 }
3f939c23 2657
65c7a6af 2658 /*
89d8e73d
SZ
2659 * Configure RSS redirect table in following fashion:
2660 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2661 */
89d8e73d
SZ
2662 reta = 0;
2663 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2664 uint32_t q;
2665
13890b61 2666 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ
2667 reta |= q << (8 * i);
2668 }
2669 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2670
65c7a6af
SZ
2671 for (i = 0; i < EMX_NRETA; ++i)
2672 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2673
65c7a6af
SZ
2674 /*
2675 * Enable multiple receive queues.
2676 * Enable IPv4 RSS standard hash functions.
2677 * Disable RSS interrupt.
2678 */
2679 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2680 E1000_MRQC_ENABLE_RSS_2Q |
2681 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2682 E1000_MRQC_RSS_FIELD_IPV4);
2683 }
3f939c23
SZ
2684
2685 /*
5330213c
SZ
2686 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2687 * long latencies are observed, like Lenovo X60. This
2688 * change eliminates the problem, but since having positive
2689 * values in RDTR is a known source of problems on other
2690 * platforms another solution is being sought.
2691 */
2692 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2693 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2694 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2695 }
2696
13890b61 2697 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ
2698 struct emx_rxdata *rdata = &sc->rx_data[i];
2699
2700 /*
2701 * Setup the Base and Length of the Rx Descriptor Ring
2702 */
2703 bus_addr = rdata->rx_desc_paddr;
2704 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2705 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2706 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2707 (uint32_t)(bus_addr >> 32));
2708 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2709 (uint32_t)bus_addr);
2710
2711 /*
2712 * Setup the HW Rx Head and Tail Descriptor Pointers
2713 */
3f939c23
SZ
2714 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2715 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2716 sc->rx_data[i].num_rx_desc - 1);
2717 }
2718
2d0e5700
SZ
2719 /* Setup the Receive Control Register */
2720 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2721 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2722 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2723 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2724
2725 /* Make sure VLAN Filters are off */
2726 rctl &= ~E1000_RCTL_VFE;
2727
2728 /* Don't store bad paket */
2729 rctl &= ~E1000_RCTL_SBP;
2730
2731 /* MCLBYTES */
2732 rctl |= E1000_RCTL_SZ_2048;
2733
2734 if (ifp->if_mtu > ETHERMTU)
2735 rctl |= E1000_RCTL_LPE;
2736 else
2737 rctl &= ~E1000_RCTL_LPE;
2738
3f939c23
SZ
2739 /* Enable Receives */
2740 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2741}
2742
2743static void
c39e3a1f 2744emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2745{
323e5ecd 2746 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2747 int i;
2748
bdca134f 2749 /* Free Receive Descriptor ring */
235b9d30 2750 if (rdata->rx_desc) {
c39e3a1f 2751 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2752 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2753 rdata->rx_desc_dmap);
2754 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2755
235b9d30 2756 rdata->rx_desc = NULL;
a596084c 2757 }
bdca134f 2758
323e5ecd 2759 if (rdata->rx_buf == NULL)
5330213c
SZ
2760 return;
2761
2762 for (i = 0; i < ndesc; i++) {
323e5ecd 2763 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2764
2765 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2766 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2767 }
c39e3a1f
SZ
2768 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2769 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2770
323e5ecd
SZ
2771 kfree(rdata->rx_buf, M_DEVBUF);
2772 rdata->rx_buf = NULL;
5330213c
SZ
2773}
2774
2775static void
c39e3a1f 2776emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2777{
c39e3a1f 2778 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2779 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2780 uint32_t staterr;
235b9d30 2781 emx_rxdesc_t *current_desc;
5330213c
SZ
2782 struct mbuf *mp;
2783 int i;
5330213c 2784
c39e3a1f 2785 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2786 current_desc = &rdata->rx_desc[i];
2787 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2788
235b9d30 2789 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2790 return;
2791
235b9d30 2792 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2793 struct pktinfo *pi = NULL, pi0;
235b9d30 2794 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2795 struct mbuf *m = NULL;
0acc29d6 2796 int eop, len;
5330213c
SZ
2797
2798 logif(pkt_receive);
2799
235b9d30 2800 mp = rx_buf->m_head;
5330213c
SZ
2801
2802 /*
2803 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2804 * needs to access the last received byte in the mbuf.
2805 */
235b9d30 2806 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2807 BUS_DMASYNC_POSTREAD);
2808
0acc29d6 2809 len = le16toh(current_desc->rxd_length);
235b9d30 2810 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2811 count--;
2812 eop = 1;
5330213c
SZ
2813 } else {
2814 eop = 0;
5330213c
SZ
2815 }
2816
235b9d30
SZ
2817 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2818 uint16_t vlan = 0;
3f939c23 2819 uint32_t mrq, rss_hash;
235b9d30
SZ
2820
2821 /*
2822 * Save several necessary information,
2823 * before emx_newbuf() destroy it.
2824 */
2825 if ((staterr & E1000_RXD_STAT_VP) && eop)
2826 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2827
3f939c23
SZ
2828 mrq = le32toh(current_desc->rxd_mrq);
2829 rss_hash = le32toh(current_desc->rxd_rss);
2830
2831 EMX_RSS_DPRINTF(sc, 10,
2832 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2833 ring_idx, mrq, rss_hash);
2834
c39e3a1f 2835 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ
2836 ifp->if_iqdrops++;
2837 goto discard;
2838 }
2839
2840 /* Assign correct length to the current fragment */
2841 mp->m_len = len;
2842
c39e3a1f 2843 if (rdata->fmp == NULL) {
5330213c 2844 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2845 rdata->fmp = mp; /* Store the first mbuf */
2846 rdata->lmp = mp;
5330213c
SZ
2847 } else {
2848 /*
2849 * Chain mbuf's together
2850 */
c39e3a1f
SZ
2851 rdata->lmp->m_next = mp;
2852 rdata->lmp = rdata->lmp->m_next;
2853 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2854 }
2855
2856 if (eop) {
c39e3a1f 2857 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2858 ifp->if_ipackets++;
2859
235b9d30
SZ
2860 if (ifp->if_capenable & IFCAP_RXCSUM)
2861 emx_rxcsum(staterr, rdata->fmp);
5330213c 2862
235b9d30 2863 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2864 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2865 vlan;
c39e3a1f 2866 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2867 }
c39e3a1f
SZ
2868 m = rdata->fmp;
2869 rdata->fmp = NULL;
2870 rdata->lmp = NULL;
3f939c23 2871
9cc86e17
SZ
2872 if (ifp->if_capenable & IFCAP_RSS) {
2873 pi = emx_rssinfo(m, &pi0, mrq,
2874 rss_hash, staterr);
2875 }
3f939c23
SZ
2876#ifdef EMX_RSS_DEBUG
2877 rdata->rx_pkts++;
2878#endif
5330213c
SZ
2879 }
2880 } else {
2881 ifp->if_ierrors++;
2882discard:
235b9d30 2883 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2884 if (rdata->fmp != NULL) {
2885 m_freem(rdata->fmp);
2886 rdata->fmp = NULL;
2887 rdata->lmp = NULL;
5330213c
SZ
2888 }
2889 m = NULL;
2890 }
2891
5330213c 2892 if (m != NULL)
eda7db08 2893 ether_input_pkt(ifp, m, pi);
5330213c
SZ
2894
2895 /* Advance our pointers to the next descriptor. */
c39e3a1f 2896 if (++i == rdata->num_rx_desc)
5330213c 2897 i = 0;
235b9d30
SZ
2898
2899 current_desc = &rdata->rx_desc[i];
2900 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2901 }
c39e3a1f 2902 rdata->next_rx_desc_to_check = i;
5330213c 2903
3f939c23 2904 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2905 if (--i < 0)
c39e3a1f 2906 i = rdata->num_rx_desc - 1;
3f939c23 2907 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ
2908}
2909
2910static void
5330213c
SZ
2911emx_enable_intr(struct emx_softc *sc)
2912{
2d0e5700
SZ
2913 uint32_t ims_mask = IMS_ENABLE_MASK;
2914
6d435846 2915 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ
2916
2917#if 0
2918 if (sc->hw.mac.type == e1000_82574) {
2919 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2920 ims_mask |= EM_MSIX_MASK;
2921 }
2922#endif
2923 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ
2924}
2925
2926static void
2927emx_disable_intr(struct emx_softc *sc)
2928{
2d0e5700
SZ
2929 if (sc->hw.mac.type == e1000_82574)
2930 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 2931 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 2932
6d435846 2933 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
2934}
2935
2936/*
2937 * Bit of a misnomer, what this really means is
2938 * to enable OS management of the system... aka
2939 * to disable special hardware management features
2940 */
2941static void
2942emx_get_mgmt(struct emx_softc *sc)
2943{
2944 /* A shared code workaround */
2945 if (sc->has_manage) {
2946 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2947 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2948
2949 /* disable hardware interception of ARP */
2950 manc &= ~(E1000_MANC_ARP_EN);
2951
2952 /* enable receiving management packets to the host */
2953 manc |= E1000_MANC_EN_MNG2HOST;
2954#define E1000_MNG2HOST_PORT_623 (1 << 5)
2955#define E1000_MNG2HOST_PORT_664 (1 << 6)
2956 manc2h |= E1000_MNG2HOST_PORT_623;
2957 manc2h |= E1000_MNG2HOST_PORT_664;
2958 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2959
2960 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2961 }
2962}
2963
2964/*
2965 * Give control back to hardware management
2966 * controller if there is one.
2967 */
2968static void
2969emx_rel_mgmt(struct emx_softc *sc)
2970{
2971 if (sc->has_manage) {
2972 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2973
2974 /* re-enable hardware interception of ARP */
2975 manc |= E1000_MANC_ARP_EN;
2976 manc &= ~E1000_MANC_EN_MNG2HOST;
2977
2978 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2979 }
2980}
2981
2982/*
2983 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
2984 * For ASF and Pass Through versions of f/w this means that
2985 * the driver is loaded. For AMT version (only with 82573)
2986 * of the f/w this means that the network i/f is open.
2987 */
2988static void
2989emx_get_hw_control(struct emx_softc *sc)
2990{
5330213c 2991 /* Let firmware know the driver has taken over */
2d0e5700
SZ
2992 if (sc->hw.mac.type == e1000_82573) {
2993 uint32_t swsm;
2994
5330213c
SZ
2995 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
2996 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
2997 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
2998 } else {
2999 uint32_t ctrl_ext;
5330213c 3000
5330213c
SZ
3001 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3002 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3003 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3004 }
2d0e5700 3005 sc->control_hw = 1;
5330213c
SZ
3006}
3007
3008/*
3009 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3010 * For ASF and Pass Through versions of f/w this means that the
3011 * driver is no longer loaded. For AMT version (only with 82573)
3012 * of the f/w this means that the network i/f is closed.
3013 */
3014static void
3015emx_rel_hw_control(struct emx_softc *sc)
3016{
2d0e5700
SZ
3017 if (!sc->control_hw)
3018 return;
3019 sc->control_hw = 0;
5330213c
SZ
3020
3021 /* Let firmware taken over control of h/w */
2d0e5700
SZ
3022 if (sc->hw.mac.type == e1000_82573) {
3023 uint32_t swsm;
3024
5330213c
SZ
3025 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3026 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3027 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3028 } else {
3029 uint32_t ctrl_ext;
5330213c 3030
5330213c
SZ
3031 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3032 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3033 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ
3034 }
3035}
3036
3037static int
3038emx_is_valid_eaddr(const uint8_t *addr)
3039{
3040 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3041
3042 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3043 return (FALSE);
3044
3045 return (TRUE);
3046}
3047
3048/*
3049 * Enable PCI Wake On Lan capability
3050 */
3051void
3052emx_enable_wol(device_t dev)
3053{
3054 uint16_t cap, status;
3055 uint8_t id;
3056
3057 /* First find the capabilities pointer*/
3058 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3059
3060 /* Read the PM Capabilities */
3061 id = pci_read_config(dev, cap, 1);
3062 if (id != PCIY_PMG) /* Something wrong */
3063 return;
3064
3065 /*
3066 * OK, we have the power capabilities,
3067 * so now get the status register
3068 */
3069 cap += PCIR_POWER_STATUS;
3070 status = pci_read_config(dev, cap, 2);
3071 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3072 pci_write_config(dev, cap, status, 2);
3073}
3074
3075static void
3076emx_update_stats(struct emx_softc *sc)
3077{
3078 struct ifnet *ifp = &sc->arpcom.ac_if;
3079
3080 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3081 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3082 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3083 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3084 }
3085 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3086 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3087 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3088 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3089
3090 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3091 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3092 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3093 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3094 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3095 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3096 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3097 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3098 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3099 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3100 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3101 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3102 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3103 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3104 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3105 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3106 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3107 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3108 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3109 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3110
3111 /* For the 64-bit byte counters the low dword must be read first. */
3112 /* Both registers clear on the read of the high dword */
3113
3114 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3115 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3116
3117 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3118 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3119 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3120 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3121 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3122
3123 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3124 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3125
3126 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3127 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3128 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3129 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3130 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3131 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3132 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3133 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3134 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3135 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3136
3137 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3138 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3139 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3140 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3141 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3142 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3143
3144 ifp->if_collisions = sc->stats.colc;
3145
3146 /* Rx Errors */
3147 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3148 sc->stats.crcerrs + sc->stats.algnerrc +
3149 sc->stats.ruc + sc->stats.roc +
3150 sc->stats.mpc + sc->stats.cexterr;
3151
3152 /* Tx Errors */
3153 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3154 sc->watchdog_events;
3155}
3156
3157static void
3158emx_print_debug_info(struct emx_softc *sc)
3159{
3160 device_t dev = sc->dev;
3161 uint8_t *hw_addr = sc->hw.hw_addr;
3162
3163 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3164 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3165 E1000_READ_REG(&sc->hw, E1000_CTRL),
3166 E1000_READ_REG(&sc->hw, E1000_RCTL));
3167 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3168 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3169 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3170 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3171 sc->hw.fc.high_water, sc->hw.fc.low_water);
3172 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3173 E1000_READ_REG(&sc->hw, E1000_TIDV),
3174 E1000_READ_REG(&sc->hw, E1000_TADV));
3175 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3176 E1000_READ_REG(&sc->hw, E1000_RDTR),
3177 E1000_READ_REG(&sc->hw, E1000_RADV));
3178 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3179 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3180 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3181 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3182 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3183 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3184 device_printf(dev, "Num Tx descriptors avail = %d\n",
3185 sc->num_tx_desc_avail);
3186 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3187 sc->no_tx_desc_avail1);
3188 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3189 sc->no_tx_desc_avail2);
3190 device_printf(dev, "Std mbuf failed = %ld\n",
3191 sc->mbuf_alloc_failed);
3192 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3193 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ
3194 device_printf(dev, "Driver dropped packets = %ld\n",
3195 sc->dropped_pkts);
3196 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3197 sc->no_tx_dma_setup);
5330213c
SZ
3198}
3199
3200static void
3201emx_print_hw_stats(struct emx_softc *sc)
3202{
3203 device_t dev = sc->dev;
3204
3205 device_printf(dev, "Excessive collisions = %lld\n",
3206 (long long)sc->stats.ecol);
3207#if (DEBUG_HW > 0) /* Dont output these errors normally */
3208 device_printf(dev, "Symbol errors = %lld\n",
3209 (long long)sc->stats.symerrs);
3210#endif
3211 device_printf(dev, "Sequence errors = %lld\n",
3212 (long long)sc->stats.sec);
3213 device_printf(dev, "Defer count = %lld\n",
3214 (long long)sc->stats.dc);
3215 device_printf(dev, "Missed Packets = %lld\n",
3216 (long long)sc->stats.mpc);
3217 device_printf(dev, "Receive No Buffers = %lld\n",
3218 (long long)sc->stats.rnbc);
3219 /* RLEC is inaccurate on some hardware, calculate our own. */
3220 device_printf(dev, "Receive Length Errors = %lld\n",
3221 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3222 device_printf(dev, "Receive errors = %lld\n",
3223 (long long)sc->stats.rxerrc);
3224 device_printf(dev, "Crc errors = %lld\n",
3225 (long long)sc->stats.crcerrs);
3226 device_printf(dev, "Alignment errors = %lld\n",
3227 (long long)sc->stats.algnerrc);
3228 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3229 (long long)sc->stats.cexterr);
3230 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3231 device_printf(dev, "watchdog timeouts = %ld\n",
3232 sc->watchdog_events);
3233 device_printf(dev, "XON Rcvd = %lld\n",
3234 (long long)sc->stats.xonrxc);
3235 device_printf(dev, "XON Xmtd = %lld\n",
3236 (long long)sc->stats.xontxc);
3237 device_printf(dev, "XOFF Rcvd = %lld\n",
3238 (long long)sc->stats.xoffrxc);
3239 device_printf(dev, "XOFF Xmtd = %lld\n",
3240 (long long)sc->stats.xofftxc);
3241 device_printf(dev, "Good Packets Rcvd = %lld\n",
3242 (long long)sc->stats.gprc);
3243 device_printf(dev, "Good Packets Xmtd = %lld\n",
3244 (long long)sc->stats.gptc);
3245}
3246
3247static void
3248emx_print_nvm_info(struct emx_softc *sc)
3249{
3250 uint16_t eeprom_data;
3251 int i, j, row = 0;
3252
3253 /* Its a bit crude, but it gets the job done */
3254 kprintf("\nInterface EEPROM Dump:\n");
3255 kprintf("Offset\n0x0000 ");
3256 for (i = 0, j = 0; i < 32; i++, j++) {
3257 if (j == 8) { /* Make the offset block */
3258 j = 0; ++row;
3259 kprintf("\n0x00%x0 ",row);
3260 }
3261 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3262 kprintf("%04x ", eeprom_data);
3263 }
3264 kprintf("\n");
3265}
3266
3267static int
3268emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3269{
3270 struct emx_softc *sc;
3271 struct ifnet *ifp;
3272 int error, result;
3273
3274 result = -1;
3275 error = sysctl_handle_int(oidp, &result, 0, req);
3276 if (error || !req->newptr)
3277 return (error);
3278
3279 sc = (struct emx_softc *)arg1;
3280 ifp = &sc->arpcom.ac_if;
3281
6d435846 3282 ifnet_serialize_all(ifp);
5330213c
SZ
3283
3284 if (result == 1)
3285 emx_print_debug_info(sc);
3286
3287 /*
3288 * This value will cause a hex dump of the
3289 * first 32 16-bit words of the EEPROM to
3290 * the screen.
3291 */
3292 if (result == 2)
3293 emx_print_nvm_info(sc);
3294
6d435846 3295 ifnet_deserialize_all(ifp);
5330213c
SZ
3296
3297 return (error);
3298}
3299
3300static int
3301emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3302{
3303 int error, result;
3304
3305 result = -1;
3306 error = sysctl_handle_int(oidp, &result, 0, req);
3307 if (error || !req->newptr)
3308 return (error);
3309
3310 if (result == 1) {
3311 struct emx_softc *sc = (struct emx_softc *)arg1;
3312 struct ifnet *ifp = &sc->arpcom.ac_if;
3313
6d435846 3314 ifnet_serialize_all(ifp);
5330213c 3315 emx_print_hw_stats(sc);
6d435846 3316 ifnet_deserialize_all(ifp);
5330213c
SZ
3317 }
3318 return (error);
3319}
3320
3321static void
3322emx_add_sysctl(struct emx_softc *sc)
3323{
3f939c23
SZ
3324#ifdef EMX_RSS_DEBUG
3325 char rx_pkt[32];
3326 int i;
3327#endif
5330213c
SZ
3328
3329 sysctl_ctx_init(&sc->sysctl_ctx);
3330 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3331 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3332 device_get_nameunit(sc->dev),
3333 CTLFLAG_RD, 0, "");
3334 if (sc->sysctl_tree == NULL) {
3335 device_printf(sc->dev, "can't add sysctl node\n");
3336 return;
3337 }
3338
3339 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3340 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3341 emx_sysctl_debug_info, "I", "Debug Information");
3342
3343 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3344 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3345 emx_sysctl_stats, "I", "Statistics");
3346
3347 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3348 OID_AUTO, "rxd", CTLFLAG_RD,
3349 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3350 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3351 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3352
5330213c
SZ
3353 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3354 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3355 sc, 0, emx_sysctl_int_throttle, "I",
3356 "interrupt throttling rate");
3357 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3358 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3359 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3360 "# segments per TX interrupt");
3f939c23 3361
8434a83b 3362 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ
3363 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3364 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3365
3f939c23
SZ
3366#ifdef EMX_RSS_DEBUG
3367 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3368 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3369 0, "RSS debug level");
65c7a6af 3370 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3371 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3372 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3373 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3374 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3375 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3376 }
3377#endif
5330213c
SZ
3378}
3379
3380static int
3381emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3382{
3383 struct emx_softc *sc = (void *)arg1;
3384 struct ifnet *ifp = &sc->arpcom.ac_if;
3385 int error, throttle;
3386
3387 throttle = sc->int_throttle_ceil;
3388 error = sysctl_handle_int(oidp, &throttle, 0, req);
3389 if (error || req->newptr == NULL)
3390 return error;
3391 if (throttle < 0 || throttle > 1000000000 / 256)
3392 return EINVAL;
3393
3394 if (throttle) {
3395 /*
3396 * Set the interrupt throttling rate in 256ns increments,
3397 * recalculate sysctl value assignment to get exact frequency.
3398 */
3399 throttle = 1000000000 / 256 / throttle;
3400
3401 /* Upper 16bits of ITR is reserved and should be zero */
3402 if (throttle & 0xffff0000)
3403 return EINVAL;
3404 }
3405
6d435846 3406 ifnet_serialize_all(ifp);
5330213c
SZ
3407
3408 if (throttle)
3409 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3410 else
3411 sc->int_throttle_ceil = 0;
3412
3413 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3414 emx_set_itr(sc, throttle);
5330213c 3415
6d435846 3416 ifnet_deserialize_all(ifp);
5330213c
SZ
3417
3418 if (bootverbose) {
3419 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3420 sc->int_throttle_ceil);
3421 }
3422 return 0;
3423}
3424
3425static int
3426emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3427{
3428 struct emx_softc *sc = (void *)arg1;
3429 struct ifnet *ifp = &sc->arpcom.ac_if;
3430 int error, segs;
3431
3432 segs = sc->tx_int_nsegs;
3433 error = sysctl_handle_int(oidp, &segs, 0, req);
3434 if (error || req->newptr == NULL)
3435 return error;
3436 if (segs <= 0)
3437 return EINVAL;
3438
6d435846 3439 ifnet_serialize_all(ifp);
5330213c
SZ
3440
3441 /*
3442 * Don't allow int_tx_nsegs to become:
3443 * o Less the oact_tx_desc
3444 * o Too large that no TX desc will cause TX interrupt to
3445 * be generated (OACTIVE will never recover)
3446 * o Too small that will cause tx_dd[] overflow
3447 */
3448 if (segs < sc->oact_tx_desc ||
3449 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3450 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3451 error = EINVAL;
3452 } else {
3453 error = 0;
3454 sc->tx_int_nsegs = segs;
3455 }
3456
6d435846 3457 ifnet_deserialize_all(ifp);
5330213c
SZ
3458
3459 return error;
3460}
071699f8
SZ
3461
3462static int
3463emx_dma_alloc(struct emx_softc *sc)
3464{
3f939c23 3465 int error, i;
071699f8
SZ
3466
3467 /*
3468 * Create top level busdma tag
3469 */
3470 error = bus_dma_tag_create(NULL, 1, 0,
3471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3472 NULL, NULL,
3473 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3474 0, &sc->parent_dtag);
3475 if (error) {
3476 device_printf(sc->dev, "could not create top level DMA tag\n");
3477 return error;
3478 }
3479
3480 /*
3481 * Allocate transmit descriptors ring and buffers
3482 */
3483 error = emx_create_tx_ring(sc);
3484 if (error) {
3485 device_printf(sc->dev, "Could not setup transmit structures\n");
3486 return error;
3487 }
3488
3489 /*
3490 * Allocate receive descriptors ring and buffers
3491 */
65c7a6af 3492 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3493 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3494 if (error) {
3495 device_printf(sc->dev,
3496 "Could not setup receive structures\n");
3497 return error;
3498 }
071699f8
SZ
3499 }
3500 return 0;
3501}
3502
3503static void
3504emx_dma_free(struct emx_softc *sc)
3505{
3f939c23
SZ
3506 int i;
3507
071699f8 3508 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3509
65c7a6af 3510 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3511 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3512 sc->rx_data[i].num_rx_desc);
3513 }
071699f8
SZ
3514
3515 /* Free top level busdma tag */
3516 if (sc->parent_dtag != NULL)
3517 bus_dma_tag_destroy(sc->parent_dtag);
3518}
6d435846
SZ
3519
3520static void
3521emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3522{
3523 struct emx_softc *sc = ifp->if_softc;
6d435846 3524
8f594b38
SZ
3525 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3526 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3527}
3528
3529static void
3530emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3531{
3532 struct emx_softc *sc = ifp->if_softc;
6d435846 3533
8f594b38
SZ
3534 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3535 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3536}
3537
3538static int
3539emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3540{
3541 struct emx_softc *sc = ifp->if_softc;
6d435846 3542
8f594b38
SZ
3543 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3544 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846 3545}
bca7c435
SZ
3546
3547static void
3548emx_serialize_skipmain(struct emx_softc *sc)
3549{
3550 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3551}
3552
3553static void
3554emx_deserialize_skipmain(struct emx_softc *sc)
3555{
3556 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3557}
2c9effcf
SZ
3558
3559#ifdef INVARIANTS
3560
3561static void
3562emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
8f594b38 3563 boolean_t serialized)
2c9effcf
SZ
3564{
3565 struct emx_softc *sc = ifp->if_softc;
2c9effcf 3566
8f594b38
SZ
3567 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3568 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
2c9effcf
SZ
3569}
3570
3571#endif /* INVARIANTS */
b3a7093f
SZ
3572
3573#ifdef IFPOLL_ENABLE
3574
3575static void
3576emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3577{
3578 struct emx_softc *sc = ifp->if_softc;
3579 uint32_t reg_icr;
3580
3581 ASSERT_SERIALIZED(&sc->main_serialize);
3582
3583 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3584 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3cbe4103
SZ
3585 emx_serialize_skipmain(sc);
3586
3587 callout_stop(&sc->timer);
3588 sc->hw.mac.get_link_status = 1;
3589 emx_update_link_status(sc);
3590 callout_reset(&sc->timer, hz, emx_timer, sc);
3591
3592 emx_deserialize_skipmain(sc);
b3a7093f
SZ
3593 }
3594}
3595
3596static void
3597emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3598{
3599 struct emx_softc *sc = ifp->if_softc;
3600
3601 ASSERT_SERIALIZED(&sc->tx_serialize);
3602
3603 emx_txeof(sc);
3604 if (!ifq_is_empty(&ifp->if_snd))
3605 if_devstart(ifp);
3606}
3607
3608static void
3609emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3610{
3611 struct emx_softc *sc = ifp->if_softc;
3612 struct emx_rxdata *rdata = arg;
3613
3614 ASSERT_SERIALIZED(&rdata->rx_serialize);
3615
3616 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3617}
3618
3619static void
3620emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3621{
3622 struct emx_softc *sc = ifp->if_softc;
3623
3624 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3625
3626 if (info) {
3627 int i;
3628
3629 info->ifpi_status.status_func = emx_qpoll_status;
3630 info->ifpi_status.serializer = &sc->main_serialize;
3631
3632 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3633 info->ifpi_tx[0].arg = NULL;
3634 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3635
3636 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3637 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3638 info->ifpi_rx[i].arg = &sc->rx_data[i];
3639 info->ifpi_rx[i].serializer =
3640 &sc->rx_data[i].rx_serialize;
3641 }
3642
3643 if (ifp->if_flags & IFF_RUNNING)
3644 emx_disable_intr(sc);
3645 } else if (ifp->if_flags & IFF_RUNNING) {
3646 emx_enable_intr(sc);
3647 }
3648}
3649
3650#endif /* IFPOLL_ENABLE */
2d0e5700
SZ
3651
3652static void
3653emx_set_itr(struct emx_softc *sc, uint32_t itr)
3654{
3655 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3656 if (sc->hw.mac.type == e1000_82574) {
3657 int i;
3658
3659 /*
3660 * When using MSIX interrupts we need to
3661 * throttle using the EITR register
3662 */
3663 for (i = 0; i < 4; ++i)
3664 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3665 }
3666}
6d5e2922
SZ
3667
3668/*
3669 * Disable the L0s, 82574L Errata #20
3670 */
3671static void
3672emx_disable_aspm(struct emx_softc *sc)
3673{
04eb0cef 3674 uint16_t link_cap, link_ctrl, disable;
6d5e2922
SZ
3675 uint8_t pcie_ptr, reg;
3676 device_t dev = sc->dev;
3677
3678 switch (sc->hw.mac.type) {
04eb0cef
SZ
3679 case e1000_82571:
3680 case e1000_82572:
6d5e2922 3681 case e1000_82573:
04eb0cef
SZ
3682 /*
3683 * 82573 specification update
a835687d
SZ
3684 * errata #8 disable L0s
3685 * errata #41 disable L1
04eb0cef
SZ
3686 *
3687 * 82571/82572 specification update
a835687d
SZ
3688 # errata #13 disable L1
3689 * errata #68 disable L0s
04eb0cef
SZ
3690 */
3691 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3692 break;
3693
6d5e2922 3694 case e1000_82574:
04eb0cef 3695 /*
a835687d 3696 * 82574 specification update errata #20
04eb0cef
SZ
3697 *
3698 * There is no need to disable L1
3699 */
3700 disable = PCIEM_LNKCTL_ASPM_L0S;
6d5e2922
SZ
3701 break;
3702
3703 default:
3704 return;
3705 }
3706
3707 pcie_ptr = pci_get_pciecap_ptr(dev);
3708 if (pcie_ptr == 0)
3709 return;
3710
3711 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3712 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3713 return;
3714
3715 if (bootverbose)
04eb0cef 3716 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
6d5e2922
SZ
3717
3718 reg = pcie_ptr + PCIER_LINKCTRL;
3719 link_ctrl = pci_read_config(dev, reg, 2);
04eb0cef 3720 link_ctrl &= ~disable;
6d5e2922
SZ
3721 pci_write_config(dev, reg, link_ctrl, 2);
3722}