emx: Utilize mbuf's header lengthes
[dragonfly.git] / sys / dev / netif / emx / if_emx.h
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1/*
2 * Copyright (c) 2001-2008, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _IF_EMX_H_
33#define _IF_EMX_H_
34
35/* Tunables */
36
37/*
38 * EMX_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256-4096 for others
40 * Default Value: 512
41 * This value is the number of transmit descriptors allocated by the driver.
42 * Increasing this value allows the driver to queue more transmits. Each
43 * descriptor is 16 bytes.
44 * Since TDLEN should be multiple of 128bytes, the number of transmit
45 * desscriptors should meet the following condition.
46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
47 */
48#define EMX_MIN_TXD 256
49#define EMX_MAX_TXD 4096
50#define EMX_DEFAULT_TXD 512
51
52/*
53 * EMX_RXD - Maximum number of receive Descriptors
54 * Valid Range: 256-4096 for others
55 * Default Value: 512
56 * This value is the number of receive descriptors allocated by the driver.
57 * Increasing this value allows the driver to buffer more incoming packets.
58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
59 * descriptor. The maximum MTU size is 16110.
60 * Since TDLEN should be multiple of 128bytes, the number of transmit
61 * desscriptors should meet the following condition.
62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
63 */
64#define EMX_MIN_RXD 256
65#define EMX_MAX_RXD 4096
66#define EMX_DEFAULT_RXD 512
67
68/*
69 * Receive Interrupt Delay Timer (Packet Timer)
70 *
71 * NOTE:
72 * RDTR and RADV are deprecated; use ITR instead. They are only used to
73 * workaround hardware bug on certain 82573 based NICs.
74 */
75#define EMX_RDTR_82573 32
76
77/*
78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
79 *
80 * NOTE:
81 * RDTR and RADV are deprecated; use ITR instead. They are only used to
82 * workaround hardware bug on certain 82573 based NICs.
83 */
84#define EMX_RADV_82573 64
85
86/*
87 * This parameter controls the duration of transmit watchdog timer.
88 */
89#define EMX_TX_TIMEOUT 5
90
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91/* One for TX csum offloading desc, the other 2 are reserved */
92#define EMX_TX_RESERVED 3
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93
94/* Large enough for 16K jumbo frame */
95#define EMX_TX_SPARE 8
96
97#define EMX_TX_OACTIVE_MAX 64
98
99/* Interrupt throttle rate */
100#define EMX_DEFAULT_ITR 10000
101
102/*
103 * This parameter controls whether or not autonegotation is enabled.
104 * 0 - Disable autonegotiation
105 * 1 - Enable autonegotiation
106 */
107#define EMX_DO_AUTO_NEG 1
108
109/* Tunables -- End */
110
111#define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
112 ADVERTISE_10_FULL | \
113 ADVERTISE_100_HALF | \
114 ADVERTISE_100_FULL | \
115 ADVERTISE_1000_FULL)
116
117#define EMX_AUTO_ALL_MODES 0
118
119/* PHY master/slave setting */
120#define EMX_MASTER_SLAVE e1000_ms_hw_default
121
122/*
123 * Micellaneous constants
124 */
125#define EMX_VENDOR_ID 0x8086
126
127#define EMX_BAR_MEM PCIR_BAR(0)
128
129#define EMX_JUMBO_PBA 0x00000028
130#define EMX_DEFAULT_PBA 0x00000030
131#define EMX_SMARTSPEED_DOWNSHIFT 3
132#define EMX_SMARTSPEED_MAX 15
133#define EMX_MAX_INTR 10
134
135#define EMX_MCAST_ADDR_MAX 128
136#define EMX_FC_PAUSE_TIME 1000
137#define EMX_EEPROM_APME 0x400;
138
139/*
140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
142 * also optimize cache line size effect. H/W supports up to cache line size 128.
143 */
144#define EMX_DBA_ALIGN 128
145
146/*
147 * Speed mode bit in TARC0/TARC1.
148 * 82571EB/82572EI only, used to improve small packet transmit performance.
149 */
150#define EMX_TARC_SPEED_MODE (1 << 21)
151
152#define EMX_MAX_SCATTER 64
153#define EMX_TSO_SIZE (65535 + \
154 sizeof(struct ether_vlan_header))
155#define EMX_MAX_SEGSIZE 4096
156#define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
157
158#define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159#define EMX_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
160#define EMX_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
161 EMX_IPVHL_SIZE)
162
163/*
164 * 82574 has a nonstandard address for EIAC
165 * and since its only used in MSIX, and in
166 * the em driver only 82574 uses MSIX we can
167 * solve it just using this define.
168 */
169#define EMX_EIAC 0x000DC
170
3f939c23 171#define EMX_NRSSRK 10
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172#define EMX_RSSRK_SIZE 4
173#define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \
174 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
175 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
176 key[(i) * EMX_RSSRK_SIZE + 3] << 24)
177
3f939c23 178#define EMX_NRETA 32
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179#define EMX_RETA_SIZE 4
180#define EMX_RETA_RINGIDX_SHIFT 7
3f939c23 181
c39e3a1f 182#define EMX_NRX_RING 2
6d435846 183#define EMX_NSERIALIZE 4
c39e3a1f 184
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185typedef union e1000_rx_desc_extended emx_rxdesc_t;
186
187#define rxd_bufaddr read.buffer_addr /* 64bits */
188#define rxd_length wb.upper.length /* 16bits */
189#define rxd_vlan wb.upper.vlan /* 16bits */
190#define rxd_staterr wb.upper.status_error /* 32bits */
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191#define rxd_mrq wb.lower.mrq /* 32bits */
192#define rxd_rss wb.lower.hi_dword.rss /* 32bits */
235b9d30 193
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194#define EMX_RXDMRQ_RSSTYPE_MASK 0xf
195#define EMX_RXDMRQ_NO_HASH 0
196#define EMX_RXDMRQ_IPV4_TCP 1
197#define EMX_RXDMRQ_IPV4 2
198#define EMX_RXDMRQ_IPV6_TCP 3
199#define EMX_RXDMRQ_IPV6 5
200
c39e3a1f 201struct emx_rxdata {
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202 struct lwkt_serialize rx_serialize;
203
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204 /*
205 * Receive definitions
206 *
207 * we have an array of num_rx_desc rx_desc (handled by the
208 * controller), and paired with an array of rx_buffers
209 * (at rx_buffer_area).
210 * The next pair to check on receive is at offset next_rx_desc_to_check
211 */
235b9d30 212 emx_rxdesc_t *rx_desc;
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213 uint32_t next_rx_desc_to_check;
214 int num_rx_desc;
323e5ecd 215 struct emx_rxbuf *rx_buf;
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216 bus_dma_tag_t rxtag;
217 bus_dmamap_t rx_sparemap;
218
219 /*
220 * First/last mbuf pointers, for
221 * collecting multisegment RX packets.
222 */
223 struct mbuf *fmp;
224 struct mbuf *lmp;
225
226 /* RX statistics */
3f939c23 227 unsigned long rx_pkts;
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228 unsigned long mbuf_cluster_failed;
229
230 bus_dma_tag_t rx_desc_dtag;
231 bus_dmamap_t rx_desc_dmap;
232 bus_addr_t rx_desc_paddr;
d721525c 233} __cachealign;
c39e3a1f 234
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235struct emx_softc {
236 struct arpcom arpcom;
237 struct e1000_hw hw;
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238 int flags;
239#define EMX_FLAG_SHARED_INTR 0x1
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240
241 /* DragonFly operating-system-specific structures. */
242 struct e1000_osdep osdep;
243 device_t dev;
244
245 bus_dma_tag_t parent_dtag;
a596084c 246
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247 bus_dma_tag_t tx_desc_dtag;
248 bus_dmamap_t tx_desc_dmap;
249 bus_addr_t tx_desc_paddr;
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250
251 struct resource *memory;
252 int memory_rid;
253
254 struct resource *intr_res;
255 void *intr_tag;
256 int intr_rid;
704b6287 257 int intr_type;
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258
259 struct ifmedia media;
260 struct callout timer;
261 int if_flags;
262 int max_frame_size;
263 int min_frame_size;
264
265 /* Management and WOL features */
266 int wol;
267 int has_manage;
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268 int has_amt;
269 int control_hw;
270
271 /* Multicast array memory */
272 uint8_t *mta;
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273
274 /* Info about the board itself */
275 uint8_t link_active;
276 uint16_t link_speed;
277 uint16_t link_duplex;
278 uint32_t smartspeed;
279 int int_throttle_ceil;
280
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281 struct lwkt_serialize main_serialize;
282 struct lwkt_serialize tx_serialize;
283 struct lwkt_serialize *serializes[EMX_NSERIALIZE];
284
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285 /*
286 * Transmit definitions
287 *
288 * We have an array of num_tx_desc descriptors (handled
289 * by the controller) paired with an array of tx_buffers
290 * (at tx_buffer_area).
291 * The index of the next available descriptor is next_avail_tx_desc.
292 * The number of remaining tx_desc is num_tx_desc_avail.
293 */
294 struct e1000_tx_desc *tx_desc_base;
323e5ecd 295 struct emx_txbuf *tx_buf;
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296 uint32_t next_avail_tx_desc;
297 uint32_t next_tx_to_clean;
298 int num_tx_desc_avail;
299 int num_tx_desc;
300 bus_dma_tag_t txtag; /* dma tag for tx */
301 int spare_tx_desc;
302 int oact_tx_desc;
303
304 /* Saved csum offloading context information */
305 int csum_flags;
306 int csum_ehlen;
307 int csum_iphlen;
308 uint32_t csum_txd_upper;
309 uint32_t csum_txd_lower;
310
311 /*
312 * Variables used to reduce TX interrupt rate and
313 * number of device's TX ring write requests.
314 *
315 * tx_nsegs:
316 * Number of TX descriptors setup so far.
317 *
318 * tx_int_nsegs:
319 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
320 * in the last TX descriptor of the packet, and
321 * tx_nsegs will be reset to 0. So TX interrupt and
322 * TX ring write request should be generated roughly
323 * every tx_int_nsegs TX descriptors.
324 *
325 * tx_dd[]:
326 * Index of the TX descriptors which have RS bit set,
327 * i.e. DD bit will be set on this TX descriptor after
328 * the data of the TX descriptor are transfered to
329 * hardware's internal packet buffer. Only the TX
330 * descriptors listed in tx_dd[] will be checked upon
331 * TX interrupt. This array is used as circular ring.
332 *
333 * tx_dd_tail, tx_dd_head:
334 * Tail and head index of valid elements in tx_dd[].
335 * tx_dd_tail == tx_dd_head means there is no valid
336 * elements in tx_dd[]. tx_dd_tail points to the position
337 * which is one beyond the last valid element in tx_dd[].
338 * tx_dd_head points to the first valid element in
339 * tx_dd[].
340 */
341 int tx_int_nsegs;
342 int tx_nsegs;
343 int tx_dd_tail;
344 int tx_dd_head;
345#define EMX_TXDD_MAX 64
346#define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
347 int tx_dd[EMX_TXDD_MAX];
348
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349 int rss_debug;
350 int rx_ring_cnt;
c39e3a1f 351 struct emx_rxdata rx_data[EMX_NRX_RING];
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352
353 /* Misc stats maintained by the driver */
354 unsigned long dropped_pkts;
355 unsigned long mbuf_alloc_failed;
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356 unsigned long no_tx_desc_avail1;
357 unsigned long no_tx_desc_avail2;
358 unsigned long no_tx_map_avail;
359 unsigned long no_tx_dma_setup;
360 unsigned long watchdog_events;
361 unsigned long rx_overruns;
362 unsigned long rx_irq;
363 unsigned long tx_irq;
364 unsigned long link_irq;
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365
366 /* sysctl tree glue */
367 struct sysctl_ctx_list sysctl_ctx;
368 struct sysctl_oid *sysctl_tree;
369
370 struct e1000_hw_stats stats;
371};
372
323e5ecd 373struct emx_txbuf {
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374 struct mbuf *m_head;
375 bus_dmamap_t map;
376};
377
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378struct emx_rxbuf {
379 struct mbuf *m_head;
380 bus_dmamap_t map;
381 bus_addr_t paddr;
382};
383
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384#define EMX_IS_OACTIVE(sc) ((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc)
385
386#define EMX_INC_TXDD_IDX(idx) \
387do { \
388 if (++(idx) == EMX_TXDD_MAX) \
389 (idx) = 0; \
390} while (0)
391
392#endif /* !_IF_EMX_H_ */