ioapic: Don't assert that interrupt mode are level/low or edge/high
[dragonfly.git] / sys / platform / pc32 / apic / ioapic_abi.c
CommitLineData
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
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6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
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9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
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12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
37e7efec 39 *
0b692e79 40 * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
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41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
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47#include <sys/interrupt.h>
48#include <sys/bus.h>
0b692e79 49
37e7efec 50#include <machine/smp.h>
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51#include <machine/segments.h>
52#include <machine/md_var.h>
87cf6827 53#include <machine/intr_machdep.h>
a9295349 54#include <machine_base/icu/icu.h>
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55#include <machine/globaldata.h>
56
57#include <sys/thread2.h>
58
6b809ec7 59#include <machine_base/icu/icu_var.h>
929c940f 60#include <machine_base/apic/ioapic_abi.h>
77f86d14 61#include <machine_base/apic/ioapic_ipl.h>
37e7efec 62
30c5f287 63#ifdef SMP /* APIC-IO */
37e7efec 64
10ff1029 65extern inthand_t
9e0e3f85
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66 IDTVEC(ioapic_intr0),
67 IDTVEC(ioapic_intr1),
68 IDTVEC(ioapic_intr2),
69 IDTVEC(ioapic_intr3),
70 IDTVEC(ioapic_intr4),
71 IDTVEC(ioapic_intr5),
72 IDTVEC(ioapic_intr6),
73 IDTVEC(ioapic_intr7),
74 IDTVEC(ioapic_intr8),
75 IDTVEC(ioapic_intr9),
76 IDTVEC(ioapic_intr10),
77 IDTVEC(ioapic_intr11),
78 IDTVEC(ioapic_intr12),
79 IDTVEC(ioapic_intr13),
80 IDTVEC(ioapic_intr14),
81 IDTVEC(ioapic_intr15),
82 IDTVEC(ioapic_intr16),
83 IDTVEC(ioapic_intr17),
84 IDTVEC(ioapic_intr18),
85 IDTVEC(ioapic_intr19),
86 IDTVEC(ioapic_intr20),
87 IDTVEC(ioapic_intr21),
88 IDTVEC(ioapic_intr22),
89 IDTVEC(ioapic_intr23),
90 IDTVEC(ioapic_intr24),
91 IDTVEC(ioapic_intr25),
92 IDTVEC(ioapic_intr26),
93 IDTVEC(ioapic_intr27),
94 IDTVEC(ioapic_intr28),
95 IDTVEC(ioapic_intr29),
96 IDTVEC(ioapic_intr30),
97 IDTVEC(ioapic_intr31),
98 IDTVEC(ioapic_intr32),
99 IDTVEC(ioapic_intr33),
100 IDTVEC(ioapic_intr34),
101 IDTVEC(ioapic_intr35),
102 IDTVEC(ioapic_intr36),
103 IDTVEC(ioapic_intr37),
104 IDTVEC(ioapic_intr38),
105 IDTVEC(ioapic_intr39),
106 IDTVEC(ioapic_intr40),
107 IDTVEC(ioapic_intr41),
108 IDTVEC(ioapic_intr42),
109 IDTVEC(ioapic_intr43),
110 IDTVEC(ioapic_intr44),
111 IDTVEC(ioapic_intr45),
112 IDTVEC(ioapic_intr46),
113 IDTVEC(ioapic_intr47),
114 IDTVEC(ioapic_intr48),
115 IDTVEC(ioapic_intr49),
116 IDTVEC(ioapic_intr50),
117 IDTVEC(ioapic_intr51),
118 IDTVEC(ioapic_intr52),
119 IDTVEC(ioapic_intr53),
120 IDTVEC(ioapic_intr54),
121 IDTVEC(ioapic_intr55),
122 IDTVEC(ioapic_intr56),
123 IDTVEC(ioapic_intr57),
124 IDTVEC(ioapic_intr58),
125 IDTVEC(ioapic_intr59),
126 IDTVEC(ioapic_intr60),
127 IDTVEC(ioapic_intr61),
128 IDTVEC(ioapic_intr62),
129 IDTVEC(ioapic_intr63),
130 IDTVEC(ioapic_intr64),
131 IDTVEC(ioapic_intr65),
132 IDTVEC(ioapic_intr66),
133 IDTVEC(ioapic_intr67),
134 IDTVEC(ioapic_intr68),
135 IDTVEC(ioapic_intr69),
136 IDTVEC(ioapic_intr70),
137 IDTVEC(ioapic_intr71),
138 IDTVEC(ioapic_intr72),
139 IDTVEC(ioapic_intr73),
140 IDTVEC(ioapic_intr74),
141 IDTVEC(ioapic_intr75),
142 IDTVEC(ioapic_intr76),
143 IDTVEC(ioapic_intr77),
144 IDTVEC(ioapic_intr78),
145 IDTVEC(ioapic_intr79),
146 IDTVEC(ioapic_intr80),
147 IDTVEC(ioapic_intr81),
148 IDTVEC(ioapic_intr82),
149 IDTVEC(ioapic_intr83),
150 IDTVEC(ioapic_intr84),
151 IDTVEC(ioapic_intr85),
152 IDTVEC(ioapic_intr86),
153 IDTVEC(ioapic_intr87),
154 IDTVEC(ioapic_intr88),
155 IDTVEC(ioapic_intr89),
156 IDTVEC(ioapic_intr90),
157 IDTVEC(ioapic_intr91),
158 IDTVEC(ioapic_intr92),
159 IDTVEC(ioapic_intr93),
160 IDTVEC(ioapic_intr94),
161 IDTVEC(ioapic_intr95),
162 IDTVEC(ioapic_intr96),
163 IDTVEC(ioapic_intr97),
164 IDTVEC(ioapic_intr98),
165 IDTVEC(ioapic_intr99),
166 IDTVEC(ioapic_intr100),
167 IDTVEC(ioapic_intr101),
168 IDTVEC(ioapic_intr102),
169 IDTVEC(ioapic_intr103),
170 IDTVEC(ioapic_intr104),
171 IDTVEC(ioapic_intr105),
172 IDTVEC(ioapic_intr106),
173 IDTVEC(ioapic_intr107),
174 IDTVEC(ioapic_intr108),
175 IDTVEC(ioapic_intr109),
176 IDTVEC(ioapic_intr110),
177 IDTVEC(ioapic_intr111),
178 IDTVEC(ioapic_intr112),
179 IDTVEC(ioapic_intr113),
180 IDTVEC(ioapic_intr114),
181 IDTVEC(ioapic_intr115),
182 IDTVEC(ioapic_intr116),
183 IDTVEC(ioapic_intr117),
184 IDTVEC(ioapic_intr118),
185 IDTVEC(ioapic_intr119),
186 IDTVEC(ioapic_intr120),
187 IDTVEC(ioapic_intr121),
188 IDTVEC(ioapic_intr122),
189 IDTVEC(ioapic_intr123),
190 IDTVEC(ioapic_intr124),
191 IDTVEC(ioapic_intr125),
192 IDTVEC(ioapic_intr126),
193 IDTVEC(ioapic_intr127),
194 IDTVEC(ioapic_intr128),
195 IDTVEC(ioapic_intr129),
196 IDTVEC(ioapic_intr130),
197 IDTVEC(ioapic_intr131),
198 IDTVEC(ioapic_intr132),
199 IDTVEC(ioapic_intr133),
200 IDTVEC(ioapic_intr134),
201 IDTVEC(ioapic_intr135),
202 IDTVEC(ioapic_intr136),
203 IDTVEC(ioapic_intr137),
204 IDTVEC(ioapic_intr138),
205 IDTVEC(ioapic_intr139),
206 IDTVEC(ioapic_intr140),
207 IDTVEC(ioapic_intr141),
208 IDTVEC(ioapic_intr142),
209 IDTVEC(ioapic_intr143),
210 IDTVEC(ioapic_intr144),
211 IDTVEC(ioapic_intr145),
212 IDTVEC(ioapic_intr146),
213 IDTVEC(ioapic_intr147),
214 IDTVEC(ioapic_intr148),
215 IDTVEC(ioapic_intr149),
216 IDTVEC(ioapic_intr150),
217 IDTVEC(ioapic_intr151),
218 IDTVEC(ioapic_intr152),
219 IDTVEC(ioapic_intr153),
220 IDTVEC(ioapic_intr154),
221 IDTVEC(ioapic_intr155),
222 IDTVEC(ioapic_intr156),
223 IDTVEC(ioapic_intr157),
224 IDTVEC(ioapic_intr158),
225 IDTVEC(ioapic_intr159),
226 IDTVEC(ioapic_intr160),
227 IDTVEC(ioapic_intr161),
228 IDTVEC(ioapic_intr162),
229 IDTVEC(ioapic_intr163),
230 IDTVEC(ioapic_intr164),
231 IDTVEC(ioapic_intr165),
232 IDTVEC(ioapic_intr166),
233 IDTVEC(ioapic_intr167),
234 IDTVEC(ioapic_intr168),
235 IDTVEC(ioapic_intr169),
236 IDTVEC(ioapic_intr170),
237 IDTVEC(ioapic_intr171),
238 IDTVEC(ioapic_intr172),
239 IDTVEC(ioapic_intr173),
240 IDTVEC(ioapic_intr174),
241 IDTVEC(ioapic_intr175),
242 IDTVEC(ioapic_intr176),
243 IDTVEC(ioapic_intr177),
244 IDTVEC(ioapic_intr178),
245 IDTVEC(ioapic_intr179),
246 IDTVEC(ioapic_intr180),
247 IDTVEC(ioapic_intr181),
248 IDTVEC(ioapic_intr182),
249 IDTVEC(ioapic_intr183),
250 IDTVEC(ioapic_intr184),
251 IDTVEC(ioapic_intr185),
252 IDTVEC(ioapic_intr186),
253 IDTVEC(ioapic_intr187),
254 IDTVEC(ioapic_intr188),
255 IDTVEC(ioapic_intr189),
256 IDTVEC(ioapic_intr190),
257 IDTVEC(ioapic_intr191);
258
259static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
260 &IDTVEC(ioapic_intr0),
261 &IDTVEC(ioapic_intr1),
262 &IDTVEC(ioapic_intr2),
263 &IDTVEC(ioapic_intr3),
264 &IDTVEC(ioapic_intr4),
265 &IDTVEC(ioapic_intr5),
266 &IDTVEC(ioapic_intr6),
267 &IDTVEC(ioapic_intr7),
268 &IDTVEC(ioapic_intr8),
269 &IDTVEC(ioapic_intr9),
270 &IDTVEC(ioapic_intr10),
271 &IDTVEC(ioapic_intr11),
272 &IDTVEC(ioapic_intr12),
273 &IDTVEC(ioapic_intr13),
274 &IDTVEC(ioapic_intr14),
275 &IDTVEC(ioapic_intr15),
276 &IDTVEC(ioapic_intr16),
277 &IDTVEC(ioapic_intr17),
278 &IDTVEC(ioapic_intr18),
279 &IDTVEC(ioapic_intr19),
280 &IDTVEC(ioapic_intr20),
281 &IDTVEC(ioapic_intr21),
282 &IDTVEC(ioapic_intr22),
283 &IDTVEC(ioapic_intr23),
284 &IDTVEC(ioapic_intr24),
285 &IDTVEC(ioapic_intr25),
286 &IDTVEC(ioapic_intr26),
287 &IDTVEC(ioapic_intr27),
288 &IDTVEC(ioapic_intr28),
289 &IDTVEC(ioapic_intr29),
290 &IDTVEC(ioapic_intr30),
291 &IDTVEC(ioapic_intr31),
292 &IDTVEC(ioapic_intr32),
293 &IDTVEC(ioapic_intr33),
294 &IDTVEC(ioapic_intr34),
295 &IDTVEC(ioapic_intr35),
296 &IDTVEC(ioapic_intr36),
297 &IDTVEC(ioapic_intr37),
298 &IDTVEC(ioapic_intr38),
299 &IDTVEC(ioapic_intr39),
300 &IDTVEC(ioapic_intr40),
301 &IDTVEC(ioapic_intr41),
302 &IDTVEC(ioapic_intr42),
303 &IDTVEC(ioapic_intr43),
304 &IDTVEC(ioapic_intr44),
305 &IDTVEC(ioapic_intr45),
306 &IDTVEC(ioapic_intr46),
307 &IDTVEC(ioapic_intr47),
308 &IDTVEC(ioapic_intr48),
309 &IDTVEC(ioapic_intr49),
310 &IDTVEC(ioapic_intr50),
311 &IDTVEC(ioapic_intr51),
312 &IDTVEC(ioapic_intr52),
313 &IDTVEC(ioapic_intr53),
314 &IDTVEC(ioapic_intr54),
315 &IDTVEC(ioapic_intr55),
316 &IDTVEC(ioapic_intr56),
317 &IDTVEC(ioapic_intr57),
318 &IDTVEC(ioapic_intr58),
319 &IDTVEC(ioapic_intr59),
320 &IDTVEC(ioapic_intr60),
321 &IDTVEC(ioapic_intr61),
322 &IDTVEC(ioapic_intr62),
323 &IDTVEC(ioapic_intr63),
324 &IDTVEC(ioapic_intr64),
325 &IDTVEC(ioapic_intr65),
326 &IDTVEC(ioapic_intr66),
327 &IDTVEC(ioapic_intr67),
328 &IDTVEC(ioapic_intr68),
329 &IDTVEC(ioapic_intr69),
330 &IDTVEC(ioapic_intr70),
331 &IDTVEC(ioapic_intr71),
332 &IDTVEC(ioapic_intr72),
333 &IDTVEC(ioapic_intr73),
334 &IDTVEC(ioapic_intr74),
335 &IDTVEC(ioapic_intr75),
336 &IDTVEC(ioapic_intr76),
337 &IDTVEC(ioapic_intr77),
338 &IDTVEC(ioapic_intr78),
339 &IDTVEC(ioapic_intr79),
340 &IDTVEC(ioapic_intr80),
341 &IDTVEC(ioapic_intr81),
342 &IDTVEC(ioapic_intr82),
343 &IDTVEC(ioapic_intr83),
344 &IDTVEC(ioapic_intr84),
345 &IDTVEC(ioapic_intr85),
346 &IDTVEC(ioapic_intr86),
347 &IDTVEC(ioapic_intr87),
348 &IDTVEC(ioapic_intr88),
349 &IDTVEC(ioapic_intr89),
350 &IDTVEC(ioapic_intr90),
351 &IDTVEC(ioapic_intr91),
352 &IDTVEC(ioapic_intr92),
353 &IDTVEC(ioapic_intr93),
354 &IDTVEC(ioapic_intr94),
355 &IDTVEC(ioapic_intr95),
356 &IDTVEC(ioapic_intr96),
357 &IDTVEC(ioapic_intr97),
358 &IDTVEC(ioapic_intr98),
359 &IDTVEC(ioapic_intr99),
360 &IDTVEC(ioapic_intr100),
361 &IDTVEC(ioapic_intr101),
362 &IDTVEC(ioapic_intr102),
363 &IDTVEC(ioapic_intr103),
364 &IDTVEC(ioapic_intr104),
365 &IDTVEC(ioapic_intr105),
366 &IDTVEC(ioapic_intr106),
367 &IDTVEC(ioapic_intr107),
368 &IDTVEC(ioapic_intr108),
369 &IDTVEC(ioapic_intr109),
370 &IDTVEC(ioapic_intr110),
371 &IDTVEC(ioapic_intr111),
372 &IDTVEC(ioapic_intr112),
373 &IDTVEC(ioapic_intr113),
374 &IDTVEC(ioapic_intr114),
375 &IDTVEC(ioapic_intr115),
376 &IDTVEC(ioapic_intr116),
377 &IDTVEC(ioapic_intr117),
378 &IDTVEC(ioapic_intr118),
379 &IDTVEC(ioapic_intr119),
380 &IDTVEC(ioapic_intr120),
381 &IDTVEC(ioapic_intr121),
382 &IDTVEC(ioapic_intr122),
383 &IDTVEC(ioapic_intr123),
384 &IDTVEC(ioapic_intr124),
385 &IDTVEC(ioapic_intr125),
386 &IDTVEC(ioapic_intr126),
387 &IDTVEC(ioapic_intr127),
388 &IDTVEC(ioapic_intr128),
389 &IDTVEC(ioapic_intr129),
390 &IDTVEC(ioapic_intr130),
391 &IDTVEC(ioapic_intr131),
392 &IDTVEC(ioapic_intr132),
393 &IDTVEC(ioapic_intr133),
394 &IDTVEC(ioapic_intr134),
395 &IDTVEC(ioapic_intr135),
396 &IDTVEC(ioapic_intr136),
397 &IDTVEC(ioapic_intr137),
398 &IDTVEC(ioapic_intr138),
399 &IDTVEC(ioapic_intr139),
400 &IDTVEC(ioapic_intr140),
401 &IDTVEC(ioapic_intr141),
402 &IDTVEC(ioapic_intr142),
403 &IDTVEC(ioapic_intr143),
404 &IDTVEC(ioapic_intr144),
405 &IDTVEC(ioapic_intr145),
406 &IDTVEC(ioapic_intr146),
407 &IDTVEC(ioapic_intr147),
408 &IDTVEC(ioapic_intr148),
409 &IDTVEC(ioapic_intr149),
410 &IDTVEC(ioapic_intr150),
411 &IDTVEC(ioapic_intr151),
412 &IDTVEC(ioapic_intr152),
413 &IDTVEC(ioapic_intr153),
414 &IDTVEC(ioapic_intr154),
415 &IDTVEC(ioapic_intr155),
416 &IDTVEC(ioapic_intr156),
417 &IDTVEC(ioapic_intr157),
418 &IDTVEC(ioapic_intr158),
419 &IDTVEC(ioapic_intr159),
420 &IDTVEC(ioapic_intr160),
421 &IDTVEC(ioapic_intr161),
422 &IDTVEC(ioapic_intr162),
423 &IDTVEC(ioapic_intr163),
424 &IDTVEC(ioapic_intr164),
425 &IDTVEC(ioapic_intr165),
426 &IDTVEC(ioapic_intr166),
427 &IDTVEC(ioapic_intr167),
428 &IDTVEC(ioapic_intr168),
429 &IDTVEC(ioapic_intr169),
430 &IDTVEC(ioapic_intr170),
431 &IDTVEC(ioapic_intr171),
432 &IDTVEC(ioapic_intr172),
433 &IDTVEC(ioapic_intr173),
434 &IDTVEC(ioapic_intr174),
435 &IDTVEC(ioapic_intr175),
436 &IDTVEC(ioapic_intr176),
437 &IDTVEC(ioapic_intr177),
438 &IDTVEC(ioapic_intr178),
439 &IDTVEC(ioapic_intr179),
440 &IDTVEC(ioapic_intr180),
441 &IDTVEC(ioapic_intr181),
442 &IDTVEC(ioapic_intr182),
443 &IDTVEC(ioapic_intr183),
444 &IDTVEC(ioapic_intr184),
445 &IDTVEC(ioapic_intr185),
446 &IDTVEC(ioapic_intr186),
447 &IDTVEC(ioapic_intr187),
448 &IDTVEC(ioapic_intr188),
449 &IDTVEC(ioapic_intr189),
450 &IDTVEC(ioapic_intr190),
451 &IDTVEC(ioapic_intr191)
c571da4a 452};
10ff1029 453
474ba684
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454#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
455
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456static struct ioapic_irqmap {
457 int im_type; /* IOAPIC_IMT_ */
458 enum intr_trigger im_trig;
f6915355 459 enum intr_polarity im_pola;
a3dd9120 460 int im_gsi;
d1ae7328 461 uint32_t im_flags; /* IOAPIC_IMF_ */
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462} ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
463
464#define IOAPIC_IMT_UNUSED 0
465#define IOAPIC_IMT_RESERVED 1
466#define IOAPIC_IMT_LINE 2
474ba684 467#define IOAPIC_IMT_SYSCALL 3
a3dd9120 468
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469#define IOAPIC_IMF_CONF 0x1
470
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471extern void IOAPIC_INTREN(int);
472extern void IOAPIC_INTRDIS(int);
473
474static int ioapic_setvar(int, const void *);
475static int ioapic_getvar(int, void *);
476static int ioapic_vectorctl(int, int, int);
477static void ioapic_finalize(void);
478static void ioapic_cleanup(void);
479static void ioapic_setdefault(void);
7bf5fa56 480static void ioapic_stabilize(void);
a3dd9120 481static void ioapic_initmap(void);
d1ae7328 482static void ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
9e0e3f85 483
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484struct machintr_abi MachIntrABI_IOAPIC = {
485 MACHINTR_IOAPIC,
486 .intrdis = IOAPIC_INTRDIS,
487 .intren = IOAPIC_INTREN,
488 .vectorctl = ioapic_vectorctl,
489 .setvar = ioapic_setvar,
490 .getvar = ioapic_getvar,
491 .finalize = ioapic_finalize,
492 .cleanup = ioapic_cleanup,
7bf5fa56 493 .setdefault = ioapic_setdefault,
a3dd9120 494 .stabilize = ioapic_stabilize,
d1ae7328
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495 .initmap = ioapic_initmap,
496 .intr_config = ioapic_intr_config
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497};
498
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499static int ioapic_abi_extint_irq = -1;
500
37e7efec 501static int
9e0e3f85 502ioapic_setvar(int varid, const void *buf)
37e7efec 503{
9d758cc4 504 return ENOENT;
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505}
506
507static int
9e0e3f85 508ioapic_getvar(int varid, void *buf)
37e7efec 509{
9d758cc4 510 return ENOENT;
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511}
512
37e7efec 513static void
9e0e3f85 514ioapic_finalize(void)
37e7efec 515{
e0918665 516 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
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517 KKASSERT(apic_io_enable);
518
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519 /*
520 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 521 * from the BSP.
54e1df6b 522 */
9d758cc4 523 if (imcr_present) {
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524 outb(0x22, 0x70); /* select IMCR */
525 outb(0x23, 0x01); /* disconnect 8259 */
526 }
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527}
528
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529/*
530 * This routine is called after physical interrupts are enabled but before
531 * the critical section is released. We need to clean out any interrupts
532 * that had already been posted to the cpu.
533 */
534static void
9e0e3f85 535ioapic_cleanup(void)
0b692e79 536{
c263294b 537 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
0b692e79
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538}
539
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540/* Must never be called */
541static void
542ioapic_stabilize(void)
543{
544 panic("ioapic_stabilize() is called\n");
545}
546
54e1df6b 547static int
9e0e3f85 548ioapic_vectorctl(int op, int intr, int flags)
10ff1029 549{
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550 int error;
551 int vector;
552 int select;
553 uint32_t value;
554 u_long ef;
10ff1029 555
9e0e3f85 556 if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
474ba684 557 intr == IOAPIC_HWI_SYSCALL)
54e1df6b 558 return EINVAL;
10ff1029 559
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560 ef = read_eflags();
561 cpu_disable_intr();
562 error = 0;
10ff1029 563
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564 switch(op) {
565 case MACHINTR_VECTOR_SETUP:
566 vector = IDT_OFFSET + intr;
9e0e3f85 567 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT,
54e1df6b 568 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
35408d22 569
54e1df6b
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570 /*
571 * Now reprogram the vector in the IO APIC. In order to avoid
572 * losing an EOI for a level interrupt, which is vector based,
573 * make sure that the IO APIC is programmed for edge-triggering
574 * first, then reprogrammed with the new vector. This should
575 * clear the IRR bit.
576 */
577 if (int_to_apicintpin[intr].ioapic >= 0) {
578 if (bootverbose) {
579 kprintf("IOAPIC: try clearing IRR for "
580 "irq %d\n", intr);
581 }
35408d22 582
54e1df6b
SZ
583 imen_lock();
584
585 select = int_to_apicintpin[intr].redirindex;
e17120aa 586 value = ioapic_read(int_to_apicintpin[intr].apic_address,
9e0e3f85 587 select);
54e1df6b
SZ
588 value |= IOART_INTMSET;
589
e17120aa 590 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 591 select, (value & ~APIC_TRIGMOD_MASK));
e17120aa 592 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 593 select, (value & ~IOART_INTVEC) | vector);
54e1df6b
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594
595 imen_unlock();
596 }
597
598 machintr_intren(intr);
599 break;
600
601 case MACHINTR_VECTOR_TEARDOWN:
602 /*
603 * Teardown an interrupt vector. The vector should already be
604 * installed in the cpu's IDT, but make sure.
605 */
606 machintr_intrdis(intr);
607
608 vector = IDT_OFFSET + intr;
9e0e3f85 609 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT, SEL_KPL,
54e1df6b
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610 GSEL(GCODE_SEL, SEL_KPL));
611
612 /*
54e1df6b
SZ
613 * In order to avoid losing an EOI for a level interrupt, which
614 * is vector based, make sure that the IO APIC is programmed for
615 * edge-triggering first, then reprogrammed with the new vector.
616 * This should clear the IRR bit.
617 */
618 if (int_to_apicintpin[intr].ioapic >= 0) {
619 imen_lock();
620
621 select = int_to_apicintpin[intr].redirindex;
e17120aa 622 value = ioapic_read(int_to_apicintpin[intr].apic_address,
9e0e3f85 623 select);
54e1df6b 624
e17120aa 625 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 626 select, (value & ~APIC_TRIGMOD_MASK));
e17120aa 627 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 628 select, (value & ~IOART_INTVEC) | vector);
54e1df6b
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629
630 imen_unlock();
631 }
632 break;
633
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SZ
634 default:
635 error = EOPNOTSUPP;
636 break;
35408d22 637 }
10ff1029 638
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639 write_eflags(ef);
640 return error;
641}
06f5be02 642
10db3cc6 643static void
9e0e3f85 644ioapic_setdefault(void)
10db3cc6
SZ
645{
646 int intr;
647
9e0e3f85 648 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 649 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 650 continue;
9e0e3f85 651 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
10db3cc6
SZ
652 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
653 }
654}
655
a3dd9120
SZ
656static void
657ioapic_initmap(void)
658{
659 int i;
660
c36b581c
SZ
661 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
662 ioapic_irqmaps[i].im_gsi = -1;
474ba684 663 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
a3dd9120
SZ
664}
665
929c940f
SZ
666void
667ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
668 enum intr_polarity pola)
669{
670 struct apic_intmapinfo *info;
671 struct ioapic_irqmap *map;
672 void *ioaddr;
673 int pin;
674
675 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
676 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
677
678 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
679 map = &ioapic_irqmaps[irq];
680
681 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
682 map->im_type = IOAPIC_IMT_LINE;
683
684 map->im_gsi = gsi;
685 map->im_trig = trig;
686 map->im_pola = pola;
687
688 if (bootverbose) {
689 kprintf("IOAPIC: irq %d -> gsi %d %c\n", irq, map->im_gsi,
d1ae7328 690 map->im_trig == INTR_TRIGGER_LEVEL ? 'L' : 'E');
929c940f
SZ
691 }
692
d1ae7328
SZ
693 pin = ioapic_gsi_pin(map->im_gsi);
694 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f
SZ
695
696 info = &int_to_apicintpin[irq];
697
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SZ
698 imen_lock();
699
929c940f
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700 info->ioapic = 0; /* XXX unused */
701 info->int_pin = pin;
702 info->apic_address = ioaddr;
703 info->redirindex = IOAPIC_REDTBL + (2 * pin);
704 info->flags = IOAPIC_IM_FLAG_MASKED;
d1ae7328
SZ
705 if (map->im_trig == INTR_TRIGGER_LEVEL)
706 info->flags |= IOAPIC_IM_FLAG_LEVEL;
707
708 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
709 map->im_trig, map->im_pola);
7bceaa10
SZ
710
711 imen_unlock();
d1ae7328
SZ
712}
713
4a913811
SZ
714void
715ioapic_abi_fixup_irqmap(void)
716{
717 int i;
718
719 for (i = 0; i < 16; ++i) {
720 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
721
722 if (map->im_type == IOAPIC_IMT_UNUSED) {
723 map->im_type = IOAPIC_IMT_RESERVED;
724 if (bootverbose)
725 kprintf("IOAPIC: irq %d reserved\n", i);
726 }
727 }
728}
729
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730int
731ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
732{
733 int irq;
734
735 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
736 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
737
738 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
739 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
740
741 if (map->im_gsi == gsi) {
742 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
743
744 if (map->im_flags & IOAPIC_IMF_CONF) {
745 if (map->im_trig != trig ||
746 map->im_pola != pola)
747 return -1;
748 }
749 return irq;
750 }
751 }
752 return -1;
753}
754
755int
756ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
757{
758 const struct ioapic_irqmap *map;
759
760 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
761 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
762
763 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
764 return -1;
765 map = &ioapic_irqmaps[irq];
766
767 if (map->im_type != IOAPIC_IMT_LINE)
768 return -1;
769
770 if (map->im_flags & IOAPIC_IMF_CONF) {
771 if (map->im_trig != trig || map->im_pola != pola)
772 return -1;
773 }
774 return irq;
775}
776
d1ae7328
SZ
777static void
778ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
779{
780 struct apic_intmapinfo *info;
781 struct ioapic_irqmap *map;
782 void *ioaddr;
783 int pin;
784
a49b03f0
SZ
785 if (ioapic_use_old) {
786 if (bootverbose) {
787 kprintf("irq %d, trig %c\n", irq,
788 trig == INTR_TRIGGER_EDGE ? 'E' : 'L');
789 }
d1ae7328 790 return;
a49b03f0 791 }
d1ae7328
SZ
792
793 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
794 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328
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795
796 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
797 map = &ioapic_irqmaps[irq];
798
799 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
800
801 if (map->im_flags & IOAPIC_IMF_CONF) {
802 if (trig != map->im_trig) {
803 panic("ioapic_intr_config: trig %c -> %c\n",
804 map->im_trig == INTR_TRIGGER_EDGE ? 'E' : 'L',
805 trig == INTR_TRIGGER_EDGE ? 'E' : 'L');
806 }
807 if (pola != map->im_pola) {
808 panic("ioapic_intr_config: pola %s -> %s\n",
809 map->im_pola == INTR_POLARITY_HIGH ? "hi" : "lo",
810 pola == INTR_POLARITY_HIGH ? "hi" : "lo");
811 }
812 return;
813 }
814 map->im_flags |= IOAPIC_IMF_CONF;
815
816 if (trig == map->im_trig && pola == map->im_pola)
817 return;
818
819 if (bootverbose) {
820 kprintf("IOAPIC: irq %d, gsi %d %c -> %c\n", irq, map->im_gsi,
821 map->im_trig == INTR_TRIGGER_LEVEL ? 'L' : 'E',
822 trig == INTR_TRIGGER_LEVEL ? 'L' : 'E');
823 }
824
825 map->im_trig = trig;
826 map->im_pola = pola;
827
828 pin = ioapic_gsi_pin(map->im_gsi);
829 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
830
831 info = &int_to_apicintpin[irq];
832
7bceaa10
SZ
833 imen_lock();
834
d1ae7328
SZ
835 info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
836 if (map->im_trig == INTR_TRIGGER_LEVEL)
929c940f
SZ
837 info->flags |= IOAPIC_IM_FLAG_LEVEL;
838
ecec8ddc
SZ
839 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
840 map->im_trig, map->im_pola);
7bceaa10
SZ
841
842 imen_unlock();
929c940f
SZ
843}
844
6b809ec7
SZ
845int
846ioapic_abi_extint_irqmap(int irq)
847{
848 struct apic_intmapinfo *info;
849 struct ioapic_irqmap *map;
850 void *ioaddr;
851 int pin, error, vec;
852
853 vec = IDT_OFFSET + irq;
854
855 if (ioapic_abi_extint_irq == irq)
856 return 0;
857 else if (ioapic_abi_extint_irq >= 0)
858 return EEXIST;
859
860 error = icu_ioapic_extint(irq, vec);
861 if (error)
862 return error;
863
864 map = &ioapic_irqmaps[irq];
865
866 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
867 map->im_type == IOAPIC_IMT_LINE);
868 if (map->im_type == IOAPIC_IMT_LINE) {
869 if (map->im_flags & IOAPIC_IMF_CONF)
870 return EEXIST;
871 }
872 ioapic_abi_extint_irq = irq;
873
874 map->im_type = IOAPIC_IMT_LINE;
875 map->im_trig = INTR_TRIGGER_EDGE;
876 map->im_pola = INTR_POLARITY_HIGH;
877 map->im_flags = IOAPIC_IMF_CONF;
878
879 map->im_gsi = ioapic_extpin_gsi();
880 KKASSERT(map->im_gsi >= 0);
881
882 if (bootverbose) {
883 kprintf("IOAPIC: irq %d -> extint gsi %d E\n", irq,
884 map->im_gsi);
885 }
886
887 pin = ioapic_gsi_pin(map->im_gsi);
888 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
889
890 info = &int_to_apicintpin[irq];
891
892 imen_lock();
893
894 info->ioapic = 0; /* XXX unused */
895 info->int_pin = pin;
896 info->apic_address = ioaddr;
897 info->redirindex = IOAPIC_REDTBL + (2 * pin);
898 info->flags = IOAPIC_IM_FLAG_MASKED;
899
900 ioapic_extpin_setup(ioaddr, pin, vec);
901
902 imen_unlock();
903
904 return 0;
905}
906
54e1df6b 907#endif /* SMP */