i386: Move CPU ID and APIC ID maps from mp_machdep.c to lapic.c
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
984263bc
MD
27 */
28
29#include "opt_cpu.h"
984263bc 30
984263bc
MD
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
984263bc
MD
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
984263bc
MD
39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
984263bc
MD
45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
984263bc 51
684a93c4
MD
52#include <sys/mplock2.h>
53
984263bc 54#include <machine/smp.h>
a9295349 55#include <machine_base/apic/apicreg.h>
984263bc
MD
56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
90e8a35b 58#include <machine/cputypes.h>
e0918665 59#include <machine_base/apic/ioapic_abi.h>
3340ac41 60#include <machine_base/apic/lapic.h>
4298586a 61#include <machine_base/apic/ioapic.h>
984263bc
MD
62#include <machine/psl.h>
63#include <machine/segments.h>
984263bc
MD
64#include <machine/tss.h>
65#include <machine/specialreg.h>
66#include <machine/globaldata.h>
4117f2fd 67#include <machine/pmap_inval.h>
984263bc 68
984263bc 69#include <machine/md_var.h> /* setidt() */
87cf6827
SZ
70#include <machine_base/icu/icu.h> /* IPIs */
71#include <machine/intr_machdep.h> /* IPIs */
984263bc 72
984263bc
MD
73#define WARMBOOT_TARGET 0
74#define WARMBOOT_OFF (KERNBASE + 0x0467)
75#define WARMBOOT_SEG (KERNBASE + 0x0469)
76
984263bc
MD
77#define CMOS_REG (0x70)
78#define CMOS_DATA (0x71)
79#define BIOS_RESET (0x0f)
80#define BIOS_WARM (0x0a)
81
984263bc
MD
82/*
83 * this code MUST be enabled here and in mpboot.s.
84 * it follows the very early stages of AP boot by placing values in CMOS ram.
85 * it NORMALLY will never be needed and thus the primitive method for enabling.
86 *
984263bc 87 */
7d34994c 88#if defined(CHECK_POINTS)
984263bc
MD
89#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
90#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
91
92#define CHECK_INIT(D); \
93 CHECK_WRITE(0x34, (D)); \
94 CHECK_WRITE(0x35, (D)); \
95 CHECK_WRITE(0x36, (D)); \
96 CHECK_WRITE(0x37, (D)); \
97 CHECK_WRITE(0x38, (D)); \
98 CHECK_WRITE(0x39, (D));
99
100#define CHECK_PRINT(S); \
26be20a0 101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
984263bc
MD
102 (S), \
103 CHECK_READ(0x34), \
104 CHECK_READ(0x35), \
105 CHECK_READ(0x36), \
106 CHECK_READ(0x37), \
107 CHECK_READ(0x38), \
108 CHECK_READ(0x39));
109
110#else /* CHECK_POINTS */
111
112#define CHECK_INIT(D)
113#define CHECK_PRINT(S)
114
115#endif /* CHECK_POINTS */
116
117/*
118 * Values to send to the POST hardware.
119 */
120#define MP_BOOTADDRESS_POST 0x10
121#define MP_PROBE_POST 0x11
122#define MPTABLE_PASS1_POST 0x12
123
124#define MP_START_POST 0x13
125#define MP_ENABLE_POST 0x14
126#define MPTABLE_PASS2_POST 0x15
127
128#define START_ALL_APS_POST 0x16
129#define INSTALL_AP_TRAMP_POST 0x17
130#define START_AP_POST 0x18
131
132#define MP_ANNOUNCE_POST 0x19
133
984263bc
MD
134/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
135int current_postcode;
136
137/** XXX FIXME: what system files declare these??? */
138extern struct region_descriptor r_gdt, r_idt;
139
984263bc 140int mp_naps; /* # of Applications processors */
984263bc
MD
141extern int nkpt;
142
374133e3 143int64_t tsc0_offset;
0b698dca 144extern int64_t tsc_offsets[];
984263bc 145
30c5f287 146#ifdef SMP /* APIC-IO */
8a8d5d85 147struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 148#endif
984263bc 149
984263bc
MD
150/* AP uses this during bootstrap. Do not staticize. */
151char *bootSTK;
152static int bootAP;
153
154/* Hotwire a 0->4MB V==P mapping */
155extern pt_entry_t *KPTphys;
156
f13b5eec
MD
157/*
158 * SMP page table page. Setup by locore to point to a page table
159 * page from which we allocate per-cpu privatespace areas io_apics,
160 * and so forth.
161 */
984263bc
MD
162extern pt_entry_t *SMPpt;
163
164struct pcb stoppcbs[MAXCPU];
165
984263bc
MD
166/*
167 * Local data and functions.
168 */
169
984263bc 170static u_int boot_address;
41a01a4d 171static int mp_finish;
52596b13 172static int mp_finish_lapic;
984263bc 173
984263bc
MD
174static void mp_enable(u_int boot_addr);
175
984263bc
MD
176static int start_all_aps(u_int boot_addr);
177static void install_ap_tramp(u_int boot_addr);
bb467734
MD
178static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
179static int smitest(void);
984263bc 180
41a01a4d 181static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
52596b13 182static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
0f7a3396
MD
183cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
184SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
185
117ef3aa 186u_int base_memory;
9d758cc4
SZ
187int imcr_present;
188
984263bc
MD
189/*
190 * Calculate usable address in base memory for AP trampoline code.
191 */
192u_int
193mp_bootaddress(u_int basemem)
194{
195 POSTCODE(MP_BOOTADDRESS_POST);
196
c0c5de70 197 base_memory = basemem;
984263bc
MD
198
199 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
200 if ((base_memory - boot_address) < bootMP_size)
201 boot_address -= 4096; /* not enough, lower by 4k */
202
203 return boot_address;
204}
205
984263bc
MD
206/*
207 * Startup the SMP processors.
208 */
209void
210mp_start(void)
211{
212 POSTCODE(MP_START_POST);
50bc991e 213 mp_enable(boot_address);
984263bc
MD
214}
215
216
217/*
218 * Print various information about the SMP system hardware and setup.
219 */
220void
221mp_announce(void)
222{
223 int x;
224
225 POSTCODE(MP_ANNOUNCE_POST);
226
26be20a0 227 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
fcddbf94
SZ
228 kprintf(" cpu0 (BSP): apic id: %2d\n", CPU_TO_ID(0));
229 for (x = 1; x <= mp_naps; ++x)
230 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPU_TO_ID(x));
984263bc 231
6ac31e9d
SZ
232 if (!apic_io_enable)
233 kprintf(" Warning: APIC I/O disabled\n");
984263bc
MD
234}
235
236/*
237 * AP cpu's call this to sync up protected mode.
7160572f
MD
238 *
239 * WARNING! We must ensure that the cpu is sufficiently initialized to
240 * be able to use to the FP for our optimized bzero/bcopy code before
241 * we enter more mainstream C code.
a44bdeec
MD
242 *
243 * WARNING! %fs is not set up on entry. This routine sets up %fs.
984263bc
MD
244 */
245void
246init_secondary(void)
247{
248 int gsel_tss;
249 int x, myid = bootAP;
250 u_int cr0;
8a8d5d85 251 struct mdglobaldata *md;
0f7a3396 252 struct privatespace *ps;
984263bc 253
0f7a3396
MD
254 ps = &CPU_prvspace[myid];
255
256 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 257 gdt_segs[GPROC0_SEL].ssd_base =
0f7a3396
MD
258 (int) &ps->mdglobaldata.gd_common_tss;
259 ps->mdglobaldata.mi.gd_prvspace = ps;
984263bc
MD
260
261 for (x = 0; x < NGDT; x++) {
262 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
263 }
264
265 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
266 r_gdt.rd_base = (int) &gdt[myid * NGDT];
267 lgdt(&r_gdt); /* does magic intra-segment return */
268
269 lidt(&r_idt);
270
271 lldt(_default_ldt);
7b95be2a 272 mdcpu->gd_currentldt = _default_ldt;
984263bc
MD
273
274 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
275 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 276
0f7a3396 277 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
MD
278
279 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
280 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
281 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
282 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
283 md->gd_common_tssd = *md->gd_tss_gdt;
984263bc
MD
284 ltr(gsel_tss);
285
286 /*
287 * Set to a known state:
288 * Set by mpboot.s: CR0_PG, CR0_PE
289 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
290 */
291 cr0 = rcr0();
292 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
293 load_cr0(cr0);
7160572f 294 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 295
7160572f
MD
296 /* set up CPU registers and state */
297 cpu_setregs();
298
299 /* set up FPU state on the AP */
300 npxinit(__INITIAL_NPXCW__);
301
302 /* set up SSE registers */
303 enable_sse();
984263bc
MD
304}
305
984263bc
MD
306/*******************************************************************
307 * local functions and data
308 */
309
310/*
311 * start the SMP system
312 */
313static void
314mp_enable(u_int boot_addr)
315{
984263bc
MD
316 POSTCODE(MP_ENABLE_POST);
317
281d9482 318 lapic_config();
984263bc 319
a40ec003
SZ
320 /* Initialize BSP's local APIC */
321 lapic_init(TRUE);
322
52596b13
SZ
323 /* start each Application Processor */
324 start_all_aps(boot_addr);
325
65b2387f
SZ
326 if (apic_io_enable)
327 ioapic_config();
328
a40ec003
SZ
329 /* Finalize PIC */
330 MachIntrABI.finalize();
984263bc
MD
331}
332
a9112655
SZ
333void
334mp_set_cpuids(int cpu_id, int apic_id)
335{
336 CPU_TO_ID(cpu_id) = apic_id;
337 ID_TO_CPU(apic_id) = cpu_id;
338}
339
984263bc
MD
340/*
341 * start each AP in our list
342 */
343static int
344start_all_aps(u_int boot_addr)
345{
b45759e1
MD
346 int x, i, pg;
347 int shift;
bb467734
MD
348 int smicount;
349 int smibest;
350 int smilast;
984263bc
MD
351 u_char mpbiosreason;
352 u_long mpbioswarmvec;
8a8d5d85 353 struct mdglobaldata *gd;
0f7a3396 354 struct privatespace *ps;
984263bc
MD
355 char *stack;
356 uintptr_t kptbase;
357
358 POSTCODE(START_ALL_APS_POST);
359
984263bc
MD
360 /* install the AP 1st level boot code */
361 install_ap_tramp(boot_addr);
362
363
364 /* save the current value of the warm-start vector */
365 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
366 outb(CMOS_REG, BIOS_RESET);
367 mpbiosreason = inb(CMOS_DATA);
984263bc 368
bb467734
MD
369 /* setup a vector to our boot code */
370 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
371 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
372 outb(CMOS_REG, BIOS_RESET);
373 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
374
375 /*
376 * If we have a TSC we can figure out the SMI interrupt rate.
377 * The SMI does not necessarily use a constant rate. Spend
378 * up to 250ms trying to figure it out.
379 */
380 smibest = 0;
381 if (cpu_feature & CPUID_TSC) {
382 set_apic_timer(275000);
383 smilast = read_apic_timer();
384 for (x = 0; x < 20 && read_apic_timer(); ++x) {
385 smicount = smitest();
386 if (smibest == 0 || smilast - smicount < smibest)
387 smibest = smilast - smicount;
388 smilast = smicount;
389 }
390 if (smibest > 250000)
391 smibest = 0;
392 if (smibest) {
393 smibest = smibest * (int64_t)1000000 /
394 get_apic_timer_frequency();
395 }
396 }
397 if (smibest)
398 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
399 1000000 / smibest, smibest);
400
401
984263bc
MD
402 /* set up temporary P==V mapping for AP boot */
403 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
404 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 405 for (x = 0; x < NKPT; x++) {
984263bc
MD
406 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
407 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 408 }
0f7a3396 409 cpu_invltlb();
984263bc
MD
410
411 /* start each AP */
412 for (x = 1; x <= mp_naps; ++x) {
413
414 /* This is a bit verbose, it will go away soon. */
415
416 /* first page of AP's private space */
417 pg = x * i386_btop(sizeof(struct privatespace));
418
81c04d07 419 /* allocate new private data page(s) */
e4846942 420 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 421 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 422 /* wire it into the private page table page */
81c04d07
MD
423 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
424 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
425 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
426 }
427 pg += MDGLOBALDATA_BASEALLOC_PAGES;
428
429 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
430 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
431 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
432 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
433
434 /* allocate and set up an idle stack data page */
e4846942 435 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 436 for (i = 0; i < UPAGES; i++) {
81c04d07 437 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 438 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 439 }
984263bc 440
8a8d5d85
MD
441 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
442 bzero(gd, sizeof(*gd));
0f7a3396 443 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 444
984263bc 445 /* prime data page for it to use */
8a8d5d85 446 mi_gdinit(&gd->mi, x);
8ad65e08 447 cpu_gdinit(gd, x);
81c04d07
MD
448 gd->gd_CMAP1 = &SMPpt[pg + 0];
449 gd->gd_CMAP2 = &SMPpt[pg + 1];
450 gd->gd_CMAP3 = &SMPpt[pg + 2];
451 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
452 gd->gd_CADDR1 = ps->CPAGE1;
453 gd->gd_CADDR2 = ps->CPAGE2;
454 gd->gd_CADDR3 = ps->CPAGE3;
455 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
9388fcaa
MD
456
457 /*
458 * Per-cpu pmap for get_ptbase().
459 */
460 gd->gd_GDADDR1= (unsigned *)
461 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
462 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
463
e4846942 464 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 465 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc 466
8a8d5d85
MD
467 /*
468 * Setup the AP boot stack
469 */
0f7a3396 470 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
471 bootAP = x;
472
473 /* attempt to start the Application Processor */
474 CHECK_INIT(99); /* setup checkpoints */
bb467734 475 if (!start_ap(gd, boot_addr, smibest)) {
26be20a0 476 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
477 CHECK_PRINT("trace"); /* show checkpoints */
478 /* better panic as the AP may be running loose */
26be20a0 479 kprintf("panic y/n? [y] ");
984263bc
MD
480 if (cngetc() != 'n')
481 panic("bye-bye");
482 }
483 CHECK_PRINT("trace"); /* show checkpoints */
984263bc
MD
484 }
485
0f7a3396
MD
486 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
487 ncpus = x;
488
b45759e1
MD
489 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
490 for (shift = 0; (1 << shift) <= ncpus; ++shift)
491 ;
492 --shift;
493 ncpus2_shift = shift;
494 ncpus2 = 1 << shift;
90100055
JH
495 ncpus2_mask = ncpus2 - 1;
496
b45759e1
MD
497 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
498 if ((1 << shift) < ncpus)
499 ++shift;
500 ncpus_fit = 1 << shift;
501 ncpus_fit_mask = ncpus_fit - 1;
502
984263bc 503 /* build our map of 'other' CPUs */
da23a592 504 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
e4846942 505 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 506 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc 507
984263bc
MD
508 /* restore the warmstart vector */
509 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
510 outb(CMOS_REG, BIOS_RESET);
511 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
512
513 /*
8a8d5d85
MD
514 * NOTE! The idlestack for the BSP was setup by locore. Finish
515 * up, clean out the P==V mapping we did earlier.
984263bc 516 */
984263bc
MD
517 for (x = 0; x < NKPT; x++)
518 PTD[x] = 0;
519 pmap_set_opt();
520
52596b13
SZ
521 /*
522 * Wait all APs to finish initializing LAPIC
523 */
524 mp_finish_lapic = 1;
525 if (bootverbose)
526 kprintf("SMP: Waiting APs LAPIC initialization\n");
527 if (cpu_feature & CPUID_TSC)
528 tsc0_offset = rdtsc();
529 tsc_offsets[0] = 0;
530 rel_mplock();
531 while (smp_lapic_mask != smp_startup_mask) {
532 cpu_lfence();
533 if (cpu_feature & CPUID_TSC)
534 tsc0_offset = rdtsc();
535 }
536 while (try_mplock() == 0)
537 ;
538
984263bc 539 /* number of APs actually started */
8a8d5d85 540 return ncpus - 1;
984263bc
MD
541}
542
984263bc
MD
543/*
544 * load the 1st level AP boot code into base memory.
545 */
546
547/* targets for relocation */
548extern void bigJump(void);
549extern void bootCodeSeg(void);
550extern void bootDataSeg(void);
551extern void MPentry(void);
552extern u_int MP_GDT;
553extern u_int mp_gdtbase;
554
555static void
556install_ap_tramp(u_int boot_addr)
557{
558 int x;
559 int size = *(int *) ((u_long) & bootMP_size);
560 u_char *src = (u_char *) ((u_long) bootMP);
561 u_char *dst = (u_char *) boot_addr + KERNBASE;
562 u_int boot_base = (u_int) bootMP;
563 u_int8_t *dst8;
564 u_int16_t *dst16;
565 u_int32_t *dst32;
566
567 POSTCODE(INSTALL_AP_TRAMP_POST);
568
569 for (x = 0; x < size; ++x)
570 *dst++ = *src++;
571
572 /*
573 * modify addresses in code we just moved to basemem. unfortunately we
574 * need fairly detailed info about mpboot.s for this to work. changes
575 * to mpboot.s might require changes here.
576 */
577
578 /* boot code is located in KERNEL space */
579 dst = (u_char *) boot_addr + KERNBASE;
580
581 /* modify the lgdt arg */
582 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
583 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
584
585 /* modify the ljmp target for MPentry() */
586 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
587 *dst32 = ((u_int) MPentry - KERNBASE);
588
589 /* modify the target for boot code segment */
590 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
591 dst8 = (u_int8_t *) (dst16 + 1);
592 *dst16 = (u_int) boot_addr & 0xffff;
593 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
594
595 /* modify the target for boot data segment */
596 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
597 dst8 = (u_int8_t *) (dst16 + 1);
598 *dst16 = (u_int) boot_addr & 0xffff;
599 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
600}
601
602
603/*
bb467734 604 * This function starts the AP (application processor) identified
984263bc
MD
605 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
606 * to accomplish this. This is necessary because of the nuances
607 * of the different hardware we might encounter. It ain't pretty,
608 * but it seems to work.
a108bf71
MD
609 *
610 * NOTE: eventually an AP gets to ap_init(), which is called just
611 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
612 */
613static int
bb467734 614start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
984263bc
MD
615{
616 int physical_cpu;
617 int vector;
984263bc
MD
618 u_long icr_lo, icr_hi;
619
620 POSTCODE(START_AP_POST);
621
622 /* get the PHYSICAL APIC ID# */
0f7a3396 623 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
624
625 /* calculate the vector */
626 vector = (boot_addr >> 12) & 0xff;
627
bb467734
MD
628 /* We don't want anything interfering */
629 cpu_disable_intr();
630
8a8d5d85
MD
631 /* Make sure the target cpu sees everything */
632 wbinvd();
984263bc 633
bb467734
MD
634 /*
635 * Try to detect when a SMI has occurred, wait up to 200ms.
636 *
637 * If a SMI occurs during an AP reset but before we issue
638 * the STARTUP command, the AP may brick. To work around
639 * this problem we hold off doing the AP startup until
640 * after we have detected the SMI. Hopefully another SMI
641 * will not occur before we finish the AP startup.
642 *
643 * Retries don't seem to help. SMIs have a window of opportunity
644 * and if USB->legacy keyboard emulation is enabled in the BIOS
645 * the interrupt rate can be quite high.
646 *
647 * NOTE: Don't worry about the L1 cache load, it might bloat
648 * ldelta a little but ndelta will be so huge when the SMI
649 * occurs the detection logic will still work fine.
650 */
651 if (smibest) {
652 set_apic_timer(200000);
653 smitest();
654 }
655
984263bc
MD
656 /*
657 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
658 * and running the target CPU. OR this INIT IPI might be latched (P5
659 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
660 * ignored.
bb467734
MD
661 *
662 * see apic/apicreg.h for icr bit definitions.
663 *
664 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
984263bc
MD
665 */
666
bb467734
MD
667 /*
668 * Setup the address for the target AP. We can setup
669 * icr_hi once and then just trigger operations with
670 * icr_lo.
671 */
cb7d6921 672 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
984263bc 673 icr_hi |= (physical_cpu << 24);
cb7d6921
SZ
674 icr_lo = lapic->icr_lo & 0xfff00000;
675 lapic->icr_hi = icr_hi;
984263bc 676
bb467734
MD
677 /*
678 * Do an INIT IPI: assert RESET
679 *
680 * Use edge triggered mode to assert INIT
681 */
cb7d6921
SZ
682 lapic->icr_lo = icr_lo | 0x0000c500;
683 while (lapic->icr_lo & APIC_DELSTAT_MASK)
984263bc
MD
684 /* spin */ ;
685
bb467734
MD
686 /*
687 * The spec calls for a 10ms delay but we may have to use a
688 * MUCH lower delay to avoid bricking an AP due to a fast SMI
689 * interrupt. We have other loops here too and dividing by 2
690 * doesn't seem to be enough even after subtracting 350us,
691 * so we divide by 4.
692 *
693 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
694 * interrupt was detected we use the full 10ms.
695 */
696 if (smibest == 0)
697 u_sleep(10000);
698 else if (smibest < 150 * 4 + 350)
699 u_sleep(150);
700 else if ((smibest - 350) / 4 < 10000)
701 u_sleep((smibest - 350) / 4);
702 else
703 u_sleep(10000);
984263bc 704
bb467734
MD
705 /*
706 * Do an INIT IPI: deassert RESET
707 *
708 * Use level triggered mode to deassert. It is unclear
709 * why we need to do this.
710 */
cb7d6921
SZ
711 lapic->icr_lo = icr_lo | 0x00008500;
712 while (lapic->icr_lo & APIC_DELSTAT_MASK)
984263bc 713 /* spin */ ;
bb467734 714 u_sleep(150); /* wait 150us */
984263bc
MD
715
716 /*
bb467734 717 * Next we do a STARTUP IPI: the previous INIT IPI might still be
984263bc
MD
718 * latched, (P5 bug) this 1st STARTUP would then terminate
719 * immediately, and the previously started INIT IPI would continue. OR
720 * the previous INIT IPI has already run. and this STARTUP IPI will
721 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
722 * will run.
723 */
cb7d6921
SZ
724 lapic->icr_lo = icr_lo | 0x00000600 | vector;
725 while (lapic->icr_lo & APIC_DELSTAT_MASK)
984263bc
MD
726 /* spin */ ;
727 u_sleep(200); /* wait ~200uS */
728
729 /*
bb467734 730 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
984263bc
MD
731 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
732 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
733 * recognized after hardware RESET or INIT IPI.
734 */
cb7d6921
SZ
735 lapic->icr_lo = icr_lo | 0x00000600 | vector;
736 while (lapic->icr_lo & APIC_DELSTAT_MASK)
984263bc 737 /* spin */ ;
bb467734
MD
738
739 /* Resume normal operation */
740 cpu_enable_intr();
984263bc 741
8a8d5d85 742 /* wait for it to start, see ap_init() */
984263bc 743 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 744 while (read_apic_timer()) {
da23a592 745 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
984263bc 746 return 1; /* return SUCCESS */
8a8d5d85 747 }
bb467734 748
984263bc
MD
749 return 0; /* return FAILURE */
750}
751
bb467734
MD
752static
753int
754smitest(void)
755{
756 int64_t ltsc;
757 int64_t ntsc;
758 int64_t ldelta;
759 int64_t ndelta;
760 int count;
761
762 ldelta = 0;
763 ndelta = 0;
764 while (read_apic_timer()) {
765 ltsc = rdtsc();
766 for (count = 0; count < 100; ++count)
767 ntsc = rdtsc(); /* force loop to occur */
768 if (ldelta) {
769 ndelta = ntsc - ltsc;
770 if (ldelta > ndelta)
771 ldelta = ndelta;
772 if (ndelta > ldelta * 2)
773 break;
774 } else {
775 ldelta = ntsc - ltsc;
776 }
777 }
778 return(read_apic_timer());
779}
984263bc
MD
780
781/*
0f7a3396 782 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 783 *
0f7a3396
MD
784 * If for some reason we were unable to start all cpus we cannot safely
785 * use broadcast IPIs.
984263bc 786 */
7d4d6fdb
MD
787
788static cpumask_t smp_invltlb_req;
b4b1a37a 789#define SMP_INVLTLB_DEBUG
7d4d6fdb 790
984263bc
MD
791void
792smp_invltlb(void)
793{
97359a5b 794#ifdef SMP
7d4d6fdb 795 struct mdglobaldata *md = mdcpu;
2d910aaf
MD
796#ifdef SMP_INVLTLB_DEBUG
797 long count = 0;
798 long xcount = 0;
799#endif
4117f2fd 800
7d4d6fdb
MD
801 crit_enter_gd(&md->mi);
802 md->gd_invltlb_ret = 0;
803 ++md->mi.gd_cnt.v_smpinvltlb;
da23a592 804 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2d910aaf
MD
805#ifdef SMP_INVLTLB_DEBUG
806again:
807#endif
0f7a3396 808 if (smp_startup_mask == smp_active_mask) {
984263bc 809 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396 810 } else {
7d4d6fdb
MD
811 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
812 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
0f7a3396 813 }
2d910aaf
MD
814
815#ifdef SMP_INVLTLB_DEBUG
816 if (xcount)
817 kprintf("smp_invltlb: ipi sent\n");
818#endif
7d4d6fdb
MD
819 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
820 (smp_active_mask & ~md->mi.gd_cpumask)) {
821 cpu_mfence();
822 cpu_pause();
2d910aaf
MD
823#ifdef SMP_INVLTLB_DEBUG
824 /* DEBUGGING */
825 if (++count == 400000000) {
826 print_backtrace(-1);
827 kprintf("smp_invltlb: endless loop %08lx %08lx, "
828 "rflags %016lx retry",
829 (long)md->gd_invltlb_ret,
830 (long)smp_invltlb_req,
831 (long)read_eflags());
832 __asm __volatile ("sti");
833 ++xcount;
834 if (xcount > 2)
835 lwkt_process_ipiq();
836 if (xcount > 3) {
da23a592
MD
837 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
838 ~md->mi.gd_cpumask &
839 smp_active_mask);
2d910aaf
MD
840 globaldata_t xgd;
841 kprintf("bcpu %d\n", bcpu);
842 xgd = globaldata_find(bcpu);
843 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
844 }
845 if (xcount > 5)
846 panic("giving up");
847 count = 0;
848 goto again;
849 }
850#endif
7d4d6fdb 851 }
da23a592 852 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
7d4d6fdb 853 crit_exit_gd(&md->mi);
4117f2fd 854#endif
984263bc
MD
855}
856
7d4d6fdb
MD
857#ifdef SMP
858
859/*
860 * Called from Xinvltlb assembly with interrupts disabled. We didn't
861 * bother to bump the critical section count or nested interrupt count
862 * so only do very low level operations here.
863 */
864void
865smp_invltlb_intr(void)
866{
867 struct mdglobaldata *md = mdcpu;
868 struct mdglobaldata *omd;
869 cpumask_t mask;
870 int cpu;
871
872 mask = smp_invltlb_req;
873 cpu_mfence();
874 cpu_invltlb();
875 while (mask) {
da23a592
MD
876 cpu = BSFCPUMASK(mask);
877 mask &= ~CPUMASK(cpu);
7d4d6fdb 878 omd = (struct mdglobaldata *)globaldata_find(cpu);
da23a592 879 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
7d4d6fdb
MD
880 }
881}
882
883#endif
884
984263bc
MD
885/*
886 * When called the executing CPU will send an IPI to all other CPUs
887 * requesting that they halt execution.
888 *
889 * Usually (but not necessarily) called with 'other_cpus' as its arg.
890 *
891 * - Signals all CPUs in map to stop.
892 * - Waits for each to stop.
893 *
894 * Returns:
895 * -1: error
896 * 0: NA
897 * 1: ok
898 *
899 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
900 * from executing at same time.
901 */
902int
da23a592 903stop_cpus(cpumask_t map)
984263bc 904{
0f7a3396 905 map &= smp_active_mask;
984263bc
MD
906
907 /* send the Xcpustop IPI to all CPUs in map */
908 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
909
910 while ((stopped_cpus & map) != map)
911 /* spin */ ;
912
913 return 1;
914}
915
916
917/*
918 * Called by a CPU to restart stopped CPUs.
919 *
920 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
921 *
922 * - Signals all CPUs in map to restart.
923 * - Waits for each to restart.
924 *
925 * Returns:
926 * -1: error
927 * 0: NA
928 * 1: ok
929 */
930int
da23a592 931restart_cpus(cpumask_t map)
984263bc 932{
0f7a3396
MD
933 /* signal other cpus to restart */
934 started_cpus = map & smp_active_mask;
984263bc
MD
935
936 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
937 /* spin */ ;
938
939 return 1;
940}
941
984263bc 942/*
8a8d5d85
MD
943 * This is called once the mpboot code has gotten us properly relocated
944 * and the MMU turned on, etc. ap_init() is actually the idle thread,
945 * and when it returns the scheduler will call the real cpu_idle() main
946 * loop for the idlethread. Interrupts are disabled on entry and should
947 * remain disabled at return.
984263bc 948 */
984263bc 949void
8a8d5d85 950ap_init(void)
984263bc
MD
951{
952 u_int apic_id;
953
8a8d5d85 954 /*
0f7a3396
MD
955 * Adjust smp_startup_mask to signal the BSP that we have started
956 * up successfully. Note that we do not yet hold the BGL. The BSP
957 * is waiting for our signal.
958 *
959 * We can't set our bit in smp_active_mask yet because we are holding
960 * interrupts physically disabled and remote cpus could deadlock
961 * trying to send us an IPI.
8a8d5d85 962 */
da23a592 963 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
35238fa5 964 cpu_mfence();
8a8d5d85
MD
965
966 /*
52596b13
SZ
967 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
968 * non-zero, then get the MP lock.
41a01a4d
MD
969 *
970 * Note: We are in a critical section.
971 *
41a01a4d
MD
972 * Note: we are the idle thread, we can only spin.
973 *
35238fa5 974 * Note: The load fence is memory volatile and prevents the compiler
52596b13 975 * from improperly caching mp_finish_lapic, and the cpu from improperly
35238fa5 976 * caching it.
8a8d5d85 977 */
52596b13 978 while (mp_finish_lapic == 0)
b5d16701
MD
979 cpu_lfence();
980 while (try_mplock() == 0)
981 ;
8a8d5d85 982
374133e3 983 if (cpu_feature & CPUID_TSC) {
b5d16701
MD
984 /*
985 * The BSP is constantly updating tsc0_offset, figure out
986 * the relative difference to synchronize ktrdump.
987 */
988 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
374133e3
MD
989 }
990
984263bc
MD
991 /* BSP may have changed PTD while we're waiting for the lock */
992 cpu_invltlb();
993
984263bc
MD
994#if defined(I586_CPU) && !defined(NO_F00F_HACK)
995 lidt(&r_idt);
996#endif
997
998 /* Build our map of 'other' CPUs. */
da23a592 999 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
984263bc 1000
984263bc 1001 /* A quick check from sanity claus */
cb7d6921 1002 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
8a8d5d85 1003 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
1004 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1005 kprintf("SMP: apic_id = %d\n", apic_id);
1006 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
1007 panic("cpuid mismatch! boom!!");
1008 }
1009
b52c8db0 1010 /* Initialize AP's local APIC for irq's */
5ddeabb9 1011 lapic_init(FALSE);
984263bc 1012
52596b13
SZ
1013 /* LAPIC initialization is done */
1014 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1015 cpu_mfence();
1016
1017 /* Let BSP move onto the next initialization stage */
1018 rel_mplock();
1019
1020 /*
1021 * Interlock for finalization. Wait until mp_finish is non-zero,
1022 * then get the MP lock.
1023 *
1024 * Note: We are in a critical section.
1025 *
1026 * Note: we are the idle thread, we can only spin.
1027 *
1028 * Note: The load fence is memory volatile and prevents the compiler
1029 * from improperly caching mp_finish, and the cpu from improperly
1030 * caching it.
1031 */
1032 while (mp_finish == 0)
1033 cpu_lfence();
1034 while (try_mplock() == 0)
1035 ;
1036
1037 /* BSP may have changed PTD while we're waiting for the lock */
1038 cpu_invltlb();
1039
984263bc
MD
1040 /* Set memory range attributes for this CPU to match the BSP */
1041 mem_range_AP_init();
1042
8a8d5d85 1043 /*
4c9f5a7f
MD
1044 * Once we go active we must process any IPIQ messages that may
1045 * have been queued, because no actual IPI will occur until we
1046 * set our bit in the smp_active_mask. If we don't the IPI
1047 * message interlock could be left set which would also prevent
1048 * further IPIs.
1049 *
8a8d5d85
MD
1050 * The idle loop doesn't expect the BGL to be held and while
1051 * lwkt_switch() normally cleans things up this is a special case
1052 * because we returning almost directly into the idle loop.
41a01a4d
MD
1053 *
1054 * The idle thread is never placed on the runq, make sure
4c9f5a7f 1055 * nothing we've done put it there.
8a8d5d85 1056 */
b5d16701 1057 KKASSERT(get_mplock_count(curthread) == 1);
da23a592 1058 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
d19f6edf
MD
1059
1060 /*
1061 * Enable interrupts here. idle_restore will also do it, but
1062 * doing it here lets us clean up any strays that got posted to
1063 * the CPU during the AP boot while we are still in a critical
1064 * section.
1065 */
1066 __asm __volatile("sti; pause; pause"::);
c263294b 1067 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
d19f6edf 1068
4a19580d 1069 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 1070 lwkt_process_ipiq();
d19f6edf
MD
1071
1072 /*
1073 * Releasing the mp lock lets the BSP finish up the SMP init
1074 */
96728c05 1075 rel_mplock();
41a01a4d 1076 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
1077}
1078
41a01a4d
MD
1079/*
1080 * Get SMP fully working before we start initializing devices.
1081 */
1082static
1083void
1084ap_finish(void)
1085{
1086 mp_finish = 1;
1087 if (bootverbose)
26be20a0 1088 kprintf("Finish MP startup\n");
41a01a4d 1089 rel_mplock();
52596b13 1090 while (smp_active_mask != smp_startup_mask)
35238fa5 1091 cpu_lfence();
4da43e1f 1092 while (try_mplock() == 0)
41a01a4d
MD
1093 ;
1094 if (bootverbose)
26be20a0 1095 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
1096}
1097
ba39e2e0 1098SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 1099
96728c05
MD
1100void
1101cpu_send_ipiq(int dcpu)
1102{
da23a592 1103 if (CPUMASK(dcpu) & smp_active_mask)
41a01a4d 1104 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 1105}
41a01a4d
MD
1106
1107#if 0 /* single_apic_ipi_passive() not working yet */
1108/*
1109 * Returns 0 on failure, 1 on success
1110 */
1111int
1112cpu_send_ipiq_passive(int dcpu)
1113{
1114 int r = 0;
da23a592 1115 if (CPUMASK(dcpu) & smp_active_mask) {
41a01a4d
MD
1116 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1117 APIC_DELMODE_FIXED);
1118 }
1119 return(r);
1120}
1121#endif