jme: Don't immediately recycle the TX descriptor even if it is owned by us.
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
CommitLineData
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1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
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28 */
29
9de40864 30#include "opt_polling.h"
93bfe1b8 31#include "opt_jme.h"
9de40864 32
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33#include <sys/param.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/interrupt.h>
38#include <sys/malloc.h>
39#include <sys/proc.h>
40#include <sys/rman.h>
41#include <sys/serialize.h>
31f0d5a2 42#include <sys/serialize2.h>
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43#include <sys/socket.h>
44#include <sys/sockio.h>
45#include <sys/sysctl.h>
46
47#include <net/ethernet.h>
48#include <net/if.h>
49#include <net/bpf.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/ifq_var.h>
24dd1705 54#include <net/toeplitz.h>
a6acc6e2 55#include <net/toeplitz2.h>
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56#include <net/vlan/if_vlan_var.h>
57#include <net/vlan/if_vlan_ether.h>
58
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59#include <netinet/in.h>
60
76fbb0b9 61#include <dev/netif/mii_layer/miivar.h>
dbe37f03 62#include <dev/netif/mii_layer/jmphyreg.h>
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63
64#include <bus/pci/pcireg.h>
65#include <bus/pci/pcivar.h>
66#include <bus/pci/pcidevs.h>
67
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68#include <dev/netif/jme/if_jmereg.h>
69#include <dev/netif/jme/if_jmevar.h>
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70
71#include "miibus_if.h"
72
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73#define JME_TX_SERIALIZE 1
74#define JME_RX_SERIALIZE 2
75
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76#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
77
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78#ifdef JME_RSS_DEBUG
79#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
80do { \
66f75939 81 if ((sc)->jme_rss_debug >= (lvl)) \
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82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
83} while (0)
84#else /* !JME_RSS_DEBUG */
85#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86#endif /* JME_RSS_DEBUG */
87
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88static int jme_probe(device_t);
89static int jme_attach(device_t);
90static int jme_detach(device_t);
91static int jme_shutdown(device_t);
92static int jme_suspend(device_t);
93static int jme_resume(device_t);
94
95static int jme_miibus_readreg(device_t, int, int);
96static int jme_miibus_writereg(device_t, int, int, int);
97static void jme_miibus_statchg(device_t);
98
99static void jme_init(void *);
100static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101static void jme_start(struct ifnet *);
102static void jme_watchdog(struct ifnet *);
103static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104static int jme_mediachange(struct ifnet *);
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105#ifdef DEVICE_POLLING
106static void jme_poll(struct ifnet *, enum poll_cmd, int);
107#endif
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108static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
111#ifdef INVARIANTS
112static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
113 boolean_t);
114#endif
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115
116static void jme_intr(void *);
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117static void jme_msix_tx(void *);
118static void jme_msix_rx(void *);
76fbb0b9 119static void jme_txeof(struct jme_softc *);
dea2452a 120static void jme_rxeof(struct jme_rxdata *, int);
4447c752 121static void jme_rx_intr(struct jme_softc *, uint32_t);
76fbb0b9 122
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123static int jme_msix_setup(device_t);
124static void jme_msix_teardown(device_t, int);
125static int jme_intr_setup(device_t);
126static void jme_intr_teardown(device_t);
127static void jme_msix_try_alloc(device_t);
128static void jme_msix_free(device_t);
129static int jme_intr_alloc(device_t);
130static void jme_intr_free(device_t);
76fbb0b9 131static int jme_dma_alloc(struct jme_softc *);
0b3414d9 132static void jme_dma_free(struct jme_softc *);
dea2452a 133static int jme_init_rx_ring(struct jme_rxdata *);
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134static void jme_init_tx_ring(struct jme_softc *);
135static void jme_init_ssb(struct jme_softc *);
dea2452a 136static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
76fbb0b9 137static int jme_encap(struct jme_softc *, struct mbuf **);
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138static void jme_rxpkt(struct jme_rxdata *);
139static int jme_rxring_dma_alloc(struct jme_rxdata *);
140static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
064b75ed 141static int jme_rxbuf_dma_filter(void *, bus_addr_t);
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142
143static void jme_tick(void *);
144static void jme_stop(struct jme_softc *);
145static void jme_reset(struct jme_softc *);
58880b0d 146static void jme_set_msinum(struct jme_softc *);
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147static void jme_set_vlan(struct jme_softc *);
148static void jme_set_filter(struct jme_softc *);
149static void jme_stop_tx(struct jme_softc *);
150static void jme_stop_rx(struct jme_softc *);
151static void jme_mac_config(struct jme_softc *);
152static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
155#ifdef notyet
156static void jme_setwol(struct jme_softc *);
157static void jme_setlinkspeed(struct jme_softc *);
158#endif
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159static void jme_set_tx_coal(struct jme_softc *);
160static void jme_set_rx_coal(struct jme_softc *);
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161static void jme_enable_rss(struct jme_softc *);
162static void jme_disable_rss(struct jme_softc *);
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163
164static void jme_sysctl_node(struct jme_softc *);
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165static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
166static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
167static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
168static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
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169
170/*
171 * Devices supported by this driver.
172 */
173static const struct jme_dev {
174 uint16_t jme_vendorid;
175 uint16_t jme_deviceid;
3a5f3f36 176 uint32_t jme_caps;
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177 const char *jme_name;
178} jme_devs[] = {
44e8c66c 179 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
3a5f3f36 180 JME_CAP_JUMBO,
76fbb0b9 181 "JMicron Inc, JMC250 Gigabit Ethernet" },
44e8c66c 182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
3a5f3f36 183 JME_CAP_FASTETH,
76fbb0b9 184 "JMicron Inc, JMC260 Fast Ethernet" },
3a5f3f36 185 { 0, 0, 0, NULL }
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186};
187
188static device_method_t jme_methods[] = {
189 /* Device interface. */
190 DEVMETHOD(device_probe, jme_probe),
191 DEVMETHOD(device_attach, jme_attach),
192 DEVMETHOD(device_detach, jme_detach),
193 DEVMETHOD(device_shutdown, jme_shutdown),
194 DEVMETHOD(device_suspend, jme_suspend),
195 DEVMETHOD(device_resume, jme_resume),
196
197 /* Bus interface. */
198 DEVMETHOD(bus_print_child, bus_generic_print_child),
199 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
200
201 /* MII interface. */
202 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
203 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
204 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
205
206 { NULL, NULL }
207};
208
209static driver_t jme_driver = {
210 "jme",
211 jme_methods,
212 sizeof(struct jme_softc)
213};
214
215static devclass_t jme_devclass;
216
217DECLARE_DUMMY_MODULE(if_jme);
218MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
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219DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
220DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
76fbb0b9 221
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222static const struct {
223 uint32_t jme_coal;
224 uint32_t jme_comp;
58880b0d 225 uint32_t jme_empty;
4447c752 226} jme_rx_status[JME_NRXRING_MAX] = {
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227 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
228 INTR_RXQ0_DESC_EMPTY },
229 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
230 INTR_RXQ1_DESC_EMPTY },
231 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
232 INTR_RXQ2_DESC_EMPTY },
233 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
234 INTR_RXQ3_DESC_EMPTY }
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235};
236
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237static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
238static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
6afef6ab 239static int jme_rx_ring_count = 0;
3eba890a 240static int jme_msi_enable = 1;
58880b0d 241static int jme_msix_enable = 1;
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242
243TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
244TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
413d06bb 245TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
3eba890a 246TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
58880b0d 247TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
83b03786 248
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249static __inline void
250jme_setup_rxdesc(struct jme_rxdesc *rxd)
251{
252 struct jme_desc *desc;
253
254 desc = rxd->rx_desc;
255 desc->buflen = htole32(MCLBYTES);
256 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
257 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
258 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
259}
260
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261/*
262 * Read a PHY register on the MII of the JMC250.
263 */
264static int
265jme_miibus_readreg(device_t dev, int phy, int reg)
266{
267 struct jme_softc *sc = device_get_softc(dev);
268 uint32_t val;
269 int i;
270
271 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 272 if (sc->jme_caps & JME_CAP_FPGA) {
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273 if (phy == 0)
274 return (0);
275 } else {
276 if (sc->jme_phyaddr != phy)
277 return (0);
278 }
279
280 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
281 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
282
283 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
284 DELAY(1);
285 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
286 break;
287 }
288 if (i == 0) {
289 device_printf(sc->jme_dev, "phy read timeout: "
290 "phy %d, reg %d\n", phy, reg);
291 return (0);
292 }
293
294 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
295}
296
297/*
298 * Write a PHY register on the MII of the JMC250.
299 */
300static int
301jme_miibus_writereg(device_t dev, int phy, int reg, int val)
302{
303 struct jme_softc *sc = device_get_softc(dev);
304 int i;
305
306 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 307 if (sc->jme_caps & JME_CAP_FPGA) {
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308 if (phy == 0)
309 return (0);
310 } else {
311 if (sc->jme_phyaddr != phy)
312 return (0);
313 }
314
315 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
316 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
317 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
318
319 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
320 DELAY(1);
321 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
322 break;
323 }
324 if (i == 0) {
325 device_printf(sc->jme_dev, "phy write timeout: "
326 "phy %d, reg %d\n", phy, reg);
327 }
328
329 return (0);
330}
331
332/*
333 * Callback from MII layer when media changes.
334 */
335static void
336jme_miibus_statchg(device_t dev)
337{
338 struct jme_softc *sc = device_get_softc(dev);
339 struct ifnet *ifp = &sc->arpcom.ac_if;
340 struct mii_data *mii;
341 struct jme_txdesc *txd;
342 bus_addr_t paddr;
4447c752 343 int i, r;
76fbb0b9 344
31f0d5a2 345 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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346
347 if ((ifp->if_flags & IFF_RUNNING) == 0)
348 return;
349
350 mii = device_get_softc(sc->jme_miibus);
351
352 sc->jme_flags &= ~JME_FLAG_LINK;
353 if ((mii->mii_media_status & IFM_AVALID) != 0) {
354 switch (IFM_SUBTYPE(mii->mii_media_active)) {
355 case IFM_10_T:
356 case IFM_100_TX:
357 sc->jme_flags |= JME_FLAG_LINK;
358 break;
359 case IFM_1000_T:
ec7e787b 360 if (sc->jme_caps & JME_CAP_FASTETH)
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361 break;
362 sc->jme_flags |= JME_FLAG_LINK;
363 break;
364 default:
365 break;
366 }
367 }
368
369 /*
370 * Disabling Rx/Tx MACs have a side-effect of resetting
371 * JME_TXNDA/JME_RXNDA register to the first address of
372 * Tx/Rx descriptor address. So driver should reset its
373 * internal procucer/consumer pointer and reclaim any
374 * allocated resources. Note, just saving the value of
375 * JME_TXNDA and JME_RXNDA registers before stopping MAC
376 * and restoring JME_TXNDA/JME_RXNDA register is not
377 * sufficient to make sure correct MAC state because
378 * stopping MAC operation can take a while and hardware
379 * might have updated JME_TXNDA/JME_RXNDA registers
380 * during the stop operation.
381 */
382
383 /* Disable interrupts */
384 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
385
386 /* Stop driver */
387 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
388 ifp->if_timer = 0;
389 callout_stop(&sc->jme_tick_ch);
390
391 /* Stop receiver/transmitter. */
392 jme_stop_rx(sc);
393 jme_stop_tx(sc);
394
7b040092 395 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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396 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
397
dea2452a 398 jme_rxeof(rdata, -1);
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399 if (rdata->jme_rxhead != NULL)
400 m_freem(rdata->jme_rxhead);
dea2452a 401 JME_RXCHAIN_RESET(rdata);
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402
403 /*
404 * Reuse configured Rx descriptors and reset
405 * procuder/consumer index.
406 */
407 rdata->jme_rx_cons = 0;
408 }
6afef6ab 409 if (JME_ENABLE_HWRSS(sc))
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410 jme_enable_rss(sc);
411 else
412 jme_disable_rss(sc);
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413
414 jme_txeof(sc);
415 if (sc->jme_cdata.jme_tx_cnt != 0) {
416 /* Remove queued packets for transmit. */
b020bb10 417 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
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418 txd = &sc->jme_cdata.jme_txdesc[i];
419 if (txd->tx_m != NULL) {
420 bus_dmamap_unload(
421 sc->jme_cdata.jme_tx_tag,
422 txd->tx_dmamap);
423 m_freem(txd->tx_m);
424 txd->tx_m = NULL;
425 txd->tx_ndesc = 0;
426 ifp->if_oerrors++;
427 }
428 }
429 }
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430 jme_init_tx_ring(sc);
431
432 /* Initialize shadow status block. */
433 jme_init_ssb(sc);
434
435 /* Program MAC with resolved speed/duplex/flow-control. */
436 if (sc->jme_flags & JME_FLAG_LINK) {
437 jme_mac_config(sc);
438
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439 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
440
441 /* Set Tx ring address to the hardware. */
7405bec3 442 paddr = sc->jme_cdata.jme_tx_ring_paddr;
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443 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
444 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
445
7b040092 446 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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447 CSR_WRITE_4(sc, JME_RXCSR,
448 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
449
450 /* Set Rx ring address to the hardware. */
451 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
452 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
453 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
454 }
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455
456 /* Restart receiver/transmitter. */
457 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
458 RXCSR_RXQ_START);
459 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
460 }
461
462 ifp->if_flags |= IFF_RUNNING;
463 ifp->if_flags &= ~IFF_OACTIVE;
464 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
465
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466#ifdef DEVICE_POLLING
467 if (!(ifp->if_flags & IFF_POLLING))
468#endif
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469 /* Reenable interrupts. */
470 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
471}
472
473/*
474 * Get the current interface media status.
475 */
476static void
477jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
478{
479 struct jme_softc *sc = ifp->if_softc;
480 struct mii_data *mii = device_get_softc(sc->jme_miibus);
481
31f0d5a2 482 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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483
484 mii_pollstat(mii);
485 ifmr->ifm_status = mii->mii_media_status;
486 ifmr->ifm_active = mii->mii_media_active;
487}
488
489/*
490 * Set hardware to newly-selected media.
491 */
492static int
493jme_mediachange(struct ifnet *ifp)
494{
495 struct jme_softc *sc = ifp->if_softc;
496 struct mii_data *mii = device_get_softc(sc->jme_miibus);
497 int error;
498
31f0d5a2 499 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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500
501 if (mii->mii_instance != 0) {
502 struct mii_softc *miisc;
503
504 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
505 mii_phy_reset(miisc);
506 }
507 error = mii_mediachg(mii);
508
509 return (error);
510}
511
512static int
513jme_probe(device_t dev)
514{
515 const struct jme_dev *sp;
516 uint16_t vid, did;
517
518 vid = pci_get_vendor(dev);
519 did = pci_get_device(dev);
520 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
521 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
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522 struct jme_softc *sc = device_get_softc(dev);
523
524 sc->jme_caps = sp->jme_caps;
76fbb0b9 525 device_set_desc(dev, sp->jme_name);
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526 return (0);
527 }
528 }
529 return (ENXIO);
530}
531
532static int
533jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
534{
535 uint32_t reg;
536 int i;
537
538 *val = 0;
539 for (i = JME_TIMEOUT; i > 0; i--) {
540 reg = CSR_READ_4(sc, JME_SMBCSR);
541 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
542 break;
543 DELAY(1);
544 }
545
546 if (i == 0) {
547 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
548 return (ETIMEDOUT);
549 }
550
551 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
552 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
553 for (i = JME_TIMEOUT; i > 0; i--) {
554 DELAY(1);
555 reg = CSR_READ_4(sc, JME_SMBINTF);
556 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
557 break;
558 }
559
560 if (i == 0) {
561 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
562 return (ETIMEDOUT);
563 }
564
565 reg = CSR_READ_4(sc, JME_SMBINTF);
566 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
567
568 return (0);
569}
570
571static int
572jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
573{
574 uint8_t fup, reg, val;
575 uint32_t offset;
576 int match;
577
578 offset = 0;
579 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
580 fup != JME_EEPROM_SIG0)
581 return (ENOENT);
582 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
583 fup != JME_EEPROM_SIG1)
584 return (ENOENT);
585 match = 0;
586 do {
587 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
588 break;
09927fe6
SZ
589 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
590 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
76fbb0b9
SZ
591 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
592 break;
593 if (reg >= JME_PAR0 &&
594 reg < JME_PAR0 + ETHER_ADDR_LEN) {
595 if (jme_eeprom_read_byte(sc, offset + 2,
596 &val) != 0)
597 break;
598 eaddr[reg - JME_PAR0] = val;
599 match++;
600 }
601 }
09927fe6
SZ
602 /* Check for the end of EEPROM descriptor. */
603 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
604 break;
76fbb0b9
SZ
605 /* Try next eeprom descriptor. */
606 offset += JME_EEPROM_DESC_BYTES;
607 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
608
609 if (match == ETHER_ADDR_LEN)
610 return (0);
611
612 return (ENOENT);
613}
614
615static void
616jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
617{
618 uint32_t par0, par1;
619
620 /* Read station address. */
621 par0 = CSR_READ_4(sc, JME_PAR0);
622 par1 = CSR_READ_4(sc, JME_PAR1);
623 par1 &= 0xFFFF;
624 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
625 device_printf(sc->jme_dev,
626 "generating fake ethernet address.\n");
627 par0 = karc4random();
628 /* Set OUI to JMicron. */
629 eaddr[0] = 0x00;
630 eaddr[1] = 0x1B;
631 eaddr[2] = 0x8C;
632 eaddr[3] = (par0 >> 16) & 0xff;
633 eaddr[4] = (par0 >> 8) & 0xff;
634 eaddr[5] = par0 & 0xff;
635 } else {
636 eaddr[0] = (par0 >> 0) & 0xFF;
637 eaddr[1] = (par0 >> 8) & 0xFF;
638 eaddr[2] = (par0 >> 16) & 0xFF;
639 eaddr[3] = (par0 >> 24) & 0xFF;
640 eaddr[4] = (par1 >> 0) & 0xFF;
641 eaddr[5] = (par1 >> 8) & 0xFF;
642 }
643}
644
645static int
646jme_attach(device_t dev)
647{
648 struct jme_softc *sc = device_get_softc(dev);
649 struct ifnet *ifp = &sc->arpcom.ac_if;
650 uint32_t reg;
b249905b
SZ
651 uint16_t did;
652 uint8_t pcie_ptr, rev;
7b040092 653 int error = 0, i, j, rx_desc_cnt;
76fbb0b9
SZ
654 uint8_t eaddr[ETHER_ADDR_LEN];
655
31f0d5a2
SZ
656 lwkt_serialize_init(&sc->jme_serialize);
657 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
658 for (i = 0; i < JME_NRXRING_MAX; ++i) {
659 lwkt_serialize_init(
660 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
661 }
662
7b040092 663 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
1cc217a9 664 jme_rx_desc_count);
7b040092
SZ
665 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
666 if (rx_desc_cnt > JME_NDESC_MAX)
667 rx_desc_cnt = JME_NDESC_MAX;
69325526 668
b020bb10 669 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
1cc217a9 670 jme_tx_desc_count);
b020bb10
SZ
671 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
672 JME_NDESC_ALIGN);
673 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
674 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
83b03786 675
9389fe19 676 /*
a317449e 677 * Calculate rx rings
9389fe19 678 */
7b040092 679 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
1cc217a9 680 jme_rx_ring_count);
7b040092
SZ
681 sc->jme_cdata.jme_rx_ring_cnt =
682 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
4447c752 683
31f0d5a2
SZ
684 i = 0;
685 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
29890f78
SZ
686
687 KKASSERT(i == JME_TX_SERIALIZE);
31f0d5a2 688 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
29890f78
SZ
689
690 KKASSERT(i == JME_RX_SERIALIZE);
7b040092 691 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
31f0d5a2
SZ
692 sc->jme_serialize_arr[i++] =
693 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
694 }
695 KKASSERT(i <= JME_NSERIALIZE);
696 sc->jme_serialize_cnt = i;
697
58880b0d 698 sc->jme_cdata.jme_sc = sc;
7b040092 699 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
58880b0d
SZ
700 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
701
702 rdata->jme_sc = sc;
703 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
704 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
705 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
706 rdata->jme_rx_idx = i;
7b040092 707 rdata->jme_rx_desc_cnt = rx_desc_cnt;
58880b0d
SZ
708 }
709
76fbb0b9 710 sc->jme_dev = dev;
b249905b
SZ
711 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
712
76fbb0b9
SZ
713 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
714
715 callout_init(&sc->jme_tick_ch);
716
717#ifndef BURN_BRIDGES
718 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
719 uint32_t irq, mem;
720
721 irq = pci_read_config(dev, PCIR_INTLINE, 4);
722 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
723
724 device_printf(dev, "chip is in D%d power mode "
725 "-- setting to D0\n", pci_get_powerstate(dev));
726
727 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
728
729 pci_write_config(dev, PCIR_INTLINE, irq, 4);
730 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
731 }
732#endif /* !BURN_BRIDGE */
733
734 /* Enable bus mastering */
735 pci_enable_busmaster(dev);
736
737 /*
738 * Allocate IO memory
739 *
740 * JMC250 supports both memory mapped and I/O register space
741 * access. Because I/O register access should use different
742 * BARs to access registers it's waste of time to use I/O
743 * register spce access. JMC250 uses 16K to map entire memory
744 * space.
745 */
746 sc->jme_mem_rid = JME_PCIR_BAR;
747 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
748 &sc->jme_mem_rid, RF_ACTIVE);
749 if (sc->jme_mem_res == NULL) {
750 device_printf(dev, "can't allocate IO memory\n");
751 return ENXIO;
752 }
753 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
754 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
755
756 /*
757 * Allocate IRQ
758 */
58880b0d
SZ
759 error = jme_intr_alloc(dev);
760 if (error)
76fbb0b9 761 goto fail;
76fbb0b9
SZ
762
763 /*
b249905b 764 * Extract revisions
76fbb0b9
SZ
765 */
766 reg = CSR_READ_4(sc, JME_CHIPMODE);
767 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
768 CHIPMODE_NOT_FPGA) {
ec7e787b 769 sc->jme_caps |= JME_CAP_FPGA;
76fbb0b9 770 if (bootverbose) {
b249905b 771 device_printf(dev, "FPGA revision: 0x%04x\n",
76fbb0b9
SZ
772 (reg & CHIPMODE_FPGA_REV_MASK) >>
773 CHIPMODE_FPGA_REV_SHIFT);
774 }
775 }
776
b249905b
SZ
777 /* NOTE: FM revision is put in the upper 4 bits */
778 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
779 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
780 if (bootverbose)
781 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
782
783 did = pci_get_device(dev);
784 switch (did) {
785 case PCI_PRODUCT_JMICRON_JMC250:
786 if (rev == JME_REV1_A2)
787 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
788 break;
789
790 case PCI_PRODUCT_JMICRON_JMC260:
791 if (rev == JME_REV2)
792 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
793 break;
794
795 default:
ed20d0e3 796 panic("unknown device id 0x%04x", did);
b249905b
SZ
797 }
798 if (rev >= JME_REV2) {
799 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
800 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
801 GHC_TXMAC_CLKSRC_1000;
802 }
803
76fbb0b9
SZ
804 /* Reset the ethernet controller. */
805 jme_reset(sc);
806
58880b0d
SZ
807 /* Map MSI/MSI-X vectors */
808 jme_set_msinum(sc);
809
76fbb0b9
SZ
810 /* Get station address. */
811 reg = CSR_READ_4(sc, JME_SMBCSR);
812 if (reg & SMBCSR_EEPROM_PRESENT)
813 error = jme_eeprom_macaddr(sc, eaddr);
814 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
815 if (error != 0 && (bootverbose)) {
816 device_printf(dev, "ethernet hardware address "
817 "not found in EEPROM.\n");
818 }
819 jme_reg_macaddr(sc, eaddr);
820 }
821
822 /*
823 * Save PHY address.
824 * Integrated JR0211 has fixed PHY address whereas FPGA version
825 * requires PHY probing to get correct PHY address.
826 */
ec7e787b 827 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
76fbb0b9
SZ
828 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
829 GPREG0_PHY_ADDR_MASK;
830 if (bootverbose) {
831 device_printf(dev, "PHY is at address %d.\n",
832 sc->jme_phyaddr);
833 }
834 } else {
835 sc->jme_phyaddr = 0;
836 }
837
838 /* Set max allowable DMA size. */
839 pcie_ptr = pci_get_pciecap_ptr(dev);
840 if (pcie_ptr != 0) {
841 uint16_t ctrl;
842
ec7e787b 843 sc->jme_caps |= JME_CAP_PCIE;
76fbb0b9
SZ
844 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
845 if (bootverbose) {
846 device_printf(dev, "Read request size : %d bytes.\n",
847 128 << ((ctrl >> 12) & 0x07));
848 device_printf(dev, "TLP payload size : %d bytes.\n",
849 128 << ((ctrl >> 5) & 0x07));
850 }
851 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
852 case PCIEM_DEVCTL_MAX_READRQ_128:
853 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
854 break;
855 case PCIEM_DEVCTL_MAX_READRQ_256:
856 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
857 break;
858 default:
859 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
860 break;
861 }
862 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
863 } else {
864 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
865 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
866 }
867
868#ifdef notyet
869 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
ec7e787b 870 sc->jme_caps |= JME_CAP_PMCAP;
76fbb0b9
SZ
871#endif
872
873 /*
874 * Create sysctl tree
875 */
876 jme_sysctl_node(sc);
877
878 /* Allocate DMA stuffs */
879 error = jme_dma_alloc(sc);
880 if (error)
881 goto fail;
882
883 ifp->if_softc = sc;
884 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
885 ifp->if_init = jme_init;
886 ifp->if_ioctl = jme_ioctl;
887 ifp->if_start = jme_start;
9de40864
SZ
888#ifdef DEVICE_POLLING
889 ifp->if_poll = jme_poll;
890#endif
76fbb0b9 891 ifp->if_watchdog = jme_watchdog;
31f0d5a2
SZ
892 ifp->if_serialize = jme_serialize;
893 ifp->if_deserialize = jme_deserialize;
894 ifp->if_tryserialize = jme_tryserialize;
895#ifdef INVARIANTS
896 ifp->if_serialize_assert = jme_serialize_assert;
897#endif
b020bb10
SZ
898 ifq_set_maxlen(&ifp->if_snd,
899 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
76fbb0b9
SZ
900 ifq_set_ready(&ifp->if_snd);
901
902 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
903 ifp->if_capabilities = IFCAP_HWCSUM |
904 IFCAP_VLAN_MTU |
905 IFCAP_VLAN_HWTAGGING;
7b040092 906 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
d585233c 907 ifp->if_capabilities |= IFCAP_RSS;
76fbb0b9
SZ
908 ifp->if_capenable = ifp->if_capabilities;
909
3d2aeb15
SZ
910 /*
911 * Disable TXCSUM by default to improve bulk data
912 * transmit performance (+20Mbps improvement).
913 */
914 ifp->if_capenable &= ~IFCAP_TXCSUM;
915
916 if (ifp->if_capenable & IFCAP_TXCSUM)
917 ifp->if_hwassist = JME_CSUM_FEATURES;
918
76fbb0b9
SZ
919 /* Set up MII bus. */
920 error = mii_phy_probe(dev, &sc->jme_miibus,
921 jme_mediachange, jme_mediastatus);
922 if (error) {
923 device_printf(dev, "no PHY found!\n");
924 goto fail;
925 }
926
927 /*
928 * Save PHYADDR for FPGA mode PHY.
929 */
ec7e787b 930 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ
931 struct mii_data *mii = device_get_softc(sc->jme_miibus);
932
933 if (mii->mii_instance != 0) {
934 struct mii_softc *miisc;
935
936 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
937 if (miisc->mii_phy != 0) {
938 sc->jme_phyaddr = miisc->mii_phy;
939 break;
940 }
941 }
942 if (sc->jme_phyaddr != 0) {
943 device_printf(sc->jme_dev,
944 "FPGA PHY is at %d\n", sc->jme_phyaddr);
945 /* vendor magic. */
dbe37f03
SZ
946 jme_miibus_writereg(dev, sc->jme_phyaddr,
947 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
948
ad22907f 949 /* XXX should we clear JME_WA_EXTFIFO */
76fbb0b9
SZ
950 }
951 }
952 }
953
954 ether_ifattach(ifp, eaddr, NULL);
955
956 /* Tell the upper layer(s) we support long frames. */
957 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
958
58880b0d 959 error = jme_intr_setup(dev);
76fbb0b9 960 if (error) {
76fbb0b9
SZ
961 ether_ifdetach(ifp);
962 goto fail;
963 }
964
76fbb0b9
SZ
965 return 0;
966fail:
967 jme_detach(dev);
968 return (error);
969}
970
971static int
972jme_detach(device_t dev)
973{
974 struct jme_softc *sc = device_get_softc(dev);
975
976 if (device_is_attached(dev)) {
977 struct ifnet *ifp = &sc->arpcom.ac_if;
978
31f0d5a2 979 ifnet_serialize_all(ifp);
76fbb0b9 980 jme_stop(sc);
58880b0d 981 jme_intr_teardown(dev);
31f0d5a2 982 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
983
984 ether_ifdetach(ifp);
985 }
986
987 if (sc->jme_sysctl_tree != NULL)
988 sysctl_ctx_free(&sc->jme_sysctl_ctx);
989
990 if (sc->jme_miibus != NULL)
991 device_delete_child(dev, sc->jme_miibus);
992 bus_generic_detach(dev);
993
58880b0d 994 jme_intr_free(dev);
76fbb0b9
SZ
995
996 if (sc->jme_mem_res != NULL) {
997 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
998 sc->jme_mem_res);
999 }
1000
0b3414d9 1001 jme_dma_free(sc);
76fbb0b9
SZ
1002
1003 return (0);
1004}
1005
1006static void
1007jme_sysctl_node(struct jme_softc *sc)
1008{
83b03786 1009 int coal_max;
760c056c 1010#ifdef JME_RSS_DEBUG
760c056c
SZ
1011 int r;
1012#endif
83b03786 1013
76fbb0b9
SZ
1014 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1015 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1016 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1017 device_get_nameunit(sc->jme_dev),
1018 CTLFLAG_RD, 0, "");
1019 if (sc->jme_sysctl_tree == NULL) {
1020 device_printf(sc->jme_dev, "can't add sysctl node\n");
1021 return;
1022 }
1023
1024 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1025 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1026 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1027 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
76fbb0b9
SZ
1028
1029 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1030 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1031 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1032 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
76fbb0b9
SZ
1033
1034 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1035 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1036 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1037 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
76fbb0b9
SZ
1038
1039 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1040 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1041 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1042 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
76fbb0b9 1043
83b03786
SZ
1044 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1045 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1046 "rx_desc_count", CTLFLAG_RD,
1047 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
83b03786
SZ
1048 0, "RX desc count");
1049 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1050 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
b020bb10
SZ
1051 "tx_desc_count", CTLFLAG_RD,
1052 &sc->jme_cdata.jme_tx_desc_cnt,
83b03786 1053 0, "TX desc count");
760c056c
SZ
1054 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1055 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1056 "rx_ring_count", CTLFLAG_RD,
1057 &sc->jme_cdata.jme_rx_ring_cnt,
760c056c 1058 0, "RX ring count");
760c056c
SZ
1059#ifdef JME_RSS_DEBUG
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
24dd1705 1062 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
760c056c 1063 0, "RSS debug level");
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1064 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1065 char rx_ring_pkt[32];
1066
760c056c 1067 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
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1068 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1069 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1070 rx_ring_pkt, CTLFLAG_RW,
1071 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
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1072 }
1073#endif
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1074
1075 /*
1076 * Set default coalesce valves
1077 */
76fbb0b9 1078 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
76fbb0b9 1079 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
76fbb0b9 1080 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
76fbb0b9 1081 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
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1082
1083 /*
1084 * Adjust coalesce valves, in case that the number of TX/RX
1085 * descs are set to small values by users.
1086 *
1087 * NOTE: coal_max will not be zero, since number of descs
1088 * must aligned by JME_NDESC_ALIGN (16 currently)
1089 */
b020bb10 1090 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
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1091 if (coal_max < sc->jme_tx_coal_pkt)
1092 sc->jme_tx_coal_pkt = coal_max;
1093
7b040092 1094 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
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1095 if (coal_max < sc->jme_rx_coal_pkt)
1096 sc->jme_rx_coal_pkt = coal_max;
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1097}
1098
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1099static int
1100jme_dma_alloc(struct jme_softc *sc)
1101{
1102 struct jme_txdesc *txd;
1128a202 1103 bus_dmamem_t dmem;
ff7f3632 1104 int error, i, asize;
76fbb0b9 1105
83b03786 1106 sc->jme_cdata.jme_txdesc =
b020bb10 1107 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
83b03786 1108 M_DEVBUF, M_WAITOK | M_ZERO);
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1109 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1110 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1111
1112 rdata->jme_rxdesc =
1113 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
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1114 M_DEVBUF, M_WAITOK | M_ZERO);
1115 }
83b03786 1116
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1117 /* Create parent ring tag. */
1118 error = bus_dma_tag_create(NULL,/* parent */
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1119 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1120 sc->jme_lowaddr, /* lowaddr */
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1121 BUS_SPACE_MAXADDR, /* highaddr */
1122 NULL, NULL, /* filter, filterarg */
1123 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1124 0, /* nsegments */
1125 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1126 0, /* flags */
1127 &sc->jme_cdata.jme_ring_tag);
1128 if (error) {
1129 device_printf(sc->jme_dev,
1130 "could not create parent ring DMA tag.\n");
1131 return error;
1132 }
1133
1134 /*
1135 * Create DMA stuffs for TX ring
1136 */
ff7f3632 1137 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
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1138 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1139 JME_TX_RING_ALIGN, 0,
0eb220ec 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1141 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9 1142 if (error) {
1128a202 1143 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
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1144 return error;
1145 }
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1146 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1147 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1148 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1149 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
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1150
1151 /*
1128a202 1152 * Create DMA stuffs for RX rings
76fbb0b9 1153 */
7b040092 1154 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1155 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
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1156 if (error)
1157 return error;
76fbb0b9 1158 }
76fbb0b9 1159
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1160 /* Create parent buffer tag. */
1161 error = bus_dma_tag_create(NULL,/* parent */
1162 1, 0, /* algnmnt, boundary */
b249905b 1163 sc->jme_lowaddr, /* lowaddr */
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1164 BUS_SPACE_MAXADDR, /* highaddr */
1165 NULL, NULL, /* filter, filterarg */
1166 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1167 0, /* nsegments */
1168 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1169 0, /* flags */
1170 &sc->jme_cdata.jme_buffer_tag);
1171 if (error) {
1172 device_printf(sc->jme_dev,
1173 "could not create parent buffer DMA tag.\n");
1174 return error;
1175 }
1176
1177 /*
1178 * Create DMA stuffs for shadow status block
1179 */
ff7f3632 1180 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1128a202 1181 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
0eb220ec 1182 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1183 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
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1184 if (error) {
1185 device_printf(sc->jme_dev,
1128a202 1186 "could not create shadow status block.\n");
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1187 return error;
1188 }
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1189 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1190 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1191 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1192 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
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1193
1194 /*
1195 * Create DMA stuffs for TX buffers
1196 */
1197
1198 /* Create tag for Tx buffers. */
1199 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1200 1, 0, /* algnmnt, boundary */
0eb220ec 1201 BUS_SPACE_MAXADDR, /* lowaddr */
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1202 BUS_SPACE_MAXADDR, /* highaddr */
1203 NULL, NULL, /* filter, filterarg */
9d424cee 1204 JME_JUMBO_FRAMELEN, /* maxsize */
76fbb0b9 1205 JME_MAXTXSEGS, /* nsegments */
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1206 JME_MAXSEGSIZE, /* maxsegsize */
1207 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
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1208 &sc->jme_cdata.jme_tx_tag);
1209 if (error != 0) {
1210 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1211 return error;
1212 }
1213
1214 /* Create DMA maps for Tx buffers. */
b020bb10 1215 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9 1216 txd = &sc->jme_cdata.jme_txdesc[i];
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1217 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1218 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1219 &txd->tx_dmamap);
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1220 if (error) {
1221 int j;
1222
1223 device_printf(sc->jme_dev,
1224 "could not create %dth Tx dmamap.\n", i);
1225
1226 for (j = 0; j < i; ++j) {
1227 txd = &sc->jme_cdata.jme_txdesc[j];
1228 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1229 txd->tx_dmamap);
1230 }
1231 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1232 sc->jme_cdata.jme_tx_tag = NULL;
1233 return error;
1234 }
1235 }
1236
1237 /*
1238 * Create DMA stuffs for RX buffers
1239 */
7b040092 1240 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1241 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752 1242 if (error)
76fbb0b9 1243 return error;
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1244 }
1245 return 0;
1246}
1247
1248static void
0b3414d9 1249jme_dma_free(struct jme_softc *sc)
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1250{
1251 struct jme_txdesc *txd;
1252 struct jme_rxdesc *rxd;
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1253 struct jme_rxdata *rdata;
1254 int i, r;
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1255
1256 /* Tx ring */
1257 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1258 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1259 sc->jme_cdata.jme_tx_ring_map);
1260 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
560616bf 1261 sc->jme_cdata.jme_tx_ring,
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1262 sc->jme_cdata.jme_tx_ring_map);
1263 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1264 sc->jme_cdata.jme_tx_ring_tag = NULL;
1265 }
1266
1267 /* Rx ring */
7b040092 1268 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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1269 rdata = &sc->jme_cdata.jme_rx_data[r];
1270 if (rdata->jme_rx_ring_tag != NULL) {
1271 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1272 rdata->jme_rx_ring_map);
1273 bus_dmamem_free(rdata->jme_rx_ring_tag,
1274 rdata->jme_rx_ring,
1275 rdata->jme_rx_ring_map);
1276 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1277 rdata->jme_rx_ring_tag = NULL;
1278 }
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1279 }
1280
1281 /* Tx buffers */
1282 if (sc->jme_cdata.jme_tx_tag != NULL) {
b020bb10 1283 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
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1284 txd = &sc->jme_cdata.jme_txdesc[i];
1285 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1286 txd->tx_dmamap);
1287 }
1288 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1289 sc->jme_cdata.jme_tx_tag = NULL;
1290 }
1291
1292 /* Rx buffers */
7b040092 1293 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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1294 rdata = &sc->jme_cdata.jme_rx_data[r];
1295 if (rdata->jme_rx_tag != NULL) {
7b040092 1296 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
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1297 rxd = &rdata->jme_rxdesc[i];
1298 bus_dmamap_destroy(rdata->jme_rx_tag,
1299 rxd->rx_dmamap);
1300 }
1301 bus_dmamap_destroy(rdata->jme_rx_tag,
1302 rdata->jme_rx_sparemap);
1303 bus_dma_tag_destroy(rdata->jme_rx_tag);
1304 rdata->jme_rx_tag = NULL;
76fbb0b9 1305 }
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1306 }
1307
1308 /* Shadow status block. */
1309 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1310 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1311 sc->jme_cdata.jme_ssb_map);
1312 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
560616bf 1313 sc->jme_cdata.jme_ssb_block,
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1314 sc->jme_cdata.jme_ssb_map);
1315 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1316 sc->jme_cdata.jme_ssb_tag = NULL;
1317 }
1318
1319 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1320 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1321 sc->jme_cdata.jme_buffer_tag = NULL;
1322 }
1323 if (sc->jme_cdata.jme_ring_tag != NULL) {
1324 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1325 sc->jme_cdata.jme_ring_tag = NULL;
1326 }
83b03786 1327
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1328 if (sc->jme_cdata.jme_txdesc != NULL) {
1329 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1330 sc->jme_cdata.jme_txdesc = NULL;
1331 }
7b040092 1332 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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1333 rdata = &sc->jme_cdata.jme_rx_data[r];
1334 if (rdata->jme_rxdesc != NULL) {
1335 kfree(rdata->jme_rxdesc, M_DEVBUF);
1336 rdata->jme_rxdesc = NULL;
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1337 }
1338 }
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1339}
1340
1341/*
1342 * Make sure the interface is stopped at reboot time.
1343 */
1344static int
1345jme_shutdown(device_t dev)
1346{
1347 return jme_suspend(dev);
1348}
1349
1350#ifdef notyet
1351/*
1352 * Unlike other ethernet controllers, JMC250 requires
1353 * explicit resetting link speed to 10/100Mbps as gigabit
1354 * link will cunsume more power than 375mA.
1355 * Note, we reset the link speed to 10/100Mbps with
1356 * auto-negotiation but we don't know whether that operation
1357 * would succeed or not as we have no control after powering
1358 * off. If the renegotiation fail WOL may not work. Running
1359 * at 1Gbps draws more power than 375mA at 3.3V which is
1360 * specified in PCI specification and that would result in
1361 * complete shutdowning power to ethernet controller.
1362 *
1363 * TODO
1364 * Save current negotiated media speed/duplex/flow-control
1365 * to softc and restore the same link again after resuming.
1366 * PHY handling such as power down/resetting to 100Mbps
1367 * may be better handled in suspend method in phy driver.
1368 */
1369static void
1370jme_setlinkspeed(struct jme_softc *sc)
1371{
1372 struct mii_data *mii;
1373 int aneg, i;
1374
1375 JME_LOCK_ASSERT(sc);
1376
1377 mii = device_get_softc(sc->jme_miibus);
1378 mii_pollstat(mii);
1379 aneg = 0;
1380 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1381 switch IFM_SUBTYPE(mii->mii_media_active) {
1382 case IFM_10_T:
1383 case IFM_100_TX:
1384 return;
1385 case IFM_1000_T:
1386 aneg++;
1387 default:
1388 break;
1389 }
1390 }
1391 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1392 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1393 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1394 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1395 BMCR_AUTOEN | BMCR_STARTNEG);
1396 DELAY(1000);
1397 if (aneg != 0) {
1398 /* Poll link state until jme(4) get a 10/100 link. */
1399 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1400 mii_pollstat(mii);
1401 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1402 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1403 case IFM_10_T:
1404 case IFM_100_TX:
1405 jme_mac_config(sc);
1406 return;
1407 default:
1408 break;
1409 }
1410 }
1411 JME_UNLOCK(sc);
1412 pause("jmelnk", hz);
1413 JME_LOCK(sc);
1414 }
1415 if (i == MII_ANEGTICKS_GIGE)
1416 device_printf(sc->jme_dev, "establishing link failed, "
1417 "WOL may not work!");
1418 }
1419 /*
1420 * No link, force MAC to have 100Mbps, full-duplex link.
1421 * This is the last resort and may/may not work.
1422 */
1423 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1424 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1425 jme_mac_config(sc);
1426}
1427
1428static void
1429jme_setwol(struct jme_softc *sc)
1430{
1431 struct ifnet *ifp = &sc->arpcom.ac_if;
1432 uint32_t gpr, pmcs;
1433 uint16_t pmstat;
1434 int pmc;
1435
1436 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1437 /* No PME capability, PHY power down. */
1438 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1439 MII_BMCR, BMCR_PDOWN);
1440 return;
1441 }
1442
1443 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1444 pmcs = CSR_READ_4(sc, JME_PMCS);
1445 pmcs &= ~PMCS_WOL_ENB_MASK;
1446 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1447 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1448 /* Enable PME message. */
1449 gpr |= GPREG0_PME_ENB;
1450 /* For gigabit controllers, reset link speed to 10/100. */
ec7e787b 1451 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
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1452 jme_setlinkspeed(sc);
1453 }
1454
1455 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1456 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1457
1458 /* Request PME. */
1459 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1460 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1461 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1462 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1463 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1464 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1465 /* No WOL, PHY power down. */
1466 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1467 MII_BMCR, BMCR_PDOWN);
1468 }
1469}
1470#endif
1471
1472static int
1473jme_suspend(device_t dev)
1474{
1475 struct jme_softc *sc = device_get_softc(dev);
1476 struct ifnet *ifp = &sc->arpcom.ac_if;
1477
31f0d5a2 1478 ifnet_serialize_all(ifp);
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1479 jme_stop(sc);
1480#ifdef notyet
1481 jme_setwol(sc);
1482#endif
31f0d5a2 1483 ifnet_deserialize_all(ifp);
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1484
1485 return (0);
1486}
1487
1488static int
1489jme_resume(device_t dev)
1490{
1491 struct jme_softc *sc = device_get_softc(dev);
1492 struct ifnet *ifp = &sc->arpcom.ac_if;
1493#ifdef notyet
1494 int pmc;
1495#endif
1496
31f0d5a2 1497 ifnet_serialize_all(ifp);
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1498
1499#ifdef notyet
1500 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1501 uint16_t pmstat;
1502
1503 pmstat = pci_read_config(sc->jme_dev,
1504 pmc + PCIR_POWER_STATUS, 2);
1505 /* Disable PME clear PME status. */
1506 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1507 pci_write_config(sc->jme_dev,
1508 pmc + PCIR_POWER_STATUS, pmstat, 2);
1509 }
1510#endif
1511
1512 if (ifp->if_flags & IFF_UP)
1513 jme_init(sc);
1514
31f0d5a2 1515 ifnet_deserialize_all(ifp);
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1516
1517 return (0);
1518}
1519
1520static int
1521jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1522{
1523 struct jme_txdesc *txd;
1524 struct jme_desc *desc;
1525 struct mbuf *m;
76fbb0b9 1526 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
b0ba1747 1527 int maxsegs, nsegs;
9b3ee148 1528 int error, i, prod, symbol_desc;
7228f061 1529 uint32_t cflags, flag64;
76fbb0b9
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1530
1531 M_ASSERTPKTHDR((*m_head));
1532
1533 prod = sc->jme_cdata.jme_tx_prod;
1534 txd = &sc->jme_cdata.jme_txdesc[prod];
1535
9b3ee148
SZ
1536 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1537 symbol_desc = 1;
1538 else
1539 symbol_desc = 0;
1540
b020bb10 1541 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
9b3ee148 1542 (JME_TXD_RSVD + symbol_desc);
76fbb0b9
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1543 if (maxsegs > JME_MAXTXSEGS)
1544 maxsegs = JME_MAXTXSEGS;
9b3ee148 1545 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
ed20d0e3 1546 ("not enough segments %d", maxsegs));
76fbb0b9 1547
b0ba1747
SZ
1548 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1549 txd->tx_dmamap, m_head,
1550 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1551 if (error)
ecc6de9e 1552 goto fail;
76fbb0b9 1553
4458ee95
SZ
1554 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1555 BUS_DMASYNC_PREWRITE);
1556
76fbb0b9
SZ
1557 m = *m_head;
1558 cflags = 0;
1559
1560 /* Configure checksum offload. */
1561 if (m->m_pkthdr.csum_flags & CSUM_IP)
1562 cflags |= JME_TD_IPCSUM;
1563 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1564 cflags |= JME_TD_TCPCSUM;
1565 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1566 cflags |= JME_TD_UDPCSUM;
1567
1568 /* Configure VLAN. */
1569 if (m->m_flags & M_VLANTAG) {
1570 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1571 cflags |= JME_TD_VLAN_TAG;
1572 }
1573
560616bf 1574 desc = &sc->jme_cdata.jme_tx_ring[prod];
76fbb0b9 1575 desc->flags = htole32(cflags);
76fbb0b9 1576 desc->addr_hi = htole32(m->m_pkthdr.len);
7228f061
SZ
1577 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1578 /*
1579 * Use 64bits TX desc chain format.
1580 *
1581 * The first TX desc of the chain, which is setup here,
1582 * is just a symbol TX desc carrying no payload.
1583 */
1584 flag64 = JME_TD_64BIT;
1585 desc->buflen = 0;
1586 desc->addr_lo = 0;
1587
1588 /* No effective TX desc is consumed */
1589 i = 0;
1590 } else {
1591 /*
1592 * Use 32bits TX desc chain format.
1593 *
1594 * The first TX desc of the chain, which is setup here,
1595 * is an effective TX desc carrying the first segment of
1596 * the mbuf chain.
1597 */
1598 flag64 = 0;
1599 desc->buflen = htole32(txsegs[0].ds_len);
1600 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1601
1602 /* One effective TX desc is consumed */
1603 i = 1;
1604 }
76fbb0b9 1605 sc->jme_cdata.jme_tx_cnt++;
9de40864 1606 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
022f915e 1607 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
b020bb10 1608 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
7228f061
SZ
1609
1610 txd->tx_ndesc = 1 - i;
b0ba1747 1611 for (; i < nsegs; i++) {
560616bf 1612 desc = &sc->jme_cdata.jme_tx_ring[prod];
76fbb0b9
SZ
1613 desc->buflen = htole32(txsegs[i].ds_len);
1614 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1615 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
a54bd021 1616 desc->flags = htole32(JME_TD_OWN | flag64);
76fbb0b9
SZ
1617
1618 sc->jme_cdata.jme_tx_cnt++;
1619 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
022f915e 1620 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
b020bb10 1621 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ
1622 }
1623
1624 /* Update producer index. */
1625 sc->jme_cdata.jme_tx_prod = prod;
1626 /*
1627 * Finally request interrupt and give the first descriptor
1628 * owenership to hardware.
1629 */
1630 desc = txd->tx_desc;
1631 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1632
1633 txd->tx_m = m;
b0ba1747 1634 txd->tx_ndesc += nsegs;
76fbb0b9 1635
ecc6de9e
SZ
1636 return 0;
1637fail:
1638 m_freem(*m_head);
1639 *m_head = NULL;
1640 return error;
76fbb0b9
SZ
1641}
1642
1643static void
1644jme_start(struct ifnet *ifp)
1645{
1646 struct jme_softc *sc = ifp->if_softc;
1647 struct mbuf *m_head;
1648 int enq = 0;
1649
31f0d5a2 1650 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1651
1652 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1653 ifq_purge(&ifp->if_snd);
1654 return;
1655 }
1656
1657 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1658 return;
1659
83b03786 1660 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
76fbb0b9
SZ
1661 jme_txeof(sc);
1662
1663 while (!ifq_is_empty(&ifp->if_snd)) {
1664 /*
1665 * Check number of available TX descs, always
1666 * leave JME_TXD_RSVD free TX descs.
1667 */
1668 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
b020bb10 1669 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
76fbb0b9
SZ
1670 ifp->if_flags |= IFF_OACTIVE;
1671 break;
1672 }
1673
1674 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1675 if (m_head == NULL)
1676 break;
1677
1678 /*
1679 * Pack the data into the transmit ring. If we
1680 * don't have room, set the OACTIVE flag and wait
1681 * for the NIC to drain the ring.
1682 */
1683 if (jme_encap(sc, &m_head)) {
ecc6de9e
SZ
1684 KKASSERT(m_head == NULL);
1685 ifp->if_oerrors++;
76fbb0b9
SZ
1686 ifp->if_flags |= IFF_OACTIVE;
1687 break;
1688 }
1689 enq++;
1690
1691 /*
1692 * If there's a BPF listener, bounce a copy of this frame
1693 * to him.
1694 */
1695 ETHER_BPF_MTAP(ifp, m_head);
1696 }
1697
1698 if (enq > 0) {
1699 /*
1700 * Reading TXCSR takes very long time under heavy load
1701 * so cache TXCSR value and writes the ORed value with
1702 * the kick command to the TXCSR. This saves one register
1703 * access cycle.
1704 */
1705 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1706 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1707 /* Set a timeout in case the chip goes out to lunch. */
1708 ifp->if_timer = JME_TX_TIMEOUT;
1709 }
1710}
1711
1712static void
1713jme_watchdog(struct ifnet *ifp)
1714{
1715 struct jme_softc *sc = ifp->if_softc;
1716
31f0d5a2 1717 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
1718
1719 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1720 if_printf(ifp, "watchdog timeout (missed link)\n");
1721 ifp->if_oerrors++;
1722 jme_init(sc);
1723 return;
1724 }
1725
1726 jme_txeof(sc);
1727 if (sc->jme_cdata.jme_tx_cnt == 0) {
1728 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1729 "-- recovering\n");
1730 if (!ifq_is_empty(&ifp->if_snd))
1731 if_devstart(ifp);
1732 return;
1733 }
1734
1735 if_printf(ifp, "watchdog timeout\n");
1736 ifp->if_oerrors++;
1737 jme_init(sc);
1738 if (!ifq_is_empty(&ifp->if_snd))
1739 if_devstart(ifp);
1740}
1741
1742static int
1743jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1744{
1745 struct jme_softc *sc = ifp->if_softc;
1746 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1747 struct ifreq *ifr = (struct ifreq *)data;
1748 int error = 0, mask;
1749
31f0d5a2 1750 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
1751
1752 switch (cmd) {
1753 case SIOCSIFMTU:
1754 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
3a5f3f36 1755 (!(sc->jme_caps & JME_CAP_JUMBO) &&
76fbb0b9
SZ
1756 ifr->ifr_mtu > JME_MAX_MTU)) {
1757 error = EINVAL;
1758 break;
1759 }
1760
1761 if (ifp->if_mtu != ifr->ifr_mtu) {
1762 /*
1763 * No special configuration is required when interface
1764 * MTU is changed but availability of Tx checksum
1765 * offload should be chcked against new MTU size as
1766 * FIFO size is just 2K.
1767 */
1768 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1769 ifp->if_capenable &= ~IFCAP_TXCSUM;
1770 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1771 }
1772 ifp->if_mtu = ifr->ifr_mtu;
1773 if (ifp->if_flags & IFF_RUNNING)
1774 jme_init(sc);
1775 }
1776 break;
1777
1778 case SIOCSIFFLAGS:
1779 if (ifp->if_flags & IFF_UP) {
1780 if (ifp->if_flags & IFF_RUNNING) {
1781 if ((ifp->if_flags ^ sc->jme_if_flags) &
1782 (IFF_PROMISC | IFF_ALLMULTI))
1783 jme_set_filter(sc);
1784 } else {
1785 jme_init(sc);
1786 }
1787 } else {
1788 if (ifp->if_flags & IFF_RUNNING)
1789 jme_stop(sc);
1790 }
1791 sc->jme_if_flags = ifp->if_flags;
1792 break;
1793
1794 case SIOCADDMULTI:
1795 case SIOCDELMULTI:
1796 if (ifp->if_flags & IFF_RUNNING)
1797 jme_set_filter(sc);
1798 break;
1799
1800 case SIOCSIFMEDIA:
1801 case SIOCGIFMEDIA:
1802 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1803 break;
1804
1805 case SIOCSIFCAP:
1806 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1807
1808 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
e4616e94
SZ
1809 ifp->if_capenable ^= IFCAP_TXCSUM;
1810 if (IFCAP_TXCSUM & ifp->if_capenable)
1811 ifp->if_hwassist |= JME_CSUM_FEATURES;
1812 else
1813 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
76fbb0b9 1814 }
e4616e94 1815 if (mask & IFCAP_RXCSUM) {
76fbb0b9
SZ
1816 uint32_t reg;
1817
1818 ifp->if_capenable ^= IFCAP_RXCSUM;
1819 reg = CSR_READ_4(sc, JME_RXMAC);
1820 reg &= ~RXMAC_CSUM_ENB;
1821 if (ifp->if_capenable & IFCAP_RXCSUM)
1822 reg |= RXMAC_CSUM_ENB;
1823 CSR_WRITE_4(sc, JME_RXMAC, reg);
1824 }
1825
e4616e94 1826 if (mask & IFCAP_VLAN_HWTAGGING) {
76fbb0b9
SZ
1827 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1828 jme_set_vlan(sc);
1829 }
e4616e94 1830
9f20b7b3 1831 if (mask & IFCAP_RSS)
d585233c 1832 ifp->if_capenable ^= IFCAP_RSS;
76fbb0b9
SZ
1833 break;
1834
1835 default:
1836 error = ether_ioctl(ifp, cmd, data);
1837 break;
1838 }
1839 return (error);
1840}
1841
1842static void
1843jme_mac_config(struct jme_softc *sc)
1844{
1845 struct mii_data *mii;
3b3da110
SZ
1846 uint32_t ghc, rxmac, txmac, txpause, gp1;
1847 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
76fbb0b9
SZ
1848
1849 mii = device_get_softc(sc->jme_miibus);
1850
1851 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1852 DELAY(10);
1853 CSR_WRITE_4(sc, JME_GHC, 0);
1854 ghc = 0;
1855 rxmac = CSR_READ_4(sc, JME_RXMAC);
1856 rxmac &= ~RXMAC_FC_ENB;
1857 txmac = CSR_READ_4(sc, JME_TXMAC);
1858 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1859 txpause = CSR_READ_4(sc, JME_TXPFC);
1860 txpause &= ~TXPFC_PAUSE_ENB;
1861 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1862 ghc |= GHC_FULL_DUPLEX;
1863 rxmac &= ~RXMAC_COLL_DET_ENB;
1864 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1865 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1866 TXMAC_FRAME_BURST);
1867#ifdef notyet
1868 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1869 txpause |= TXPFC_PAUSE_ENB;
1870 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1871 rxmac |= RXMAC_FC_ENB;
1872#endif
1873 /* Disable retry transmit timer/retry limit. */
1874 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1875 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1876 } else {
1877 rxmac |= RXMAC_COLL_DET_ENB;
1878 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1879 /* Enable retry transmit timer/retry limit. */
1880 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1881 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1882 }
1883
3b3da110
SZ
1884 /*
1885 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1886 */
1887 gp1 = CSR_READ_4(sc, JME_GPREG1);
1888 gp1 &= ~GPREG1_WA_HDX;
1889
1890 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1891 hdx = 1;
1892
76fbb0b9
SZ
1893 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1894 case IFM_10_T:
b249905b 1895 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
3b3da110
SZ
1896 if (hdx)
1897 gp1 |= GPREG1_WA_HDX;
76fbb0b9 1898 break;
dbe37f03 1899
76fbb0b9 1900 case IFM_100_TX:
b249905b 1901 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
3b3da110
SZ
1902 if (hdx)
1903 gp1 |= GPREG1_WA_HDX;
dbe37f03
SZ
1904
1905 /*
1906 * Use extended FIFO depth to workaround CRC errors
1907 * emitted by chips before JMC250B
1908 */
1909 phyconf = JMPHY_CONF_EXTFIFO;
76fbb0b9 1910 break;
dbe37f03 1911
76fbb0b9 1912 case IFM_1000_T:
ec7e787b 1913 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 1914 break;
dbe37f03 1915
b249905b 1916 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
3b3da110 1917 if (hdx)
76fbb0b9
SZ
1918 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1919 break;
dbe37f03 1920
76fbb0b9
SZ
1921 default:
1922 break;
1923 }
1924 CSR_WRITE_4(sc, JME_GHC, ghc);
1925 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1926 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1927 CSR_WRITE_4(sc, JME_TXPFC, txpause);
dbe37f03 1928
ad22907f 1929 if (sc->jme_workaround & JME_WA_EXTFIFO) {
dbe37f03
SZ
1930 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1931 JMPHY_CONF, phyconf);
1932 }
3b3da110
SZ
1933 if (sc->jme_workaround & JME_WA_HDX)
1934 CSR_WRITE_4(sc, JME_GPREG1, gp1);
76fbb0b9
SZ
1935}
1936
1937static void
1938jme_intr(void *xsc)
1939{
1940 struct jme_softc *sc = xsc;
1941 struct ifnet *ifp = &sc->arpcom.ac_if;
1942 uint32_t status;
4447c752 1943 int r;
76fbb0b9 1944
31f0d5a2 1945 ASSERT_SERIALIZED(&sc->jme_serialize);
76fbb0b9
SZ
1946
1947 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1948 if (status == 0 || status == 0xFFFFFFFF)
1949 return;
1950
1951 /* Disable interrupts. */
1952 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1953
1954 status = CSR_READ_4(sc, JME_INTR_STATUS);
1955 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1956 goto back;
1957
1958 /* Reset PCC counter/timer and Ack interrupts. */
1959 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
4447c752 1960
76fbb0b9
SZ
1961 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1962 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
4447c752 1963
7b040092 1964 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1965 if (status & jme_rx_status[r].jme_coal) {
1966 status |= jme_rx_status[r].jme_coal |
1967 jme_rx_status[r].jme_comp;
1968 }
1969 }
1970
76fbb0b9
SZ
1971 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1972
1973 if (ifp->if_flags & IFF_RUNNING) {
1974 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
4447c752 1975 jme_rx_intr(sc, status);
76fbb0b9
SZ
1976
1977 if (status & INTR_RXQ_DESC_EMPTY) {
1978 /*
1979 * Notify hardware availability of new Rx buffers.
1980 * Reading RXCSR takes very long time under heavy
1981 * load so cache RXCSR value and writes the ORed
1982 * value with the kick command to the RXCSR. This
1983 * saves one register access cycle.
1984 */
1985 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1986 RXCSR_RX_ENB | RXCSR_RXQ_START);
1987 }
1988
1989 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
31f0d5a2 1990 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1991 jme_txeof(sc);
1992 if (!ifq_is_empty(&ifp->if_snd))
1993 if_devstart(ifp);
31f0d5a2 1994 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1995 }
1996 }
1997back:
1998 /* Reenable interrupts. */
1999 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2000}
2001
2002static void
2003jme_txeof(struct jme_softc *sc)
2004{
2005 struct ifnet *ifp = &sc->arpcom.ac_if;
6960d7d2 2006 int cons;
76fbb0b9
SZ
2007
2008 cons = sc->jme_cdata.jme_tx_cons;
2009 if (cons == sc->jme_cdata.jme_tx_prod)
2010 return;
2011
76fbb0b9
SZ
2012 /*
2013 * Go through our Tx list and free mbufs for those
2014 * frames which have been transmitted.
2015 */
2016 while (cons != sc->jme_cdata.jme_tx_prod) {
6960d7d2
SZ
2017 struct jme_txdesc *txd, *next_txd;
2018 uint32_t status, next_status;
2019 int next_cons, nsegs;
2020
76fbb0b9
SZ
2021 txd = &sc->jme_cdata.jme_txdesc[cons];
2022 KASSERT(txd->tx_m != NULL,
ed20d0e3 2023 ("%s: freeing NULL mbuf!", __func__));
76fbb0b9
SZ
2024
2025 status = le32toh(txd->tx_desc->flags);
2026 if ((status & JME_TD_OWN) == JME_TD_OWN)
2027 break;
2028
6960d7d2
SZ
2029 /*
2030 * NOTE:
2031 * This chip will always update the TX descriptor's
2032 * buflen field and this updating always happens
2033 * after clearing the OWN bit, so even if the OWN
2034 * bit is cleared by the chip, we still don't sure
2035 * about whether the buflen field has been updated
2036 * by the chip or not. To avoid this race, we wait
2037 * for the next TX descriptor's OWN bit to be cleared
2038 * by the chip before reusing this TX descriptor.
2039 */
2040 next_cons = cons;
2041 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2042 sc->jme_cdata.jme_tx_desc_cnt);
2043 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2044 if (next_txd->tx_m == NULL)
2045 break;
2046 next_status = le32toh(next_txd->tx_desc->flags);
2047 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2048 break;
2049
76fbb0b9
SZ
2050 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2051 ifp->if_oerrors++;
2052 } else {
2053 ifp->if_opackets++;
2054 if (status & JME_TD_COLLISION) {
2055 ifp->if_collisions +=
2056 le32toh(txd->tx_desc->buflen) &
2057 JME_TD_BUF_LEN_MASK;
2058 }
2059 }
2060
2061 /*
2062 * Only the first descriptor of multi-descriptor
2063 * transmission is updated so driver have to skip entire
2064 * chained buffers for the transmiited frame. In other
2065 * words, JME_TD_OWN bit is valid only at the first
2066 * descriptor of a multi-descriptor transmission.
2067 */
2068 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
560616bf 2069 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
b020bb10 2070 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ
2071 }
2072
2073 /* Reclaim transferred mbufs. */
2074 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2075 m_freem(txd->tx_m);
2076 txd->tx_m = NULL;
2077 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2078 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
ed20d0e3 2079 ("%s: Active Tx desc counter was garbled", __func__));
76fbb0b9
SZ
2080 txd->tx_ndesc = 0;
2081 }
2082 sc->jme_cdata.jme_tx_cons = cons;
2083
6960d7d2 2084 if (sc->jme_cdata.jme_tx_cnt < JME_MAXTXSEGS + 1)
76fbb0b9
SZ
2085 ifp->if_timer = 0;
2086
2087 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
b020bb10 2088 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
76fbb0b9 2089 ifp->if_flags &= ~IFF_OACTIVE;
76fbb0b9
SZ
2090}
2091
2092static __inline void
dea2452a 2093jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
76fbb0b9
SZ
2094{
2095 int i;
2096
2097 for (i = 0; i < count; ++i) {
fd2a6d2c 2098 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
7b040092 2099 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
76fbb0b9
SZ
2100 }
2101}
2102
a6acc6e2
SZ
2103static __inline struct pktinfo *
2104jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2105{
2106 if (flags & JME_RD_IPV4)
2107 pi->pi_netisr = NETISR_IP;
2108 else if (flags & JME_RD_IPV6)
2109 pi->pi_netisr = NETISR_IPV6;
2110 else
2111 return NULL;
2112
2113 pi->pi_flags = 0;
2114 pi->pi_l3proto = IPPROTO_UNKNOWN;
2115
2116 if (flags & JME_RD_MORE_FRAG)
2117 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2118 else if (flags & JME_RD_TCP)
2119 pi->pi_l3proto = IPPROTO_TCP;
2120 else if (flags & JME_RD_UDP)
2121 pi->pi_l3proto = IPPROTO_UDP;
7345eb80
SZ
2122 else
2123 pi = NULL;
a6acc6e2
SZ
2124 return pi;
2125}
2126
76fbb0b9
SZ
2127/* Receive a frame. */
2128static void
dea2452a 2129jme_rxpkt(struct jme_rxdata *rdata)
76fbb0b9 2130{
dea2452a 2131 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
76fbb0b9
SZ
2132 struct jme_desc *desc;
2133 struct jme_rxdesc *rxd;
2134 struct mbuf *mp, *m;
a6acc6e2 2135 uint32_t flags, status, hash, hashinfo;
76fbb0b9
SZ
2136 int cons, count, nsegs;
2137
4447c752
SZ
2138 cons = rdata->jme_rx_cons;
2139 desc = &rdata->jme_rx_ring[cons];
9d4f763d 2140
76fbb0b9
SZ
2141 flags = le32toh(desc->flags);
2142 status = le32toh(desc->buflen);
a6acc6e2
SZ
2143 hash = le32toh(desc->addr_hi);
2144 hashinfo = le32toh(desc->addr_lo);
76fbb0b9
SZ
2145 nsegs = JME_RX_NSEGS(status);
2146
9d4f763d
SZ
2147 if (nsegs > 1) {
2148 /* Skip the first descriptor. */
2149 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2150
2151 /*
2152 * Clear the OWN bit of the following RX descriptors;
2153 * hardware will not clear the OWN bit except the first
2154 * RX descriptor.
2155 *
2156 * Since the first RX descriptor is setup, i.e. OWN bit
2157 * on, before its followins RX descriptors, leaving the
2158 * OWN bit on the following RX descriptors will trick
2159 * the hardware into thinking that the following RX
2160 * descriptors are ready to be used too.
2161 */
2162 for (count = 1; count < nsegs; count++,
2163 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2164 rdata->jme_rx_ring[cons].flags = 0;
2165
2166 cons = rdata->jme_rx_cons;
2167 }
2168
7b040092 2169 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
a6acc6e2 2170 "hash 0x%08x, hash info 0x%08x\n",
7b040092 2171 rdata->jme_rx_idx, flags, hash, hashinfo);
760c056c 2172
76fbb0b9
SZ
2173 if (status & JME_RX_ERR_STAT) {
2174 ifp->if_ierrors++;
dea2452a 2175 jme_discard_rxbufs(rdata, cons, nsegs);
76fbb0b9 2176#ifdef JME_SHOW_ERRORS
7b040092 2177 if_printf(ifp, "%s : receive error = 0x%b\n",
76fbb0b9
SZ
2178 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2179#endif
4447c752 2180 rdata->jme_rx_cons += nsegs;
7b040092 2181 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2182 return;
2183 }
2184
4447c752 2185 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
76fbb0b9 2186 for (count = 0; count < nsegs; count++,
7b040092 2187 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
4447c752 2188 rxd = &rdata->jme_rxdesc[cons];
76fbb0b9
SZ
2189 mp = rxd->rx_m;
2190
2191 /* Add a new receive buffer to the ring. */
dea2452a 2192 if (jme_newbuf(rdata, rxd, 0) != 0) {
76fbb0b9
SZ
2193 ifp->if_iqdrops++;
2194 /* Reuse buffer. */
dea2452a 2195 jme_discard_rxbufs(rdata, cons, nsegs - count);
4447c752
SZ
2196 if (rdata->jme_rxhead != NULL) {
2197 m_freem(rdata->jme_rxhead);
dea2452a 2198 JME_RXCHAIN_RESET(rdata);
76fbb0b9
SZ
2199 }
2200 break;
2201 }
2202
2203 /*
2204 * Assume we've received a full sized frame.
2205 * Actual size is fixed when we encounter the end of
2206 * multi-segmented frame.
2207 */
2208 mp->m_len = MCLBYTES;
2209
2210 /* Chain received mbufs. */
4447c752
SZ
2211 if (rdata->jme_rxhead == NULL) {
2212 rdata->jme_rxhead = mp;
2213 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2214 } else {
2215 /*
2216 * Receive processor can receive a maximum frame
2217 * size of 65535 bytes.
2218 */
4447c752
SZ
2219 rdata->jme_rxtail->m_next = mp;
2220 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2221 }
2222
2223 if (count == nsegs - 1) {
a6acc6e2
SZ
2224 struct pktinfo pi0, *pi;
2225
76fbb0b9 2226 /* Last desc. for this frame. */
4447c752 2227 m = rdata->jme_rxhead;
4447c752 2228 m->m_pkthdr.len = rdata->jme_rxlen;
76fbb0b9
SZ
2229 if (nsegs > 1) {
2230 /* Set first mbuf size. */
2231 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2232 /* Set last mbuf size. */
4447c752 2233 mp->m_len = rdata->jme_rxlen -
76fbb0b9
SZ
2234 ((MCLBYTES - JME_RX_PAD_BYTES) +
2235 (MCLBYTES * (nsegs - 2)));
2236 } else {
4447c752 2237 m->m_len = rdata->jme_rxlen;
76fbb0b9
SZ
2238 }
2239 m->m_pkthdr.rcvif = ifp;
2240
2241 /*
2242 * Account for 10bytes auto padding which is used
2243 * to align IP header on 32bit boundary. Also note,
2244 * CRC bytes is automatically removed by the
2245 * hardware.
2246 */
2247 m->m_data += JME_RX_PAD_BYTES;
2248
2249 /* Set checksum information. */
2250 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2251 (flags & JME_RD_IPV4)) {
2252 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2253 if (flags & JME_RD_IPCSUM)
2254 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2255 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2256 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2257 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2258 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2259 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2260 m->m_pkthdr.csum_flags |=
2261 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2262 m->m_pkthdr.csum_data = 0xffff;
2263 }
2264 }
2265
2266 /* Check for VLAN tagged packets. */
2267 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2268 (flags & JME_RD_VLAN_TAG)) {
2269 m->m_pkthdr.ether_vlantag =
2270 flags & JME_RD_VLAN_MASK;
2271 m->m_flags |= M_VLANTAG;
2272 }
2273
2274 ifp->if_ipackets++;
a6acc6e2
SZ
2275
2276 if (ifp->if_capenable & IFCAP_RSS)
2277 pi = jme_pktinfo(&pi0, flags);
2278 else
2279 pi = NULL;
2280
2281 if (pi != NULL &&
2282 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2283 m->m_flags |= M_HASH;
2284 m->m_pkthdr.hash = toeplitz_hash(hash);
2285 }
2286
2287#ifdef JME_RSS_DEBUG
2288 if (pi != NULL) {
7b040092 2289 JME_RSS_DPRINTF(rdata->jme_sc, 10,
a6acc6e2
SZ
2290 "isr %d flags %08x, l3 %d %s\n",
2291 pi->pi_netisr, pi->pi_flags,
2292 pi->pi_l3proto,
2293 (m->m_flags & M_HASH) ? "hash" : "");
2294 }
2295#endif
2296
76fbb0b9 2297 /* Pass it on. */
eda7db08 2298 ether_input_pkt(ifp, m, pi);
76fbb0b9
SZ
2299
2300 /* Reset mbuf chains. */
dea2452a 2301 JME_RXCHAIN_RESET(rdata);
760c056c 2302#ifdef JME_RSS_DEBUG
7b040092 2303 rdata->jme_rx_pkt++;
760c056c 2304#endif
76fbb0b9
SZ
2305 }
2306 }
2307
4447c752 2308 rdata->jme_rx_cons += nsegs;
7b040092 2309 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2310}
2311
eda7db08 2312static void
dea2452a 2313jme_rxeof(struct jme_rxdata *rdata, int count)
76fbb0b9
SZ
2314{
2315 struct jme_desc *desc;
eda7db08 2316 int nsegs, pktlen;
76fbb0b9 2317
76fbb0b9 2318 for (;;) {
3fa06afc
SZ
2319#ifdef DEVICE_POLLING
2320 if (count >= 0 && count-- == 0)
2321 break;
2322#endif
4447c752 2323 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
76fbb0b9
SZ
2324 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2325 break;
2326 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2327 break;
2328
2329 /*
2330 * Check number of segments against received bytes.
2331 * Non-matching value would indicate that hardware
2332 * is still trying to update Rx descriptors. I'm not
2333 * sure whether this check is needed.
2334 */
2335 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2336 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2337 if (nsegs != howmany(pktlen, MCLBYTES)) {
dea2452a
SZ
2338 if_printf(&rdata->jme_sc->arpcom.ac_if,
2339 "RX fragment count(%d) and "
2340 "packet size(%d) mismach\n", nsegs, pktlen);
76fbb0b9
SZ
2341 break;
2342 }
2343
6afef6ab
SZ
2344 /*
2345 * NOTE:
2346 * RSS hash and hash information may _not_ be set by the
2347 * hardware even if the OWN bit is cleared and VALID bit
2348 * is set.
2349 *
2350 * If the RSS information is not delivered by the hardware
2351 * yet, we MUST NOT accept this packet, let alone reusing
2352 * its RX descriptor. If this packet was accepted and its
2353 * RX descriptor was reused before hardware delivering the
2354 * RSS information, the RX buffer's address would be trashed
2355 * by the RSS information delivered by the hardware.
2356 */
2357 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2358 struct jme_rxdesc *rxd;
2359 uint32_t hashinfo;
2360
2361 hashinfo = le32toh(desc->addr_lo);
2362 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2363
2364 /*
2365 * This test should be enough to detect the pending
2366 * RSS information delivery, given:
2367 * - If RSS hash is not calculated, the hashinfo
064b75ed
SZ
2368 * will be 0. Howvever, the lower 32bits of RX
2369 * buffers' physical address will never be 0.
2370 * (see jme_rxbuf_dma_filter)
6afef6ab
SZ
2371 * - If RSS hash is calculated, the lowest 4 bits
2372 * of hashinfo will be set, while the RX buffers
2373 * are at least 2K aligned.
2374 */
2375 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2376#ifdef JME_SHOW_RSSWB
2377 if_printf(&rdata->jme_sc->arpcom.ac_if,
2378 "RSS is not written back yet\n");
2379#endif
2380 break;
2381 }
2382 }
2383
76fbb0b9 2384 /* Received a frame. */
dea2452a 2385 jme_rxpkt(rdata);
76fbb0b9 2386 }
76fbb0b9
SZ
2387}
2388
2389static void
2390jme_tick(void *xsc)
2391{
2392 struct jme_softc *sc = xsc;
2393 struct ifnet *ifp = &sc->arpcom.ac_if;
2394 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2395
31f0d5a2 2396 ifnet_serialize_all(ifp);
76fbb0b9
SZ
2397
2398 mii_tick(mii);
2399 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2400
31f0d5a2 2401 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
2402}
2403
2404static void
2405jme_reset(struct jme_softc *sc)
2406{
409fe405
SZ
2407 uint32_t val;
2408
2409 /* Make sure that TX and RX are stopped */
76fbb0b9 2410 jme_stop_tx(sc);
409fe405
SZ
2411 jme_stop_rx(sc);
2412
2413 /* Start reset */
76fbb0b9 2414 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
409fe405
SZ
2415 DELAY(20);
2416
2417 /*
2418 * Hold reset bit before stop reset
2419 */
2420
2421 /* Disable TXMAC and TXOFL clock sources */
2422 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2423 /* Disable RXMAC clock source */
2424 val = CSR_READ_4(sc, JME_GPREG1);
2425 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2426 /* Flush */
2427 CSR_READ_4(sc, JME_GHC);
2428
2429 /* Stop reset */
2430 CSR_WRITE_4(sc, JME_GHC, 0);
2431 /* Flush */
2432 CSR_READ_4(sc, JME_GHC);
2433
2434 /*
2435 * Clear reset bit after stop reset
2436 */
2437
2438 /* Enable TXMAC and TXOFL clock sources */
2439 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2440 /* Enable RXMAC clock source */
2441 val = CSR_READ_4(sc, JME_GPREG1);
2442 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2443 /* Flush */
2444 CSR_READ_4(sc, JME_GHC);
2445
2446 /* Disable TXMAC and TXOFL clock sources */
76fbb0b9 2447 CSR_WRITE_4(sc, JME_GHC, 0);
409fe405
SZ
2448 /* Disable RXMAC clock source */
2449 val = CSR_READ_4(sc, JME_GPREG1);
2450 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2451 /* Flush */
2452 CSR_READ_4(sc, JME_GHC);
2453
2454 /* Enable TX and RX */
2455 val = CSR_READ_4(sc, JME_TXCSR);
2456 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2457 val = CSR_READ_4(sc, JME_RXCSR);
2458 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2459 /* Flush */
2460 CSR_READ_4(sc, JME_TXCSR);
2461 CSR_READ_4(sc, JME_RXCSR);
2462
2463 /* Enable TXMAC and TXOFL clock sources */
2464 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2465 /* Eisable RXMAC clock source */
2466 val = CSR_READ_4(sc, JME_GPREG1);
2467 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2468 /* Flush */
2469 CSR_READ_4(sc, JME_GHC);
2470
2471 /* Stop TX and RX */
2472 jme_stop_tx(sc);
2473 jme_stop_rx(sc);
76fbb0b9
SZ
2474}
2475
2476static void
2477jme_init(void *xsc)
2478{
2479 struct jme_softc *sc = xsc;
2480 struct ifnet *ifp = &sc->arpcom.ac_if;
2481 struct mii_data *mii;
2482 uint8_t eaddr[ETHER_ADDR_LEN];
2483 bus_addr_t paddr;
2484 uint32_t reg;
4447c752 2485 int error, r;
76fbb0b9 2486
31f0d5a2 2487 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2488
2489 /*
2490 * Cancel any pending I/O.
2491 */
2492 jme_stop(sc);
2493
2494 /*
2495 * Reset the chip to a known state.
2496 */
2497 jme_reset(sc);
2498
58880b0d
SZ
2499 /*
2500 * Setup MSI/MSI-X vectors to interrupts mapping
2501 */
2502 jme_set_msinum(sc);
2503
9b3ee148
SZ
2504 sc->jme_txd_spare =
2505 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2506 KKASSERT(sc->jme_txd_spare >= 1);
2507
76fbb0b9 2508 /*
9b3ee148
SZ
2509 * If we use 64bit address mode for transmitting, each Tx request
2510 * needs one more symbol descriptor.
76fbb0b9 2511 */
9b3ee148
SZ
2512 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2513 sc->jme_txd_spare += 1;
76fbb0b9 2514
6afef6ab 2515 if (JME_ENABLE_HWRSS(sc))
760c056c
SZ
2516 jme_enable_rss(sc);
2517 else
2518 jme_disable_rss(sc);
4447c752
SZ
2519
2520 /* Init RX descriptors */
7b040092 2521 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
dea2452a 2522 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
4447c752
SZ
2523 if (error) {
2524 if_printf(ifp, "initialization failed: "
2525 "no memory for %dth RX ring.\n", r);
2526 jme_stop(sc);
2527 return;
2528 }
2529 }
2530
2531 /* Init TX descriptors */
76fbb0b9
SZ
2532 jme_init_tx_ring(sc);
2533
2534 /* Initialize shadow status block. */
2535 jme_init_ssb(sc);
2536
2537 /* Reprogram the station address. */
2538 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2539 CSR_WRITE_4(sc, JME_PAR0,
2540 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2541 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2542
2543 /*
2544 * Configure Tx queue.
2545 * Tx priority queue weight value : 0
2546 * Tx FIFO threshold for processing next packet : 16QW
2547 * Maximum Tx DMA length : 512
2548 * Allow Tx DMA burst.
2549 */
2550 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2551 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2552 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2553 sc->jme_txcsr |= sc->jme_tx_dma_size;
2554 sc->jme_txcsr |= TXCSR_DMA_BURST;
2555 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2556
2557 /* Set Tx descriptor counter. */
b020bb10 2558 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
76fbb0b9
SZ
2559
2560 /* Set Tx ring address to the hardware. */
7405bec3 2561 paddr = sc->jme_cdata.jme_tx_ring_paddr;
76fbb0b9
SZ
2562 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2563 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2564
2565 /* Configure TxMAC parameters. */
2566 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2567 reg |= TXMAC_THRESH_1_PKT;
2568 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2569 CSR_WRITE_4(sc, JME_TXMAC, reg);
2570
2571 /*
2572 * Configure Rx queue.
2573 * FIFO full threshold for transmitting Tx pause packet : 128T
2574 * FIFO threshold for processing next packet : 128QW
2575 * Rx queue 0 select
2576 * Max Rx DMA length : 128
2577 * Rx descriptor retry : 32
2578 * Rx descriptor retry time gap : 256ns
2579 * Don't receive runt/bad frame.
2580 */
2581 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
223cfc2f 2582#if 0
76fbb0b9
SZ
2583 /*
2584 * Since Rx FIFO size is 4K bytes, receiving frames larger
2585 * than 4K bytes will suffer from Rx FIFO overruns. So
2586 * decrease FIFO threshold to reduce the FIFO overruns for
2587 * frames larger than 4000 bytes.
2588 * For best performance of standard MTU sized frames use
2589 * maximum allowable FIFO threshold, 128QW.
2590 */
2591 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2592 JME_RX_FIFO_SIZE)
2593 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2594 else
2595 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
223cfc2f
SZ
2596#else
2597 /* Improve PCI Express compatibility */
2598 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2599#endif
2600 sc->jme_rxcsr |= sc->jme_rx_dma_size;
76fbb0b9
SZ
2601 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2602 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2603 /* XXX TODO DROP_BAD */
76fbb0b9 2604
7b040092
SZ
2605 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2606 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2607
4447c752
SZ
2608 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2609
2610 /* Set Rx descriptor counter. */
7b040092 2611 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
76fbb0b9 2612
4447c752 2613 /* Set Rx ring address to the hardware. */
7b040092 2614 paddr = rdata->jme_rx_ring_paddr;
4447c752
SZ
2615 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2616 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2617 }
76fbb0b9
SZ
2618
2619 /* Clear receive filter. */
2620 CSR_WRITE_4(sc, JME_RXMAC, 0);
2621
2622 /* Set up the receive filter. */
2623 jme_set_filter(sc);
2624 jme_set_vlan(sc);
2625
2626 /*
2627 * Disable all WOL bits as WOL can interfere normal Rx
2628 * operation. Also clear WOL detection status bits.
2629 */
2630 reg = CSR_READ_4(sc, JME_PMCS);
2631 reg &= ~PMCS_WOL_ENB_MASK;
2632 CSR_WRITE_4(sc, JME_PMCS, reg);
2633
2634 /*
2635 * Pad 10bytes right before received frame. This will greatly
2636 * help Rx performance on strict-alignment architectures as
2637 * it does not need to copy the frame to align the payload.
2638 */
2639 reg = CSR_READ_4(sc, JME_RXMAC);
2640 reg |= RXMAC_PAD_10BYTES;
2641
2642 if (ifp->if_capenable & IFCAP_RXCSUM)
2643 reg |= RXMAC_CSUM_ENB;
2644 CSR_WRITE_4(sc, JME_RXMAC, reg);
2645
2646 /* Configure general purpose reg0 */
2647 reg = CSR_READ_4(sc, JME_GPREG0);
2648 reg &= ~GPREG0_PCC_UNIT_MASK;
2649 /* Set PCC timer resolution to micro-seconds unit. */
2650 reg |= GPREG0_PCC_UNIT_US;
2651 /*
2652 * Disable all shadow register posting as we have to read
2653 * JME_INTR_STATUS register in jme_intr. Also it seems
2654 * that it's hard to synchronize interrupt status between
2655 * hardware and software with shadow posting due to
2656 * requirements of bus_dmamap_sync(9).
2657 */
2658 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2659 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2660 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2661 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2662 /* Disable posting of DW0. */
2663 reg &= ~GPREG0_POST_DW0_ENB;
2664 /* Clear PME message. */
2665 reg &= ~GPREG0_PME_ENB;
2666 /* Set PHY address. */
2667 reg &= ~GPREG0_PHY_ADDR_MASK;
2668 reg |= sc->jme_phyaddr;
2669 CSR_WRITE_4(sc, JME_GPREG0, reg);
2670
2671 /* Configure Tx queue 0 packet completion coalescing. */
2870abc4 2672 jme_set_tx_coal(sc);
76fbb0b9 2673
dea2452a 2674 /* Configure Rx queues packet completion coalescing. */
2870abc4 2675 jme_set_rx_coal(sc);
76fbb0b9
SZ
2676
2677 /* Configure shadow status block but don't enable posting. */
560616bf 2678 paddr = sc->jme_cdata.jme_ssb_block_paddr;
76fbb0b9
SZ
2679 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2680 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2681
2682 /* Disable Timer 1 and Timer 2. */
2683 CSR_WRITE_4(sc, JME_TIMER1, 0);
2684 CSR_WRITE_4(sc, JME_TIMER2, 0);
2685
2686 /* Configure retry transmit period, retry limit value. */
2687 CSR_WRITE_4(sc, JME_TXTRHD,
2688 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2689 TXTRHD_RT_PERIOD_MASK) |
2690 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2691 TXTRHD_RT_LIMIT_SHIFT));
2692
9de40864
SZ
2693#ifdef DEVICE_POLLING
2694 if (!(ifp->if_flags & IFF_POLLING))
2695#endif
76fbb0b9
SZ
2696 /* Initialize the interrupt mask. */
2697 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2698 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2699
2700 /*
2701 * Enabling Tx/Rx DMA engines and Rx queue processing is
2702 * done after detection of valid link in jme_miibus_statchg.
2703 */
2704 sc->jme_flags &= ~JME_FLAG_LINK;
2705
2706 /* Set the current media. */
2707 mii = device_get_softc(sc->jme_miibus);
2708 mii_mediachg(mii);
2709
2710 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2711
2712 ifp->if_flags |= IFF_RUNNING;
2713 ifp->if_flags &= ~IFF_OACTIVE;
2714}
2715
2716static void
2717jme_stop(struct jme_softc *sc)
2718{
2719 struct ifnet *ifp = &sc->arpcom.ac_if;
2720 struct jme_txdesc *txd;
2721 struct jme_rxdesc *rxd;
4447c752
SZ
2722 struct jme_rxdata *rdata;
2723 int i, r;
76fbb0b9 2724
31f0d5a2 2725 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2726
2727 /*
2728 * Mark the interface down and cancel the watchdog timer.
2729 */
2730 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2731 ifp->if_timer = 0;
2732
2733 callout_stop(&sc->jme_tick_ch);
2734 sc->jme_flags &= ~JME_FLAG_LINK;
2735
2736 /*
2737 * Disable interrupts.
2738 */
2739 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2740 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2741
2742 /* Disable updating shadow status block. */
2743 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2744 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2745
2746 /* Stop receiver, transmitter. */
2747 jme_stop_rx(sc);
2748 jme_stop_tx(sc);
2749
76fbb0b9
SZ
2750 /*
2751 * Free partial finished RX segments
2752 */
7b040092 2753 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
2754 rdata = &sc->jme_cdata.jme_rx_data[r];
2755 if (rdata->jme_rxhead != NULL)
2756 m_freem(rdata->jme_rxhead);
dea2452a 2757 JME_RXCHAIN_RESET(rdata);
4447c752 2758 }
76fbb0b9
SZ
2759
2760 /*
2761 * Free RX and TX mbufs still in the queues.
2762 */
7b040092 2763 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752 2764 rdata = &sc->jme_cdata.jme_rx_data[r];
7b040092 2765 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
2766 rxd = &rdata->jme_rxdesc[i];
2767 if (rxd->rx_m != NULL) {
2768 bus_dmamap_unload(rdata->jme_rx_tag,
2769 rxd->rx_dmamap);
2770 m_freem(rxd->rx_m);
2771 rxd->rx_m = NULL;
2772 }
76fbb0b9 2773 }
4447c752 2774 }
b020bb10 2775 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ
2776 txd = &sc->jme_cdata.jme_txdesc[i];
2777 if (txd->tx_m != NULL) {
2778 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2779 txd->tx_dmamap);
2780 m_freem(txd->tx_m);
2781 txd->tx_m = NULL;
2782 txd->tx_ndesc = 0;
2783 }
2784 }
2785}
2786
2787static void
2788jme_stop_tx(struct jme_softc *sc)
2789{
2790 uint32_t reg;
2791 int i;
2792
2793 reg = CSR_READ_4(sc, JME_TXCSR);
2794 if ((reg & TXCSR_TX_ENB) == 0)
2795 return;
2796 reg &= ~TXCSR_TX_ENB;
2797 CSR_WRITE_4(sc, JME_TXCSR, reg);
2798 for (i = JME_TIMEOUT; i > 0; i--) {
2799 DELAY(1);
2800 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2801 break;
2802 }
2803 if (i == 0)
2804 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2805}
2806
2807static void
2808jme_stop_rx(struct jme_softc *sc)
2809{
2810 uint32_t reg;
2811 int i;
2812
2813 reg = CSR_READ_4(sc, JME_RXCSR);
2814 if ((reg & RXCSR_RX_ENB) == 0)
2815 return;
2816 reg &= ~RXCSR_RX_ENB;
2817 CSR_WRITE_4(sc, JME_RXCSR, reg);
2818 for (i = JME_TIMEOUT; i > 0; i--) {
2819 DELAY(1);
2820 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2821 break;
2822 }
2823 if (i == 0)
2824 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2825}
2826
2827static void
2828jme_init_tx_ring(struct jme_softc *sc)
2829{
560616bf 2830 struct jme_chain_data *cd;
76fbb0b9
SZ
2831 struct jme_txdesc *txd;
2832 int i;
2833
2834 sc->jme_cdata.jme_tx_prod = 0;
2835 sc->jme_cdata.jme_tx_cons = 0;
2836 sc->jme_cdata.jme_tx_cnt = 0;
2837
560616bf
SZ
2838 cd = &sc->jme_cdata;
2839 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
b020bb10 2840 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
76fbb0b9
SZ
2841 txd = &sc->jme_cdata.jme_txdesc[i];
2842 txd->tx_m = NULL;
560616bf 2843 txd->tx_desc = &cd->jme_tx_ring[i];
76fbb0b9
SZ
2844 txd->tx_ndesc = 0;
2845 }
76fbb0b9
SZ
2846}
2847
2848static void
2849jme_init_ssb(struct jme_softc *sc)
2850{
560616bf 2851 struct jme_chain_data *cd;
76fbb0b9 2852
560616bf
SZ
2853 cd = &sc->jme_cdata;
2854 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
76fbb0b9
SZ
2855}
2856
2857static int
dea2452a 2858jme_init_rx_ring(struct jme_rxdata *rdata)
76fbb0b9 2859{
76fbb0b9
SZ
2860 struct jme_rxdesc *rxd;
2861 int i;
2862
4447c752
SZ
2863 KKASSERT(rdata->jme_rxhead == NULL &&
2864 rdata->jme_rxtail == NULL &&
2865 rdata->jme_rxlen == 0);
2866 rdata->jme_rx_cons = 0;
76fbb0b9 2867
7b040092
SZ
2868 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2869 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
76fbb0b9
SZ
2870 int error;
2871
4447c752 2872 rxd = &rdata->jme_rxdesc[i];
76fbb0b9 2873 rxd->rx_m = NULL;
4447c752 2874 rxd->rx_desc = &rdata->jme_rx_ring[i];
dea2452a 2875 error = jme_newbuf(rdata, rxd, 1);
76fbb0b9 2876 if (error)
4447c752 2877 return error;
76fbb0b9 2878 }
4447c752 2879 return 0;
76fbb0b9
SZ
2880}
2881
2882static int
dea2452a 2883jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
76fbb0b9 2884{
76fbb0b9 2885 struct mbuf *m;
76fbb0b9
SZ
2886 bus_dma_segment_t segs;
2887 bus_dmamap_t map;
b0ba1747 2888 int error, nsegs;
76fbb0b9
SZ
2889
2890 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2891 if (m == NULL)
4447c752 2892 return ENOBUFS;
76fbb0b9
SZ
2893 /*
2894 * JMC250 has 64bit boundary alignment limitation so jme(4)
2895 * takes advantage of 10 bytes padding feature of hardware
2896 * in order not to copy entire frame to align IP header on
2897 * 32bit boundary.
2898 */
2899 m->m_len = m->m_pkthdr.len = MCLBYTES;
2900
b0ba1747
SZ
2901 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2902 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2903 BUS_DMA_NOWAIT);
2904 if (error) {
76fbb0b9 2905 m_freem(m);
dea2452a
SZ
2906 if (init) {
2907 if_printf(&rdata->jme_sc->arpcom.ac_if,
2908 "can't load RX mbuf\n");
2909 }
4447c752 2910 return error;
76fbb0b9
SZ
2911 }
2912
2913 if (rxd->rx_m != NULL) {
4447c752 2914 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
76fbb0b9 2915 BUS_DMASYNC_POSTREAD);
4447c752 2916 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
76fbb0b9
SZ
2917 }
2918 map = rxd->rx_dmamap;
4447c752
SZ
2919 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2920 rdata->jme_rx_sparemap = map;
76fbb0b9 2921 rxd->rx_m = m;
fd2a6d2c 2922 rxd->rx_paddr = segs.ds_addr;
76fbb0b9 2923
fd2a6d2c 2924 jme_setup_rxdesc(rxd);
4447c752 2925 return 0;
76fbb0b9
SZ
2926}
2927
2928static void
2929jme_set_vlan(struct jme_softc *sc)
2930{
2931 struct ifnet *ifp = &sc->arpcom.ac_if;
2932 uint32_t reg;
2933
31f0d5a2 2934 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2935
2936 reg = CSR_READ_4(sc, JME_RXMAC);
2937 reg &= ~RXMAC_VLAN_ENB;
2938 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2939 reg |= RXMAC_VLAN_ENB;
2940 CSR_WRITE_4(sc, JME_RXMAC, reg);
2941}
2942
2943static void
2944jme_set_filter(struct jme_softc *sc)
2945{
2946 struct ifnet *ifp = &sc->arpcom.ac_if;
2947 struct ifmultiaddr *ifma;
2948 uint32_t crc;
2949 uint32_t mchash[2];
2950 uint32_t rxcfg;
2951
31f0d5a2 2952 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2953
2954 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2955 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2956 RXMAC_ALLMULTI);
2957
2958 /*
2959 * Always accept frames destined to our station address.
2960 * Always accept broadcast frames.
2961 */
2962 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2963
2964 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2965 if (ifp->if_flags & IFF_PROMISC)
2966 rxcfg |= RXMAC_PROMISC;
2967 if (ifp->if_flags & IFF_ALLMULTI)
2968 rxcfg |= RXMAC_ALLMULTI;
2969 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2970 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2971 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2972 return;
2973 }
2974
2975 /*
2976 * Set up the multicast address filter by passing all multicast
2977 * addresses through a CRC generator, and then using the low-order
2978 * 6 bits as an index into the 64 bit multicast hash table. The
2979 * high order bits select the register, while the rest of the bits
2980 * select the bit within the register.
2981 */
2982 rxcfg |= RXMAC_MULTICAST;
2983 bzero(mchash, sizeof(mchash));
2984
441d34b2 2985 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
76fbb0b9
SZ
2986 if (ifma->ifma_addr->sa_family != AF_LINK)
2987 continue;
2988 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2989 ifma->ifma_addr), ETHER_ADDR_LEN);
2990
2991 /* Just want the 6 least significant bits. */
2992 crc &= 0x3f;
2993
2994 /* Set the corresponding bit in the hash table. */
2995 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2996 }
2997
2998 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2999 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3000 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3001}
3002
3003static int
2870abc4 3004jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3005{
2870abc4
SZ
3006 struct jme_softc *sc = arg1;
3007 struct ifnet *ifp = &sc->arpcom.ac_if;
3008 int error, v;
3009
31f0d5a2 3010 ifnet_serialize_all(ifp);
2870abc4
SZ
3011
3012 v = sc->jme_tx_coal_to;
3013 error = sysctl_handle_int(oidp, &v, 0, req);
3014 if (error || req->newptr == NULL)
3015 goto back;
3016
3017 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3018 error = EINVAL;
3019 goto back;
3020 }
3021
3022 if (v != sc->jme_tx_coal_to) {
3023 sc->jme_tx_coal_to = v;
3024 if (ifp->if_flags & IFF_RUNNING)
3025 jme_set_tx_coal(sc);
3026 }
3027back:
31f0d5a2 3028 ifnet_deserialize_all(ifp);
2870abc4 3029 return error;
76fbb0b9
SZ
3030}
3031
3032static int
2870abc4 3033jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
76fbb0b9 3034{
2870abc4
SZ
3035 struct jme_softc *sc = arg1;
3036 struct ifnet *ifp = &sc->arpcom.ac_if;
3037 int error, v;
3038
31f0d5a2 3039 ifnet_serialize_all(ifp);
2870abc4
SZ
3040
3041 v = sc->jme_tx_coal_pkt;
3042 error = sysctl_handle_int(oidp, &v, 0, req);
3043 if (error || req->newptr == NULL)
3044 goto back;
3045
3046 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3047 error = EINVAL;
3048 goto back;
3049 }
3050
3051 if (v != sc->jme_tx_coal_pkt) {
3052 sc->jme_tx_coal_pkt = v;
3053 if (ifp->if_flags & IFF_RUNNING)
3054 jme_set_tx_coal(sc);
3055 }
3056back:
31f0d5a2 3057 ifnet_deserialize_all(ifp);
2870abc4 3058 return error;
76fbb0b9
SZ
3059}
3060
3061static int
2870abc4 3062jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3063{
2870abc4
SZ
3064 struct jme_softc *sc = arg1;
3065 struct ifnet *ifp = &sc->arpcom.ac_if;
3066 int error, v;
3067
31f0d5a2 3068 ifnet_serialize_all(ifp);
2870abc4
SZ
3069
3070 v = sc->jme_rx_coal_to;
3071 error = sysctl_handle_int(oidp, &v, 0, req);
3072 if (error || req->newptr == NULL)
3073 goto back;
3074
3075 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3076 error = EINVAL;
3077 goto back;
3078 }
3079
3080 if (v != sc->jme_rx_coal_to) {
3081 sc->jme_rx_coal_to = v;
3082 if (ifp->if_flags & IFF_RUNNING)
3083 jme_set_rx_coal(sc);
3084 }
3085back:
31f0d5a2 3086 ifnet_deserialize_all(ifp);
2870abc4 3087 return error;
76fbb0b9
SZ
3088}
3089
3090static int
2870abc4
SZ
3091jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3092{
3093 struct jme_softc *sc = arg1;
3094 struct ifnet *ifp = &sc->arpcom.ac_if;
3095 int error, v;
3096
31f0d5a2 3097 ifnet_serialize_all(ifp);
2870abc4
SZ
3098
3099 v = sc->jme_rx_coal_pkt;
3100 error = sysctl_handle_int(oidp, &v, 0, req);
3101 if (error || req->newptr == NULL)
3102 goto back;
3103
3104 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3105 error = EINVAL;
3106 goto back;
3107 }
3108
3109 if (v != sc->jme_rx_coal_pkt) {
3110 sc->jme_rx_coal_pkt = v;
3111 if (ifp->if_flags & IFF_RUNNING)
3112 jme_set_rx_coal(sc);
3113 }
3114back:
31f0d5a2 3115 ifnet_deserialize_all(ifp);
2870abc4
SZ
3116 return error;
3117}
3118
3119static void
3120jme_set_tx_coal(struct jme_softc *sc)
3121{
3122 uint32_t reg;
3123
3124 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3125 PCCTX_COAL_TO_MASK;
3126 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3127 PCCTX_COAL_PKT_MASK;
3128 reg |= PCCTX_COAL_TXQ0;
3129 CSR_WRITE_4(sc, JME_PCCTX, reg);
3130}
3131
3132static void
3133jme_set_rx_coal(struct jme_softc *sc)
76fbb0b9 3134{
2870abc4 3135 uint32_t reg;
4447c752 3136 int r;
2870abc4
SZ
3137
3138 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3139 PCCRX_COAL_TO_MASK;
3140 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3141 PCCRX_COAL_PKT_MASK;
7b040092 3142 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
9f20b7b3 3143 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
76fbb0b9 3144}
9de40864
SZ
3145
3146#ifdef DEVICE_POLLING
3147
3148static void
3149jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3150{
3151 struct jme_softc *sc = ifp->if_softc;
3152 uint32_t status;
eda7db08 3153 int r;
9de40864 3154
31f0d5a2 3155 ASSERT_SERIALIZED(&sc->jme_serialize);
9de40864
SZ
3156
3157 switch (cmd) {
3158 case POLL_REGISTER:
3159 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3160 break;
3161
3162 case POLL_DEREGISTER:
3163 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3164 break;
3165
3166 case POLL_AND_CHECK_STATUS:
3167 case POLL_ONLY:
3168 status = CSR_READ_4(sc, JME_INTR_STATUS);
0e7f1e6f 3169
7b040092 3170 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31f0d5a2
SZ
3171 struct jme_rxdata *rdata =
3172 &sc->jme_cdata.jme_rx_data[r];
3173
3174 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3175 jme_rxeof(rdata, count);
31f0d5a2
SZ
3176 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3177 }
9de40864
SZ
3178
3179 if (status & INTR_RXQ_DESC_EMPTY) {
3180 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3181 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3182 RXCSR_RX_ENB | RXCSR_RXQ_START);
3183 }
3184
31f0d5a2 3185 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ
3186 jme_txeof(sc);
3187 if (!ifq_is_empty(&ifp->if_snd))
3188 if_devstart(ifp);
31f0d5a2 3189 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ
3190 break;
3191 }
3192}
3193
3194#endif /* DEVICE_POLLING */
4447c752
SZ
3195
3196static int
dea2452a 3197jme_rxring_dma_alloc(struct jme_rxdata *rdata)
4447c752 3198{
1128a202 3199 bus_dmamem_t dmem;
ff7f3632 3200 int error, asize;
4447c752 3201
ff7f3632 3202 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
dea2452a 3203 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
1128a202 3204 JME_RX_RING_ALIGN, 0,
0eb220ec 3205 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 3206 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4447c752 3207 if (error) {
dea2452a
SZ
3208 device_printf(rdata->jme_sc->jme_dev,
3209 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
4447c752
SZ
3210 return error;
3211 }
1128a202
SZ
3212 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3213 rdata->jme_rx_ring_map = dmem.dmem_map;
3214 rdata->jme_rx_ring = dmem.dmem_addr;
3215 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
4447c752
SZ
3216
3217 return 0;
3218}
3219
3220static int
064b75ed
SZ
3221jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3222{
3223 if ((paddr & 0xffffffff) == 0) {
3224 /*
3225 * Don't allow lower 32bits of the RX buffer's
3226 * physical address to be 0, else it will break
3227 * hardware pending RSS information delivery
3228 * detection on RX path.
3229 */
3230 return 1;
3231 }
3232 return 0;
3233}
3234
3235static int
dea2452a 3236jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
4447c752 3237{
064b75ed 3238 bus_addr_t lowaddr;
4447c752
SZ
3239 int i, error;
3240
064b75ed
SZ
3241 lowaddr = BUS_SPACE_MAXADDR;
3242 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3243 /* jme_rxbuf_dma_filter will be called */
3244 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3245 }
3246
4447c752 3247 /* Create tag for Rx buffers. */
dea2452a
SZ
3248 error = bus_dma_tag_create(
3249 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
4447c752 3250 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
064b75ed 3251 lowaddr, /* lowaddr */
4447c752 3252 BUS_SPACE_MAXADDR, /* highaddr */
064b75ed 3253 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
4447c752
SZ
3254 MCLBYTES, /* maxsize */
3255 1, /* nsegments */
3256 MCLBYTES, /* maxsegsize */
9d424cee 3257 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
4447c752
SZ
3258 &rdata->jme_rx_tag);
3259 if (error) {
dea2452a
SZ
3260 device_printf(rdata->jme_sc->jme_dev,
3261 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
4447c752
SZ
3262 return error;
3263 }
3264
3265 /* Create DMA maps for Rx buffers. */
9d424cee 3266 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3267 &rdata->jme_rx_sparemap);
3268 if (error) {
dea2452a
SZ
3269 device_printf(rdata->jme_sc->jme_dev,
3270 "could not create %dth spare Rx dmamap.\n",
3271 rdata->jme_rx_idx);
4447c752
SZ
3272 bus_dma_tag_destroy(rdata->jme_rx_tag);
3273 rdata->jme_rx_tag = NULL;
3274 return error;
3275 }
7b040092 3276 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
3277 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3278
9d424cee 3279 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3280 &rxd->rx_dmamap);
3281 if (error) {
3282 int j;
3283
dea2452a 3284 device_printf(rdata->jme_sc->jme_dev,
4447c752 3285 "could not create %dth Rx dmamap "
dea2452a 3286 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
4447c752
SZ
3287
3288 for (j = 0; j < i; ++j) {
3289 rxd = &rdata->jme_rxdesc[j];
3290 bus_dmamap_destroy(rdata->jme_rx_tag,
3291 rxd->rx_dmamap);
3292 }
3293 bus_dmamap_destroy(rdata->jme_rx_tag,
3294 rdata->jme_rx_sparemap);
3295 bus_dma_tag_destroy(rdata->jme_rx_tag);
3296 rdata->jme_rx_tag = NULL;
3297 return error;
3298 }
3299 }
3300 return 0;
3301}
3302
3303static void
3304jme_rx_intr(struct jme_softc *sc, uint32_t status)
3305{
eda7db08 3306 int r;
4447c752 3307
7b040092 3308 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31810fb8 3309 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
31f0d5a2 3310
31810fb8 3311 if (status & rdata->jme_rx_coal) {
31f0d5a2 3312 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3313 jme_rxeof(rdata, -1);
31f0d5a2
SZ
3314 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3315 }
4447c752
SZ
3316 }
3317}
760c056c
SZ
3318
3319static void
3320jme_enable_rss(struct jme_softc *sc)
3321{
24dd1705
SZ
3322 uint32_t rssc, ind;
3323 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
760c056c
SZ
3324 int i;
3325
022f915e
SZ
3326 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3327 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
ed20d0e3 3328 ("%s: invalid # of RX rings (%d)",
022f915e 3329 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
66f75939 3330
760c056c
SZ
3331 rssc = RSSC_HASH_64_ENTRY;
3332 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
7b040092 3333 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
760c056c
SZ
3334 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3335 CSR_WRITE_4(sc, JME_RSSC, rssc);
3336
24dd1705
SZ
3337 toeplitz_get_key(key, sizeof(key));
3338 for (i = 0; i < RSSKEY_NREGS; ++i) {
3339 uint32_t keyreg;
3340
3341 keyreg = RSSKEY_REGVAL(key, i);
3342 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3343
3344 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3345 }
760c056c 3346
66f75939
SZ
3347 /*
3348 * Create redirect table in following fashion:
3349 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3350 */
760c056c 3351 ind = 0;
66f75939
SZ
3352 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3353 int q;
3354
7b040092 3355 q = i % sc->jme_cdata.jme_rx_ring_cnt;
66f75939 3356 ind |= q << (i * 8);
760c056c
SZ
3357 }
3358 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
66f75939 3359
760c056c
SZ
3360 for (i = 0; i < RSSTBL_NREGS; ++i)
3361 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3362}
3363
3364static void
3365jme_disable_rss(struct jme_softc *sc)
3366{
760c056c
SZ
3367 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3368}
31f0d5a2
SZ
3369
3370static void
3371jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3372{
3373 struct jme_softc *sc = ifp->if_softc;
3374
29890f78
SZ
3375 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3376 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ
3377}
3378
3379static void
3380jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3381{
3382 struct jme_softc *sc = ifp->if_softc;
3383
29890f78
SZ
3384 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3385 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ
3386}
3387
3388static int
3389jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3390{
3391 struct jme_softc *sc = ifp->if_softc;
3392
29890f78
SZ
3393 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3394 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
31f0d5a2
SZ
3395}
3396
3397#ifdef INVARIANTS
3398
3399static void
3400jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3401 boolean_t serialized)
3402{
3403 struct jme_softc *sc = ifp->if_softc;
31f0d5a2 3404
29890f78
SZ
3405 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3406 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3407 slz, serialized);
31f0d5a2
SZ
3408}
3409
3410#endif /* INVARIANTS */
58880b0d
SZ
3411
3412static void
3413jme_msix_try_alloc(device_t dev)
3414{
3415 struct jme_softc *sc = device_get_softc(dev);
3416 struct jme_msix_data *msix;
3417 int error, i, r, msix_enable, msix_count;
58880b0d 3418
7b040092 3419 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
58880b0d
SZ
3420 KKASSERT(msix_count <= JME_NMSIX);
3421
1cc217a9 3422 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
58880b0d
SZ
3423
3424 /*
3425 * We leave the 1st MSI-X vector unused, so we
3426 * actually need msix_count + 1 MSI-X vectors.
3427 */
3428 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3429 return;
3430
3431 for (i = 0; i < msix_count; ++i)
3432 sc->jme_msix[i].jme_msix_rid = -1;
3433
3434 i = 0;
3435
3436 msix = &sc->jme_msix[i++];
3437 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3438 msix->jme_msix_arg = &sc->jme_cdata;
3439 msix->jme_msix_func = jme_msix_tx;
3440 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3441 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3442 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3443 device_get_nameunit(dev));
3444
7b040092 3445 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
58880b0d
SZ
3446 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3447
3448 msix = &sc->jme_msix[i++];
3449 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3450 msix->jme_msix_arg = rdata;
3451 msix->jme_msix_func = jme_msix_rx;
3452 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3453 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3454 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3455 "%s rx%d", device_get_nameunit(dev), r);
3456 }
3457
3458 KKASSERT(i == msix_count);
3459
3460 error = pci_setup_msix(dev);
3461 if (error)
3462 return;
3463
3464 /* Setup jme_msix_cnt early, so we could cleanup */
3465 sc->jme_msix_cnt = msix_count;
3466
3467 for (i = 0; i < msix_count; ++i) {
3468 msix = &sc->jme_msix[i];
3469
3470 msix->jme_msix_vector = i + 1;
3471 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3472 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3473 if (error)
3474 goto back;
3475
3476 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3477 &msix->jme_msix_rid, RF_ACTIVE);
3478 if (msix->jme_msix_res == NULL) {
3479 error = ENOMEM;
3480 goto back;
3481 }
3482 }
3483
3484 for (i = 0; i < JME_INTR_CNT; ++i) {
3485 uint32_t intr_mask = (1 << i);
3486 int x;
3487
3488 if ((JME_INTRS & intr_mask) == 0)
3489 continue;
3490
3491 for (x = 0; x < msix_count; ++x) {
3492 msix = &sc->jme_msix[x];
3493 if (msix->jme_msix_intrs & intr_mask) {
3494 int reg, shift;
3495
3496 reg = i / JME_MSINUM_FACTOR;
3497 KKASSERT(reg < JME_MSINUM_CNT);
3498
3499 shift = (i % JME_MSINUM_FACTOR) * 4;
3500
3501 sc->jme_msinum[reg] |=
3502 (msix->jme_msix_vector << shift);
3503
3504 break;
3505 }
3506 }
3507 }
3508
3509 if (bootverbose) {
3510 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3511 device_printf(dev, "MSINUM%d: %#x\n", i,
3512 sc->jme_msinum[i]);
3513 }
3514 }
3515
3516 pci_enable_msix(dev);
3517 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3518
3519back:
3520 if (error)
3521 jme_msix_free(dev);
3522}
3523
3524static int
3525jme_intr_alloc(device_t dev)
3526{
3527 struct jme_softc *sc = device_get_softc(dev);
3528 u_int irq_flags;
3529
3530 jme_msix_try_alloc(dev);
3531
3532 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3533 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3534 &sc->jme_irq_rid, &irq_flags);
3535
3536 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3537 &sc->jme_irq_rid, irq_flags);
3538 if (sc->jme_irq_res == NULL) {
3539 device_printf(dev, "can't allocate irq\n");
3540 return ENXIO;
3541 }
3542 }
3543 return 0;
3544}
3545
3546static void
3547jme_msix_free(device_t dev)
3548{
3549 struct jme_softc *sc = device_get_softc(dev);
3550 int i;
3551
3552 KKASSERT(sc->jme_msix_cnt > 1);
3553
3554 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3555 struct jme_msix_data *msix = &sc->jme_msix[i];
3556
3557 if (msix->jme_msix_res != NULL) {
3558 bus_release_resource(dev, SYS_RES_IRQ,
3559 msix->jme_msix_rid, msix->jme_msix_res);
3560 msix->jme_msix_res = NULL;
3561 }
3562 if (msix->jme_msix_rid >= 0) {
3563 pci_release_msix_vector(dev, msix->jme_msix_rid);
3564 msix->jme_msix_rid = -1;
3565 }
3566 }
3567 pci_teardown_msix(dev);
3568}
3569
3570static void
3571jme_intr_free(device_t dev)
3572{
3573 struct jme_softc *sc = device_get_softc(dev);
3574
3575 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3576 if (sc->jme_irq_res != NULL) {
3577 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3578 sc->jme_irq_res);
3579 }
3580 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3581 pci_release_msi(dev);
3582 } else {
3583 jme_msix_free(dev);
3584 }
3585}
3586
3587static void
3588jme_msix_tx(void *xcd)
3589{
3590 struct jme_chain_data *cd = xcd;
3591 struct jme_softc *sc = cd->jme_sc;
3592 struct ifnet *ifp = &sc->arpcom.ac_if;
3593
3594 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3595
875547c0
SZ
3596 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3597
58880b0d
SZ
3598 CSR_WRITE_4(sc, JME_INTR_STATUS,
3599 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3600
3601 if (ifp->if_flags & IFF_RUNNING) {
3602 jme_txeof(sc);
3603 if (!ifq_is_empty(&ifp->if_snd))
3604 if_devstart(ifp);
3605 }
875547c0
SZ
3606
3607 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
58880b0d
SZ
3608}
3609
3610static void
3611jme_msix_rx(void *xrdata)
3612{
3613 struct jme_rxdata *rdata = xrdata;
3614 struct jme_softc *sc = rdata->jme_sc;
3615 struct ifnet *ifp = &sc->arpcom.ac_if;
3616 uint32_t status;
3617
3618 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3619
875547c0
SZ
3620 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,