ioapic/x86_64: Per-cpu irqmap array
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
CommitLineData
c8fe38ae
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1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
47#include <sys/interrupt.h>
48#include <sys/bus.h>
95874ffd 49#include <sys/thread2.h>
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50
51#include <machine/smp.h>
52#include <machine/segments.h>
53#include <machine/md_var.h>
57a9c56b 54#include <machine/intr_machdep.h>
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55#include <machine/globaldata.h>
56
104463f2 57#include <machine_base/isa/isa_intr.h>
61452645 58#include <machine_base/icu/icu.h>
6b809ec7 59#include <machine_base/icu/icu_var.h>
61452645 60#include <machine_base/apic/ioapic.h>
929c940f 61#include <machine_base/apic/ioapic_abi.h>
77f86d14 62#include <machine_base/apic/ioapic_ipl.h>
9a4bd8f3 63#include <machine_base/apic/apicreg.h>
c8fe38ae 64
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65#include <dev/acpica5/acpi_sci_var.h>
66
451af8d9
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67#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
68
c8fe38ae 69extern inthand_t
9e0e3f85
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70 IDTVEC(ioapic_intr0),
71 IDTVEC(ioapic_intr1),
72 IDTVEC(ioapic_intr2),
73 IDTVEC(ioapic_intr3),
74 IDTVEC(ioapic_intr4),
75 IDTVEC(ioapic_intr5),
76 IDTVEC(ioapic_intr6),
77 IDTVEC(ioapic_intr7),
78 IDTVEC(ioapic_intr8),
79 IDTVEC(ioapic_intr9),
80 IDTVEC(ioapic_intr10),
81 IDTVEC(ioapic_intr11),
82 IDTVEC(ioapic_intr12),
83 IDTVEC(ioapic_intr13),
84 IDTVEC(ioapic_intr14),
85 IDTVEC(ioapic_intr15),
86 IDTVEC(ioapic_intr16),
87 IDTVEC(ioapic_intr17),
88 IDTVEC(ioapic_intr18),
89 IDTVEC(ioapic_intr19),
90 IDTVEC(ioapic_intr20),
91 IDTVEC(ioapic_intr21),
92 IDTVEC(ioapic_intr22),
93 IDTVEC(ioapic_intr23),
94 IDTVEC(ioapic_intr24),
95 IDTVEC(ioapic_intr25),
96 IDTVEC(ioapic_intr26),
97 IDTVEC(ioapic_intr27),
98 IDTVEC(ioapic_intr28),
99 IDTVEC(ioapic_intr29),
100 IDTVEC(ioapic_intr30),
101 IDTVEC(ioapic_intr31),
102 IDTVEC(ioapic_intr32),
103 IDTVEC(ioapic_intr33),
104 IDTVEC(ioapic_intr34),
105 IDTVEC(ioapic_intr35),
106 IDTVEC(ioapic_intr36),
107 IDTVEC(ioapic_intr37),
108 IDTVEC(ioapic_intr38),
109 IDTVEC(ioapic_intr39),
110 IDTVEC(ioapic_intr40),
111 IDTVEC(ioapic_intr41),
112 IDTVEC(ioapic_intr42),
113 IDTVEC(ioapic_intr43),
114 IDTVEC(ioapic_intr44),
115 IDTVEC(ioapic_intr45),
116 IDTVEC(ioapic_intr46),
117 IDTVEC(ioapic_intr47),
118 IDTVEC(ioapic_intr48),
119 IDTVEC(ioapic_intr49),
120 IDTVEC(ioapic_intr50),
121 IDTVEC(ioapic_intr51),
122 IDTVEC(ioapic_intr52),
123 IDTVEC(ioapic_intr53),
124 IDTVEC(ioapic_intr54),
125 IDTVEC(ioapic_intr55),
126 IDTVEC(ioapic_intr56),
127 IDTVEC(ioapic_intr57),
128 IDTVEC(ioapic_intr58),
129 IDTVEC(ioapic_intr59),
130 IDTVEC(ioapic_intr60),
131 IDTVEC(ioapic_intr61),
132 IDTVEC(ioapic_intr62),
133 IDTVEC(ioapic_intr63),
134 IDTVEC(ioapic_intr64),
135 IDTVEC(ioapic_intr65),
136 IDTVEC(ioapic_intr66),
137 IDTVEC(ioapic_intr67),
138 IDTVEC(ioapic_intr68),
139 IDTVEC(ioapic_intr69),
140 IDTVEC(ioapic_intr70),
141 IDTVEC(ioapic_intr71),
142 IDTVEC(ioapic_intr72),
143 IDTVEC(ioapic_intr73),
144 IDTVEC(ioapic_intr74),
145 IDTVEC(ioapic_intr75),
146 IDTVEC(ioapic_intr76),
147 IDTVEC(ioapic_intr77),
148 IDTVEC(ioapic_intr78),
149 IDTVEC(ioapic_intr79),
150 IDTVEC(ioapic_intr80),
151 IDTVEC(ioapic_intr81),
152 IDTVEC(ioapic_intr82),
153 IDTVEC(ioapic_intr83),
154 IDTVEC(ioapic_intr84),
155 IDTVEC(ioapic_intr85),
156 IDTVEC(ioapic_intr86),
157 IDTVEC(ioapic_intr87),
158 IDTVEC(ioapic_intr88),
159 IDTVEC(ioapic_intr89),
160 IDTVEC(ioapic_intr90),
161 IDTVEC(ioapic_intr91),
162 IDTVEC(ioapic_intr92),
163 IDTVEC(ioapic_intr93),
164 IDTVEC(ioapic_intr94),
165 IDTVEC(ioapic_intr95),
166 IDTVEC(ioapic_intr96),
167 IDTVEC(ioapic_intr97),
168 IDTVEC(ioapic_intr98),
169 IDTVEC(ioapic_intr99),
170 IDTVEC(ioapic_intr100),
171 IDTVEC(ioapic_intr101),
172 IDTVEC(ioapic_intr102),
173 IDTVEC(ioapic_intr103),
174 IDTVEC(ioapic_intr104),
175 IDTVEC(ioapic_intr105),
176 IDTVEC(ioapic_intr106),
177 IDTVEC(ioapic_intr107),
178 IDTVEC(ioapic_intr108),
179 IDTVEC(ioapic_intr109),
180 IDTVEC(ioapic_intr110),
181 IDTVEC(ioapic_intr111),
182 IDTVEC(ioapic_intr112),
183 IDTVEC(ioapic_intr113),
184 IDTVEC(ioapic_intr114),
185 IDTVEC(ioapic_intr115),
186 IDTVEC(ioapic_intr116),
187 IDTVEC(ioapic_intr117),
188 IDTVEC(ioapic_intr118),
189 IDTVEC(ioapic_intr119),
190 IDTVEC(ioapic_intr120),
191 IDTVEC(ioapic_intr121),
192 IDTVEC(ioapic_intr122),
193 IDTVEC(ioapic_intr123),
194 IDTVEC(ioapic_intr124),
195 IDTVEC(ioapic_intr125),
196 IDTVEC(ioapic_intr126),
197 IDTVEC(ioapic_intr127),
198 IDTVEC(ioapic_intr128),
199 IDTVEC(ioapic_intr129),
200 IDTVEC(ioapic_intr130),
201 IDTVEC(ioapic_intr131),
202 IDTVEC(ioapic_intr132),
203 IDTVEC(ioapic_intr133),
204 IDTVEC(ioapic_intr134),
205 IDTVEC(ioapic_intr135),
206 IDTVEC(ioapic_intr136),
207 IDTVEC(ioapic_intr137),
208 IDTVEC(ioapic_intr138),
209 IDTVEC(ioapic_intr139),
210 IDTVEC(ioapic_intr140),
211 IDTVEC(ioapic_intr141),
212 IDTVEC(ioapic_intr142),
213 IDTVEC(ioapic_intr143),
214 IDTVEC(ioapic_intr144),
215 IDTVEC(ioapic_intr145),
216 IDTVEC(ioapic_intr146),
217 IDTVEC(ioapic_intr147),
218 IDTVEC(ioapic_intr148),
219 IDTVEC(ioapic_intr149),
220 IDTVEC(ioapic_intr150),
221 IDTVEC(ioapic_intr151),
222 IDTVEC(ioapic_intr152),
223 IDTVEC(ioapic_intr153),
224 IDTVEC(ioapic_intr154),
225 IDTVEC(ioapic_intr155),
226 IDTVEC(ioapic_intr156),
227 IDTVEC(ioapic_intr157),
228 IDTVEC(ioapic_intr158),
229 IDTVEC(ioapic_intr159),
230 IDTVEC(ioapic_intr160),
231 IDTVEC(ioapic_intr161),
232 IDTVEC(ioapic_intr162),
233 IDTVEC(ioapic_intr163),
234 IDTVEC(ioapic_intr164),
235 IDTVEC(ioapic_intr165),
236 IDTVEC(ioapic_intr166),
237 IDTVEC(ioapic_intr167),
238 IDTVEC(ioapic_intr168),
239 IDTVEC(ioapic_intr169),
240 IDTVEC(ioapic_intr170),
241 IDTVEC(ioapic_intr171),
242 IDTVEC(ioapic_intr172),
243 IDTVEC(ioapic_intr173),
244 IDTVEC(ioapic_intr174),
245 IDTVEC(ioapic_intr175),
246 IDTVEC(ioapic_intr176),
247 IDTVEC(ioapic_intr177),
248 IDTVEC(ioapic_intr178),
249 IDTVEC(ioapic_intr179),
250 IDTVEC(ioapic_intr180),
251 IDTVEC(ioapic_intr181),
252 IDTVEC(ioapic_intr182),
253 IDTVEC(ioapic_intr183),
254 IDTVEC(ioapic_intr184),
255 IDTVEC(ioapic_intr185),
256 IDTVEC(ioapic_intr186),
257 IDTVEC(ioapic_intr187),
258 IDTVEC(ioapic_intr188),
259 IDTVEC(ioapic_intr189),
260 IDTVEC(ioapic_intr190),
261 IDTVEC(ioapic_intr191);
262
263static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
264 &IDTVEC(ioapic_intr0),
265 &IDTVEC(ioapic_intr1),
266 &IDTVEC(ioapic_intr2),
267 &IDTVEC(ioapic_intr3),
268 &IDTVEC(ioapic_intr4),
269 &IDTVEC(ioapic_intr5),
270 &IDTVEC(ioapic_intr6),
271 &IDTVEC(ioapic_intr7),
272 &IDTVEC(ioapic_intr8),
273 &IDTVEC(ioapic_intr9),
274 &IDTVEC(ioapic_intr10),
275 &IDTVEC(ioapic_intr11),
276 &IDTVEC(ioapic_intr12),
277 &IDTVEC(ioapic_intr13),
278 &IDTVEC(ioapic_intr14),
279 &IDTVEC(ioapic_intr15),
280 &IDTVEC(ioapic_intr16),
281 &IDTVEC(ioapic_intr17),
282 &IDTVEC(ioapic_intr18),
283 &IDTVEC(ioapic_intr19),
284 &IDTVEC(ioapic_intr20),
285 &IDTVEC(ioapic_intr21),
286 &IDTVEC(ioapic_intr22),
287 &IDTVEC(ioapic_intr23),
288 &IDTVEC(ioapic_intr24),
289 &IDTVEC(ioapic_intr25),
290 &IDTVEC(ioapic_intr26),
291 &IDTVEC(ioapic_intr27),
292 &IDTVEC(ioapic_intr28),
293 &IDTVEC(ioapic_intr29),
294 &IDTVEC(ioapic_intr30),
295 &IDTVEC(ioapic_intr31),
296 &IDTVEC(ioapic_intr32),
297 &IDTVEC(ioapic_intr33),
298 &IDTVEC(ioapic_intr34),
299 &IDTVEC(ioapic_intr35),
300 &IDTVEC(ioapic_intr36),
301 &IDTVEC(ioapic_intr37),
302 &IDTVEC(ioapic_intr38),
303 &IDTVEC(ioapic_intr39),
304 &IDTVEC(ioapic_intr40),
305 &IDTVEC(ioapic_intr41),
306 &IDTVEC(ioapic_intr42),
307 &IDTVEC(ioapic_intr43),
308 &IDTVEC(ioapic_intr44),
309 &IDTVEC(ioapic_intr45),
310 &IDTVEC(ioapic_intr46),
311 &IDTVEC(ioapic_intr47),
312 &IDTVEC(ioapic_intr48),
313 &IDTVEC(ioapic_intr49),
314 &IDTVEC(ioapic_intr50),
315 &IDTVEC(ioapic_intr51),
316 &IDTVEC(ioapic_intr52),
317 &IDTVEC(ioapic_intr53),
318 &IDTVEC(ioapic_intr54),
319 &IDTVEC(ioapic_intr55),
320 &IDTVEC(ioapic_intr56),
321 &IDTVEC(ioapic_intr57),
322 &IDTVEC(ioapic_intr58),
323 &IDTVEC(ioapic_intr59),
324 &IDTVEC(ioapic_intr60),
325 &IDTVEC(ioapic_intr61),
326 &IDTVEC(ioapic_intr62),
327 &IDTVEC(ioapic_intr63),
328 &IDTVEC(ioapic_intr64),
329 &IDTVEC(ioapic_intr65),
330 &IDTVEC(ioapic_intr66),
331 &IDTVEC(ioapic_intr67),
332 &IDTVEC(ioapic_intr68),
333 &IDTVEC(ioapic_intr69),
334 &IDTVEC(ioapic_intr70),
335 &IDTVEC(ioapic_intr71),
336 &IDTVEC(ioapic_intr72),
337 &IDTVEC(ioapic_intr73),
338 &IDTVEC(ioapic_intr74),
339 &IDTVEC(ioapic_intr75),
340 &IDTVEC(ioapic_intr76),
341 &IDTVEC(ioapic_intr77),
342 &IDTVEC(ioapic_intr78),
343 &IDTVEC(ioapic_intr79),
344 &IDTVEC(ioapic_intr80),
345 &IDTVEC(ioapic_intr81),
346 &IDTVEC(ioapic_intr82),
347 &IDTVEC(ioapic_intr83),
348 &IDTVEC(ioapic_intr84),
349 &IDTVEC(ioapic_intr85),
350 &IDTVEC(ioapic_intr86),
351 &IDTVEC(ioapic_intr87),
352 &IDTVEC(ioapic_intr88),
353 &IDTVEC(ioapic_intr89),
354 &IDTVEC(ioapic_intr90),
355 &IDTVEC(ioapic_intr91),
356 &IDTVEC(ioapic_intr92),
357 &IDTVEC(ioapic_intr93),
358 &IDTVEC(ioapic_intr94),
359 &IDTVEC(ioapic_intr95),
360 &IDTVEC(ioapic_intr96),
361 &IDTVEC(ioapic_intr97),
362 &IDTVEC(ioapic_intr98),
363 &IDTVEC(ioapic_intr99),
364 &IDTVEC(ioapic_intr100),
365 &IDTVEC(ioapic_intr101),
366 &IDTVEC(ioapic_intr102),
367 &IDTVEC(ioapic_intr103),
368 &IDTVEC(ioapic_intr104),
369 &IDTVEC(ioapic_intr105),
370 &IDTVEC(ioapic_intr106),
371 &IDTVEC(ioapic_intr107),
372 &IDTVEC(ioapic_intr108),
373 &IDTVEC(ioapic_intr109),
374 &IDTVEC(ioapic_intr110),
375 &IDTVEC(ioapic_intr111),
376 &IDTVEC(ioapic_intr112),
377 &IDTVEC(ioapic_intr113),
378 &IDTVEC(ioapic_intr114),
379 &IDTVEC(ioapic_intr115),
380 &IDTVEC(ioapic_intr116),
381 &IDTVEC(ioapic_intr117),
382 &IDTVEC(ioapic_intr118),
383 &IDTVEC(ioapic_intr119),
384 &IDTVEC(ioapic_intr120),
385 &IDTVEC(ioapic_intr121),
386 &IDTVEC(ioapic_intr122),
387 &IDTVEC(ioapic_intr123),
388 &IDTVEC(ioapic_intr124),
389 &IDTVEC(ioapic_intr125),
390 &IDTVEC(ioapic_intr126),
391 &IDTVEC(ioapic_intr127),
392 &IDTVEC(ioapic_intr128),
393 &IDTVEC(ioapic_intr129),
394 &IDTVEC(ioapic_intr130),
395 &IDTVEC(ioapic_intr131),
396 &IDTVEC(ioapic_intr132),
397 &IDTVEC(ioapic_intr133),
398 &IDTVEC(ioapic_intr134),
399 &IDTVEC(ioapic_intr135),
400 &IDTVEC(ioapic_intr136),
401 &IDTVEC(ioapic_intr137),
402 &IDTVEC(ioapic_intr138),
403 &IDTVEC(ioapic_intr139),
404 &IDTVEC(ioapic_intr140),
405 &IDTVEC(ioapic_intr141),
406 &IDTVEC(ioapic_intr142),
407 &IDTVEC(ioapic_intr143),
408 &IDTVEC(ioapic_intr144),
409 &IDTVEC(ioapic_intr145),
410 &IDTVEC(ioapic_intr146),
411 &IDTVEC(ioapic_intr147),
412 &IDTVEC(ioapic_intr148),
413 &IDTVEC(ioapic_intr149),
414 &IDTVEC(ioapic_intr150),
415 &IDTVEC(ioapic_intr151),
416 &IDTVEC(ioapic_intr152),
417 &IDTVEC(ioapic_intr153),
418 &IDTVEC(ioapic_intr154),
419 &IDTVEC(ioapic_intr155),
420 &IDTVEC(ioapic_intr156),
421 &IDTVEC(ioapic_intr157),
422 &IDTVEC(ioapic_intr158),
423 &IDTVEC(ioapic_intr159),
424 &IDTVEC(ioapic_intr160),
425 &IDTVEC(ioapic_intr161),
426 &IDTVEC(ioapic_intr162),
427 &IDTVEC(ioapic_intr163),
428 &IDTVEC(ioapic_intr164),
429 &IDTVEC(ioapic_intr165),
430 &IDTVEC(ioapic_intr166),
431 &IDTVEC(ioapic_intr167),
432 &IDTVEC(ioapic_intr168),
433 &IDTVEC(ioapic_intr169),
434 &IDTVEC(ioapic_intr170),
435 &IDTVEC(ioapic_intr171),
436 &IDTVEC(ioapic_intr172),
437 &IDTVEC(ioapic_intr173),
438 &IDTVEC(ioapic_intr174),
439 &IDTVEC(ioapic_intr175),
440 &IDTVEC(ioapic_intr176),
441 &IDTVEC(ioapic_intr177),
442 &IDTVEC(ioapic_intr178),
443 &IDTVEC(ioapic_intr179),
444 &IDTVEC(ioapic_intr180),
445 &IDTVEC(ioapic_intr181),
446 &IDTVEC(ioapic_intr182),
447 &IDTVEC(ioapic_intr183),
448 &IDTVEC(ioapic_intr184),
449 &IDTVEC(ioapic_intr185),
450 &IDTVEC(ioapic_intr186),
451 &IDTVEC(ioapic_intr187),
452 &IDTVEC(ioapic_intr188),
453 &IDTVEC(ioapic_intr189),
454 &IDTVEC(ioapic_intr190),
455 &IDTVEC(ioapic_intr191)
c571da4a 456};
c8fe38ae 457
474ba684
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458#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
459
a3dd9120
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460static struct ioapic_irqmap {
461 int im_type; /* IOAPIC_IMT_ */
462 enum intr_trigger im_trig;
f6915355 463 enum intr_polarity im_pola;
a3dd9120 464 int im_gsi;
d1ae7328 465 uint32_t im_flags; /* IOAPIC_IMF_ */
6f072945 466} ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
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467
468#define IOAPIC_IMT_UNUSED 0
469#define IOAPIC_IMT_RESERVED 1
470#define IOAPIC_IMT_LINE 2
474ba684 471#define IOAPIC_IMT_SYSCALL 3
a3dd9120 472
d1ae7328
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473#define IOAPIC_IMF_CONF 0x1
474
9e0e3f85
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475extern void IOAPIC_INTREN(int);
476extern void IOAPIC_INTRDIS(int);
477
85bcaa51
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478extern int imcr_present;
479
35b2edcb
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480static void ioapic_abi_intr_enable(int);
481static void ioapic_abi_intr_disable(int);
f416026e
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482static void ioapic_abi_intr_setup(int, int);
483static void ioapic_abi_intr_teardown(int);
aea76754
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484static void ioapic_abi_intr_config(int,
485 enum intr_trigger, enum intr_polarity);
a05c798c 486static int ioapic_abi_intr_cpuid(int);
35b2edcb 487
aea76754
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488static void ioapic_abi_finalize(void);
489static void ioapic_abi_cleanup(void);
490static void ioapic_abi_setdefault(void);
491static void ioapic_abi_stabilize(void);
492static void ioapic_abi_initmap(void);
9e0e3f85 493
95874ffd
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494static int ioapic_abi_gsi_cpuid(int, int);
495
9e0e3f85
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496struct machintr_abi MachIntrABI_IOAPIC = {
497 MACHINTR_IOAPIC,
35b2edcb
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498 .intr_disable = ioapic_abi_intr_disable,
499 .intr_enable = ioapic_abi_intr_enable,
f416026e
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500 .intr_setup = ioapic_abi_intr_setup,
501 .intr_teardown = ioapic_abi_intr_teardown,
aea76754 502 .intr_config = ioapic_abi_intr_config,
a05c798c 503 .intr_cpuid = ioapic_abi_intr_cpuid,
35b2edcb 504
aea76754
SZ
505 .finalize = ioapic_abi_finalize,
506 .cleanup = ioapic_abi_cleanup,
507 .setdefault = ioapic_abi_setdefault,
508 .stabilize = ioapic_abi_stabilize,
509 .initmap = ioapic_abi_initmap
c8fe38ae
MD
510};
511
6b809ec7 512static int ioapic_abi_extint_irq = -1;
bf2e6ffb 513static int ioapic_abi_line_irq_max;
6b809ec7 514
5ac5ccd2 515struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
566d27d4
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516
517static void
35b2edcb 518ioapic_abi_intr_enable(int irq)
566d27d4
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519{
520 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 521 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
566d27d4
SZ
522 return;
523 }
524 IOAPIC_INTREN(irq);
525}
526
527static void
35b2edcb 528ioapic_abi_intr_disable(int irq)
566d27d4
SZ
529{
530 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 531 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
566d27d4
SZ
532 return;
533 }
534 IOAPIC_INTRDIS(irq);
535}
536
c8fe38ae 537static void
aea76754 538ioapic_abi_finalize(void)
c8fe38ae 539{
e0918665 540 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 541 KKASSERT(ioapic_enable);
10db3cc6 542
339478ac
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543 /*
544 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 545 * from the BSP.
339478ac 546 */
9d758cc4 547 if (imcr_present) {
339478ac
SZ
548 outb(0x22, 0x70); /* select IMCR */
549 outb(0x23, 0x01); /* disconnect 8259 */
550 }
c8fe38ae
MD
551}
552
553/*
554 * This routine is called after physical interrupts are enabled but before
555 * the critical section is released. We need to clean out any interrupts
556 * that had already been posted to the cpu.
557 */
558static void
aea76754 559ioapic_abi_cleanup(void)
c8fe38ae 560{
9611ff20 561 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
c8fe38ae
MD
562}
563
7bf5fa56
SZ
564/* Must never be called */
565static void
aea76754 566ioapic_abi_stabilize(void)
7bf5fa56
SZ
567{
568 panic("ioapic_stabilize is called\n");
569}
570
f416026e
SZ
571static void
572ioapic_abi_intr_setup(int intr, int flags)
c8fe38ae 573{
f416026e 574 int vector, select;
339478ac 575 uint32_t value;
7bf5fa56 576 register_t ef;
c8fe38ae 577
f416026e
SZ
578 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
579 intr != IOAPIC_HWI_SYSCALL);
580 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
581
582 ef = read_rflags();
583 cpu_disable_intr();
584
585 vector = IDT_OFFSET + intr;
f416026e
SZ
586
587 /*
588 * Now reprogram the vector in the IO APIC. In order to avoid
589 * losing an EOI for a level interrupt, which is vector based,
590 * make sure that the IO APIC is programmed for edge-triggering
591 * first, then reprogrammed with the new vector. This should
592 * clear the IRR bit.
593 */
594 imen_lock();
595
596 select = ioapic_irqs[intr].io_idx;
597 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
598 value |= IOART_INTMSET;
599
600 ioapic_write(ioapic_irqs[intr].io_addr, select,
601 (value & ~APIC_TRIGMOD_MASK));
602 ioapic_write(ioapic_irqs[intr].io_addr, select,
603 (value & ~IOART_INTVEC) | vector);
604
605 imen_unlock();
606
35b2edcb 607 machintr_intr_enable(intr);
c8fe38ae 608
f416026e
SZ
609 write_rflags(ef);
610}
611
612static void
613ioapic_abi_intr_teardown(int intr)
614{
615 int vector, select;
616 uint32_t value;
617 register_t ef;
618
619 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
620 intr != IOAPIC_HWI_SYSCALL);
621 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
5ac5ccd2 622
339478ac
SZ
623 ef = read_rflags();
624 cpu_disable_intr();
f416026e
SZ
625
626 /*
627 * Teardown an interrupt vector. The vector should already be
628 * installed in the cpu's IDT, but make sure.
629 */
35b2edcb 630 machintr_intr_disable(intr);
f416026e
SZ
631
632 vector = IDT_OFFSET + intr;
f416026e
SZ
633
634 /*
635 * In order to avoid losing an EOI for a level interrupt, which
636 * is vector based, make sure that the IO APIC is programmed for
637 * edge-triggering first, then reprogrammed with the new vector.
638 * This should clear the IRR bit.
639 */
640 imen_lock();
641
642 select = ioapic_irqs[intr].io_idx;
643 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
644
645 ioapic_write(ioapic_irqs[intr].io_addr, select,
646 (value & ~APIC_TRIGMOD_MASK));
647 ioapic_write(ioapic_irqs[intr].io_addr, select,
648 (value & ~IOART_INTVEC) | vector);
649
650 imen_unlock();
c8fe38ae 651
339478ac 652 write_rflags(ef);
339478ac 653}
c8fe38ae 654
10db3cc6 655static void
aea76754 656ioapic_abi_setdefault(void)
10db3cc6
SZ
657{
658 int intr;
659
9e0e3f85 660 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 661 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 662 continue;
9e0e3f85 663 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
10db3cc6
SZ
664 SEL_KPL, 0);
665 }
666}
667
a3dd9120 668static void
aea76754 669ioapic_abi_initmap(void)
a3dd9120 670{
6f072945 671 int cpu;
a3dd9120 672
6f072945
SZ
673 /*
674 * NOTE: ncpus is not ready yet
675 */
676 for (cpu = 0; cpu < MAXCPU; ++cpu) {
677 int i;
678
679 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
680 ioapic_irqmaps[cpu][i].im_gsi = -1;
681 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
682 IOAPIC_IMT_SYSCALL;
683 }
a3dd9120
SZ
684}
685
929c940f
SZ
686void
687ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
688 enum intr_polarity pola)
689{
5ac5ccd2 690 struct ioapic_irqinfo *info;
929c940f
SZ
691 struct ioapic_irqmap *map;
692 void *ioaddr;
95874ffd 693 int pin, cpuid;
929c940f
SZ
694
695 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
696 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
697
698 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
bf2e6ffb
SZ
699 if (irq > ioapic_abi_line_irq_max)
700 ioapic_abi_line_irq_max = irq;
701
6f072945
SZ
702 cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
703
704 map = &ioapic_irqmaps[cpuid][irq];
929c940f
SZ
705
706 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
707 map->im_type = IOAPIC_IMT_LINE;
708
709 map->im_gsi = gsi;
710 map->im_trig = trig;
711 map->im_pola = pola;
712
713 if (bootverbose) {
4ecd5d4d
SZ
714 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
715 irq, map->im_gsi,
716 intr_str_trigger(map->im_trig),
717 intr_str_polarity(map->im_pola));
929c940f
SZ
718 }
719
d1ae7328
SZ
720 pin = ioapic_gsi_pin(map->im_gsi);
721 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 722
5ac5ccd2 723 info = &ioapic_irqs[irq];
929c940f 724
7bceaa10
SZ
725 imen_lock();
726
5ac5ccd2
SZ
727 info->io_addr = ioaddr;
728 info->io_idx = IOAPIC_REDTBL + (2 * pin);
729 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 730 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 731 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ
732
733 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 734 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
735
736 imen_unlock();
d1ae7328
SZ
737}
738
4a913811
SZ
739void
740ioapic_abi_fixup_irqmap(void)
741{
6f072945
SZ
742 int cpu;
743
744 for (cpu = 0; cpu < ncpus; ++cpu) {
745 int i;
4a913811 746
6f072945
SZ
747 for (i = 0; i < ISA_IRQ_CNT; ++i) {
748 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
4a913811 749
6f072945
SZ
750 if (map->im_type == IOAPIC_IMT_UNUSED) {
751 map->im_type = IOAPIC_IMT_RESERVED;
752 if (bootverbose) {
753 kprintf("IOAPIC: "
754 "cpu%d irq %d reserved\n", cpu, i);
755 }
756 }
4a913811
SZ
757 }
758 }
6f072945 759
bf2e6ffb
SZ
760 ioapic_abi_line_irq_max += 1;
761 if (bootverbose)
762 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
4a913811
SZ
763}
764
e90e7ac4
SZ
765int
766ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
767{
6f072945 768 int cpu;
e90e7ac4
SZ
769
770 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
771 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 772
6f072945
SZ
773 for (cpu = 0; cpu < ncpus; ++cpu) {
774 int irq;
e90e7ac4 775
6f072945
SZ
776 for (irq = 0; irq < ioapic_abi_line_irq_max; ++irq) {
777 const struct ioapic_irqmap *map =
778 &ioapic_irqmaps[cpu][irq];
e90e7ac4 779
6f072945
SZ
780 if (map->im_gsi == gsi) {
781 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
782
783 if (map->im_flags & IOAPIC_IMF_CONF) {
784 if (map->im_trig != trig ||
785 map->im_pola != pola)
786 return -1;
787 }
788 return irq;
e90e7ac4 789 }
e90e7ac4
SZ
790 }
791 }
792 return -1;
793}
794
795int
796ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
797{
6f072945 798 int cpu;
e90e7ac4
SZ
799
800 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
801 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 802
6f072945 803 if (irq < 0 || irq >= ioapic_abi_line_irq_max)
e90e7ac4 804 return -1;
e90e7ac4 805
6f072945
SZ
806 for (cpu = 0; cpu < ncpus; ++cpu) {
807 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
e90e7ac4 808
6f072945
SZ
809 if (map->im_type == IOAPIC_IMT_LINE) {
810 if (map->im_flags & IOAPIC_IMF_CONF) {
811 if (map->im_trig != trig ||
812 map->im_pola != pola)
813 return -1;
814 }
815 return irq;
816 }
e90e7ac4 817 }
6f072945 818 return -1;
e90e7ac4
SZ
819}
820
d1ae7328 821static void
aea76754 822ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
d1ae7328 823{
5ac5ccd2 824 struct ioapic_irqinfo *info;
6f072945 825 struct ioapic_irqmap *map = NULL;
d1ae7328 826 void *ioaddr;
95874ffd 827 int pin, cpuid;
d1ae7328 828
d1ae7328
SZ
829 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
830 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328 831
6f072945
SZ
832 KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
833 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
834 map = &ioapic_irqmaps[cpuid][irq];
835 if (map->im_type == IOAPIC_IMT_LINE)
836 break;
837 }
838 KKASSERT(cpuid < ncpus);
d1ae7328 839
7962296e 840#ifdef notyet
d1ae7328
SZ
841 if (map->im_flags & IOAPIC_IMF_CONF) {
842 if (trig != map->im_trig) {
4ecd5d4d
SZ
843 panic("ioapic_intr_config: trig %s -> %s\n",
844 intr_str_trigger(map->im_trig),
845 intr_str_trigger(trig));
d1ae7328
SZ
846 }
847 if (pola != map->im_pola) {
848 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ
849 intr_str_polarity(map->im_pola),
850 intr_str_polarity(pola));
d1ae7328
SZ
851 }
852 return;
853 }
7962296e 854#endif
d1ae7328
SZ
855 map->im_flags |= IOAPIC_IMF_CONF;
856
857 if (trig == map->im_trig && pola == map->im_pola)
858 return;
859
860 if (bootverbose) {
4ecd5d4d
SZ
861 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
862 irq, map->im_gsi,
863 intr_str_trigger(map->im_trig),
864 intr_str_polarity(map->im_pola),
865 intr_str_trigger(trig),
866 intr_str_polarity(pola));
d1ae7328 867 }
d1ae7328
SZ
868 map->im_trig = trig;
869 map->im_pola = pola;
870
871 pin = ioapic_gsi_pin(map->im_gsi);
872 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
873
5ac5ccd2 874 info = &ioapic_irqs[irq];
d1ae7328 875
7bceaa10
SZ
876 imen_lock();
877
5ac5ccd2 878 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 879 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 880 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 881
ecec8ddc 882 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 883 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
884
885 imen_unlock();
929c940f
SZ
886}
887
6b809ec7
SZ
888int
889ioapic_abi_extint_irqmap(int irq)
890{
5ac5ccd2 891 struct ioapic_irqinfo *info;
6b809ec7
SZ
892 struct ioapic_irqmap *map;
893 void *ioaddr;
894 int pin, error, vec;
895
95874ffd
SZ
896 /* XXX only irq0 is allowed */
897 KKASSERT(irq == 0);
898
6b809ec7
SZ
899 vec = IDT_OFFSET + irq;
900
901 if (ioapic_abi_extint_irq == irq)
902 return 0;
903 else if (ioapic_abi_extint_irq >= 0)
904 return EEXIST;
905
906 error = icu_ioapic_extint(irq, vec);
907 if (error)
908 return error;
909
6f072945
SZ
910 /* ExtINT is always targeted to cpu0 */
911 map = &ioapic_irqmaps[0][irq];
6b809ec7
SZ
912
913 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
914 map->im_type == IOAPIC_IMT_LINE);
915 if (map->im_type == IOAPIC_IMT_LINE) {
916 if (map->im_flags & IOAPIC_IMF_CONF)
917 return EEXIST;
918 }
919 ioapic_abi_extint_irq = irq;
920
921 map->im_type = IOAPIC_IMT_LINE;
922 map->im_trig = INTR_TRIGGER_EDGE;
923 map->im_pola = INTR_POLARITY_HIGH;
924 map->im_flags = IOAPIC_IMF_CONF;
925
926 map->im_gsi = ioapic_extpin_gsi();
927 KKASSERT(map->im_gsi >= 0);
928
929 if (bootverbose) {
4ecd5d4d
SZ
930 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
931 irq, map->im_gsi,
932 intr_str_trigger(map->im_trig),
933 intr_str_polarity(map->im_pola));
6b809ec7
SZ
934 }
935
936 pin = ioapic_gsi_pin(map->im_gsi);
937 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
938
5ac5ccd2 939 info = &ioapic_irqs[irq];
6b809ec7
SZ
940
941 imen_lock();
942
5ac5ccd2
SZ
943 info->io_addr = ioaddr;
944 info->io_idx = IOAPIC_REDTBL + (2 * pin);
945 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
946
947 ioapic_extpin_setup(ioaddr, pin, vec);
948
949 imen_unlock();
950
951 return 0;
952}
a05c798c
SZ
953
954static int
95874ffd 955ioapic_abi_intr_cpuid(int irq)
a05c798c 956{
6f072945
SZ
957 const struct ioapic_irqmap *map = NULL;
958 int cpuid;
95874ffd 959
6f072945 960 KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
95874ffd 961
6f072945
SZ
962 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
963 map = &ioapic_irqmaps[cpuid][irq];
964 if (map->im_type == IOAPIC_IMT_LINE)
965 return cpuid;
95874ffd
SZ
966 }
967
6f072945
SZ
968 /* XXX some drivers tries to peek at reserved IRQs */
969 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
970 map = &ioapic_irqmaps[cpuid][irq];
971 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
972 }
973 return 0;
95874ffd
SZ
974}
975
976static int
977ioapic_abi_gsi_cpuid(int irq, int gsi)
978{
979 char envpath[32];
980 int cpuid = -1;
981
982 KKASSERT(gsi >= 0);
983
984 if (irq == 0 || gsi == 0) {
621d2ccf
SZ
985 if (bootverbose) {
986 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
987 irq, gsi);
988 }
95874ffd
SZ
989 return 0;
990 }
991
992 if (irq == acpi_sci_irqno()) {
621d2ccf
SZ
993 if (bootverbose) {
994 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
995 irq, gsi);
996 }
95874ffd
SZ
997 return 0;
998 }
999
1000 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1001 kgetenv_int(envpath, &cpuid);
1002
1003 if (cpuid < 0) {
1004 cpuid = gsi % ncpus;
621d2ccf
SZ
1005 if (bootverbose) {
1006 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1007 irq, gsi, cpuid);
1008 }
95874ffd
SZ
1009 } else if (cpuid >= ncpus) {
1010 cpuid = ncpus - 1;
621d2ccf
SZ
1011 if (bootverbose) {
1012 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1013 irq, gsi, cpuid);
1014 }
95874ffd 1015 } else {
621d2ccf
SZ
1016 if (bootverbose) {
1017 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1018 irq, gsi, cpuid);
1019 }
95874ffd
SZ
1020 }
1021 return cpuid;
a05c798c 1022}