kernel - Rewrite the x86-64 pmap code
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
45#include "opt_atalk.h"
46#include "opt_compat.h"
47#include "opt_cpu.h"
48#include "opt_ddb.h"
49#include "opt_directio.h"
50#include "opt_inet.h"
51#include "opt_ipx.h"
52#include "opt_msgbuf.h"
53#include "opt_swap.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sysproto.h>
58#include <sys/signalvar.h>
59#include <sys/kernel.h>
60#include <sys/linker.h>
61#include <sys/malloc.h>
62#include <sys/proc.h>
895c1f85 63#include <sys/priv.h>
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64#include <sys/buf.h>
65#include <sys/reboot.h>
66#include <sys/mbuf.h>
67#include <sys/msgbuf.h>
68#include <sys/sysent.h>
69#include <sys/sysctl.h>
70#include <sys/vmmeter.h>
71#include <sys/bus.h>
72#include <sys/upcall.h>
73#include <sys/usched.h>
74#include <sys/reg.h>
75
76#include <vm/vm.h>
77#include <vm/vm_param.h>
78#include <sys/lock.h>
79#include <vm/vm_kern.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_map.h>
83#include <vm/vm_pager.h>
84#include <vm/vm_extern.h>
85
86#include <sys/thread2.h>
684a93c4 87#include <sys/mplock2.h>
320c681e 88#include <sys/mutex2.h>
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89
90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
96#include <machine/cpu.h>
97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#if JG
100#include <machine/bootinfo.h>
101#endif
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102#include <machine/md_var.h>
103#include <machine/metadata.h>
104#include <machine/pc/bios.h>
105#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
106#include <machine/globaldata.h> /* CPU_prvspace */
107#include <machine/smp.h>
108#ifdef PERFMON
109#include <machine/perfmon.h>
110#endif
111#include <machine/cputypes.h>
57a9c56b 112#include <machine/intr_machdep.h>
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113
114#ifdef OLD_BUS_ARCH
46d4e165 115#include <bus/isa/isa_device.h>
c8fe38ae 116#endif
57a9c56b 117#include <machine_base/isa/isa_intr.h>
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118#include <bus/isa/rtc.h>
119#include <sys/random.h>
120#include <sys/ptrace.h>
121#include <machine/sigframe.h>
122
faaf4131 123#include <sys/machintr.h>
9284cddf 124#include <machine_base/icu/icu_abi.h>
7265a4fe 125#include <machine_base/icu/elcr_var.h>
2e0ed166 126#include <machine_base/apic/lapic.h>
ed4d621d 127#include <machine_base/apic/ioapic.h>
a3dd9120 128#include <machine_base/apic/ioapic_abi.h>
8cc9a8d1 129#include <machine/mptable.h>
faaf4131 130
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131#define PHYSMAP_ENTRIES 10
132
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133extern u_int64_t hammer_time(u_int64_t, u_int64_t);
134
135extern void printcpuinfo(void); /* XXX header file */
136extern void identify_cpu(void);
137#if JG
138extern void finishidentcpu(void);
139#endif
140extern void panicifcpuunsupported(void);
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141
142static void cpu_startup(void *);
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143static void pic_finish(void *);
144static void cpu_finish(void *);
145
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146#ifndef CPU_DISABLE_SSE
147static void set_fpregs_xmm(struct save87 *, struct savexmm *);
148static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
149#endif /* CPU_DISABLE_SSE */
150#ifdef DIRECTIO
151extern void ffs_rawread_setup(void);
152#endif /* DIRECTIO */
153static void init_locks(void);
154
7c006a9e 155SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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156SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
157SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
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158
159#ifdef DDB
160extern vm_offset_t ksym_start, ksym_end;
161#endif
162
da23a592 163struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 164
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165int _udatasel, _ucodesel, _ucode32sel;
166u_long atdevbase;
167#ifdef SMP
168int64_t tsc_offsets[MAXCPU];
169#else
170int64_t tsc_offsets[1];
171#endif
172
173#if defined(SWTCH_OPTIM_STATS)
174extern int swtch_optim_stats;
175SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
179#endif
180
39d69dae 181long physmem = 0;
c8fe38ae 182
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183u_long ebda_addr = 0;
184
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185int imcr_present = 0;
186
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187int naps = 0; /* # of Applications processors */
188
8936cd9b 189u_int base_memory;
320c681e 190struct mtx dt_lock; /* lock for GDT and LDT */
8936cd9b 191
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192static int
193sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
194{
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195 u_long pmem = ctob(physmem);
196
197 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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198 return (error);
199}
200
39d69dae 201SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 202 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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203
204static int
205sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
206{
207 int error = sysctl_handle_int(oidp, 0,
208 ctob(physmem - vmstats.v_wire_count), req);
209 return (error);
210}
211
212SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
213 0, 0, sysctl_hw_usermem, "IU", "");
214
215static int
216sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
217{
c8fe38ae 218 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 219 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 220 return (error);
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221}
222
223SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
224 0, 0, sysctl_hw_availpages, "I", "");
225
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226vm_paddr_t Maxmem;
227vm_paddr_t Realmem;
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228
229/*
230 * The number of PHYSMAP entries must be one less than the number of
231 * PHYSSEG entries because the PHYSMAP entry that spans the largest
232 * physical address that is accessible by ISA DMA is split into two
233 * PHYSSEG entries.
234 */
235#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
236
237vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
238vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
239
240/* must be 2 less so 0 0 can signal end of chunks */
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241#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
242#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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243
244static vm_offset_t buffer_sva, buffer_eva;
245vm_offset_t clean_sva, clean_eva;
246static vm_offset_t pager_sva, pager_eva;
247static struct trapframe proc0_tf;
248
249static void
250cpu_startup(void *dummy)
251{
252 caddr_t v;
253 vm_size_t size = 0;
254 vm_offset_t firstaddr;
255
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256 /*
257 * Good {morning,afternoon,evening,night}.
258 */
259 kprintf("%s", version);
260 startrtclock();
261 printcpuinfo();
262 panicifcpuunsupported();
263#ifdef PERFMON
264 perfmon_init();
265#endif
15dc6550 266 kprintf("real memory = %ju (%ju MB)\n",
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267 (intmax_t)Realmem,
268 (intmax_t)Realmem / 1024 / 1024);
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269 /*
270 * Display any holes after the first chunk of extended memory.
271 */
272 if (bootverbose) {
273 int indx;
274
275 kprintf("Physical memory chunk(s):\n");
276 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
277 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
278
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279 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
280 (intmax_t)phys_avail[indx],
281 (intmax_t)phys_avail[indx + 1] - 1,
282 (intmax_t)size1,
283 (intmax_t)(size1 / PAGE_SIZE));
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284 }
285 }
286
287 /*
288 * Allocate space for system data structures.
289 * The first available kernel virtual address is in "v".
290 * As pages of kernel virtual memory are allocated, "v" is incremented.
291 * As pages of memory are allocated and cleared,
292 * "firstaddr" is incremented.
293 * An index into the kernel page table corresponding to the
294 * virtual memory address maintained in "v" is kept in "mapaddr".
295 */
296
297 /*
298 * Make two passes. The first pass calculates how much memory is
299 * needed and allocates it. The second pass assigns virtual
300 * addresses to the various data structures.
301 */
302 firstaddr = 0;
303again:
304 v = (caddr_t)firstaddr;
305
306#define valloc(name, type, num) \
307 (name) = (type *)v; v = (caddr_t)((name)+(num))
308#define valloclim(name, type, num, lim) \
309 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
310
311 /*
312 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
313 * For the first 64MB of ram nominally allocate sufficient buffers to
314 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
315 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
316 * the buffer cache we limit the eventual kva reservation to
317 * maxbcache bytes.
318 *
319 * factor represents the 1/4 x ram conversion.
320 */
321 if (nbuf == 0) {
322 int factor = 4 * BKVASIZE / 1024;
323 int kbytes = physmem * (PAGE_SIZE / 1024);
324
325 nbuf = 50;
326 if (kbytes > 4096)
327 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
328 if (kbytes > 65536)
329 nbuf += (kbytes - 65536) * 2 / (factor * 5);
330 if (maxbcache && nbuf > maxbcache / BKVASIZE)
331 nbuf = maxbcache / BKVASIZE;
332 }
333
334 /*
335 * Do not allow the buffer_map to be more then 1/2 the size of the
336 * kernel_map.
337 */
338 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
339 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
340 kprintf("Warning: nbufs capped at %d\n", nbuf);
341 }
342
343 nswbuf = max(min(nbuf/4, 256), 16);
344#ifdef NSWBUF_MIN
345 if (nswbuf < NSWBUF_MIN)
346 nswbuf = NSWBUF_MIN;
347#endif
348#ifdef DIRECTIO
349 ffs_rawread_setup();
350#endif
351
352 valloc(swbuf, struct buf, nswbuf);
353 valloc(buf, struct buf, nbuf);
354
355 /*
356 * End of first pass, size has been calculated so allocate memory
357 */
358 if (firstaddr == 0) {
359 size = (vm_size_t)(v - firstaddr);
360 firstaddr = kmem_alloc(&kernel_map, round_page(size));
361 if (firstaddr == 0)
362 panic("startup: no room for tables");
363 goto again;
364 }
365
366 /*
367 * End of second pass, addresses have been assigned
368 */
369 if ((vm_size_t)(v - firstaddr) != size)
370 panic("startup: table size inconsistency");
371
372 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
373 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
374 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
375 (nbuf*BKVASIZE));
376 buffer_map.system_map = 1;
377 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
378 (nswbuf*MAXPHYS) + pager_map_size);
379 pager_map.system_map = 1;
380
381#if defined(USERCONFIG)
382 userconfig();
383 cninit(); /* the preferred console may have changed */
384#endif
385
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386 kprintf("avail memory = %ju (%ju MB)\n",
387 (uintmax_t)ptoa(vmstats.v_free_count),
388 (uintmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
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389
390 /*
391 * Set up buffers, so they can be used to read disk labels.
392 */
393 bufinit();
394 vm_pager_bufferinit();
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395}
396
397static void
398cpu_finish(void *dummy __unused)
399{
400 cpu_setregs();
401}
402
403static void
404pic_finish(void *dummy __unused)
405{
406 /* Log ELCR information */
407 elcr_dump();
8dc88f05 408
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409 /* Log MPTABLE information */
410 mptable_pci_int_dump();
411
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412 /* Finalize PCI */
413 MachIntrABI.finalize();
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414}
415
416/*
417 * Send an interrupt to process.
418 *
419 * Stack is set up to allow sigcode stored
420 * at top to call routine, followed by kcall
421 * to sigreturn routine below. After sigreturn
422 * resets the signal mask, the stack, and the
423 * frame pointer, it returns to the user
424 * specified pc, psl.
425 */
426void
427sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
428{
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429 struct lwp *lp = curthread->td_lwp;
430 struct proc *p = lp->lwp_proc;
431 struct trapframe *regs;
432 struct sigacts *psp = p->p_sigacts;
433 struct sigframe sf, *sfp;
434 int oonstack;
a6a09809 435 char *sp;
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436
437 regs = lp->lwp_md.md_regs;
438 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
439
a6a09809 440 /* Save user context */
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441 bzero(&sf, sizeof(struct sigframe));
442 sf.sf_uc.uc_sigmask = *mask;
443 sf.sf_uc.uc_stack = lp->lwp_sigstk;
444 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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445 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
446 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 447
a6a09809 448 /* Make the size of the saved context visible to userland */
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449 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
450
a6a09809 451 /* Save mailbox pending state for syscall interlock semantics */
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452 if (p->p_flag & P_MAILBOX)
453 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
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454
455 /* Allocate and validate space for the signal handler context. */
456 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
457 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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458 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
459 sizeof(struct sigframe));
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460 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
461 } else {
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462 /* We take red zone into account */
463 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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464 }
465
a6a09809 466 /* Align to 16 bytes */
4117f2fd 467 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 468
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469 /* Translate the signal is appropriate */
470 if (p->p_sysent->sv_sigtbl) {
471 if (sig <= p->p_sysent->sv_sigsize)
472 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
473 }
474
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475 /*
476 * Build the argument list for the signal handler.
477 *
478 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
479 */
480 regs->tf_rdi = sig; /* argument 1 */
481 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
482
c8fe38ae 483 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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484 /*
485 * Signal handler installed with SA_SIGINFO.
486 *
487 * action(signo, siginfo, ucontext)
488 */
489 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 490 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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491 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
492
493 /* fill siginfo structure */
494 sf.sf_si.si_signo = sig;
495 sf.sf_si.si_code = code;
630d9ab4 496 sf.sf_si.si_addr = (void *)regs->tf_addr;
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497 } else {
498 /*
499 * Old FreeBSD-style arguments.
500 *
501 * handler (signo, code, [uc], addr)
502 */
503 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 504 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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505 sf.sf_ahu.sf_handler = catcher;
506 }
507
508 /*
509 * If we're a vm86 process, we want to save the segment registers.
510 * We also change eflags to be our emulated eflags, not the actual
511 * eflags.
512 */
513#if JG
514 if (regs->tf_eflags & PSL_VM) {
515 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
516 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
517
518 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
519 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
520 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
521 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
522
523 if (vm86->vm86_has_vme == 0)
524 sf.sf_uc.uc_mcontext.mc_eflags =
525 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
526 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
527
528 /*
529 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
530 * syscalls made by the signal handler. This just avoids
531 * wasting time for our lazy fixup of such faults. PSL_NT
532 * does nothing in vm86 mode, but vm86 programs can set it
533 * almost legitimately in probes for old cpu types.
534 */
535 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
536 }
537#endif
538
539 /*
540 * Save the FPU state and reinit the FP unit
541 */
c8fe38ae 542 npxpush(&sf.sf_uc.uc_mcontext);
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543
544 /*
545 * Copy the sigframe out to the user's stack.
546 */
547 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
548 /*
549 * Something is wrong with the stack pointer.
550 * ...Kill the process.
551 */
552 sigexit(lp, SIGILL);
553 }
554
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555 regs->tf_rsp = (register_t)sfp;
556 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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557
558 /*
559 * i386 abi specifies that the direction flag must be cleared
560 * on function entry
561 */
5b9f6cc4 562 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 563
c8fe38ae 564 /*
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565 * 64 bit mode has a code and stack selector but
566 * no data or extra selector. %fs and %gs are not
567 * stored in-context.
c8fe38ae 568 */
a6a09809 569 regs->tf_cs = _ucodesel;
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570 regs->tf_ss = _udatasel;
571}
572
573/*
574 * Sanitize the trapframe for a virtual kernel passing control to a custom
575 * VM context. Remove any items that would otherwise create a privilage
576 * issue.
577 *
578 * XXX at the moment we allow userland to set the resume flag. Is this a
579 * bad idea?
580 */
581int
582cpu_sanitize_frame(struct trapframe *frame)
583{
c8fe38ae 584 frame->tf_cs = _ucodesel;
c8fe38ae 585 frame->tf_ss = _udatasel;
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586 /* XXX VM (8086) mode not supported? */
587 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
588 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
589
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590 return(0);
591}
592
593/*
594 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 595 * on us. For x86_64 we don't have to do anything.
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596 */
597int
598cpu_sanitize_tls(struct savetls *tls)
599{
600 return(0);
601}
602
603/*
604 * sigreturn(ucontext_t *sigcntxp)
605 *
606 * System call to cleanup state after a signal
607 * has been taken. Reset signal mask and
608 * stack state from context left by sendsig (above).
609 * Return to previous pc and psl as specified by
610 * context left by sendsig. Check carefully to
611 * make sure that the user has not modified the
612 * state to gain improper privileges.
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613 *
614 * MPSAFE
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615 */
616#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
617#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
618
619int
620sys_sigreturn(struct sigreturn_args *uap)
621{
622 struct lwp *lp = curthread->td_lwp;
623 struct proc *p = lp->lwp_proc;
624 struct trapframe *regs;
625 ucontext_t uc;
626 ucontext_t *ucp;
5b9f6cc4 627 register_t rflags;
c8fe38ae 628 int cs;
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629 int error;
630
631 /*
632 * We have to copy the information into kernel space so userland
633 * can't modify it while we are sniffing it.
634 */
635 regs = lp->lwp_md.md_regs;
636 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
637 if (error)
638 return (error);
639 ucp = &uc;
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640 rflags = ucp->uc_mcontext.mc_rflags;
641
642 /* VM (8086) mode not supported */
643 rflags &= ~PSL_VM_UNSUPP;
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644
645#if JG
646 if (eflags & PSL_VM) {
647 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
648 struct vm86_kernel *vm86;
649
650 /*
651 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
652 * set up the vm86 area, and we can't enter vm86 mode.
653 */
654 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
655 return (EINVAL);
656 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
657 if (vm86->vm86_inited == 0)
658 return (EINVAL);
659
660 /* go back to user mode if both flags are set */
661 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
662 trapsignal(lp, SIGBUS, 0);
663
664 if (vm86->vm86_has_vme) {
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665 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
666 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 667 } else {
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668 vm86->vm86_eflags = eflags; /* save VIF, VIP */
669 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
670 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 671 }
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672 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
673 tf->tf_eflags = eflags;
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674 tf->tf_vm86_ds = tf->tf_ds;
675 tf->tf_vm86_es = tf->tf_es;
676 tf->tf_vm86_fs = tf->tf_fs;
677 tf->tf_vm86_gs = tf->tf_gs;
678 tf->tf_ds = _udatasel;
679 tf->tf_es = _udatasel;
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680 tf->tf_fs = _udatasel;
681 tf->tf_gs = _udatasel;
5b9f6cc4 682 } else
c8fe38ae 683#endif
5b9f6cc4 684 {
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685 /*
686 * Don't allow users to change privileged or reserved flags.
687 */
688 /*
689 * XXX do allow users to change the privileged flag PSL_RF.
690 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
691 * should sometimes set it there too. tf_eflags is kept in
692 * the signal context during signal handling and there is no
693 * other place to remember it, so the PSL_RF bit may be
694 * corrupted by the signal handler without us knowing.
695 * Corruption of the PSL_RF bit at worst causes one more or
696 * one less debugger trap, so allowing it is fairly harmless.
697 */
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698 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
699 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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700 return(EINVAL);
701 }
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702
703 /*
704 * Don't allow users to load a valid privileged %cs. Let the
705 * hardware check for invalid selectors, excess privilege in
706 * other selectors, invalid %eip's and invalid %esp's.
707 */
708 cs = ucp->uc_mcontext.mc_cs;
709 if (!CS_SECURE(cs)) {
710 kprintf("sigreturn: cs = 0x%x\n", cs);
711 trapsignal(lp, SIGBUS, T_PROTFLT);
712 return(EINVAL);
713 }
5b9f6cc4 714 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 715 }
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716
717 /*
718 * Restore the FPU state from the frame
719 */
3919ced0 720 crit_enter();
c8fe38ae 721 npxpop(&ucp->uc_mcontext);
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722
723 /*
724 * Merge saved signal mailbox pending flag to maintain interlock
725 * semantics against system calls.
726 */
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727 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
728 p->p_flag |= P_MAILBOX;
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729
730 if (ucp->uc_mcontext.mc_onstack & 1)
731 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
732 else
733 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
734
735 lp->lwp_sigmask = ucp->uc_sigmask;
736 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 737 crit_exit();
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738 return(EJUSTRETURN);
739}
740
741/*
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742 * Stack frame on entry to function. %rax will contain the function vector,
743 * %rcx will contain the function data. flags, rcx, and rax will have
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744 * already been pushed on the stack.
745 */
746struct upc_frame {
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747 register_t rax;
748 register_t rcx;
749 register_t rdx;
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750 register_t flags;
751 register_t oldip;
752};
753
754void
755sendupcall(struct vmupcall *vu, int morepending)
756{
757 struct lwp *lp = curthread->td_lwp;
758 struct trapframe *regs;
759 struct upcall upcall;
760 struct upc_frame upc_frame;
761 int crit_count = 0;
762
763 /*
764 * If we are a virtual kernel running an emulated user process
765 * context, switch back to the virtual kernel context before
766 * trying to post the signal.
767 */
768 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
769 lp->lwp_md.md_regs->tf_trapno = 0;
770 vkernel_trap(lp, lp->lwp_md.md_regs);
771 }
772
773 /*
774 * Get the upcall data structure
775 */
776 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
777 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
778 ) {
779 vu->vu_pending = 0;
780 kprintf("bad upcall address\n");
781 return;
782 }
783
784 /*
785 * If the data structure is already marked pending or has a critical
786 * section count, mark the data structure as pending and return
787 * without doing an upcall. vu_pending is left set.
788 */
789 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
790 if (upcall.upc_pending < vu->vu_pending) {
791 upcall.upc_pending = vu->vu_pending;
792 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
793 sizeof(upcall.upc_pending));
794 }
795 return;
796 }
797
798 /*
799 * We can run this upcall now, clear vu_pending.
800 *
801 * Bump our critical section count and set or clear the
802 * user pending flag depending on whether more upcalls are
803 * pending. The user will be responsible for calling
804 * upc_dispatch(-1) to process remaining upcalls.
805 */
806 vu->vu_pending = 0;
807 upcall.upc_pending = morepending;
f9235b6d 808 ++crit_count;
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809 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
810 sizeof(upcall.upc_pending));
811 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
812 sizeof(int));
813
814 /*
815 * Construct a stack frame and issue the upcall
816 */
817 regs = lp->lwp_md.md_regs;
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818 upc_frame.rax = regs->tf_rax;
819 upc_frame.rcx = regs->tf_rcx;
820 upc_frame.rdx = regs->tf_rdx;
821 upc_frame.flags = regs->tf_rflags;
822 upc_frame.oldip = regs->tf_rip;
823 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame)),
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824 sizeof(upc_frame)) != 0) {
825 kprintf("bad stack on upcall\n");
826 } else {
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827 regs->tf_rax = (register_t)vu->vu_func;
828 regs->tf_rcx = (register_t)vu->vu_data;
829 regs->tf_rdx = (register_t)lp->lwp_upcall;
830 regs->tf_rip = (register_t)vu->vu_ctx;
831 regs->tf_rsp -= sizeof(upc_frame);
c8fe38ae 832 }
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833}
834
835/*
836 * fetchupcall occurs in the context of a system call, which means that
837 * we have to return EJUSTRETURN in order to prevent eax and edx from
838 * being overwritten by the syscall return value.
839 *
840 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
841 * and the function pointer in %eax.
842 */
843int
844fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
845{
846 struct upc_frame upc_frame;
847 struct lwp *lp = curthread->td_lwp;
848 struct trapframe *regs;
849 int error;
850 struct upcall upcall;
851 int crit_count;
852
853 regs = lp->lwp_md.md_regs;
854
855 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
856 if (error == 0) {
857 if (vu) {
858 /*
859 * This jumps us to the next ready context.
860 */
861 vu->vu_pending = 0;
862 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
863 crit_count = 0;
864 if (error == 0)
865 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 866 ++crit_count;
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867 if (error == 0)
868 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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869 regs->tf_rax = (register_t)vu->vu_func;
870 regs->tf_rcx = (register_t)vu->vu_data;
871 regs->tf_rdx = (register_t)lp->lwp_upcall;
872 regs->tf_rip = (register_t)vu->vu_ctx;
873 regs->tf_rsp = (register_t)rsp;
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874 } else {
875 /*
876 * This returns us to the originally interrupted code.
877 */
878 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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879 regs->tf_rax = upc_frame.rax;
880 regs->tf_rcx = upc_frame.rcx;
881 regs->tf_rdx = upc_frame.rdx;
882 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 883 (upc_frame.flags & PSL_USERCHANGE);
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884 regs->tf_rip = upc_frame.oldip;
885 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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886 }
887 }
888 if (error == 0)
889 error = EJUSTRETURN;
890 return(error);
891}
892
893/*
894 * Machine dependent boot() routine
895 *
896 * I haven't seen anything to put here yet
897 * Possibly some stuff might be grafted back here from boot()
898 */
899void
900cpu_boot(int howto)
901{
902}
903
904/*
905 * Shutdown the CPU as much as possible
906 */
907void
908cpu_halt(void)
909{
910 for (;;)
911 __asm__ __volatile("hlt");
912}
913
914/*
915 * cpu_idle() represents the idle LWKT. You cannot return from this function
916 * (unless you want to blow things up!). Instead we look for runnable threads
917 * and loop or halt as appropriate. Giant is not held on entry to the thread.
918 *
919 * The main loop is entered with a critical section held, we must release
920 * the critical section before doing anything else. lwkt_switch() will
921 * check for pending interrupts due to entering and exiting its own
922 * critical section.
923 *
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924 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
925 * However, there are cases where the idlethread will be entered with
926 * the possibility that no IPI will occur and in such cases
927 * lwkt_switch() sets TDF_IDLE_NOHLT.
928 *
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929 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
930 * 1 to just use hlt and for debugging purposes.
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931 *
932 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
933 * must occur before it starts using ACPI halt.
c8fe38ae 934 */
46e562ce 935static int cpu_idle_hlt = 2;
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936static int cpu_idle_hltcnt;
937static int cpu_idle_spincnt;
be71787b 938static u_int cpu_idle_repeat = 4;
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939SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
940 &cpu_idle_hlt, 0, "Idle loop HLT enable");
941SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
942 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
943SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
944 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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945SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
946 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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947
948static void
949cpu_idle_default_hook(void)
950{
951 /*
952 * We must guarentee that hlt is exactly the instruction
953 * following the sti.
954 */
955 __asm __volatile("sti; hlt");
956}
957
958/* Other subsystems (e.g., ACPI) can hook this later. */
959void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
960
961void
962cpu_idle(void)
963{
0f0466c0 964 globaldata_t gd = mycpu;
86232a57 965 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 966 int reqflags;
be71787b 967 int quick;
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968
969 crit_exit();
f9235b6d 970 KKASSERT(td->td_critcount == 0);
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971 for (;;) {
972 /*
973 * See if there are any LWKTs ready to go.
974 */
975 lwkt_switch();
976
977 /*
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978 * When halting inside a cli we must check for reqflags
979 * races, particularly [re]schedule requests. Running
980 * splz() does the job.
981 *
982 * cpu_idle_hlt:
983 * 0 Never halt, just spin
984 *
985 * 1 Always use HLT (or MONITOR/MWAIT if avail).
986 * This typically eats more power than the
987 * ACPI halt.
988 *
989 * 2 Use HLT/MONITOR/MWAIT up to a point and then
990 * use the ACPI halt (default). This is a hybrid
991 * approach. See machdep.cpu_idle_repeat.
992 *
993 * 3 Always use the ACPI halt. This typically
994 * eats the least amount of power but the cpu
995 * will be slow waking up. Slows down e.g.
996 * compiles and other pipe/event oriented stuff.
997 *
998 * NOTE: Interrupts are enabled and we are not in a critical
999 * section.
1000 *
1001 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1002 * don't bother capping gd_idle_repeat, it is ok if
1003 * it overflows.
c8fe38ae 1004 */
be71787b 1005 ++gd->gd_idle_repeat;
0f0466c0 1006 reqflags = gd->gd_reqflags;
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1007 quick = (cpu_idle_hlt == 1) ||
1008 (cpu_idle_hlt < 3 &&
1009 gd->gd_idle_repeat < cpu_idle_repeat);
1010
1011 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
0f0466c0 1012 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
701c977e 1013 splz(); /* XXX */
0f0466c0 1014 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 1015 ++cpu_idle_hltcnt;
0f0466c0 1016 } else if (cpu_idle_hlt) {
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1017 __asm __volatile("cli");
1018 splz();
0f0466c0 1019 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 1020 if (quick)
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1021 cpu_idle_default_hook();
1022 else
1023 cpu_idle_hook();
1024 }
7d4d6fdb 1025 __asm __volatile("sti");
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1026 ++cpu_idle_hltcnt;
1027 } else {
c8fe38ae 1028 splz();
c5724852 1029 __asm __volatile("sti");
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1030 ++cpu_idle_spincnt;
1031 }
1032 }
1033}
1034
7ad8cc6c
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1035#ifdef SMP
1036
c8fe38ae 1037/*
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1038 * This routine is called if a spinlock has been held through the
1039 * exponential backoff period and is seriously contested. On a real cpu
1040 * we let it spin.
1041 */
1042void
1043cpu_spinlock_contested(void)
1044{
1045 cpu_pause();
1046}
1047
7ad8cc6c
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1048#endif
1049
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1050/*
1051 * Clear registers on exec
1052 */
1053void
1054exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1055{
1056 struct thread *td = curthread;
1057 struct lwp *lp = td->td_lwp;
1058 struct pcb *pcb = td->td_pcb;
1059 struct trapframe *regs = lp->lwp_md.md_regs;
1060
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1061 /* was i386_user_cleanup() in NetBSD */
1062 user_ldt_free(pcb);
1063
1064 bzero((char *)regs, sizeof(struct trapframe));
1065 regs->tf_rip = entry;
1066 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1067 regs->tf_rdi = stack; /* argv */
1068 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1069 regs->tf_ss = _udatasel;
1070 regs->tf_cs = _ucodesel;
1071 regs->tf_rbx = ps_strings;
1072
1073 /*
1074 * Reset the hardware debug registers if they were in use.
1075 * They won't have any meaning for the newly exec'd process.
1076 */
1077 if (pcb->pcb_flags & PCB_DBREGS) {
1078 pcb->pcb_dr0 = 0;
1079 pcb->pcb_dr1 = 0;
1080 pcb->pcb_dr2 = 0;
1081 pcb->pcb_dr3 = 0;
1082 pcb->pcb_dr6 = 0;
0855a2af 1083 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1084 if (pcb == td->td_pcb) {
1085 /*
1086 * Clear the debug registers on the running
1087 * CPU, otherwise they will end up affecting
1088 * the next process we switch to.
1089 */
1090 reset_dbregs();
1091 }
1092 pcb->pcb_flags &= ~PCB_DBREGS;
1093 }
1094
1095 /*
1096 * Initialize the math emulator (if any) for the current process.
1097 * Actually, just clear the bit that says that the emulator has
1098 * been initialized. Initialization is delayed until the process
1099 * traps to the emulator (if it is done at all) mainly because
1100 * emulators don't provide an entry point for initialization.
1101 */
c8fe38ae 1102 pcb->pcb_flags &= ~FP_SOFTFP;
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1103
1104 /*
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1105 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1106 * gd_npxthread. Otherwise a preemptive interrupt thread
1107 * may panic in npxdna().
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1108 */
1109 crit_enter();
1110 load_cr0(rcr0() | CR0_MP);
1111
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1112 /*
1113 * NOTE: The MSR values must be correct so we can return to
1114 * userland. gd_user_fs/gs must be correct so the switch
1115 * code knows what the current MSR values are.
1116 */
1117 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1118 pcb->pcb_gsbase = 0;
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1119 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1120 mdcpu->gd_user_gs = 0;
1121 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1122 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1123
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1124 /* Initialize the npx (if any) for the current process. */
1125 npxinit(__INITIAL_NPXCW__);
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1126 crit_exit();
1127
1128 pcb->pcb_ds = _udatasel;
1129 pcb->pcb_es = _udatasel;
1130 pcb->pcb_fs = _udatasel;
1131 pcb->pcb_gs = _udatasel;
1132}
1133
1134void
1135cpu_setregs(void)
1136{
1137 register_t cr0;
1138
1139 cr0 = rcr0();
1140 cr0 |= CR0_NE; /* Done by npxinit() */
1141 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1142 cr0 |= CR0_WP | CR0_AM;
1143 load_cr0(cr0);
1144 load_gs(_udatasel);
1145}
1146
1147static int
1148sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1149{
1150 int error;
1151 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1152 req);
1153 if (!error && req->newptr)
1154 resettodr();
1155 return (error);
1156}
1157
1158SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1159 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1160
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1161SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1162 CTLFLAG_RW, &disable_rtc_set, 0, "");
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1163
1164#if JG
1165SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1166 CTLFLAG_RD, &bootinfo, bootinfo, "");
1167#endif
1168
1169SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1170 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1171
1172extern u_long bootdev; /* not a cdev_t - encoding is different */
1173SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1174 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1175
1176/*
1177 * Initialize 386 and configure to run kernel
1178 */
1179
1180/*
1181 * Initialize segments & interrupt table
1182 */
1183
1184int _default_ldt;
1185struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1186static struct gate_descriptor idt0[NIDT];
1187struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1188#if JG
1189union descriptor ldt[NLDT]; /* local descriptor table */
1190#endif
1191
1192/* table descriptors - used to load tables by cpu */
1193struct region_descriptor r_gdt, r_idt;
1194
c8fe38ae
MD
1195/* JG proc0paddr is a virtual address */
1196void *proc0paddr;
1197/* JG alignment? */
1198char proc0paddr_buff[LWKT_THREAD_STACK];
1199
1200
1201/* software prototypes -- in more palatable form */
1202struct soft_segment_descriptor gdt_segs[] = {
1203/* GNULL_SEL 0 Null Descriptor */
1204{ 0x0, /* segment base address */
1205 0x0, /* length */
1206 0, /* segment type */
1207 0, /* segment descriptor priority level */
1208 0, /* segment descriptor present */
1209 0, /* long */
1210 0, /* default 32 vs 16 bit size */
1211 0 /* limit granularity (byte/page units)*/ },
1212/* GCODE_SEL 1 Code Descriptor for kernel */
1213{ 0x0, /* segment base address */
1214 0xfffff, /* length - all address space */
1215 SDT_MEMERA, /* segment type */
1216 SEL_KPL, /* segment descriptor priority level */
1217 1, /* segment descriptor present */
1218 1, /* long */
1219 0, /* default 32 vs 16 bit size */
1220 1 /* limit granularity (byte/page units)*/ },
1221/* GDATA_SEL 2 Data Descriptor for kernel */
1222{ 0x0, /* segment base address */
1223 0xfffff, /* length - all address space */
1224 SDT_MEMRWA, /* segment type */
1225 SEL_KPL, /* segment descriptor priority level */
1226 1, /* segment descriptor present */
1227 1, /* long */
1228 0, /* default 32 vs 16 bit size */
1229 1 /* limit granularity (byte/page units)*/ },
1230/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1231{ 0x0, /* segment base address */
1232 0xfffff, /* length - all address space */
1233 SDT_MEMERA, /* segment type */
1234 SEL_UPL, /* segment descriptor priority level */
1235 1, /* segment descriptor present */
1236 0, /* long */
1237 1, /* default 32 vs 16 bit size */
1238 1 /* limit granularity (byte/page units)*/ },
1239/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1240{ 0x0, /* segment base address */
1241 0xfffff, /* length - all address space */
1242 SDT_MEMRWA, /* segment type */
1243 SEL_UPL, /* segment descriptor priority level */
1244 1, /* segment descriptor present */
1245 0, /* long */
1246 1, /* default 32 vs 16 bit size */
1247 1 /* limit granularity (byte/page units)*/ },
1248/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1249{ 0x0, /* segment base address */
1250 0xfffff, /* length - all address space */
1251 SDT_MEMERA, /* segment type */
1252 SEL_UPL, /* segment descriptor priority level */
1253 1, /* segment descriptor present */
1254 1, /* long */
1255 0, /* default 32 vs 16 bit size */
1256 1 /* limit granularity (byte/page units)*/ },
1257/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1258{
1259 0x0, /* segment base address */
b2b3ffcd 1260 sizeof(struct x86_64tss)-1,/* length - all address space */
c8fe38ae
MD
1261 SDT_SYSTSS, /* segment type */
1262 SEL_KPL, /* segment descriptor priority level */
1263 1, /* segment descriptor present */
1264 0, /* long */
1265 0, /* unused - default 32 vs 16 bit size */
1266 0 /* limit granularity (byte/page units)*/ },
1267/* Actually, the TSS is a system descriptor which is double size */
1268{ 0x0, /* segment base address */
1269 0x0, /* length */
1270 0, /* segment type */
1271 0, /* segment descriptor priority level */
1272 0, /* segment descriptor present */
1273 0, /* long */
1274 0, /* default 32 vs 16 bit size */
1275 0 /* limit granularity (byte/page units)*/ },
1276/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1277{ 0x0, /* segment base address */
1278 0xfffff, /* length - all address space */
1279 SDT_MEMRWA, /* segment type */
1280 SEL_UPL, /* segment descriptor priority level */
1281 1, /* segment descriptor present */
1282 0, /* long */
1283 1, /* default 32 vs 16 bit size */
1284 1 /* limit granularity (byte/page units)*/ },
1285};
1286
1287void
1288setidt(int idx, inthand_t *func, int typ, int dpl, int ist)
1289{
1290 struct gate_descriptor *ip;
1291
1292 ip = idt + idx;
1293 ip->gd_looffset = (uintptr_t)func;
1294 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1295 ip->gd_ist = ist;
1296 ip->gd_xx = 0;
1297 ip->gd_type = typ;
1298 ip->gd_dpl = dpl;
1299 ip->gd_p = 1;
1300 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1301}
1302
1303#define IDTVEC(name) __CONCAT(X,name)
1304
1305extern inthand_t
1306 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1307 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1308 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1309 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1310 IDTVEC(xmm), IDTVEC(dblfault),
1311 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1312
1313#ifdef DEBUG_INTERRUPTS
1314extern inthand_t *Xrsvdary[256];
1315#endif
1316
1317void
1318sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1319{
1320 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1321 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1322 ssd->ssd_type = sd->sd_type;
1323 ssd->ssd_dpl = sd->sd_dpl;
1324 ssd->ssd_p = sd->sd_p;
1325 ssd->ssd_def32 = sd->sd_def32;
1326 ssd->ssd_gran = sd->sd_gran;
1327}
1328
1329void
1330ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1331{
1332
1333 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1334 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1335 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1336 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1337 sd->sd_type = ssd->ssd_type;
1338 sd->sd_dpl = ssd->ssd_dpl;
1339 sd->sd_p = ssd->ssd_p;
1340 sd->sd_long = ssd->ssd_long;
1341 sd->sd_def32 = ssd->ssd_def32;
1342 sd->sd_gran = ssd->ssd_gran;
1343}
1344
1345void
1346ssdtosyssd(struct soft_segment_descriptor *ssd,
1347 struct system_segment_descriptor *sd)
1348{
1349
1350 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1351 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1352 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1353 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1354 sd->sd_type = ssd->ssd_type;
1355 sd->sd_dpl = ssd->ssd_dpl;
1356 sd->sd_p = ssd->ssd_p;
1357 sd->sd_gran = ssd->ssd_gran;
1358}
1359
c8fe38ae
MD
1360/*
1361 * Populate the (physmap) array with base/bound pairs describing the
1362 * available physical memory in the system, then test this memory and
1363 * build the phys_avail array describing the actually-available memory.
1364 *
1365 * If we cannot accurately determine the physical memory map, then use
1366 * value from the 0xE801 call, and failing that, the RTC.
1367 *
1368 * Total memory size may be set by the kernel environment variable
1369 * hw.physmem or the compile-time define MAXMEM.
1370 *
b4d9abe2
MD
1371 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1372 * of PAGE_SIZE. This also greatly reduces the memory test time
1373 * which would otherwise be excessive on machines with > 8G of ram.
1374 *
c8fe38ae
MD
1375 * XXX first should be vm_paddr_t.
1376 */
b4d9abe2
MD
1377
1378#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1379#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1380
c8fe38ae
MD
1381static void
1382getmemsize(caddr_t kmdp, u_int64_t first)
1383{
b4d9abe2
MD
1384 int off, physmap_idx, pa_indx, da_indx;
1385 int i, j;
1386 vm_paddr_t physmap[PHYSMAP_SIZE];
1387 vm_paddr_t pa;
1388 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1389 u_long physmem_tunable;
1390 pt_entry_t *pte;
1391 struct bios_smap *smapbase, *smap, *smapend;
1392 u_int32_t smapsize;
1393 quad_t dcons_addr, dcons_size;
1394
1395 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1396 physmap_idx = 0;
1397
1398 /*
1399 * get memory map from INT 15:E820, kindly supplied by the loader.
1400 *
1401 * subr_module.c says:
1402 * "Consumer may safely assume that size value precedes data."
1403 * ie: an int32_t immediately precedes smap.
1404 */
1405 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1406 MODINFO_METADATA | MODINFOMD_SMAP);
1407 if (smapbase == NULL)
1408 panic("No BIOS smap info from loader!");
1409
1410 smapsize = *((u_int32_t *)smapbase - 1);
1411 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1412
1413 for (smap = smapbase; smap < smapend; smap++) {
1414 if (boothowto & RB_VERBOSE)
1415 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1416 smap->type, smap->base, smap->length);
1417
1418 if (smap->type != SMAP_TYPE_MEMORY)
1419 continue;
1420
1421 if (smap->length == 0)
1422 continue;
1423
1424 for (i = 0; i <= physmap_idx; i += 2) {
1425 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1426 if (boothowto & RB_VERBOSE) {
1427 kprintf("Overlapping or non-monotonic "
1428 "memory region, ignoring "
1429 "second region\n");
1430 }
c8fe38ae
MD
1431 continue;
1432 }
1433 }
1bda0d3d 1434 Realmem += smap->length;
c8fe38ae
MD
1435
1436 if (smap->base == physmap[physmap_idx + 1]) {
1437 physmap[physmap_idx + 1] += smap->length;
1438 continue;
1439 }
1440
1441 physmap_idx += 2;
1442 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1443 kprintf("Too many segments in the physical "
1444 "address map, giving up\n");
c8fe38ae
MD
1445 break;
1446 }
1447 physmap[physmap_idx] = smap->base;
1448 physmap[physmap_idx + 1] = smap->base + smap->length;
1449 }
1450
8936cd9b 1451 base_memory = physmap[1] / 1024;
c8fe38ae
MD
1452#ifdef SMP
1453 /* make hole for AP bootstrap code */
8936cd9b 1454 physmap[1] = mp_bootaddress(base_memory);
2c36eb24 1455#endif
2331304b 1456
927c4c1f
MN
1457 /* Save EBDA address, if any */
1458 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1459 ebda_addr <<= 4;
c8fe38ae
MD
1460
1461 /*
1462 * Maxmem isn't the "maximum memory", it's one larger than the
1463 * highest page of the physical address space. It should be
1464 * called something like "Maxphyspage". We may adjust this
1465 * based on ``hw.physmem'' and the results of the memory test.
1466 */
1467 Maxmem = atop(physmap[physmap_idx + 1]);
1468
1469#ifdef MAXMEM
1470 Maxmem = MAXMEM / 4;
1471#endif
1472
1473 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1474 Maxmem = atop(physmem_tunable);
1475
1476 /*
1477 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1478 * in the system.
1479 */
1480 if (Maxmem > atop(physmap[physmap_idx + 1]))
1481 Maxmem = atop(physmap[physmap_idx + 1]);
1482
8e5ea5f7 1483 /*
b4d9abe2 1484 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1485 */
1486 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1487 kprintf("Limiting Maxmem due to DMAP size\n");
1488 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1489 }
1490
c8fe38ae 1491 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1492 (boothowto & RB_VERBOSE)) {
c8fe38ae 1493 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1494 }
c8fe38ae 1495
b4d9abe2
MD
1496 /*
1497 * Call pmap initialization to make new kernel address space
1498 *
1499 * Mask off page 0.
1500 */
48ffc236 1501 pmap_bootstrap(&first);
b4d9abe2
MD
1502 physmap[0] = PAGE_SIZE;
1503
1504 /*
1505 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1506 * exceeding Maxmem.
1507 */
1508 for (i = j = 0; i <= physmap_idx; i += 2) {
1509 if (physmap[i+1] > ptoa((vm_paddr_t)Maxmem))
1510 physmap[i+1] = ptoa((vm_paddr_t)Maxmem);
1511 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1512 ~PHYSMAP_ALIGN_MASK;
1513 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1514
1515 physmap[j] = physmap[i];
1516 physmap[j+1] = physmap[i+1];
1517
1518 if (physmap[i] < physmap[i+1])
1519 j += 2;
1520 }
1521 physmap_idx = j - 2;
1522
1523 /*
1524 * Align anything else used in the validation loop.
1525 */
1526 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1527
1528 /*
1529 * Size up each available chunk of physical memory.
1530 */
c8fe38ae
MD
1531 pa_indx = 0;
1532 da_indx = 1;
1533 phys_avail[pa_indx++] = physmap[0];
1534 phys_avail[pa_indx] = physmap[0];
1535 dump_avail[da_indx] = physmap[0];
1536 pte = CMAP1;
1537
1538 /*
1539 * Get dcons buffer address
1540 */
1541 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1542 kgetenv_quad("dcons.size", &dcons_size) == 0)
1543 dcons_addr = 0;
1544
1545 /*
b4d9abe2
MD
1546 * Validate the physical memory. The physical memory segments
1547 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1548 * of PAGE_SIZE.
c8fe38ae
MD
1549 */
1550 for (i = 0; i <= physmap_idx; i += 2) {
1551 vm_paddr_t end;
1552
b4d9abe2
MD
1553 end = physmap[i + 1];
1554
1555 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1556 int tmp, page_bad, full;
1557 int *ptr = (int *)CADDR1;
1558
1559 full = FALSE;
1560 /*
1561 * block out kernel memory as not available.
1562 */
1563 if (pa >= 0x100000 && pa < first)
1564 goto do_dump_avail;
1565
1566 /*
1567 * block out dcons buffer
1568 */
1569 if (dcons_addr > 0
1570 && pa >= trunc_page(dcons_addr)
b4d9abe2 1571 && pa < dcons_addr + dcons_size) {
c8fe38ae 1572 goto do_dump_avail;
b4d9abe2 1573 }
c8fe38ae
MD
1574
1575 page_bad = FALSE;
1576
1577 /*
1578 * map page into kernel: valid, read/write,non-cacheable
1579 */
1580 *pte = pa | PG_V | PG_RW | PG_N;
1581 cpu_invltlb();
1582
1583 tmp = *(int *)ptr;
1584 /*
1585 * Test for alternating 1's and 0's
1586 */
1587 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1588 cpu_mfence();
c8fe38ae
MD
1589 if (*(volatile int *)ptr != 0xaaaaaaaa)
1590 page_bad = TRUE;
1591 /*
1592 * Test for alternating 0's and 1's
1593 */
1594 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1595 cpu_mfence();
c8fe38ae
MD
1596 if (*(volatile int *)ptr != 0x55555555)
1597 page_bad = TRUE;
1598 /*
1599 * Test for all 1's
1600 */
1601 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1602 cpu_mfence();
c8fe38ae
MD
1603 if (*(volatile int *)ptr != 0xffffffff)
1604 page_bad = TRUE;
1605 /*
1606 * Test for all 0's
1607 */
1608 *(volatile int *)ptr = 0x0;
b4d9abe2 1609 cpu_mfence();
c8fe38ae
MD
1610 if (*(volatile int *)ptr != 0x0)
1611 page_bad = TRUE;
1612 /*
1613 * Restore original value.
1614 */
1615 *(int *)ptr = tmp;
1616
1617 /*
1618 * Adjust array of valid/good pages.
1619 */
1620 if (page_bad == TRUE)
1621 continue;
1622 /*
1623 * If this good page is a continuation of the
1624 * previous set of good pages, then just increase
1625 * the end pointer. Otherwise start a new chunk.
1626 * Note that "end" points one higher than end,
1627 * making the range >= start and < end.
1628 * If we're also doing a speculative memory
1629 * test and we at or past the end, bump up Maxmem
1630 * so that we keep going. The first bad page
1631 * will terminate the loop.
1632 */
1633 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1634 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1635 } else {
1636 pa_indx++;
1637 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1638 kprintf(
1639 "Too many holes in the physical address space, giving up\n");
1640 pa_indx--;
1641 full = TRUE;
1642 goto do_dump_avail;
1643 }
b4d9abe2
MD
1644 phys_avail[pa_indx++] = pa;
1645 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae 1646 }
7a3eee88 1647 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
c8fe38ae
MD
1648do_dump_avail:
1649 if (dump_avail[da_indx] == pa) {
b4d9abe2 1650 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1651 } else {
1652 da_indx++;
1653 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1654 da_indx--;
1655 goto do_next;
1656 }
b4d9abe2
MD
1657 dump_avail[da_indx++] = pa;
1658 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1659 }
1660do_next:
1661 if (full)
1662 break;
1663 }
1664 }
1665 *pte = 0;
1666 cpu_invltlb();
1667
1668 /*
c8fe38ae
MD
1669 * The last chunk must contain at least one page plus the message
1670 * buffer to avoid complicating other code (message buffer address
1671 * calculation, etc.).
1672 */
b4d9abe2
MD
1673 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1674
1675 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1676 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1677 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1678 phys_avail[pa_indx--] = 0;
1679 phys_avail[pa_indx--] = 0;
1680 }
1681
1682 Maxmem = atop(phys_avail[pa_indx]);
1683
1684 /* Trim off space for the message buffer. */
b4d9abe2 1685 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1686
1185babf
JG
1687 avail_end = phys_avail[pa_indx];
1688
c8fe38ae 1689 /* Map the message buffer. */
b4d9abe2
MD
1690 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1691 pmap_kenter((vm_offset_t)msgbufp + off,
1692 phys_avail[pa_indx] + off);
1693 }
c8fe38ae
MD
1694}
1695
faaf4131
MN
1696struct machintr_abi MachIntrABI;
1697
c8fe38ae
MD
1698/*
1699 * IDT VECTORS:
1700 * 0 Divide by zero
1701 * 1 Debug
1702 * 2 NMI
1703 * 3 BreakPoint
1704 * 4 OverFlow
1705 * 5 Bound-Range
1706 * 6 Invalid OpCode
1707 * 7 Device Not Available (x87)
1708 * 8 Double-Fault
1709 * 9 Coprocessor Segment overrun (unsupported, reserved)
1710 * 10 Invalid-TSS
1711 * 11 Segment not present
1712 * 12 Stack
1713 * 13 General Protection
1714 * 14 Page Fault
1715 * 15 Reserved
1716 * 16 x87 FP Exception pending
1717 * 17 Alignment Check
1718 * 18 Machine Check
1719 * 19 SIMD floating point
1720 * 20-31 reserved
1721 * 32-255 INTn/external sources
1722 */
1723u_int64_t
1724hammer_time(u_int64_t modulep, u_int64_t physfree)
1725{
1726 caddr_t kmdp;
5b9f6cc4
MD
1727 int gsel_tss, x;
1728#if JG
1729 int metadata_missing, off;
1730#endif
c8fe38ae
MD
1731 struct mdglobaldata *gd;
1732 u_int64_t msr;
c8fe38ae 1733
c8fe38ae
MD
1734 /*
1735 * Prevent lowering of the ipl if we call tsleep() early.
1736 */
1737 gd = &CPU_prvspace[0].mdglobaldata;
1738 bzero(gd, sizeof(*gd));
1739
1740 /*
1741 * Note: on both UP and SMP curthread must be set non-NULL
1742 * early in the boot sequence because the system assumes
1743 * that 'curthread' is never NULL.
1744 */
1745
1746 gd->mi.gd_curthread = &thread0;
1747 thread0.td_gd = &gd->mi;
1748
1749 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1750
1751#if JG
1752 metadata_missing = 0;
1753 if (bootinfo.bi_modulep) {
1754 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1755 preload_bootstrap_relocate(KERNBASE);
1756 } else {
1757 metadata_missing = 1;
1758 }
1759 if (bootinfo.bi_envp)
1760 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1761#endif
1762
1763 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1764 preload_bootstrap_relocate(PTOV_OFFSET);
1765 kmdp = preload_search_by_type("elf kernel");
1766 if (kmdp == NULL)
1767 kmdp = preload_search_by_type("elf64 kernel");
1768 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1769 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1770#ifdef DDB
1771 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1772 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1773#endif
1774
27af435a
SZ
1775 if (boothowto & RB_VERBOSE)
1776 bootverbose++;
1777
c8fe38ae 1778 /*
10db3cc6 1779 * Default MachIntrABI to ICU
faaf4131
MN
1780 */
1781 MachIntrABI = MachIntrABI_ICU;
9a4bd8f3 1782
d745d2b8
SZ
1783 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1784 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2e0ed166 1785 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
faaf4131
MN
1786
1787 /*
c8fe38ae
MD
1788 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1789 * and ncpus_fit_mask remain 0.
1790 */
1791 ncpus = 1;
1792 ncpus2 = 1;
1793 ncpus_fit = 1;
1794 /* Init basic tunables, hz etc */
1795 init_param1();
1796
1797 /*
1798 * make gdt memory segments
1799 */
1800 gdt_segs[GPROC0_SEL].ssd_base =
1801 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1802
1803 gd->mi.gd_prvspace = &CPU_prvspace[0];
1804
1805 for (x = 0; x < NGDT; x++) {
1806 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1807 ssdtosd(&gdt_segs[x], &gdt[x]);
1808 }
1809 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1810 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1811
c8fe38ae
MD
1812 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1813 r_gdt.rd_base = (long) gdt;
1814 lgdt(&r_gdt);
1815
1816 wrmsr(MSR_FSBASE, 0); /* User value */
1817 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1818 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1819
1820 mi_gdinit(&gd->mi, 0);
1821 cpu_gdinit(gd, 0);
1822 proc0paddr = proc0paddr_buff;
1823 mi_proc0init(&gd->mi, proc0paddr);
1824 safepri = TDPRI_MAX;
1825
1826 /* spinlocks and the BGL */
1827 init_locks();
1828
1829 /* exceptions */
1830 for (x = 0; x < NIDT; x++)
1831 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1832 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1833 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1834 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1835 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1836 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1837 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1838 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1839 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1840 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1841 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1842 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1843 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1844 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1845 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1846 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1847 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1848 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1849 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1850 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1851
1852 r_idt.rd_limit = sizeof(idt0) - 1;
1853 r_idt.rd_base = (long) idt;
1854 lidt(&r_idt);
1855
1856 /*
1857 * Initialize the console before we print anything out.
1858 */
1859 cninit();
1860
1861#if JG
1862 if (metadata_missing)
1863 kprintf("WARNING: loader(8) metadata is missing!\n");
1864#endif
1865
1866#if NISA >0
e24dd6e0 1867 elcr_probe();
c8fe38ae
MD
1868 isa_defaultirq();
1869#endif
1870 rand_initialize();
1871
a3dd9120
SZ
1872 /*
1873 * Initialize IRQ mapping
1874 *
1875 * NOTE:
1876 * SHOULD be after elcr_probe()
1877 */
1878 MachIntrABI_ICU.initmap();
1879#ifdef SMP
1880 MachIntrABI_IOAPIC.initmap();
1881#endif
1882
c8fe38ae
MD
1883#ifdef DDB
1884 kdb_init();
1885 if (boothowto & RB_KDB)
1886 Debugger("Boot flags requested debugger");
1887#endif
1888
1889#if JG
1890 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1891 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1892 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1893#endif
1894 identify_cpu(); /* Final stage of CPU initialization */
1895 initializecpu(); /* Initialize CPU registers */
1896
1897 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1898 gd->gd_common_tss.tss_rsp0 =
1899 (register_t)(thread0.td_kstack +
1900 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1901 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1902 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1903
093565f2
MD
1904 /* double fault stack */
1905 gd->gd_common_tss.tss_ist1 =
1906 (long)&gd->mi.gd_prvspace->idlestack[
1907 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1908
1909 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1910 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1911
1912 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1913 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1914 gd->gd_common_tssd = *gd->gd_tss_gdt;
1915 ltr(gsel_tss);
1916
1917 /* Set up the fast syscall stuff */
1918 msr = rdmsr(MSR_EFER) | EFER_SCE;
1919 wrmsr(MSR_EFER, msr);
1920 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1921 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1922 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1923 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1924 wrmsr(MSR_STAR, msr);
1925 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1926
1927 getmemsize(kmdp, physfree);
1928 init_param2(physmem);
1929
1930 /* now running on new page tables, configured,and u/iom is accessible */
1931
1932 /* Map the message buffer. */
1933#if JG
1934 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1935 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1936#endif
1937
1938 msgbufinit(msgbufp, MSGBUF_SIZE);
1939
1940
1941 /* transfer to user mode */
1942
1943 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1944 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1945 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1946
1947 load_ds(_udatasel);
1948 load_es(_udatasel);
1949 load_fs(_udatasel);
1950
1951 /* setup proc 0's pcb */
1952 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 1953 thread0.td_pcb->pcb_cr3 = KPML4phys;
c8fe38ae 1954 thread0.td_pcb->pcb_ext = 0;
d1368d1a 1955 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
1956
1957 /* Location of kernel stack for locore */
1958 return ((u_int64_t)thread0.td_pcb);
1959}
1960
1961/*
1962 * Initialize machine-dependant portions of the global data structure.
1963 * Note that the global data area and cpu0's idlestack in the private
1964 * data space were allocated in locore.
1965 *
1966 * Note: the idlethread's cpl is 0
1967 *
1968 * WARNING! Called from early boot, 'mycpu' may not work yet.
1969 */
1970void
1971cpu_gdinit(struct mdglobaldata *gd, int cpu)
1972{
1973 if (cpu)
1974 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1975
1976 lwkt_init_thread(&gd->mi.gd_idlethread,
1977 gd->mi.gd_prvspace->idlestack,
1978 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 1979 0, &gd->mi);
c8fe38ae
MD
1980 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1981 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1982 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1983 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
1984}
1985
1986int
1987is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
1988{
1989 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
1990 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
1991 return (TRUE);
1992 }
1993 return (FALSE);
1994}
1995
1996struct globaldata *
1997globaldata_find(int cpu)
1998{
1999 KKASSERT(cpu >= 0 && cpu < ncpus);
2000 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2001}
2002
c8fe38ae
MD
2003int
2004ptrace_set_pc(struct lwp *lp, unsigned long addr)
2005{
5b9f6cc4 2006 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
2007 return (0);
2008}
2009
2010int
2011ptrace_single_step(struct lwp *lp)
2012{
5b9f6cc4 2013 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
2014 return (0);
2015}
2016
2017int
2018fill_regs(struct lwp *lp, struct reg *regs)
2019{
c8fe38ae
MD
2020 struct trapframe *tp;
2021
2022 tp = lp->lwp_md.md_regs;
5b9f6cc4 2023 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2024 return (0);
2025}
2026
2027int
2028set_regs(struct lwp *lp, struct reg *regs)
2029{
c8fe38ae
MD
2030 struct trapframe *tp;
2031
2032 tp = lp->lwp_md.md_regs;
5b9f6cc4 2033 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2034 !CS_SECURE(regs->r_cs))
2035 return (EINVAL);
5b9f6cc4 2036 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
c8fe38ae
MD
2037 return (0);
2038}
2039
2040#ifndef CPU_DISABLE_SSE
2041static void
2042fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2043{
2044 struct env87 *penv_87 = &sv_87->sv_env;
2045 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2046 int i;
2047
2048 /* FPU control/status */
2049 penv_87->en_cw = penv_xmm->en_cw;
2050 penv_87->en_sw = penv_xmm->en_sw;
2051 penv_87->en_tw = penv_xmm->en_tw;
2052 penv_87->en_fip = penv_xmm->en_fip;
2053 penv_87->en_fcs = penv_xmm->en_fcs;
2054 penv_87->en_opcode = penv_xmm->en_opcode;
2055 penv_87->en_foo = penv_xmm->en_foo;
2056 penv_87->en_fos = penv_xmm->en_fos;
2057
2058 /* FPU registers */
2059 for (i = 0; i < 8; ++i)
2060 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
c8fe38ae
MD
2061}
2062
2063static void
2064set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2065{
2066 struct env87 *penv_87 = &sv_87->sv_env;
2067 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2068 int i;
2069
2070 /* FPU control/status */
2071 penv_xmm->en_cw = penv_87->en_cw;
2072 penv_xmm->en_sw = penv_87->en_sw;
2073 penv_xmm->en_tw = penv_87->en_tw;
2074 penv_xmm->en_fip = penv_87->en_fip;
2075 penv_xmm->en_fcs = penv_87->en_fcs;
2076 penv_xmm->en_opcode = penv_87->en_opcode;
2077 penv_xmm->en_foo = penv_87->en_foo;
2078 penv_xmm->en_fos = penv_87->en_fos;
2079
2080 /* FPU registers */
2081 for (i = 0; i < 8; ++i)
2082 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
c8fe38ae
MD
2083}
2084#endif /* CPU_DISABLE_SSE */
2085
2086int
2087fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2088{
2089#ifndef CPU_DISABLE_SSE
2090 if (cpu_fxsr) {
2091 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2092 (struct save87 *)fpregs);
2093 return (0);
2094 }
2095#endif /* CPU_DISABLE_SSE */
2096 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2097 return (0);
2098}
2099
2100int
2101set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2102{
2103#ifndef CPU_DISABLE_SSE
2104 if (cpu_fxsr) {
2105 set_fpregs_xmm((struct save87 *)fpregs,
2106 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2107 return (0);
2108 }
2109#endif /* CPU_DISABLE_SSE */
2110 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2111 return (0);
2112}
2113
2114int
2115fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2116{
2117 if (lp == NULL) {
0855a2af
JG
2118 dbregs->dr[0] = rdr0();
2119 dbregs->dr[1] = rdr1();
2120 dbregs->dr[2] = rdr2();
2121 dbregs->dr[3] = rdr3();
2122 dbregs->dr[4] = rdr4();
2123 dbregs->dr[5] = rdr5();
2124 dbregs->dr[6] = rdr6();
2125 dbregs->dr[7] = rdr7();
c8fe38ae
MD
2126 } else {
2127 struct pcb *pcb;
2128
2129 pcb = lp->lwp_thread->td_pcb;
0855a2af
JG
2130 dbregs->dr[0] = pcb->pcb_dr0;
2131 dbregs->dr[1] = pcb->pcb_dr1;
2132 dbregs->dr[2] = pcb->pcb_dr2;
2133 dbregs->dr[3] = pcb->pcb_dr3;
2134 dbregs->dr[4] = 0;
2135 dbregs->dr[5] = 0;
2136 dbregs->dr[6] = pcb->pcb_dr6;
2137 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2138 }
2139 return (0);
2140}
2141
2142int
2143set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2144{
2145 if (lp == NULL) {
0855a2af
JG
2146 load_dr0(dbregs->dr[0]);
2147 load_dr1(dbregs->dr[1]);
2148 load_dr2(dbregs->dr[2]);
2149 load_dr3(dbregs->dr[3]);
2150 load_dr4(dbregs->dr[4]);
2151 load_dr5(dbregs->dr[5]);
2152 load_dr6(dbregs->dr[6]);
2153 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2154 } else {
2155 struct pcb *pcb;
2156 struct ucred *ucred;
2157 int i;
0855a2af 2158 uint64_t mask1, mask2;
c8fe38ae
MD
2159
2160 /*
2161 * Don't let an illegal value for dr7 get set. Specifically,
2162 * check for undefined settings. Setting these bit patterns
2163 * result in undefined behaviour and can lead to an unexpected
2164 * TRCTRAP.
2165 */
0855a2af
JG
2166 /* JG this loop looks unreadable */
2167 /* Check 4 2-bit fields for invalid patterns.
2168 * These fields are R/Wi, for i = 0..3
2169 */
2170 /* Is 10 in LENi allowed when running in compatibility mode? */
2171 /* Pattern 10 in R/Wi might be used to indicate
2172 * breakpoint on I/O. Further analysis should be
2173 * carried to decide if it is safe and useful to
2174 * provide access to that capability
2175 */
2176 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2177 i++, mask1 <<= 4, mask2 <<= 4)
2178 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2179 return (EINVAL);
c8fe38ae
MD
2180
2181 pcb = lp->lwp_thread->td_pcb;
2182 ucred = lp->lwp_proc->p_ucred;
2183
2184 /*
2185 * Don't let a process set a breakpoint that is not within the
2186 * process's address space. If a process could do this, it
2187 * could halt the system by setting a breakpoint in the kernel
2188 * (if ddb was enabled). Thus, we need to check to make sure
2189 * that no breakpoints are being enabled for addresses outside
2190 * process's address space, unless, perhaps, we were called by
2191 * uid 0.
2192 *
2193 * XXX - what about when the watched area of the user's
2194 * address space is written into from within the kernel
2195 * ... wouldn't that still cause a breakpoint to be generated
2196 * from within kernel mode?
2197 */
2198
895c1f85 2199 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2200 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2201 /* dr0 is enabled */
0855a2af 2202 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2203 return (EINVAL);
2204 }
2205
0855a2af 2206 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2207 /* dr1 is enabled */
0855a2af 2208 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2209 return (EINVAL);
2210 }
2211
0855a2af 2212 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2213 /* dr2 is enabled */
0855a2af 2214 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2215 return (EINVAL);
2216 }
2217
0855a2af 2218 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2219 /* dr3 is enabled */
0855a2af 2220 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2221 return (EINVAL);
2222 }
c8fe38ae
MD
2223 }
2224
0855a2af
JG
2225 pcb->pcb_dr0 = dbregs->dr[0];
2226 pcb->pcb_dr1 = dbregs->dr[1];
2227 pcb->pcb_dr2 = dbregs->dr[2];
2228 pcb->pcb_dr3 = dbregs->dr[3];
2229 pcb->pcb_dr6 = dbregs->dr[6];
2230 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2231
2232 pcb->pcb_flags |= PCB_DBREGS;
2233 }
2234
2235 return (0);
2236}
2237
2238/*
2239 * Return > 0 if a hardware breakpoint has been hit, and the
2240 * breakpoint was in user space. Return 0, otherwise.
2241 */
2242int
2243user_dbreg_trap(void)
2244{
0855a2af
JG
2245 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2246 u_int64_t bp; /* breakpoint bits extracted from dr6 */
c8fe38ae
MD
2247 int nbp; /* number of breakpoints that triggered */
2248 caddr_t addr[4]; /* breakpoint addresses */
2249 int i;
2250
2251 dr7 = rdr7();
0855a2af 2252 if ((dr7 & 0xff) == 0) {
c8fe38ae
MD
2253 /*
2254 * all GE and LE bits in the dr7 register are zero,
2255 * thus the trap couldn't have been caused by the
2256 * hardware debug registers
2257 */
2258 return 0;
2259 }
2260
2261 nbp = 0;
2262 dr6 = rdr6();
0855a2af 2263 bp = dr6 & 0xf;
c8fe38ae 2264
0855a2af 2265 if (bp == 0) {
c8fe38ae
MD
2266 /*
2267 * None of the breakpoint bits are set meaning this
2268 * trap was not caused by any of the debug registers
2269 */
2270 return 0;
2271 }
2272
2273 /*
2274 * at least one of the breakpoints were hit, check to see
2275 * which ones and if any of them are user space addresses
2276 */
2277
2278 if (bp & 0x01) {
2279 addr[nbp++] = (caddr_t)rdr0();
2280 }
2281 if (bp & 0x02) {
2282 addr[nbp++] = (caddr_t)rdr1();
2283 }
2284 if (bp & 0x04) {
2285 addr[nbp++] = (caddr_t)rdr2();
2286 }
2287 if (bp & 0x08) {
2288 addr[nbp++] = (caddr_t)rdr3();
2289 }
2290
2291 for (i=0; i<nbp; i++) {
2292 if (addr[i] <
2293 (caddr_t)VM_MAX_USER_ADDRESS) {
2294 /*
2295 * addr[i] is in user space
2296 */
2297 return nbp;
2298 }
2299 }
2300
2301 /*
2302 * None of the breakpoints are in user space.
2303 */
2304 return 0;
2305}
2306
2307
2308#ifndef DDB
2309void
2310Debugger(const char *msg)
2311{
2312 kprintf("Debugger(\"%s\") called.\n", msg);
2313}
2314#endif /* no DDB */
2315
2316#ifdef DDB
2317
2318/*
2319 * Provide inb() and outb() as functions. They are normally only
2320 * available as macros calling inlined functions, thus cannot be
2321 * called inside DDB.
2322 *
2323 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2324 */
2325
2326#undef inb
2327#undef outb
2328
2329/* silence compiler warnings */
2330u_char inb(u_int);
2331void outb(u_int, u_char);
2332
2333u_char
2334inb(u_int port)
2335{
2336 u_char data;
2337 /*
2338 * We use %%dx and not %1 here because i/o is done at %dx and not at
2339 * %edx, while gcc generates inferior code (movw instead of movl)
2340 * if we tell it to load (u_short) port.
2341 */
2342 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2343 return (data);
2344}
2345
2346void
2347outb(u_int port, u_char data)
2348{
2349 u_char al;
2350 /*
2351 * Use an unnecessary assignment to help gcc's register allocator.
2352 * This make a large difference for gcc-1.40 and a tiny difference
2353 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2354 * best results. gcc-2.6.0 can't handle this.
2355 */
2356 al = data;
2357 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2358}
2359
2360#endif /* DDB */
2361
2362
2363
2364#include "opt_cpu.h"
2365
2366
2367/*
2368 * initialize all the SMP locks
2369 */
2370
2371/* critical region when masking or unmasking interupts */
2372struct spinlock_deprecated imen_spinlock;
2373
c8fe38ae
MD
2374/* critical region for old style disable_intr/enable_intr */
2375struct spinlock_deprecated mpintr_spinlock;
2376
2377/* critical region around INTR() routines */
2378struct spinlock_deprecated intr_spinlock;
2379
2380/* lock region used by kernel profiling */
2381struct spinlock_deprecated mcount_spinlock;
2382
2383/* locks com (tty) data/hardware accesses: a FASTINTR() */
2384struct spinlock_deprecated com_spinlock;
2385
c8fe38ae
MD
2386/* lock regions around the clock hardware */
2387struct spinlock_deprecated clock_spinlock;
2388
c8fe38ae
MD
2389static void
2390init_locks(void)
2391{
b5d16701 2392#ifdef SMP
c8fe38ae 2393 /*
b5d16701 2394 * Get the initial mplock with a count of 1 for the BSP.
c8fe38ae
MD
2395 * This uses a LOGICAL cpu ID, ie BSP == 0.
2396 */
c8fe38ae
MD
2397 cpu_get_initial_mplock();
2398#endif
2399 /* DEPRECATED */
2400 spin_lock_init(&mcount_spinlock);
c8fe38ae
MD
2401 spin_lock_init(&intr_spinlock);
2402 spin_lock_init(&mpintr_spinlock);
2403 spin_lock_init(&imen_spinlock);
c8fe38ae
MD
2404 spin_lock_init(&com_spinlock);
2405 spin_lock_init(&clock_spinlock);
c8fe38ae
MD
2406
2407 /* our token pool needs to work early */
2408 lwkt_token_pool_init();
2409}
2410