usb4bsd: Perform the usual porting on the controller, storage and core code.
[dragonfly.git] / sys / bus / u4b / controller / ehci.c
CommitLineData
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1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
722d05c3 47//__FBSDID("$FreeBSD$");
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48
49#include <sys/stdint.h>
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50#include <sys/param.h>
51#include <sys/queue.h>
52#include <sys/types.h>
53#include <sys/systm.h>
54#include <sys/kernel.h>
55#include <sys/bus.h>
56#include <sys/module.h>
57#include <sys/lock.h>
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58#include <sys/condvar.h>
59#include <sys/sysctl.h>
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60#include <sys/unistd.h>
61#include <sys/callout.h>
62#include <sys/malloc.h>
63#include <sys/priv.h>
64
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65#include <bus/u4b/usb.h>
66#include <bus/u4b/usbdi.h>
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67
68#define USB_DEBUG_VAR ehcidebug
69
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70#include <bus/u4b/usb_core.h>
71#include <bus/u4b/usb_debug.h>
72#include <bus/u4b/usb_busdma.h>
73#include <bus/u4b/usb_process.h>
74#include <bus/u4b/usb_transfer.h>
75#include <bus/u4b/usb_device.h>
76#include <bus/u4b/usb_hub.h>
77#include <bus/u4b/usb_util.h>
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79#include <bus/u4b/usb_controller.h>
80#include <bus/u4b/usb_bus.h>
81#include <bus/u4b/controller/ehci.h>
82#include <bus/u4b/controller/ehcireg.h>
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83
84#define EHCI_BUS2SC(bus) \
85 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
86 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
87
88#ifdef USB_DEBUG
89static int ehcidebug = 0;
90static int ehcinohighspeed = 0;
91static int ehciiaadbug = 0;
92static int ehcilostintrbug = 0;
93
94static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
95SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
96 &ehcidebug, 0, "Debug level");
97SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
98 &ehcinohighspeed, 0, "Disable High Speed USB");
99SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW,
100 &ehciiaadbug, 0, "Enable doorbell bug workaround");
101SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW,
102 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
103
104TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
105TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
106TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
107TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
108
109static void ehci_dump_regs(ehci_softc_t *sc);
110static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
111
112#endif
113
114#define EHCI_INTR_ENDPT 1
115
116extern struct usb_bus_methods ehci_bus_methods;
117extern struct usb_pipe_methods ehci_device_bulk_methods;
118extern struct usb_pipe_methods ehci_device_ctrl_methods;
119extern struct usb_pipe_methods ehci_device_intr_methods;
120extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
121extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
122
123static void ehci_do_poll(struct usb_bus *);
124static void ehci_device_done(struct usb_xfer *, usb_error_t);
125static uint8_t ehci_check_transfer(struct usb_xfer *);
126static void ehci_timeout(void *);
127static void ehci_poll_timeout(void *);
128
129static void ehci_root_intr(ehci_softc_t *sc);
130
131struct ehci_std_temp {
132 ehci_softc_t *sc;
133 struct usb_page_cache *pc;
134 ehci_qtd_t *td;
135 ehci_qtd_t *td_next;
136 uint32_t average;
137 uint32_t qtd_status;
138 uint32_t len;
139 uint16_t max_frame_size;
140 uint8_t shortpkt;
141 uint8_t auto_data_toggle;
142 uint8_t setup_alt_next;
143 uint8_t last_frame;
144};
145
146void
147ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
148{
149 ehci_softc_t *sc = EHCI_BUS2SC(bus);
150 uint32_t i;
151
152 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
153 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
154
155 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
156 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
157
158 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
159 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
160
161 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
162 cb(bus, sc->sc_hw.intr_start_pc + i,
163 sc->sc_hw.intr_start_pg + i,
164 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
165 }
166
167 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
168 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
169 sc->sc_hw.isoc_hs_start_pg + i,
170 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
171 }
172
173 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
174 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
175 sc->sc_hw.isoc_fs_start_pg + i,
176 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
177 }
178}
179
180usb_error_t
181ehci_reset(ehci_softc_t *sc)
182{
183 uint32_t hcr;
184 int i;
185
186 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
187 for (i = 0; i < 100; i++) {
188 usb_pause_mtx(NULL, hz / 128);
189 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
190 if (!hcr) {
191 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
192 /*
193 * Force USBMODE as requested. Controllers
194 * may have multiple operating modes.
195 */
196 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
197 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
198 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
199 device_printf(sc->sc_bus.bdev,
200 "set host controller mode\n");
201 }
202 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
203 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
204 device_printf(sc->sc_bus.bdev,
205 "set big-endian mode\n");
206 }
207 EOWRITE4(sc, EHCI_USBMODE, usbmode);
208 }
209 return (0);
210 }
211 }
212 device_printf(sc->sc_bus.bdev, "Reset timeout\n");
213 return (USB_ERR_IOERROR);
214}
215
216static usb_error_t
217ehci_hcreset(ehci_softc_t *sc)
218{
219 uint32_t hcr;
220 int i;
221
222 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
223 for (i = 0; i < 100; i++) {
224 usb_pause_mtx(NULL, hz / 128);
225 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
226 if (hcr)
227 break;
228 }
229 if (!hcr)
230 /*
231 * Fall through and try reset anyway even though
232 * Table 2-9 in the EHCI spec says this will result
233 * in undefined behavior.
234 */
235 device_printf(sc->sc_bus.bdev, "stop timeout\n");
236
237 return (ehci_reset(sc));
238}
239
240static int
241ehci_init_sub(struct ehci_softc *sc)
242{
243 struct usb_page_search buf_res;
244 uint32_t cparams;
245 uint32_t hcr;
246 uint8_t i;
247
248 cparams = EREAD4(sc, EHCI_HCCPARAMS);
249
250 DPRINTF("cparams=0x%x\n", cparams);
251
252 if (EHCI_HCC_64BIT(cparams)) {
253 DPRINTF("HCC uses 64-bit structures\n");
254
255 /* MUST clear segment register if 64 bit capable */
256 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
257 }
258
259 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
260 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
261
262 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
263 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
264
265 /* enable interrupts */
266 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
267
268 /* turn on controller */
269 EOWRITE4(sc, EHCI_USBCMD,
270 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
271 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
272 EHCI_CMD_ASE |
273 EHCI_CMD_PSE |
274 EHCI_CMD_RS);
275
276 /* Take over port ownership */
277 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
278
279 for (i = 0; i < 100; i++) {
280 usb_pause_mtx(NULL, hz / 128);
281 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
282 if (!hcr) {
283 break;
284 }
285 }
286 if (hcr) {
287 device_printf(sc->sc_bus.bdev, "Run timeout\n");
288 return (USB_ERR_IOERROR);
289 }
290 return (USB_ERR_NORMAL_COMPLETION);
291}
292
293usb_error_t
294ehci_init(ehci_softc_t *sc)
295{
296 struct usb_page_search buf_res;
297 uint32_t version;
298 uint32_t sparams;
299 uint16_t i;
300 uint16_t x;
301 uint16_t y;
302 uint16_t bit;
303 usb_error_t err = 0;
304
305 DPRINTF("start\n");
306
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307 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_lock, 0);
308 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_lock, 0);
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309
310 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
311
312#ifdef USB_DEBUG
313 if (ehciiaadbug)
314 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
315 if (ehcilostintrbug)
316 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
317 if (ehcidebug > 2) {
318 ehci_dump_regs(sc);
319 }
320#endif
321
322 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
323 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
324 version >> 8, version & 0xff);
325
326 sparams = EREAD4(sc, EHCI_HCSPARAMS);
327 DPRINTF("sparams=0x%x\n", sparams);
328
329 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
330 sc->sc_bus.usbrev = USB_REV_2_0;
331
332 /* Reset the controller */
333 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
334
335 err = ehci_hcreset(sc);
336 if (err) {
337 device_printf(sc->sc_bus.bdev, "reset timeout\n");
338 return (err);
339 }
340 /*
341 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
342 * bytes 2: 256*4 bytes 3: unknown
343 */
344 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
345 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
346 return (USB_ERR_IOERROR);
347 }
348 /* set up the bus struct */
349 sc->sc_bus.methods = &ehci_bus_methods;
350
351 sc->sc_eintrs = EHCI_NORMAL_INTRS;
352
353 if (1) {
354 struct ehci_qh_sub *qh;
355
356 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
357
358 qh = buf_res.buffer;
359
360 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
361
362 /* init terminate TD */
363 qh->qtd_next =
364 htohc32(sc, EHCI_LINK_TERMINATE);
365 qh->qtd_altnext =
366 htohc32(sc, EHCI_LINK_TERMINATE);
367 qh->qtd_status =
368 htohc32(sc, EHCI_QTD_HALTED);
369 }
370
371 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
372 ehci_qh_t *qh;
373
374 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
375
376 qh = buf_res.buffer;
377
378 /* initialize page cache pointer */
379
380 qh->page_cache = sc->sc_hw.intr_start_pc + i;
381
382 /* store a pointer to queue head */
383
384 sc->sc_intr_p_last[i] = qh;
385
386 qh->qh_self =
387 htohc32(sc, buf_res.physaddr) |
388 htohc32(sc, EHCI_LINK_QH);
389
390 qh->qh_endp =
391 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
392 qh->qh_endphub =
393 htohc32(sc, EHCI_QH_SET_MULT(1));
394 qh->qh_curqtd = 0;
395
396 qh->qh_qtd.qtd_next =
397 htohc32(sc, EHCI_LINK_TERMINATE);
398 qh->qh_qtd.qtd_altnext =
399 htohc32(sc, EHCI_LINK_TERMINATE);
400 qh->qh_qtd.qtd_status =
401 htohc32(sc, EHCI_QTD_HALTED);
402 }
403
404 /*
405 * the QHs are arranged to give poll intervals that are
406 * powers of 2 times 1ms
407 */
408 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
409 while (bit) {
410 x = bit;
411 while (x & bit) {
412 ehci_qh_t *qh_x;
413 ehci_qh_t *qh_y;
414
415 y = (x ^ bit) | (bit / 2);
416
417 qh_x = sc->sc_intr_p_last[x];
418 qh_y = sc->sc_intr_p_last[y];
419
420 /*
421 * the next QH has half the poll interval
422 */
423 qh_x->qh_link = qh_y->qh_self;
424
425 x++;
426 }
427 bit >>= 1;
428 }
429
430 if (1) {
431 ehci_qh_t *qh;
432
433 qh = sc->sc_intr_p_last[0];
434
435 /* the last (1ms) QH terminates */
436 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
437 }
438 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
439 ehci_sitd_t *sitd;
440 ehci_itd_t *itd;
441
442 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
443
444 sitd = buf_res.buffer;
445
446 /* initialize page cache pointer */
447
448 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
449
450 /* store a pointer to the transfer descriptor */
451
452 sc->sc_isoc_fs_p_last[i] = sitd;
453
454 /* initialize full speed isochronous */
455
456 sitd->sitd_self =
457 htohc32(sc, buf_res.physaddr) |
458 htohc32(sc, EHCI_LINK_SITD);
459
460 sitd->sitd_back =
461 htohc32(sc, EHCI_LINK_TERMINATE);
462
463 sitd->sitd_next =
464 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
465
466
467 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
468
469 itd = buf_res.buffer;
470
471 /* initialize page cache pointer */
472
473 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
474
475 /* store a pointer to the transfer descriptor */
476
477 sc->sc_isoc_hs_p_last[i] = itd;
478
479 /* initialize high speed isochronous */
480
481 itd->itd_self =
482 htohc32(sc, buf_res.physaddr) |
483 htohc32(sc, EHCI_LINK_ITD);
484
485 itd->itd_next =
486 sitd->sitd_self;
487 }
488
489 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
490
491 if (1) {
492 uint32_t *pframes;
493
494 pframes = buf_res.buffer;
495
496 /*
497 * execution order:
498 * pframes -> high speed isochronous ->
499 * full speed isochronous -> interrupt QH's
500 */
501 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
502 pframes[i] = sc->sc_isoc_hs_p_last
503 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
504 }
505 }
506 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
507
508 if (1) {
509
510 ehci_qh_t *qh;
511
512 qh = buf_res.buffer;
513
514 /* initialize page cache pointer */
515
516 qh->page_cache = &sc->sc_hw.async_start_pc;
517
518 /* store a pointer to the queue head */
519
520 sc->sc_async_p_last = qh;
521
522 /* init dummy QH that starts the async list */
523
524 qh->qh_self =
525 htohc32(sc, buf_res.physaddr) |
526 htohc32(sc, EHCI_LINK_QH);
527
528 /* fill the QH */
529 qh->qh_endp =
530 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
531 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
532 qh->qh_link = qh->qh_self;
533 qh->qh_curqtd = 0;
534
535 /* fill the overlay qTD */
536 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
537 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
538 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
539 }
540 /* flush all cache into memory */
541
542 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
543
544#ifdef USB_DEBUG
545 if (ehcidebug) {
546 ehci_dump_sqh(sc, sc->sc_async_p_last);
547 }
548#endif
549
550 /* finial setup */
551 err = ehci_init_sub(sc);
552
553 if (!err) {
554 /* catch any lost interrupts */
555 ehci_do_poll(&sc->sc_bus);
556 }
557 return (err);
558}
559
560/*
561 * shut down the controller when the system is going down
562 */
563void
564ehci_detach(ehci_softc_t *sc)
565{
566 USB_BUS_LOCK(&sc->sc_bus);
567
568 usb_callout_stop(&sc->sc_tmo_pcd);
569 usb_callout_stop(&sc->sc_tmo_poll);
570
571 EOWRITE4(sc, EHCI_USBINTR, 0);
572 USB_BUS_UNLOCK(&sc->sc_bus);
573
574 if (ehci_hcreset(sc)) {
575 DPRINTF("reset failed!\n");
576 }
577
578 /* XXX let stray task complete */
579 usb_pause_mtx(NULL, hz / 20);
580
581 usb_callout_drain(&sc->sc_tmo_pcd);
582 usb_callout_drain(&sc->sc_tmo_poll);
583}
584
585static void
586ehci_suspend(ehci_softc_t *sc)
587{
588 DPRINTF("stopping the HC\n");
589
590 /* reset HC */
591 ehci_hcreset(sc);
592}
593
594static void
595ehci_resume(ehci_softc_t *sc)
596{
597 /* reset HC */
598 ehci_hcreset(sc);
599
600 /* setup HC */
601 ehci_init_sub(sc);
602
603 /* catch any lost interrupts */
604 ehci_do_poll(&sc->sc_bus);
605}
606
607#ifdef USB_DEBUG
608static void
609ehci_dump_regs(ehci_softc_t *sc)
610{
611 uint32_t i;
612
613 i = EOREAD4(sc, EHCI_USBCMD);
722d05c3 614 kprintf("cmd=0x%08x\n", i);
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615
616 if (i & EHCI_CMD_ITC_1)
722d05c3 617 kprintf(" EHCI_CMD_ITC_1\n");
12bd3c8b 618 if (i & EHCI_CMD_ITC_2)
722d05c3 619 kprintf(" EHCI_CMD_ITC_2\n");
12bd3c8b 620 if (i & EHCI_CMD_ITC_4)
722d05c3 621 kprintf(" EHCI_CMD_ITC_4\n");
12bd3c8b 622 if (i & EHCI_CMD_ITC_8)
722d05c3 623 kprintf(" EHCI_CMD_ITC_8\n");
12bd3c8b 624 if (i & EHCI_CMD_ITC_16)
722d05c3 625 kprintf(" EHCI_CMD_ITC_16\n");
12bd3c8b 626 if (i & EHCI_CMD_ITC_32)
722d05c3 627 kprintf(" EHCI_CMD_ITC_32\n");
12bd3c8b 628 if (i & EHCI_CMD_ITC_64)
722d05c3 629 kprintf(" EHCI_CMD_ITC_64\n");
12bd3c8b 630 if (i & EHCI_CMD_ASPME)
722d05c3 631 kprintf(" EHCI_CMD_ASPME\n");
12bd3c8b 632 if (i & EHCI_CMD_ASPMC)
722d05c3 633 kprintf(" EHCI_CMD_ASPMC\n");
12bd3c8b 634 if (i & EHCI_CMD_LHCR)
722d05c3 635 kprintf(" EHCI_CMD_LHCR\n");
12bd3c8b 636 if (i & EHCI_CMD_IAAD)
722d05c3 637 kprintf(" EHCI_CMD_IAAD\n");
12bd3c8b 638 if (i & EHCI_CMD_ASE)
722d05c3 639 kprintf(" EHCI_CMD_ASE\n");
12bd3c8b 640 if (i & EHCI_CMD_PSE)
722d05c3 641 kprintf(" EHCI_CMD_PSE\n");
12bd3c8b 642 if (i & EHCI_CMD_FLS_M)
722d05c3 643 kprintf(" EHCI_CMD_FLS_M\n");
12bd3c8b 644 if (i & EHCI_CMD_HCRESET)
722d05c3 645 kprintf(" EHCI_CMD_HCRESET\n");
12bd3c8b 646 if (i & EHCI_CMD_RS)
722d05c3 647 kprintf(" EHCI_CMD_RS\n");
12bd3c8b
SW
648
649 i = EOREAD4(sc, EHCI_USBSTS);
650
722d05c3 651 kprintf("sts=0x%08x\n", i);
12bd3c8b
SW
652
653 if (i & EHCI_STS_ASS)
722d05c3 654 kprintf(" EHCI_STS_ASS\n");
12bd3c8b 655 if (i & EHCI_STS_PSS)
722d05c3 656 kprintf(" EHCI_STS_PSS\n");
12bd3c8b 657 if (i & EHCI_STS_REC)
722d05c3 658 kprintf(" EHCI_STS_REC\n");
12bd3c8b 659 if (i & EHCI_STS_HCH)
722d05c3 660 kprintf(" EHCI_STS_HCH\n");
12bd3c8b 661 if (i & EHCI_STS_IAA)
722d05c3 662 kprintf(" EHCI_STS_IAA\n");
12bd3c8b 663 if (i & EHCI_STS_HSE)
722d05c3 664 kprintf(" EHCI_STS_HSE\n");
12bd3c8b 665 if (i & EHCI_STS_FLR)
722d05c3 666 kprintf(" EHCI_STS_FLR\n");
12bd3c8b 667 if (i & EHCI_STS_PCD)
722d05c3 668 kprintf(" EHCI_STS_PCD\n");
12bd3c8b 669 if (i & EHCI_STS_ERRINT)
722d05c3 670 kprintf(" EHCI_STS_ERRINT\n");
12bd3c8b 671 if (i & EHCI_STS_INT)
722d05c3 672 kprintf(" EHCI_STS_INT\n");
12bd3c8b 673
722d05c3 674 kprintf("ien=0x%08x\n",
12bd3c8b 675 EOREAD4(sc, EHCI_USBINTR));
722d05c3 676 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
12bd3c8b
SW
677 EOREAD4(sc, EHCI_FRINDEX),
678 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
679 EOREAD4(sc, EHCI_PERIODICLISTBASE),
680 EOREAD4(sc, EHCI_ASYNCLISTADDR));
681 for (i = 1; i <= sc->sc_noport; i++) {
722d05c3 682 kprintf("port %d status=0x%08x\n", i,
12bd3c8b
SW
683 EOREAD4(sc, EHCI_PORTSC(i)));
684 }
685}
686
687static void
688ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
689{
690 link = hc32toh(sc, link);
722d05c3 691 kprintf("0x%08x", link);
12bd3c8b 692 if (link & EHCI_LINK_TERMINATE)
722d05c3 693 kprintf("<T>");
12bd3c8b 694 else {
722d05c3 695 kprintf("<");
12bd3c8b
SW
696 if (type) {
697 switch (EHCI_LINK_TYPE(link)) {
698 case EHCI_LINK_ITD:
722d05c3 699 kprintf("ITD");
12bd3c8b
SW
700 break;
701 case EHCI_LINK_QH:
722d05c3 702 kprintf("QH");
12bd3c8b
SW
703 break;
704 case EHCI_LINK_SITD:
722d05c3 705 kprintf("SITD");
12bd3c8b
SW
706 break;
707 case EHCI_LINK_FSTN:
722d05c3 708 kprintf("FSTN");
12bd3c8b
SW
709 break;
710 }
711 }
722d05c3 712 kprintf(">");
12bd3c8b
SW
713 }
714}
715
716static void
717ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
718{
719 uint32_t s;
720
722d05c3 721 kprintf(" next=");
12bd3c8b 722 ehci_dump_link(sc, qtd->qtd_next, 0);
722d05c3 723 kprintf(" altnext=");
12bd3c8b 724 ehci_dump_link(sc, qtd->qtd_altnext, 0);
722d05c3 725 kprintf("\n");
12bd3c8b 726 s = hc32toh(sc, qtd->qtd_status);
722d05c3 727 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
12bd3c8b
SW
728 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
729 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
722d05c3 730 kprintf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
12bd3c8b
SW
731 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
732 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
733 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
734 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
735 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
736 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
737 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
738 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
739 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
740
741 for (s = 0; s < 5; s++) {
722d05c3 742 kprintf(" buffer[%d]=0x%08x\n", s,
12bd3c8b
SW
743 hc32toh(sc, qtd->qtd_buffer[s]));
744 }
745 for (s = 0; s < 5; s++) {
722d05c3 746 kprintf(" buffer_hi[%d]=0x%08x\n", s,
12bd3c8b
SW
747 hc32toh(sc, qtd->qtd_buffer_hi[s]));
748 }
749}
750
751static uint8_t
752ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
753{
754 uint8_t temp;
755
756 usb_pc_cpu_invalidate(sqtd->page_cache);
722d05c3 757 kprintf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
12bd3c8b
SW
758 ehci_dump_qtd(sc, sqtd);
759 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
760 return (temp);
761}
762
763static void
764ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
765{
766 uint16_t i;
767 uint8_t stop;
768
769 stop = 0;
770 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
771 stop = ehci_dump_sqtd(sc, sqtd);
772 }
773 if (sqtd) {
722d05c3 774 kprintf("dump aborted, too many TDs\n");
12bd3c8b
SW
775 }
776}
777
778static void
779ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
780{
781 uint32_t endp;
782 uint32_t endphub;
783
784 usb_pc_cpu_invalidate(qh->page_cache);
722d05c3
SW
785 kprintf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
786 kprintf(" link=");
12bd3c8b 787 ehci_dump_link(sc, qh->qh_link, 1);
722d05c3 788 kprintf("\n");
12bd3c8b 789 endp = hc32toh(sc, qh->qh_endp);
722d05c3
SW
790 kprintf(" endp=0x%08x\n", endp);
791 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
12bd3c8b
SW
792 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
793 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
794 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
722d05c3 795 kprintf(" mpl=0x%x ctl=%d nrl=%d\n",
12bd3c8b
SW
796 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
797 EHCI_QH_GET_NRL(endp));
798 endphub = hc32toh(sc, qh->qh_endphub);
722d05c3
SW
799 kprintf(" endphub=0x%08x\n", endphub);
800 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
12bd3c8b
SW
801 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
802 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
803 EHCI_QH_GET_MULT(endphub));
722d05c3 804 kprintf(" curqtd=");
12bd3c8b 805 ehci_dump_link(sc, qh->qh_curqtd, 0);
722d05c3
SW
806 kprintf("\n");
807 kprintf("Overlay qTD:\n");
12bd3c8b
SW
808 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
809}
810
811static void
812ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
813{
814 usb_pc_cpu_invalidate(sitd->page_cache);
722d05c3
SW
815 kprintf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
816 kprintf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
817 kprintf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
12bd3c8b
SW
818 hc32toh(sc, sitd->sitd_portaddr),
819 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
820 ? "in" : "out",
821 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
822 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
823 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
824 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
722d05c3
SW
825 kprintf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
826 kprintf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
12bd3c8b
SW
827 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
828 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
722d05c3 829 kprintf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
12bd3c8b
SW
830 hc32toh(sc, sitd->sitd_back),
831 hc32toh(sc, sitd->sitd_bp[0]),
832 hc32toh(sc, sitd->sitd_bp[1]),
833 hc32toh(sc, sitd->sitd_bp_hi[0]),
834 hc32toh(sc, sitd->sitd_bp_hi[1]));
835}
836
837static void
838ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
839{
840 usb_pc_cpu_invalidate(itd->page_cache);
722d05c3
SW
841 kprintf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
842 kprintf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
843 kprintf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
12bd3c8b 844 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 845 kprintf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
12bd3c8b 846 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 847 kprintf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
12bd3c8b 848 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 849 kprintf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
12bd3c8b 850 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 851 kprintf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
12bd3c8b 852 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 853 kprintf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
12bd3c8b 854 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 855 kprintf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
12bd3c8b 856 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3 857 kprintf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
12bd3c8b 858 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
722d05c3
SW
859 kprintf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
860 kprintf(" addr=0x%02x; endpt=0x%01x\n",
12bd3c8b
SW
861 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
862 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
722d05c3
SW
863 kprintf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
864 kprintf(" dir=%s; mpl=0x%02x\n",
12bd3c8b
SW
865 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
866 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
722d05c3 867 kprintf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
12bd3c8b
SW
868 hc32toh(sc, itd->itd_bp[2]),
869 hc32toh(sc, itd->itd_bp[3]),
870 hc32toh(sc, itd->itd_bp[4]),
871 hc32toh(sc, itd->itd_bp[5]),
872 hc32toh(sc, itd->itd_bp[6]));
722d05c3 873 kprintf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
12bd3c8b
SW
874 " 0x%08x,0x%08x,0x%08x\n",
875 hc32toh(sc, itd->itd_bp_hi[0]),
876 hc32toh(sc, itd->itd_bp_hi[1]),
877 hc32toh(sc, itd->itd_bp_hi[2]),
878 hc32toh(sc, itd->itd_bp_hi[3]),
879 hc32toh(sc, itd->itd_bp_hi[4]),
880 hc32toh(sc, itd->itd_bp_hi[5]),
881 hc32toh(sc, itd->itd_bp_hi[6]));
882}
883
884static void
885ehci_dump_isoc(ehci_softc_t *sc)
886{
887 ehci_itd_t *itd;
888 ehci_sitd_t *sitd;
889 uint16_t max = 1000;
890 uint16_t pos;
891
892 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
893 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
894
722d05c3 895 kprintf("%s: isochronous dump from frame 0x%03x:\n",
12bd3c8b
SW
896 __FUNCTION__, pos);
897
898 itd = sc->sc_isoc_hs_p_last[pos];
899 sitd = sc->sc_isoc_fs_p_last[pos];
900
901 while (itd && max && max--) {
902 ehci_dump_itd(sc, itd);
903 itd = itd->prev;
904 }
905
906 while (sitd && max && max--) {
907 ehci_dump_sitd(sc, sitd);
908 sitd = sitd->prev;
909 }
910}
911
912#endif
913
914static void
915ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
916{
917 /* check for early completion */
918 if (ehci_check_transfer(xfer)) {
919 return;
920 }
921 /* put transfer on interrupt queue */
922 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
923
924 /* start timeout, if any */
925 if (xfer->timeout != 0) {
926 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
927 }
928}
929
930#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
931static ehci_sitd_t *
932_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
933{
934 DPRINTFN(11, "%p to %p\n", std, last);
935
936 /* (sc->sc_bus.mtx) must be locked */
937
938 std->next = last->next;
939 std->sitd_next = last->sitd_next;
940
941 std->prev = last;
942
943 usb_pc_cpu_flush(std->page_cache);
944
945 /*
946 * the last->next->prev is never followed: std->next->prev = std;
947 */
948 last->next = std;
949 last->sitd_next = std->sitd_self;
950
951 usb_pc_cpu_flush(last->page_cache);
952
953 return (std);
954}
955
956#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
957static ehci_itd_t *
958_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
959{
960 DPRINTFN(11, "%p to %p\n", std, last);
961
962 /* (sc->sc_bus.mtx) must be locked */
963
964 std->next = last->next;
965 std->itd_next = last->itd_next;
966
967 std->prev = last;
968
969 usb_pc_cpu_flush(std->page_cache);
970
971 /*
972 * the last->next->prev is never followed: std->next->prev = std;
973 */
974 last->next = std;
975 last->itd_next = std->itd_self;
976
977 usb_pc_cpu_flush(last->page_cache);
978
979 return (std);
980}
981
982#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
983static ehci_qh_t *
984_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
985{
986 DPRINTFN(11, "%p to %p\n", sqh, last);
987
988 if (sqh->prev != NULL) {
989 /* should not happen */
990 DPRINTFN(0, "QH already linked!\n");
991 return (last);
992 }
993 /* (sc->sc_bus.mtx) must be locked */
994
995 sqh->next = last->next;
996 sqh->qh_link = last->qh_link;
997
998 sqh->prev = last;
999
1000 usb_pc_cpu_flush(sqh->page_cache);
1001
1002 /*
1003 * the last->next->prev is never followed: sqh->next->prev = sqh;
1004 */
1005
1006 last->next = sqh;
1007 last->qh_link = sqh->qh_self;
1008
1009 usb_pc_cpu_flush(last->page_cache);
1010
1011 return (sqh);
1012}
1013
1014#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1015static ehci_sitd_t *
1016_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1017{
1018 DPRINTFN(11, "%p from %p\n", std, last);
1019
1020 /* (sc->sc_bus.mtx) must be locked */
1021
1022 std->prev->next = std->next;
1023 std->prev->sitd_next = std->sitd_next;
1024
1025 usb_pc_cpu_flush(std->prev->page_cache);
1026
1027 if (std->next) {
1028 std->next->prev = std->prev;
1029 usb_pc_cpu_flush(std->next->page_cache);
1030 }
1031 return ((last == std) ? std->prev : last);
1032}
1033
1034#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1035static ehci_itd_t *
1036_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1037{
1038 DPRINTFN(11, "%p from %p\n", std, last);
1039
1040 /* (sc->sc_bus.mtx) must be locked */
1041
1042 std->prev->next = std->next;
1043 std->prev->itd_next = std->itd_next;
1044
1045 usb_pc_cpu_flush(std->prev->page_cache);
1046
1047 if (std->next) {
1048 std->next->prev = std->prev;
1049 usb_pc_cpu_flush(std->next->page_cache);
1050 }
1051 return ((last == std) ? std->prev : last);
1052}
1053
1054#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1055static ehci_qh_t *
1056_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1057{
1058 DPRINTFN(11, "%p from %p\n", sqh, last);
1059
1060 /* (sc->sc_bus.mtx) must be locked */
1061
1062 /* only remove if not removed from a queue */
1063 if (sqh->prev) {
1064
1065 sqh->prev->next = sqh->next;
1066 sqh->prev->qh_link = sqh->qh_link;
1067
1068 usb_pc_cpu_flush(sqh->prev->page_cache);
1069
1070 if (sqh->next) {
1071 sqh->next->prev = sqh->prev;
1072 usb_pc_cpu_flush(sqh->next->page_cache);
1073 }
1074 last = ((last == sqh) ? sqh->prev : last);
1075
1076 sqh->prev = 0;
1077
1078 usb_pc_cpu_flush(sqh->page_cache);
1079 }
1080 return (last);
1081}
1082
1083static void
1084ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1085{
1086 uint16_t rem;
1087 uint8_t dt;
1088
1089 /* count number of full packets */
1090 dt = (actlen / xfer->max_packet_size) & 1;
1091
1092 /* compute remainder */
1093 rem = actlen % xfer->max_packet_size;
1094
1095 if (rem > 0)
1096 dt ^= 1; /* short packet at the end */
1097 else if (actlen != xlen)
1098 dt ^= 1; /* zero length packet at the end */
1099 else if (xlen == 0)
1100 dt ^= 1; /* zero length transfer */
1101
1102 xfer->endpoint->toggle_next ^= dt;
1103}
1104
1105static usb_error_t
1106ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1107{
1108 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1109 ehci_qtd_t *td;
1110 ehci_qtd_t *td_alt_next;
1111 uint32_t status;
1112 uint16_t len;
1113
1114 td = xfer->td_transfer_cache;
1115 td_alt_next = td->alt_next;
1116
1117 if (xfer->aframes != xfer->nframes) {
1118 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1119 }
1120 while (1) {
1121
1122 usb_pc_cpu_invalidate(td->page_cache);
1123 status = hc32toh(sc, td->qtd_status);
1124
1125 len = EHCI_QTD_GET_BYTES(status);
1126
1127 /*
1128 * Verify the status length and
1129 * add the length to "frlengths[]":
1130 */
1131 if (len > td->len) {
1132 /* should not happen */
1133 DPRINTF("Invalid status length, "
1134 "0x%04x/0x%04x bytes\n", len, td->len);
1135 status |= EHCI_QTD_HALTED;
1136 } else if (xfer->aframes != xfer->nframes) {
1137 xfer->frlengths[xfer->aframes] += td->len - len;
1138 /* manually update data toggle */
1139 ehci_data_toggle_update(xfer, td->len - len, td->len);
1140 }
1141
1142 /* Check for last transfer */
1143 if (((void *)td) == xfer->td_transfer_last) {
1144 td = NULL;
1145 break;
1146 }
1147 /* Check for transfer error */
1148 if (status & EHCI_QTD_HALTED) {
1149 /* the transfer is finished */
1150 td = NULL;
1151 break;
1152 }
1153 /* Check for short transfer */
1154 if (len > 0) {
1155 if (xfer->flags_int.short_frames_ok) {
1156 /* follow alt next */
1157 td = td->alt_next;
1158 } else {
1159 /* the transfer is finished */
1160 td = NULL;
1161 }
1162 break;
1163 }
1164 td = td->obj_next;
1165
1166 if (td->alt_next != td_alt_next) {
1167 /* this USB frame is complete */
1168 break;
1169 }
1170 }
1171
1172 /* update transfer cache */
1173
1174 xfer->td_transfer_cache = td;
1175
1176#ifdef USB_DEBUG
1177 if (status & EHCI_QTD_STATERRS) {
1178 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1179 "status=%s%s%s%s%s%s%s%s\n",
1180 xfer->address, xfer->endpointno, xfer->aframes,
1181 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1182 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1183 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1184 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1185 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1186 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1187 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1188 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1189 }
1190#endif
1191
1192 return ((status & EHCI_QTD_HALTED) ?
1193 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1194}
1195
1196static void
1197ehci_non_isoc_done(struct usb_xfer *xfer)
1198{
1199 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1200 ehci_qh_t *qh;
1201 uint32_t status;
1202 usb_error_t err = 0;
1203
1204 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1205 xfer, xfer->endpoint);
1206
1207#ifdef USB_DEBUG
1208 if (ehcidebug > 10) {
1209 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1210
1211 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1212 }
1213#endif
1214
1215 /* extract data toggle directly from the QH's overlay area */
1216
1217 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1218
1219 usb_pc_cpu_invalidate(qh->page_cache);
1220
1221 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1222
1223 /* reset scanner */
1224
1225 xfer->td_transfer_cache = xfer->td_transfer_first;
1226
1227 if (xfer->flags_int.control_xfr) {
1228
1229 if (xfer->flags_int.control_hdr) {
1230
1231 err = ehci_non_isoc_done_sub(xfer);
1232 }
1233 xfer->aframes = 1;
1234
1235 if (xfer->td_transfer_cache == NULL) {
1236 goto done;
1237 }
1238 }
1239 while (xfer->aframes != xfer->nframes) {
1240
1241 err = ehci_non_isoc_done_sub(xfer);
1242 xfer->aframes++;
1243
1244 if (xfer->td_transfer_cache == NULL) {
1245 goto done;
1246 }
1247 }
1248
1249 if (xfer->flags_int.control_xfr &&
1250 !xfer->flags_int.control_act) {
1251
1252 err = ehci_non_isoc_done_sub(xfer);
1253 }
1254done:
1255 ehci_device_done(xfer, err);
1256}
1257
1258/*------------------------------------------------------------------------*
1259 * ehci_check_transfer
1260 *
1261 * Return values:
1262 * 0: USB transfer is not finished
1263 * Else: USB transfer is finished
1264 *------------------------------------------------------------------------*/
1265static uint8_t
1266ehci_check_transfer(struct usb_xfer *xfer)
1267{
1268 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1269 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1270
1271 uint32_t status;
1272
1273 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1274
1275 if (methods == &ehci_device_isoc_fs_methods) {
1276 ehci_sitd_t *td;
1277
1278 /* isochronous full speed transfer */
1279
1280 td = xfer->td_transfer_last;
1281 usb_pc_cpu_invalidate(td->page_cache);
1282 status = hc32toh(sc, td->sitd_status);
1283
1284 /* also check if first is complete */
1285
1286 td = xfer->td_transfer_first;
1287 usb_pc_cpu_invalidate(td->page_cache);
1288 status |= hc32toh(sc, td->sitd_status);
1289
1290 if (!(status & EHCI_SITD_ACTIVE)) {
1291 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1292 goto transferred;
1293 }
1294 } else if (methods == &ehci_device_isoc_hs_methods) {
1295 ehci_itd_t *td;
1296
1297 /* isochronous high speed transfer */
1298
1299 /* check last transfer */
1300 td = xfer->td_transfer_last;
1301 usb_pc_cpu_invalidate(td->page_cache);
1302 status = td->itd_status[0];
1303 status |= td->itd_status[1];
1304 status |= td->itd_status[2];
1305 status |= td->itd_status[3];
1306 status |= td->itd_status[4];
1307 status |= td->itd_status[5];
1308 status |= td->itd_status[6];
1309 status |= td->itd_status[7];
1310
1311 /* also check first transfer */
1312 td = xfer->td_transfer_first;
1313 usb_pc_cpu_invalidate(td->page_cache);
1314 status |= td->itd_status[0];
1315 status |= td->itd_status[1];
1316 status |= td->itd_status[2];
1317 status |= td->itd_status[3];
1318 status |= td->itd_status[4];
1319 status |= td->itd_status[5];
1320 status |= td->itd_status[6];
1321 status |= td->itd_status[7];
1322
1323 /* if no transactions are active we continue */
1324 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1325 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1326 goto transferred;
1327 }
1328 } else {
1329 ehci_qtd_t *td;
1330 ehci_qh_t *qh;
1331
1332 /* non-isochronous transfer */
1333
1334 /*
1335 * check whether there is an error somewhere in the middle,
1336 * or whether there was a short packet (SPD and not ACTIVE)
1337 */
1338 td = xfer->td_transfer_cache;
1339
1340 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1341
1342 usb_pc_cpu_invalidate(qh->page_cache);
1343
1344 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1345 if (status & EHCI_QTD_ACTIVE) {
1346 /* transfer is pending */
1347 goto done;
1348 }
1349
1350 while (1) {
1351 usb_pc_cpu_invalidate(td->page_cache);
1352 status = hc32toh(sc, td->qtd_status);
1353
1354 /*
1355 * Check if there is an active TD which
1356 * indicates that the transfer isn't done.
1357 */
1358 if (status & EHCI_QTD_ACTIVE) {
1359 /* update cache */
1360 xfer->td_transfer_cache = td;
1361 goto done;
1362 }
1363 /*
1364 * last transfer descriptor makes the transfer done
1365 */
1366 if (((void *)td) == xfer->td_transfer_last) {
1367 break;
1368 }
1369 /*
1370 * any kind of error makes the transfer done
1371 */
1372 if (status & EHCI_QTD_HALTED) {
1373 break;
1374 }
1375 /*
1376 * if there is no alternate next transfer, a short
1377 * packet also makes the transfer done
1378 */
1379 if (EHCI_QTD_GET_BYTES(status)) {
1380 if (xfer->flags_int.short_frames_ok) {
1381 /* follow alt next */
1382 if (td->alt_next) {
1383 td = td->alt_next;
1384 continue;
1385 }
1386 }
1387 /* transfer is done */
1388 break;
1389 }
1390 td = td->obj_next;
1391 }
1392 ehci_non_isoc_done(xfer);
1393 goto transferred;
1394 }
1395
1396done:
1397 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1398 return (0);
1399
1400transferred:
1401 return (1);
1402}
1403
1404static void
1405ehci_pcd_enable(ehci_softc_t *sc)
1406{
722d05c3 1407 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
12bd3c8b
SW
1408 sc->sc_eintrs |= EHCI_STS_PCD;
1409 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1410
1411 /* acknowledge any PCD interrupt */
1412 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1413
1414 ehci_root_intr(sc);
1415}
1416
1417static void
1418ehci_interrupt_poll(ehci_softc_t *sc)
1419{
1420 struct usb_xfer *xfer;
1421
1422repeat:
1423 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1424 /*
1425 * check if transfer is transferred
1426 */
1427 if (ehci_check_transfer(xfer)) {
1428 /* queue has been modified */
1429 goto repeat;
1430 }
1431 }
1432}
1433
1434/*
1435 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1436 * writing back the qTD status, or miss signalling occasionally under
1437 * heavy load. If the host machine is too fast, we can miss
1438 * transaction completion - when we scan the active list the
1439 * transaction still seems to be active. This generally exhibits
1440 * itself as a umass stall that never recovers.
1441 *
1442 * We work around this behaviour by setting up this callback after any
1443 * softintr that completes with transactions still pending, giving us
1444 * another chance to check for completion after the writeback has
1445 * taken place.
1446 */
1447static void
1448ehci_poll_timeout(void *arg)
1449{
1450 ehci_softc_t *sc = arg;
1451
1452 DPRINTFN(3, "\n");
1453 ehci_interrupt_poll(sc);
1454}
1455
1456/*------------------------------------------------------------------------*
1457 * ehci_interrupt - EHCI interrupt handler
1458 *
1459 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1460 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1461 * is present !
1462 *------------------------------------------------------------------------*/
1463void
1464ehci_interrupt(ehci_softc_t *sc)
1465{
1466 uint32_t status;
1467
1468 USB_BUS_LOCK(&sc->sc_bus);
1469
1470 DPRINTFN(16, "real interrupt\n");
1471
1472#ifdef USB_DEBUG
1473 if (ehcidebug > 15) {
1474 ehci_dump_regs(sc);
1475 }
1476#endif
1477
1478 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1479 if (status == 0) {
1480 /* the interrupt was not for us */
1481 goto done;
1482 }
1483 if (!(status & sc->sc_eintrs)) {
1484 goto done;
1485 }
1486 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1487
1488 status &= sc->sc_eintrs;
1489
1490 if (status & EHCI_STS_HSE) {
722d05c3 1491 kprintf("%s: unrecoverable error, "
12bd3c8b
SW
1492 "controller halted\n", __FUNCTION__);
1493#ifdef USB_DEBUG
1494 ehci_dump_regs(sc);
1495 ehci_dump_isoc(sc);
1496#endif
1497 }
1498 if (status & EHCI_STS_PCD) {
1499 /*
1500 * Disable PCD interrupt for now, because it will be
1501 * on until the port has been reset.
1502 */
1503 sc->sc_eintrs &= ~EHCI_STS_PCD;
1504 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1505
1506 ehci_root_intr(sc);
1507
1508 /* do not allow RHSC interrupts > 1 per second */
1509 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1510 (void *)&ehci_pcd_enable, sc);
1511 }
1512 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1513
1514 if (status != 0) {
1515 /* block unprocessed interrupts */
1516 sc->sc_eintrs &= ~status;
1517 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
722d05c3 1518 kprintf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
12bd3c8b
SW
1519 }
1520 /* poll all the USB transfers */
1521 ehci_interrupt_poll(sc);
1522
1523 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1524 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1525 (void *)&ehci_poll_timeout, sc);
1526 }
1527
1528done:
1529 USB_BUS_UNLOCK(&sc->sc_bus);
1530}
1531
1532/*
1533 * called when a request does not complete
1534 */
1535static void
1536ehci_timeout(void *arg)
1537{
1538 struct usb_xfer *xfer = arg;
1539
1540 DPRINTF("xfer=%p\n", xfer);
1541
722d05c3 1542 USB_BUS_LOCK_ASSERT(xfer->xroot->bus);
12bd3c8b
SW
1543
1544 /* transfer is transferred */
1545 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1546}
1547
1548static void
1549ehci_do_poll(struct usb_bus *bus)
1550{
1551 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1552
1553 USB_BUS_LOCK(&sc->sc_bus);
1554 ehci_interrupt_poll(sc);
1555 USB_BUS_UNLOCK(&sc->sc_bus);
1556}
1557
1558static void
1559ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1560{
1561 struct usb_page_search buf_res;
1562 ehci_qtd_t *td;
1563 ehci_qtd_t *td_next;
1564 ehci_qtd_t *td_alt_next;
1565 uint32_t buf_offset;
1566 uint32_t average;
1567 uint32_t len_old;
1568 uint32_t terminate;
1569 uint32_t qtd_altnext;
1570 uint8_t shortpkt_old;
1571 uint8_t precompute;
1572
1573 terminate = temp->sc->sc_terminate_self;
1574 qtd_altnext = temp->sc->sc_terminate_self;
1575 td_alt_next = NULL;
1576 buf_offset = 0;
1577 shortpkt_old = temp->shortpkt;
1578 len_old = temp->len;
1579 precompute = 1;
1580
1581restart:
1582
1583 td = temp->td;
1584 td_next = temp->td_next;
1585
1586 while (1) {
1587
1588 if (temp->len == 0) {
1589
1590 if (temp->shortpkt) {
1591 break;
1592 }
1593 /* send a Zero Length Packet, ZLP, last */
1594
1595 temp->shortpkt = 1;
1596 average = 0;
1597
1598 } else {
1599
1600 average = temp->average;
1601
1602 if (temp->len < average) {
1603 if (temp->len % temp->max_frame_size) {
1604 temp->shortpkt = 1;
1605 }
1606 average = temp->len;
1607 }
1608 }
1609
1610 if (td_next == NULL) {
1611 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1612 }
1613 /* get next TD */
1614
1615 td = td_next;
1616 td_next = td->obj_next;
1617
1618 /* check if we are pre-computing */
1619
1620 if (precompute) {
1621
1622 /* update remaining length */
1623
1624 temp->len -= average;
1625
1626 continue;
1627 }
1628 /* fill out current TD */
1629
1630 td->qtd_status =
1631 temp->qtd_status |
1632 htohc32(temp->sc, EHCI_QTD_IOC |
1633 EHCI_QTD_SET_BYTES(average));
1634
1635 if (average == 0) {
1636
1637 if (temp->auto_data_toggle == 0) {
1638
1639 /* update data toggle, ZLP case */
1640
1641 temp->qtd_status ^=
1642 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1643 }
1644 td->len = 0;
1645
1646 td->qtd_buffer[0] = 0;
1647 td->qtd_buffer_hi[0] = 0;
1648
1649 td->qtd_buffer[1] = 0;
1650 td->qtd_buffer_hi[1] = 0;
1651
1652 } else {
1653
1654 uint8_t x;
1655
1656 if (temp->auto_data_toggle == 0) {
1657
1658 /* update data toggle */
1659
1660 if (((average + temp->max_frame_size - 1) /
1661 temp->max_frame_size) & 1) {
1662 temp->qtd_status ^=
1663 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1664 }
1665 }
1666 td->len = average;
1667
1668 /* update remaining length */
1669
1670 temp->len -= average;
1671
1672 /* fill out buffer pointers */
1673
1674 usbd_get_page(temp->pc, buf_offset, &buf_res);
1675 td->qtd_buffer[0] =
1676 htohc32(temp->sc, buf_res.physaddr);
1677 td->qtd_buffer_hi[0] = 0;
1678
1679 x = 1;
1680
1681 while (average > EHCI_PAGE_SIZE) {
1682 average -= EHCI_PAGE_SIZE;
1683 buf_offset += EHCI_PAGE_SIZE;
1684 usbd_get_page(temp->pc, buf_offset, &buf_res);
1685 td->qtd_buffer[x] =
1686 htohc32(temp->sc,
1687 buf_res.physaddr & (~0xFFF));
1688 td->qtd_buffer_hi[x] = 0;
1689 x++;
1690 }
1691
1692 /*
1693 * NOTE: The "average" variable is never zero after
1694 * exiting the loop above !
1695 *
1696 * NOTE: We have to subtract one from the offset to
1697 * ensure that we are computing the physical address
1698 * of a valid page !
1699 */
1700 buf_offset += average;
1701 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1702 td->qtd_buffer[x] =
1703 htohc32(temp->sc,
1704 buf_res.physaddr & (~0xFFF));
1705 td->qtd_buffer_hi[x] = 0;
1706 }
1707
1708 if (td_next) {
1709 /* link the current TD with the next one */
1710 td->qtd_next = td_next->qtd_self;
1711 }
1712 td->qtd_altnext = qtd_altnext;
1713 td->alt_next = td_alt_next;
1714
1715 usb_pc_cpu_flush(td->page_cache);
1716 }
1717
1718 if (precompute) {
1719 precompute = 0;
1720
1721 /* setup alt next pointer, if any */
1722 if (temp->last_frame) {
1723 td_alt_next = NULL;
1724 qtd_altnext = terminate;
1725 } else {
1726 /* we use this field internally */
1727 td_alt_next = td_next;
1728 if (temp->setup_alt_next) {
1729 qtd_altnext = td_next->qtd_self;
1730 } else {
1731 qtd_altnext = terminate;
1732 }
1733 }
1734
1735 /* restore */
1736 temp->shortpkt = shortpkt_old;
1737 temp->len = len_old;
1738 goto restart;
1739 }
1740 temp->td = td;
1741 temp->td_next = td_next;
1742}
1743
1744static void
1745ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1746{
1747 struct ehci_std_temp temp;
1748 struct usb_pipe_methods *methods;
1749 ehci_qh_t *qh;
1750 ehci_qtd_t *td;
1751 uint32_t qh_endp;
1752 uint32_t qh_endphub;
1753 uint32_t x;
1754
1755 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1756 xfer->address, UE_GET_ADDR(xfer->endpointno),
1757 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1758
1759 temp.average = xfer->max_hc_frame_size;
1760 temp.max_frame_size = xfer->max_frame_size;
1761 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1762
1763 /* toggle the DMA set we are using */
1764 xfer->flags_int.curr_dma_set ^= 1;
1765
1766 /* get next DMA set */
1767 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1768
1769 xfer->td_transfer_first = td;
1770 xfer->td_transfer_cache = td;
1771
1772 temp.td = NULL;
1773 temp.td_next = td;
1774 temp.qtd_status = 0;
1775 temp.last_frame = 0;
1776 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1777
1778 if (xfer->flags_int.control_xfr) {
1779 if (xfer->endpoint->toggle_next) {
1780 /* DATA1 is next */
1781 temp.qtd_status |=
1782 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1783 }
1784 temp.auto_data_toggle = 0;
1785 } else {
1786 temp.auto_data_toggle = 1;
1787 }
1788
1789 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1790 (xfer->xroot->udev->address != 0)) {
1791 /* max 3 retries */
1792 temp.qtd_status |=
1793 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1794 }
1795 /* check if we should prepend a setup message */
1796
1797 if (xfer->flags_int.control_xfr) {
1798 if (xfer->flags_int.control_hdr) {
1799
1800 xfer->endpoint->toggle_next = 0;
1801
1802 temp.qtd_status &=
1803 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1804 temp.qtd_status |= htohc32(temp.sc,
1805 EHCI_QTD_ACTIVE |
1806 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1807 EHCI_QTD_SET_TOGGLE(0));
1808
1809 temp.len = xfer->frlengths[0];
1810 temp.pc = xfer->frbuffers + 0;
1811 temp.shortpkt = temp.len ? 1 : 0;
1812 /* check for last frame */
1813 if (xfer->nframes == 1) {
1814 /* no STATUS stage yet, SETUP is last */
1815 if (xfer->flags_int.control_act) {
1816 temp.last_frame = 1;
1817 temp.setup_alt_next = 0;
1818 }
1819 }
1820 ehci_setup_standard_chain_sub(&temp);
1821 }
1822 x = 1;
1823 } else {
1824 x = 0;
1825 }
1826
1827 while (x != xfer->nframes) {
1828
1829 /* DATA0 / DATA1 message */
1830
1831 temp.len = xfer->frlengths[x];
1832 temp.pc = xfer->frbuffers + x;
1833
1834 x++;
1835
1836 if (x == xfer->nframes) {
1837 if (xfer->flags_int.control_xfr) {
1838 /* no STATUS stage yet, DATA is last */
1839 if (xfer->flags_int.control_act) {
1840 temp.last_frame = 1;
1841 temp.setup_alt_next = 0;
1842 }
1843 } else {
1844 temp.last_frame = 1;
1845 temp.setup_alt_next = 0;
1846 }
1847 }
1848 /* keep previous data toggle and error count */
1849
1850 temp.qtd_status &=
1851 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1852 EHCI_QTD_SET_TOGGLE(1));
1853
1854 if (temp.len == 0) {
1855
1856 /* make sure that we send an USB packet */
1857
1858 temp.shortpkt = 0;
1859
1860 } else {
1861
1862 /* regular data transfer */
1863
1864 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1865 }
1866
1867 /* set endpoint direction */
1868
1869 temp.qtd_status |=
1870 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1871 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1872 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1873 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1874 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1875
1876 ehci_setup_standard_chain_sub(&temp);
1877 }
1878
1879 /* check if we should append a status stage */
1880
1881 if (xfer->flags_int.control_xfr &&
1882 !xfer->flags_int.control_act) {
1883
1884 /*
1885 * Send a DATA1 message and invert the current endpoint
1886 * direction.
1887 */
1888
1889 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1890 EHCI_QTD_SET_TOGGLE(1));
1891 temp.qtd_status |=
1892 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1893 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1894 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1895 EHCI_QTD_SET_TOGGLE(1)) :
1896 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1897 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1898 EHCI_QTD_SET_TOGGLE(1));
1899
1900 temp.len = 0;
1901 temp.pc = NULL;
1902 temp.shortpkt = 0;
1903 temp.last_frame = 1;
1904 temp.setup_alt_next = 0;
1905
1906 ehci_setup_standard_chain_sub(&temp);
1907 }
1908 td = temp.td;
1909
1910 /* the last TD terminates the transfer: */
1911 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1912 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1913
1914 usb_pc_cpu_flush(td->page_cache);
1915
1916 /* must have at least one frame! */
1917
1918 xfer->td_transfer_last = td;
1919
1920#ifdef USB_DEBUG
1921 if (ehcidebug > 8) {
1922 DPRINTF("nexttog=%d; data before transfer:\n",
1923 xfer->endpoint->toggle_next);
1924 ehci_dump_sqtds(temp.sc,
1925 xfer->td_transfer_first);
1926 }
1927#endif
1928
1929 methods = xfer->endpoint->methods;
1930
1931 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1932
1933 /* the "qh_link" field is filled when the QH is added */
1934
1935 qh_endp =
1936 (EHCI_QH_SET_ADDR(xfer->address) |
1937 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1938 EHCI_QH_SET_MPL(xfer->max_packet_size));
1939
1940 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1941 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1942 if (methods != &ehci_device_intr_methods)
1943 qh_endp |= EHCI_QH_SET_NRL(8);
1944 } else {
1945
1946 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1947 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1948 } else {
1949 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1950 }
1951
1952 if (methods == &ehci_device_ctrl_methods) {
1953 qh_endp |= EHCI_QH_CTL;
1954 }
1955 if (methods != &ehci_device_intr_methods) {
1956 /* Only try one time per microframe! */
1957 qh_endp |= EHCI_QH_SET_NRL(1);
1958 }
1959 }
1960
1961 if (temp.auto_data_toggle == 0) {
1962 /* software computes the data toggle */
1963 qh_endp |= EHCI_QH_DTC;
1964 }
1965
1966 qh->qh_endp = htohc32(temp.sc, qh_endp);
1967
1968 qh_endphub =
1969 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1970 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1971 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1972 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1973 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1974
1975 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1976 qh->qh_curqtd = 0;
1977
1978 /* fill the overlay qTD */
1979
1980 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
1981 /* DATA1 is next */
1982 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1983 } else {
1984 qh->qh_qtd.qtd_status = 0;
1985 }
1986
1987 td = xfer->td_transfer_first;
1988
1989 qh->qh_qtd.qtd_next = td->qtd_self;
1990 qh->qh_qtd.qtd_altnext =
1991 htohc32(temp.sc, EHCI_LINK_TERMINATE);
1992
1993 usb_pc_cpu_flush(qh->page_cache);
1994
1995 if (xfer->xroot->udev->flags.self_suspended == 0) {
1996 EHCI_APPEND_QH(qh, *qh_last);
1997 }
1998}
1999
2000static void
2001ehci_root_intr(ehci_softc_t *sc)
2002{
2003 uint16_t i;
2004 uint16_t m;
2005
722d05c3 2006 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
12bd3c8b
SW
2007
2008 /* clear any old interrupt data */
2009 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2010
2011 /* set bits */
2012 m = (sc->sc_noport + 1);
2013 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2014 m = (8 * sizeof(sc->sc_hub_idata));
2015 }
2016 for (i = 1; i < m; i++) {
2017 /* pick out CHANGE bits from the status register */
2018 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2019 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2020 DPRINTF("port %d changed\n", i);
2021 }
2022 }
2023 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2024 sizeof(sc->sc_hub_idata));
2025}
2026
2027static void
2028ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2029{
2030 uint32_t nframes = xfer->nframes;
2031 uint32_t status;
2032 uint32_t *plen = xfer->frlengths;
2033 uint16_t len = 0;
2034 ehci_sitd_t *td = xfer->td_transfer_first;
2035 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2036
2037 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2038 xfer, xfer->endpoint);
2039
2040 while (nframes--) {
2041 if (td == NULL) {
2042 panic("%s:%d: out of TD's\n",
2043 __FUNCTION__, __LINE__);
2044 }
2045 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2046 pp_last = &sc->sc_isoc_fs_p_last[0];
2047 }
2048#ifdef USB_DEBUG
2049 if (ehcidebug > 15) {
2050 DPRINTF("isoc FS-TD\n");
2051 ehci_dump_sitd(sc, td);
2052 }
2053#endif
2054 usb_pc_cpu_invalidate(td->page_cache);
2055 status = hc32toh(sc, td->sitd_status);
2056
2057 len = EHCI_SITD_GET_LEN(status);
2058
2059 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2060
2061 if (*plen >= len) {
2062 len = *plen - len;
2063 } else {
2064 len = 0;
2065 }
2066
2067 *plen = len;
2068
2069 /* remove FS-TD from schedule */
2070 EHCI_REMOVE_FS_TD(td, *pp_last);
2071
2072 pp_last++;
2073 plen++;
2074 td = td->obj_next;
2075 }
2076
2077 xfer->aframes = xfer->nframes;
2078}
2079
2080static void
2081ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2082{
2083 uint32_t nframes = xfer->nframes;
2084 uint32_t status;
2085 uint32_t *plen = xfer->frlengths;
2086 uint16_t len = 0;
2087 uint8_t td_no = 0;
2088 ehci_itd_t *td = xfer->td_transfer_first;
2089 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2090
2091 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2092 xfer, xfer->endpoint);
2093
2094 while (nframes) {
2095 if (td == NULL) {
2096 panic("%s:%d: out of TD's\n",
2097 __FUNCTION__, __LINE__);
2098 }
2099 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2100 pp_last = &sc->sc_isoc_hs_p_last[0];
2101 }
2102#ifdef USB_DEBUG
2103 if (ehcidebug > 15) {
2104 DPRINTF("isoc HS-TD\n");
2105 ehci_dump_itd(sc, td);
2106 }
2107#endif
2108
2109 usb_pc_cpu_invalidate(td->page_cache);
2110 status = hc32toh(sc, td->itd_status[td_no]);
2111
2112 len = EHCI_ITD_GET_LEN(status);
2113
2114 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2115
2116 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2117
2118 if (*plen >= len) {
2119 /*
2120 * The length is valid. NOTE: The
2121 * complete length is written back
2122 * into the status field, and not the
2123 * remainder like with other transfer
2124 * descriptor types.
2125 */
2126 } else {
2127 /* Invalid length - truncate */
2128 len = 0;
2129 }
2130
2131 *plen = len;
2132 plen++;
2133 nframes--;
2134 }
2135
2136 td_no++;
2137
2138 if ((td_no == 8) || (nframes == 0)) {
2139 /* remove HS-TD from schedule */
2140 EHCI_REMOVE_HS_TD(td, *pp_last);
2141 pp_last++;
2142
2143 td_no = 0;
2144 td = td->obj_next;
2145 }
2146 }
2147 xfer->aframes = xfer->nframes;
2148}
2149
2150/* NOTE: "done" can be run two times in a row,
2151 * from close and from interrupt
2152 */
2153static void
2154ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2155{
2156 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2157 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2158
722d05c3 2159 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
12bd3c8b
SW
2160
2161 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2162 xfer, xfer->endpoint, error);
2163
2164 if ((methods == &ehci_device_bulk_methods) ||
2165 (methods == &ehci_device_ctrl_methods)) {
2166#ifdef USB_DEBUG
2167 if (ehcidebug > 8) {
2168 DPRINTF("nexttog=%d; data after transfer:\n",
2169 xfer->endpoint->toggle_next);
2170 ehci_dump_sqtds(sc,
2171 xfer->td_transfer_first);
2172 }
2173#endif
2174
2175 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2176 sc->sc_async_p_last);
2177 }
2178 if (methods == &ehci_device_intr_methods) {
2179 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2180 sc->sc_intr_p_last[xfer->qh_pos]);
2181 }
2182 /*
2183 * Only finish isochronous transfers once which will update
2184 * "xfer->frlengths".
2185 */
2186 if (xfer->td_transfer_first &&
2187 xfer->td_transfer_last) {
2188 if (methods == &ehci_device_isoc_fs_methods) {
2189 ehci_isoc_fs_done(sc, xfer);
2190 }
2191 if (methods == &ehci_device_isoc_hs_methods) {
2192 ehci_isoc_hs_done(sc, xfer);
2193 }
2194 xfer->td_transfer_first = NULL;
2195 xfer->td_transfer_last = NULL;
2196 }
2197 /* dequeue transfer and start next transfer */
2198 usbd_transfer_done(xfer, error);
2199}
2200
2201/*------------------------------------------------------------------------*
2202 * ehci bulk support
2203 *------------------------------------------------------------------------*/
2204static void
2205ehci_device_bulk_open(struct usb_xfer *xfer)
2206{
2207 return;
2208}
2209
2210static void
2211ehci_device_bulk_close(struct usb_xfer *xfer)
2212{
2213 ehci_device_done(xfer, USB_ERR_CANCELLED);
2214}
2215
2216static void
2217ehci_device_bulk_enter(struct usb_xfer *xfer)
2218{
2219 return;
2220}
2221
2222static void
2223ehci_device_bulk_start(struct usb_xfer *xfer)
2224{
2225 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2226 uint32_t temp;
2227
2228 /* setup TD's and QH */
2229 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2230
2231 /* put transfer on interrupt queue */
2232 ehci_transfer_intr_enqueue(xfer);
2233
2234 /*
2235 * XXX Certain nVidia chipsets choke when using the IAAD
2236 * feature too frequently.
2237 */
2238 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2239 return;
2240
2241 /* XXX Performance quirk: Some Host Controllers have a too low
2242 * interrupt rate. Issue an IAAD to stimulate the Host
2243 * Controller after queueing the BULK transfer.
2244 */
2245 temp = EOREAD4(sc, EHCI_USBCMD);
2246 if (!(temp & EHCI_CMD_IAAD))
2247 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2248}
2249
2250struct usb_pipe_methods ehci_device_bulk_methods =
2251{
2252 .open = ehci_device_bulk_open,
2253 .close = ehci_device_bulk_close,
2254 .enter = ehci_device_bulk_enter,
2255 .start = ehci_device_bulk_start,
2256};
2257
2258/*------------------------------------------------------------------------*
2259 * ehci control support
2260 *------------------------------------------------------------------------*/
2261static void
2262ehci_device_ctrl_open(struct usb_xfer *xfer)
2263{
2264 return;
2265}
2266
2267static void
2268ehci_device_ctrl_close(struct usb_xfer *xfer)
2269{
2270 ehci_device_done(xfer, USB_ERR_CANCELLED);
2271}
2272
2273static void
2274ehci_device_ctrl_enter(struct usb_xfer *xfer)
2275{
2276 return;
2277}
2278
2279static void
2280ehci_device_ctrl_start(struct usb_xfer *xfer)
2281{
2282 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2283
2284 /* setup TD's and QH */
2285 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2286
2287 /* put transfer on interrupt queue */
2288 ehci_transfer_intr_enqueue(xfer);
2289}
2290
2291struct usb_pipe_methods ehci_device_ctrl_methods =
2292{
2293 .open = ehci_device_ctrl_open,
2294 .close = ehci_device_ctrl_close,
2295 .enter = ehci_device_ctrl_enter,
2296 .start = ehci_device_ctrl_start,
2297};
2298
2299/*------------------------------------------------------------------------*
2300 * ehci interrupt support
2301 *------------------------------------------------------------------------*/
2302static void
2303ehci_device_intr_open(struct usb_xfer *xfer)
2304{
2305 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2306 uint16_t best;
2307 uint16_t bit;
2308 uint16_t x;
2309
2310 usb_hs_bandwidth_alloc(xfer);
2311
2312 /*
2313 * Find the best QH position corresponding to the given interval:
2314 */
2315
2316 best = 0;
2317 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2318 while (bit) {
2319 if (xfer->interval >= bit) {
2320 x = bit;
2321 best = bit;
2322 while (x & bit) {
2323 if (sc->sc_intr_stat[x] <
2324 sc->sc_intr_stat[best]) {
2325 best = x;
2326 }
2327 x++;
2328 }
2329 break;
2330 }
2331 bit >>= 1;
2332 }
2333
2334 sc->sc_intr_stat[best]++;
2335 xfer->qh_pos = best;
2336
2337 DPRINTFN(3, "best=%d interval=%d\n",
2338 best, xfer->interval);
2339}
2340
2341static void
2342ehci_device_intr_close(struct usb_xfer *xfer)
2343{
2344 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2345
2346 sc->sc_intr_stat[xfer->qh_pos]--;
2347
2348 ehci_device_done(xfer, USB_ERR_CANCELLED);
2349
2350 /* bandwidth must be freed after device done */
2351 usb_hs_bandwidth_free(xfer);
2352}
2353
2354static void
2355ehci_device_intr_enter(struct usb_xfer *xfer)
2356{
2357 return;
2358}
2359
2360static void
2361ehci_device_intr_start(struct usb_xfer *xfer)
2362{
2363 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2364
2365 /* setup TD's and QH */
2366 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2367
2368 /* put transfer on interrupt queue */
2369 ehci_transfer_intr_enqueue(xfer);
2370}
2371
2372struct usb_pipe_methods ehci_device_intr_methods =
2373{
2374 .open = ehci_device_intr_open,
2375 .close = ehci_device_intr_close,
2376 .enter = ehci_device_intr_enter,
2377 .start = ehci_device_intr_start,
2378};
2379
2380/*------------------------------------------------------------------------*
2381 * ehci full speed isochronous support
2382 *------------------------------------------------------------------------*/
2383static void
2384ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2385{
2386 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2387 ehci_sitd_t *td;
2388 uint32_t sitd_portaddr;
2389 uint8_t ds;
2390
2391 sitd_portaddr =
2392 EHCI_SITD_SET_ADDR(xfer->address) |
2393 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2394 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2395 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2396
2397 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2398 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2399 }
2400 sitd_portaddr = htohc32(sc, sitd_portaddr);
2401
2402 /* initialize all TD's */
2403
2404 for (ds = 0; ds != 2; ds++) {
2405
2406 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2407
2408 td->sitd_portaddr = sitd_portaddr;
2409
2410 /*
2411 * TODO: make some kind of automatic
2412 * SMASK/CMASK selection based on micro-frame
2413 * usage
2414 *
2415 * micro-frame usage (8 microframes per 1ms)
2416 */
2417 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2418
2419 usb_pc_cpu_flush(td->page_cache);
2420 }
2421 }
2422}
2423
2424static void
2425ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2426{
2427 ehci_device_done(xfer, USB_ERR_CANCELLED);
2428}
2429
2430static void
2431ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2432{
2433 struct usb_page_search buf_res;
2434 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2435 struct usb_fs_isoc_schedule *fss_start;
2436 struct usb_fs_isoc_schedule *fss_end;
2437 struct usb_fs_isoc_schedule *fss;
2438 ehci_sitd_t *td;
2439 ehci_sitd_t *td_last = NULL;
2440 ehci_sitd_t **pp_last;
2441 uint32_t *plen;
2442 uint32_t buf_offset;
2443 uint32_t nframes;
2444 uint32_t temp;
2445 uint32_t sitd_mask;
2446 uint16_t tlen;
2447 uint8_t sa;
2448 uint8_t sb;
2449 uint8_t error;
2450
2451#ifdef USB_DEBUG
2452 uint8_t once = 1;
2453
2454#endif
2455
2456 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2457 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2458
2459 /* get the current frame index */
2460
2461 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2462
2463 /*
2464 * check if the frame index is within the window where the frames
2465 * will be inserted
2466 */
2467 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2468 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2469
2470 if ((xfer->endpoint->is_synced == 0) ||
2471 (buf_offset < xfer->nframes)) {
2472 /*
2473 * If there is data underflow or the pipe queue is empty we
2474 * schedule the transfer a few frames ahead of the current
2475 * frame position. Else two isochronous transfers might
2476 * overlap.
2477 */
2478 xfer->endpoint->isoc_next = (nframes + 3) &
2479 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2480 xfer->endpoint->is_synced = 1;
2481 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2482 }
2483 /*
2484 * compute how many milliseconds the insertion is ahead of the
2485 * current frame position:
2486 */
2487 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2488 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2489
2490 /*
2491 * pre-compute when the isochronous transfer will be finished:
2492 */
2493 xfer->isoc_time_complete =
2494 usbd_fs_isoc_schedule_isoc_time_expand
2495 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2496 xfer->nframes;
2497
2498 /* get the real number of frames */
2499
2500 nframes = xfer->nframes;
2501
2502 buf_offset = 0;
2503
2504 plen = xfer->frlengths;
2505
2506 /* toggle the DMA set we are using */
2507 xfer->flags_int.curr_dma_set ^= 1;
2508
2509 /* get next DMA set */
2510 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2511 xfer->td_transfer_first = td;
2512
2513 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2514
2515 /* store starting position */
2516
2517 xfer->qh_pos = xfer->endpoint->isoc_next;
2518
2519 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2520
2521 while (nframes--) {
2522 if (td == NULL) {
2523 panic("%s:%d: out of TD's\n",
2524 __FUNCTION__, __LINE__);
2525 }
2526 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2527 pp_last = &sc->sc_isoc_fs_p_last[0];
2528 }
2529 if (fss >= fss_end) {
2530 fss = fss_start;
2531 }
2532 /* reuse sitd_portaddr and sitd_back from last transfer */
2533
2534 if (*plen > xfer->max_frame_size) {
2535#ifdef USB_DEBUG
2536 if (once) {
2537 once = 0;
722d05c3 2538 kprintf("%s: frame length(%d) exceeds %d "
12bd3c8b
SW
2539 "bytes (frame truncated)\n",
2540 __FUNCTION__, *plen,
2541 xfer->max_frame_size);
2542 }
2543#endif
2544 *plen = xfer->max_frame_size;
2545 }
2546 /*
2547 * We currently don't care if the ISOCHRONOUS schedule is
2548 * full!
2549 */
2550 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2551 if (error) {
2552 /*
2553 * The FULL speed schedule is FULL! Set length
2554 * to zero.
2555 */
2556 *plen = 0;
2557 }
2558 if (*plen) {
2559 /*
2560 * only call "usbd_get_page()" when we have a
2561 * non-zero length
2562 */
2563 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2564 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2565 buf_offset += *plen;
2566 /*
2567 * NOTE: We need to subtract one from the offset so
2568 * that we are on a valid page!
2569 */
2570 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2571 &buf_res);
2572 temp = buf_res.physaddr & ~0xFFF;
2573 } else {
2574 td->sitd_bp[0] = 0;
2575 temp = 0;
2576 }
2577
2578 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2579 tlen = *plen;
2580 if (tlen <= 188) {
2581 temp |= 1; /* T-count = 1, TP = ALL */
2582 tlen = 1;
2583 } else {
2584 tlen += 187;
2585 tlen /= 188;
2586 temp |= tlen; /* T-count = [1..6] */
2587 temp |= 8; /* TP = Begin */
2588 }
2589
2590 tlen += sa;
2591
2592 if (tlen >= 8) {
2593 sb = 0;
2594 } else {
2595 sb = (1 << tlen);
2596 }
2597
2598 sa = (1 << sa);
2599 sa = (sb - sa) & 0x3F;
2600 sb = 0;
2601 } else {
2602 sb = (-(4 << sa)) & 0xFE;
2603 sa = (1 << sa) & 0x3F;
2604 }
2605
2606 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2607 EHCI_SITD_SET_CMASK(sb));
2608
2609 td->sitd_bp[1] = htohc32(sc, temp);
2610
2611 td->sitd_mask = htohc32(sc, sitd_mask);
2612
2613 if (nframes == 0) {
2614 td->sitd_status = htohc32(sc,
2615 EHCI_SITD_IOC |
2616 EHCI_SITD_ACTIVE |
2617 EHCI_SITD_SET_LEN(*plen));
2618 } else {
2619 td->sitd_status = htohc32(sc,
2620 EHCI_SITD_ACTIVE |
2621 EHCI_SITD_SET_LEN(*plen));
2622 }
2623 usb_pc_cpu_flush(td->page_cache);
2624
2625#ifdef USB_DEBUG
2626 if (ehcidebug > 15) {
2627 DPRINTF("FS-TD %d\n", nframes);
2628 ehci_dump_sitd(sc, td);
2629 }
2630#endif
2631 /* insert TD into schedule */
2632 EHCI_APPEND_FS_TD(td, *pp_last);
2633 pp_last++;
2634
2635 plen++;
2636 fss++;
2637 td_last = td;
2638 td = td->obj_next;
2639 }
2640
2641 xfer->td_transfer_last = td_last;
2642
2643 /* update isoc_next */
2644 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2645 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2646}
2647
2648static void
2649ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2650{
2651 /* put transfer on interrupt queue */
2652 ehci_transfer_intr_enqueue(xfer);
2653}
2654
2655struct usb_pipe_methods ehci_device_isoc_fs_methods =
2656{
2657 .open = ehci_device_isoc_fs_open,
2658 .close = ehci_device_isoc_fs_close,
2659 .enter = ehci_device_isoc_fs_enter,
2660 .start = ehci_device_isoc_fs_start,
2661};
2662
2663/*------------------------------------------------------------------------*
2664 * ehci high speed isochronous support
2665 *------------------------------------------------------------------------*/
2666static void
2667ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2668{
2669 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2670 ehci_itd_t *td;
2671 uint32_t temp;
2672 uint8_t ds;
2673
2674 usb_hs_bandwidth_alloc(xfer);
2675
2676 /* initialize all TD's */
2677
2678 for (ds = 0; ds != 2; ds++) {
2679
2680 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2681
2682 /* set TD inactive */
2683 td->itd_status[0] = 0;
2684 td->itd_status[1] = 0;
2685 td->itd_status[2] = 0;
2686 td->itd_status[3] = 0;
2687 td->itd_status[4] = 0;
2688 td->itd_status[5] = 0;
2689 td->itd_status[6] = 0;
2690 td->itd_status[7] = 0;
2691
2692 /* set endpoint and address */
2693 td->itd_bp[0] = htohc32(sc,
2694 EHCI_ITD_SET_ADDR(xfer->address) |
2695 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2696
2697 temp =
2698 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2699
2700 /* set direction */
2701 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2702 temp |= EHCI_ITD_SET_DIR_IN;
2703 }
2704 /* set maximum packet size */
2705 td->itd_bp[1] = htohc32(sc, temp);
2706
2707 /* set transfer multiplier */
2708 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2709
2710 usb_pc_cpu_flush(td->page_cache);
2711 }
2712 }
2713}
2714
2715static void
2716ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2717{
2718 ehci_device_done(xfer, USB_ERR_CANCELLED);
2719
2720 /* bandwidth must be freed after device done */
2721 usb_hs_bandwidth_free(xfer);
2722}
2723
2724static void
2725ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2726{
2727 struct usb_page_search buf_res;
2728 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2729 ehci_itd_t *td;
2730 ehci_itd_t *td_last = NULL;
2731 ehci_itd_t **pp_last;
2732 bus_size_t page_addr;
2733 uint32_t *plen;
2734 uint32_t status;
2735 uint32_t buf_offset;
2736 uint32_t nframes;
2737 uint32_t itd_offset[8 + 1];
2738 uint8_t x;
2739 uint8_t td_no;
2740 uint8_t page_no;
2741 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2742
2743#ifdef USB_DEBUG
2744 uint8_t once = 1;
2745
2746#endif
2747
2748 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2749 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2750
2751 /* get the current frame index */
2752
2753 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2754
2755 /*
2756 * check if the frame index is within the window where the frames
2757 * will be inserted
2758 */
2759 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2760 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2761
2762 if ((xfer->endpoint->is_synced == 0) ||
2763 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2764 /*
2765 * If there is data underflow or the pipe queue is empty we
2766 * schedule the transfer a few frames ahead of the current
2767 * frame position. Else two isochronous transfers might
2768 * overlap.
2769 */
2770 xfer->endpoint->isoc_next = (nframes + 3) &
2771 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2772 xfer->endpoint->is_synced = 1;
2773 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2774 }
2775 /*
2776 * compute how many milliseconds the insertion is ahead of the
2777 * current frame position:
2778 */
2779 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2780 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2781
2782 /*
2783 * pre-compute when the isochronous transfer will be finished:
2784 */
2785 xfer->isoc_time_complete =
2786 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2787 (((xfer->nframes << shift) + 7) / 8);
2788
2789 /* get the real number of frames */
2790
2791 nframes = xfer->nframes;
2792
2793 buf_offset = 0;
2794 td_no = 0;
2795
2796 plen = xfer->frlengths;
2797
2798 /* toggle the DMA set we are using */
2799 xfer->flags_int.curr_dma_set ^= 1;
2800
2801 /* get next DMA set */
2802 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2803 xfer->td_transfer_first = td;
2804
2805 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2806
2807 /* store starting position */
2808
2809 xfer->qh_pos = xfer->endpoint->isoc_next;
2810
2811 while (nframes) {
2812 if (td == NULL) {
2813 panic("%s:%d: out of TD's\n",
2814 __FUNCTION__, __LINE__);
2815 }
2816 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2817 pp_last = &sc->sc_isoc_hs_p_last[0];
2818 }
2819 /* range check */
2820 if (*plen > xfer->max_frame_size) {
2821#ifdef USB_DEBUG
2822 if (once) {
2823 once = 0;
722d05c3 2824 kprintf("%s: frame length(%d) exceeds %d bytes "
12bd3c8b
SW
2825 "(frame truncated)\n",
2826 __FUNCTION__, *plen, xfer->max_frame_size);
2827 }
2828#endif
2829 *plen = xfer->max_frame_size;
2830 }
2831
2832 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2833 status = (EHCI_ITD_SET_LEN(*plen) |
2834 EHCI_ITD_ACTIVE |
2835 EHCI_ITD_SET_PG(0));
2836 td->itd_status[td_no] = htohc32(sc, status);
2837 itd_offset[td_no] = buf_offset;
2838 buf_offset += *plen;
2839 plen++;
2840 nframes --;
2841 } else {
2842 td->itd_status[td_no] = 0; /* not active */
2843 itd_offset[td_no] = buf_offset;
2844 }
2845
2846 td_no++;
2847
2848 if ((td_no == 8) || (nframes == 0)) {
2849
2850 /* the rest of the transfers are not active, if any */
2851 for (x = td_no; x != 8; x++) {
2852 td->itd_status[x] = 0; /* not active */
2853 }
2854
2855 /* check if there is any data to be transferred */
2856 if (itd_offset[0] != buf_offset) {
2857 page_no = 0;
2858 itd_offset[td_no] = buf_offset;
2859
2860 /* get first page offset */
2861 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2862 /* get page address */
2863 page_addr = buf_res.physaddr & ~0xFFF;
2864 /* update page address */
2865 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2866 td->itd_bp[0] |= htohc32(sc, page_addr);
2867
2868 for (x = 0; x != td_no; x++) {
2869 /* set page number and page offset */
2870 status = (EHCI_ITD_SET_PG(page_no) |
2871 (buf_res.physaddr & 0xFFF));
2872 td->itd_status[x] |= htohc32(sc, status);
2873
2874 /* get next page offset */
2875 if (itd_offset[x + 1] == buf_offset) {
2876 /*
2877 * We subtract one so that
2878 * we don't go off the last
2879 * page!
2880 */
2881 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2882 } else {
2883 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2884 }
2885
2886 /* check if we need a new page */
2887 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2888 /* new page needed */
2889 page_addr = buf_res.physaddr & ~0xFFF;
2890 if (page_no == 6) {
2891 panic("%s: too many pages\n", __FUNCTION__);
2892 }
2893 page_no++;
2894 /* update page address */
2895 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2896 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2897 }
2898 }
2899 }
2900 /* set IOC bit if we are complete */
2901 if (nframes == 0) {
2902 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2903 }
2904 usb_pc_cpu_flush(td->page_cache);
2905#ifdef USB_DEBUG
2906 if (ehcidebug > 15) {
2907 DPRINTF("HS-TD %d\n", nframes);
2908 ehci_dump_itd(sc, td);
2909 }
2910#endif
2911 /* insert TD into schedule */
2912 EHCI_APPEND_HS_TD(td, *pp_last);
2913 pp_last++;
2914
2915 td_no = 0;
2916 td_last = td;
2917 td = td->obj_next;
2918 }
2919 }
2920
2921 xfer->td_transfer_last = td_last;
2922
2923 /* update isoc_next */
2924 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2925 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2926}
2927
2928static void
2929ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2930{
2931 /* put transfer on interrupt queue */
2932 ehci_transfer_intr_enqueue(xfer);
2933}
2934
2935struct usb_pipe_methods ehci_device_isoc_hs_methods =
2936{
2937 .open = ehci_device_isoc_hs_open,
2938 .close = ehci_device_isoc_hs_close,
2939 .enter = ehci_device_isoc_hs_enter,
2940 .start = ehci_device_isoc_hs_start,
2941};
2942
2943/*------------------------------------------------------------------------*
2944 * ehci root control support
2945 *------------------------------------------------------------------------*
2946 * Simulate a hardware hub by handling all the necessary requests.
2947 *------------------------------------------------------------------------*/
2948
2949static const
2950struct usb_device_descriptor ehci_devd =
2951{
2952 sizeof(struct usb_device_descriptor),
2953 UDESC_DEVICE, /* type */
2954 {0x00, 0x02}, /* USB version */
2955 UDCLASS_HUB, /* class */
2956 UDSUBCLASS_HUB, /* subclass */
2957 UDPROTO_HSHUBSTT, /* protocol */
2958 64, /* max packet */
2959 {0}, {0}, {0x00, 0x01}, /* device id */
2960 1, 2, 0, /* string indicies */
2961 1 /* # of configurations */
2962};
2963
2964static const
2965struct usb_device_qualifier ehci_odevd =
2966{
2967 sizeof(struct usb_device_qualifier),
2968 UDESC_DEVICE_QUALIFIER, /* type */
2969 {0x00, 0x02}, /* USB version */
2970 UDCLASS_HUB, /* class */
2971 UDSUBCLASS_HUB, /* subclass */
2972 UDPROTO_FSHUB, /* protocol */
2973 0, /* max packet */
2974 0, /* # of configurations */
2975 0
2976};
2977
2978static const struct ehci_config_desc ehci_confd = {
2979 .confd = {
2980 .bLength = sizeof(struct usb_config_descriptor),
2981 .bDescriptorType = UDESC_CONFIG,
2982 .wTotalLength[0] = sizeof(ehci_confd),
2983 .bNumInterface = 1,
2984 .bConfigurationValue = 1,
2985 .iConfiguration = 0,
2986 .bmAttributes = UC_SELF_POWERED,
2987 .bMaxPower = 0 /* max power */
2988 },
2989 .ifcd = {
2990 .bLength = sizeof(struct usb_interface_descriptor),
2991 .bDescriptorType = UDESC_INTERFACE,
2992 .bNumEndpoints = 1,
2993 .bInterfaceClass = UICLASS_HUB,
2994 .bInterfaceSubClass = UISUBCLASS_HUB,
2995 .bInterfaceProtocol = 0,
2996 },
2997 .endpd = {
2998 .bLength = sizeof(struct usb_endpoint_descriptor),
2999 .bDescriptorType = UDESC_ENDPOINT,
3000 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3001 .bmAttributes = UE_INTERRUPT,
3002 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3003 .bInterval = 255,
3004 },
3005};
3006
3007static const
3008struct usb_hub_descriptor ehci_hubd =
3009{
3010 0, /* dynamic length */
3011 UDESC_HUB,
3012 0,
3013 {0, 0},
3014 0,
3015 0,
3016 {0},
3017};
3018
3019static void
3020ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3021{
3022 uint32_t port;
3023 uint32_t v;
3024
3025 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3026
3027 port = EHCI_PORTSC(index);
3028 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3029 EOWRITE4(sc, port, v | EHCI_PS_PO);
3030}
3031
3032static usb_error_t
3033ehci_roothub_exec(struct usb_device *udev,
3034 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3035{
3036 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3037 const char *str_ptr;
3038 const void *ptr;
3039 uint32_t port;
3040 uint32_t v;
3041 uint16_t len;
3042 uint16_t i;
3043 uint16_t value;
3044 uint16_t index;
3045 usb_error_t err;
3046
722d05c3 3047 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
12bd3c8b
SW
3048
3049 /* buffer reset */
3050 ptr = (const void *)&sc->sc_hub_desc;
3051 len = 0;
3052 err = 0;
3053
3054 value = UGETW(req->wValue);
3055 index = UGETW(req->wIndex);
3056
3057 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3058 "wValue=0x%04x wIndex=0x%04x\n",
3059 req->bmRequestType, req->bRequest,
3060 UGETW(req->wLength), value, index);
3061
3062#define C(x,y) ((x) | ((y) << 8))
3063 switch (C(req->bRequest, req->bmRequestType)) {
3064 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3065 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3066 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3067 /*
3068 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3069 * for the integrated root hub.
3070 */
3071 break;
3072 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3073 len = 1;
3074 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3075 break;
3076 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3077 switch (value >> 8) {
3078 case UDESC_DEVICE:
3079 if ((value & 0xff) != 0) {
3080 err = USB_ERR_IOERROR;
3081 goto done;
3082 }
3083 len = sizeof(ehci_devd);
3084 ptr = (const void *)&ehci_devd;
3085 break;
3086 /*
3087 * We can't really operate at another speed,
3088 * but the specification says we need this
3089 * descriptor:
3090 */
3091 case UDESC_DEVICE_QUALIFIER:
3092 if ((value & 0xff) != 0) {
3093 err = USB_ERR_IOERROR;
3094 goto done;
3095 }
3096 len = sizeof(ehci_odevd);
3097 ptr = (const void *)&ehci_odevd;
3098 break;
3099
3100 case UDESC_CONFIG:
3101 if ((value & 0xff) != 0) {
3102 err = USB_ERR_IOERROR;
3103 goto done;
3104 }
3105 len = sizeof(ehci_confd);
3106 ptr = (const void *)&ehci_confd;
3107 break;
3108
3109 case UDESC_STRING:
3110 switch (value & 0xff) {
3111 case 0: /* Language table */
3112 str_ptr = "\001";
3113 break;
3114
3115 case 1: /* Vendor */
3116 str_ptr = sc->sc_vendor;
3117 break;
3118
3119 case 2: /* Product */
3120 str_ptr = "EHCI root HUB";
3121 break;
3122
3123 default:
3124 str_ptr = "";
3125 break;
3126 }
3127
3128 len = usb_make_str_desc(
3129 sc->sc_hub_desc.temp,
3130 sizeof(sc->sc_hub_desc.temp),
3131 str_ptr);
3132 break;
3133 default:
3134 err = USB_ERR_IOERROR;
3135 goto done;
3136 }
3137 break;
3138 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3139 len = 1;
3140 sc->sc_hub_desc.temp[0] = 0;
3141 break;
3142 case C(UR_GET_STATUS, UT_READ_DEVICE):
3143 len = 2;
3144 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3145 break;
3146 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3147 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3148 len = 2;
3149 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3150 break;
3151 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3152 if (value >= EHCI_MAX_DEVICES) {
3153 err = USB_ERR_IOERROR;
3154 goto done;
3155 }
3156 sc->sc_addr = value;
3157 break;
3158 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3159 if ((value != 0) && (value != 1)) {
3160 err = USB_ERR_IOERROR;
3161 goto done;
3162 }
3163 sc->sc_conf = value;
3164 break;
3165 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3166 break;
3167 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3168 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3169 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3170 err = USB_ERR_IOERROR;
3171 goto done;
3172 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3173 break;
3174 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3175 break;
3176 /* Hub requests */
3177 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3178 break;
3179 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3180 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3181
3182 if ((index < 1) ||
3183 (index > sc->sc_noport)) {
3184 err = USB_ERR_IOERROR;
3185 goto done;
3186 }
3187 port = EHCI_PORTSC(index);
3188 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3189 switch (value) {
3190 case UHF_PORT_ENABLE:
3191 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3192 break;
3193 case UHF_PORT_SUSPEND:
3194 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3195
3196 /*
3197 * waking up a High Speed device is rather
3198 * complicated if
3199 */
3200 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3201 }
3202 /* wait 20ms for resume sequence to complete */
722d05c3 3203 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50);
12bd3c8b
SW
3204
3205 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3206 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3207
3208 /* 4ms settle time */
722d05c3 3209 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250);
12bd3c8b
SW
3210 break;
3211 case UHF_PORT_POWER:
3212 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3213 break;
3214 case UHF_PORT_TEST:
3215 DPRINTFN(3, "clear port test "
3216 "%d\n", index);
3217 break;
3218 case UHF_PORT_INDICATOR:
3219 DPRINTFN(3, "clear port ind "
3220 "%d\n", index);
3221 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3222 break;
3223 case UHF_C_PORT_CONNECTION:
3224 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3225 break;
3226 case UHF_C_PORT_ENABLE:
3227 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3228 break;
3229 case UHF_C_PORT_SUSPEND:
3230 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3231 break;
3232 case UHF_C_PORT_OVER_CURRENT:
3233 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3234 break;
3235 case UHF_C_PORT_RESET:
3236 sc->sc_isreset = 0;
3237 break;
3238 default:
3239 err = USB_ERR_IOERROR;
3240 goto done;
3241 }
3242 break;
3243 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3244 if ((value & 0xff) != 0) {
3245 err = USB_ERR_IOERROR;
3246 goto done;
3247 }
3248 v = EREAD4(sc, EHCI_HCSPARAMS);
3249
3250 sc->sc_hub_desc.hubd = ehci_hubd;
3251 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3252
3253 if (EHCI_HCS_PPC(v))
3254 i = UHD_PWR_INDIVIDUAL;
3255 else
3256 i = UHD_PWR_NO_SWITCH;
3257
3258 if (EHCI_HCS_P_INDICATOR(v))
3259 i |= UHD_PORT_IND;
3260
3261 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3262 /* XXX can't find out? */
3263 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3264 /* XXX don't know if ports are removable or not */
3265 sc->sc_hub_desc.hubd.bDescLength =
3266 8 + ((sc->sc_noport + 7) / 8);
3267 len = sc->sc_hub_desc.hubd.bDescLength;
3268 break;
3269 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3270 len = 16;
3271 memset(sc->sc_hub_desc.temp, 0, 16);
3272 break;
3273 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3274 DPRINTFN(9, "get port status i=%d\n",
3275 index);
3276 if ((index < 1) ||
3277 (index > sc->sc_noport)) {
3278 err = USB_ERR_IOERROR;
3279 goto done;
3280 }
3281 v = EOREAD4(sc, EHCI_PORTSC(index));
3282 DPRINTFN(9, "port status=0x%04x\n", v);
3283 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3284 if ((v & 0xc000000) == 0x8000000)
3285 i = UPS_HIGH_SPEED;
3286 else if ((v & 0xc000000) == 0x4000000)
3287 i = UPS_LOW_SPEED;
3288 else
3289 i = 0;
3290 } else {
3291 i = UPS_HIGH_SPEED;
3292 }
3293 if (v & EHCI_PS_CS)
3294 i |= UPS_CURRENT_CONNECT_STATUS;
3295 if (v & EHCI_PS_PE)
3296 i |= UPS_PORT_ENABLED;
3297 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3298 i |= UPS_SUSPEND;
3299 if (v & EHCI_PS_OCA)
3300 i |= UPS_OVERCURRENT_INDICATOR;
3301 if (v & EHCI_PS_PR)
3302 i |= UPS_RESET;
3303 if (v & EHCI_PS_PP)
3304 i |= UPS_PORT_POWER;
3305 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3306 i = 0;
3307 if (v & EHCI_PS_CSC)
3308 i |= UPS_C_CONNECT_STATUS;
3309 if (v & EHCI_PS_PEC)
3310 i |= UPS_C_PORT_ENABLED;
3311 if (v & EHCI_PS_OCC)
3312 i |= UPS_C_OVERCURRENT_INDICATOR;
3313 if (v & EHCI_PS_FPR)
3314 i |= UPS_C_SUSPEND;
3315 if (sc->sc_isreset)
3316 i |= UPS_C_PORT_RESET;
3317 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3318 len = sizeof(sc->sc_hub_desc.ps);
3319 break;
3320 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3321 err = USB_ERR_IOERROR;
3322 goto done;
3323 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3324 break;
3325 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3326 if ((index < 1) ||
3327 (index > sc->sc_noport)) {
3328 err = USB_ERR_IOERROR;
3329 goto done;
3330 }
3331 port = EHCI_PORTSC(index);
3332 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3333 switch (value) {
3334 case UHF_PORT_ENABLE:
3335 EOWRITE4(sc, port, v | EHCI_PS_PE);
3336 break;
3337 case UHF_PORT_SUSPEND:
3338 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3339 break;
3340 case UHF_PORT_RESET:
3341 DPRINTFN(6, "reset port %d\n", index);
3342#ifdef USB_DEBUG
3343 if (ehcinohighspeed) {
3344 /*
3345 * Connect USB device to companion
3346 * controller.
3347 */
3348 ehci_disown(sc, index, 1);
3349 break;
3350 }
3351#endif
3352 if (EHCI_PS_IS_LOWSPEED(v) &&
3353 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3354 /* Low speed device, give up ownership. */
3355 ehci_disown(sc, index, 1);
3356 break;
3357 }
3358 /* Start reset sequence. */
3359 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3360 EOWRITE4(sc, port, v | EHCI_PS_PR);
3361
3362 /* Wait for reset to complete. */
722d05c3 3363 usb_pause_mtx(&sc->sc_bus.bus_lock,
12bd3c8b
SW
3364 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3365
3366 /* Terminate reset sequence. */
3367 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3368 EOWRITE4(sc, port, v);
3369
3370 /* Wait for HC to complete reset. */
722d05c3 3371 usb_pause_mtx(&sc->sc_bus.bus_lock,
12bd3c8b
SW
3372 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3373
3374 v = EOREAD4(sc, port);
3375 DPRINTF("ehci after reset, status=0x%08x\n", v);
3376 if (v & EHCI_PS_PR) {
3377 device_printf(sc->sc_bus.bdev,
3378 "port reset timeout\n");
3379 err = USB_ERR_TIMEOUT;
3380 goto done;
3381 }
3382 if (!(v & EHCI_PS_PE) &&
3383 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3384 /* Not a high speed device, give up ownership.*/
3385 ehci_disown(sc, index, 0);
3386 break;
3387 }
3388 sc->sc_isreset = 1;
3389 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3390 index, v);
3391 break;
3392
3393 case UHF_PORT_POWER:
3394 DPRINTFN(3, "set port power %d\n", index);
3395 EOWRITE4(sc, port, v | EHCI_PS_PP);
3396 break;
3397
3398 case UHF_PORT_TEST:
3399 DPRINTFN(3, "set port test %d\n", index);
3400 break;
3401
3402 case UHF_PORT_INDICATOR:
3403 DPRINTFN(3, "set port ind %d\n", index);
3404 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3405 break;
3406
3407 default:
3408 err = USB_ERR_IOERROR;
3409 goto done;
3410 }
3411 break;
3412 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3413 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3414 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3415 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3416 break;
3417 default:
3418 err = USB_ERR_IOERROR;
3419 goto done;
3420 }
3421done:
3422 *plength = len;
3423 *pptr = ptr;
3424 return (err);
3425}
3426
3427static void
3428ehci_xfer_setup(struct usb_setup_params *parm)
3429{
3430 struct usb_page_search page_info;
3431 struct usb_page_cache *pc;
3432 ehci_softc_t *sc;
3433 struct usb_xfer *xfer;
3434 void *last_obj;
3435 uint32_t nqtd;
3436 uint32_t nqh;
3437 uint32_t nsitd;
3438 uint32_t nitd;
3439 uint32_t n;
3440
3441 sc = EHCI_BUS2SC(parm->udev->bus);
3442 xfer = parm->curr_xfer;
3443
3444 nqtd = 0;
3445 nqh = 0;
3446 nsitd = 0;
3447 nitd = 0;
3448
3449 /*
3450 * compute maximum number of some structures
3451 */
3452 if (parm->methods == &ehci_device_ctrl_methods) {
3453
3454 /*
3455 * The proof for the "nqtd" formula is illustrated like
3456 * this:
3457 *
3458 * +------------------------------------+
3459 * | |
3460 * | |remainder -> |
3461 * | +-----+---+ |
3462 * | | xxx | x | frm 0 |
3463 * | +-----+---++ |
3464 * | | xxx | xx | frm 1 |
3465 * | +-----+----+ |
3466 * | ... |
3467 * +------------------------------------+
3468 *
3469 * "xxx" means a completely full USB transfer descriptor
3470 *
3471 * "x" and "xx" means a short USB packet
3472 *
3473 * For the remainder of an USB transfer modulo
3474 * "max_data_length" we need two USB transfer descriptors.
3475 * One to transfer the remaining data and one to finalise
3476 * with a zero length packet in case the "force_short_xfer"
3477 * flag is set. We only need two USB transfer descriptors in
3478 * the case where the transfer length of the first one is a
3479 * factor of "max_frame_size". The rest of the needed USB
3480 * transfer descriptors is given by the buffer size divided
3481 * by the maximum data payload.
3482 */
3483 parm->hc_max_packet_size = 0x400;
3484 parm->hc_max_packet_count = 1;
3485 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3486 xfer->flags_int.bdma_enable = 1;
3487
3488 usbd_transfer_setup_sub(parm);
3489
3490 nqh = 1;
3491 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3492 + (xfer->max_data_length / xfer->max_hc_frame_size));
3493
3494 } else if (parm->methods == &ehci_device_bulk_methods) {
3495
3496 parm->hc_max_packet_size = 0x400;
3497 parm->hc_max_packet_count = 1;
3498 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3499 xfer->flags_int.bdma_enable = 1;
3500
3501 usbd_transfer_setup_sub(parm);
3502
3503 nqh = 1;
3504 nqtd = ((2 * xfer->nframes)
3505 + (xfer->max_data_length / xfer->max_hc_frame_size));
3506
3507 } else if (parm->methods == &ehci_device_intr_methods) {
3508
3509 if (parm->speed == USB_SPEED_HIGH) {
3510 parm->hc_max_packet_size = 0x400;
3511 parm->hc_max_packet_count = 3;
3512 } else if (parm->speed == USB_SPEED_FULL) {
3513 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3514 parm->hc_max_packet_count = 1;
3515 } else {
3516 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3517 parm->hc_max_packet_count = 1;
3518 }
3519
3520 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3521 xfer->flags_int.bdma_enable = 1;
3522
3523 usbd_transfer_setup_sub(parm);
3524
3525 nqh = 1;
3526 nqtd = ((2 * xfer->nframes)
3527 + (xfer->max_data_length / xfer->max_hc_frame_size));
3528
3529 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3530
3531 parm->hc_max_packet_size = 0x3FF;
3532 parm->hc_max_packet_count = 1;
3533 parm->hc_max_frame_size = 0x3FF;
3534 xfer->flags_int.bdma_enable = 1;
3535
3536 usbd_transfer_setup_sub(parm);
3537
3538 nsitd = xfer->nframes;
3539
3540 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3541
3542 parm->hc_max_packet_size = 0x400;
3543 parm->hc_max_packet_count = 3;
3544 parm->hc_max_frame_size = 0xC00;
3545 xfer->flags_int.bdma_enable = 1;
3546
3547 usbd_transfer_setup_sub(parm);
3548
3549 nitd = ((xfer->nframes + 7) / 8) <<
3550 usbd_xfer_get_fps_shift(xfer);
3551
3552 } else {
3553
3554 parm->hc_max_packet_size = 0x400;
3555 parm->hc_max_packet_count = 1;
3556 parm->hc_max_frame_size = 0x400;
3557
3558 usbd_transfer_setup_sub(parm);
3559 }
3560
3561alloc_dma_set:
3562
3563 if (parm->err) {
3564 return;
3565 }
3566 /*
3567 * Allocate queue heads and transfer descriptors
3568 */
3569 last_obj = NULL;
3570
3571 if (usbd_transfer_setup_sub_malloc(
3572 parm, &pc, sizeof(ehci_itd_t),
3573 EHCI_ITD_ALIGN, nitd)) {
3574 parm->err = USB_ERR_NOMEM;
3575 return;
3576 }
3577 if (parm->buf) {
3578 for (n = 0; n != nitd; n++) {
3579 ehci_itd_t *td;
3580
3581 usbd_get_page(pc + n, 0, &page_info);
3582
3583 td = page_info.buffer;
3584
3585 /* init TD */
3586 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3587 td->obj_next = last_obj;
3588 td->page_cache = pc + n;
3589
3590 last_obj = td;
3591
3592 usb_pc_cpu_flush(pc + n);
3593 }
3594 }
3595 if (usbd_transfer_setup_sub_malloc(
3596 parm, &pc, sizeof(ehci_sitd_t),
3597 EHCI_SITD_ALIGN, nsitd)) {
3598 parm->err = USB_ERR_NOMEM;
3599 return;
3600 }
3601 if (parm->buf) {
3602 for (n = 0; n != nsitd; n++) {
3603 ehci_sitd_t *td;
3604
3605 usbd_get_page(pc + n, 0, &page_info);
3606
3607 td = page_info.buffer;
3608
3609 /* init TD */
3610 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3611 td->obj_next = last_obj;
3612 td->page_cache = pc + n;
3613
3614 last_obj = td;
3615
3616 usb_pc_cpu_flush(pc + n);
3617 }
3618 }
3619 if (usbd_transfer_setup_sub_malloc(
3620 parm, &pc, sizeof(ehci_qtd_t),
3621 EHCI_QTD_ALIGN, nqtd)) {
3622 parm->err = USB_ERR_NOMEM;
3623 return;
3624 }
3625 if (parm->buf) {
3626 for (n = 0; n != nqtd; n++) {
3627 ehci_qtd_t *qtd;
3628
3629 usbd_get_page(pc + n, 0, &page_info);
3630
3631 qtd = page_info.buffer;
3632
3633 /* init TD */
3634 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3635 qtd->obj_next = last_obj;
3636 qtd->page_cache = pc + n;
3637
3638 last_obj = qtd;
3639
3640 usb_pc_cpu_flush(pc + n);
3641 }
3642 }
3643 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3644
3645 last_obj = NULL;
3646
3647 if (usbd_transfer_setup_sub_malloc(
3648 parm, &pc, sizeof(ehci_qh_t),
3649 EHCI_QH_ALIGN, nqh)) {
3650 parm->err = USB_ERR_NOMEM;
3651 return;
3652 }
3653 if (parm->buf) {
3654 for (n = 0; n != nqh; n++) {
3655 ehci_qh_t *qh;
3656
3657 usbd_get_page(pc + n, 0, &page_info);
3658
3659 qh = page_info.buffer;
3660
3661 /* init QH */
3662 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3663 qh->obj_next = last_obj;
3664 qh->page_cache = pc + n;
3665
3666 last_obj = qh;
3667
3668 usb_pc_cpu_flush(pc + n);
3669 }
3670 }
3671 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3672
3673 if (!xfer->flags_int.curr_dma_set) {
3674 xfer->flags_int.curr_dma_set = 1;
3675 goto alloc_dma_set;
3676 }
3677}
3678
3679static void
3680ehci_xfer_unsetup(struct usb_xfer *xfer)
3681{
3682 return;
3683}
3684
3685static void
3686ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3687 struct usb_endpoint *ep)
3688{
3689 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3690
3691 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3692 ep, udev->address,
3693 edesc->bEndpointAddress, udev->flags.usb_mode,
3694 sc->sc_addr);
3695
3696 if (udev->flags.usb_mode != USB_MODE_HOST) {
3697 /* not supported */
3698 return;
3699 }
3700 if (udev->device_index != sc->sc_addr) {
3701
3702 if ((udev->speed != USB_SPEED_HIGH) &&
3703 ((udev->hs_hub_addr == 0) ||
3704 (udev->hs_port_no == 0) ||
3705 (udev->parent_hs_hub == NULL) ||
3706 (udev->parent_hs_hub->hub == NULL))) {
3707 /* We need a transaction translator */
3708 goto done;
3709 }
3710 switch (edesc->bmAttributes & UE_XFERTYPE) {
3711 case UE_CONTROL:
3712 ep->methods = &ehci_device_ctrl_methods;
3713 break;
3714 case UE_INTERRUPT:
3715 ep->methods = &ehci_device_intr_methods;
3716 break;
3717 case UE_ISOCHRONOUS:
3718 if (udev->speed == USB_SPEED_HIGH) {
3719 ep->methods = &ehci_device_isoc_hs_methods;
3720 } else if (udev->speed == USB_SPEED_FULL) {
3721 ep->methods = &ehci_device_isoc_fs_methods;
3722 }
3723 break;
3724 case UE_BULK:
3725 ep->methods = &ehci_device_bulk_methods;
3726 break;
3727 default:
3728 /* do nothing */
3729 break;
3730 }
3731 }
3732done:
3733 return;
3734}
3735
3736static void
3737ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3738{
3739 /*
3740 * Wait until the hardware has finished any possible use of
3741 * the transfer descriptor(s) and QH
3742 */
3743 *pus = (188); /* microseconds */
3744}
3745
3746static void
3747ehci_device_resume(struct usb_device *udev)
3748{
3749 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3750 struct usb_xfer *xfer;
3751 struct usb_pipe_methods *methods;
3752
3753 DPRINTF("\n");
3754
3755 USB_BUS_LOCK(udev->bus);
3756
3757 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3758
3759 if (xfer->xroot->udev == udev) {
3760
3761 methods = xfer->endpoint->methods;
3762
3763 if ((methods == &ehci_device_bulk_methods) ||
3764 (methods == &ehci_device_ctrl_methods)) {
3765 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3766 sc->sc_async_p_last);
3767 }
3768 if (methods == &ehci_device_intr_methods) {
3769 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3770 sc->sc_intr_p_last[xfer->qh_pos]);
3771 }
3772 }
3773 }
3774
3775 USB_BUS_UNLOCK(udev->bus);
3776
3777 return;
3778}
3779
3780static void
3781ehci_device_suspend(struct usb_device *udev)
3782{
3783 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3784 struct usb_xfer *xfer;
3785 struct usb_pipe_methods *methods;
3786
3787 DPRINTF("\n");
3788
3789 USB_BUS_LOCK(udev->bus);
3790
3791 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3792
3793 if (xfer->xroot->udev == udev) {
3794
3795 methods = xfer->endpoint->methods;
3796
3797 if ((methods == &ehci_device_bulk_methods) ||
3798 (methods == &ehci_device_ctrl_methods)) {
3799 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3800 sc->sc_async_p_last);
3801 }
3802 if (methods == &ehci_device_intr_methods) {
3803 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3804 sc->sc_intr_p_last[xfer->qh_pos]);
3805 }
3806 }
3807 }
3808
3809 USB_BUS_UNLOCK(udev->bus);
3810}
3811
3812static void
3813ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3814{
3815 struct ehci_softc *sc = EHCI_BUS2SC(bus);
3816
3817 switch (state) {
3818 case USB_HW_POWER_SUSPEND:
3819 case USB_HW_POWER_SHUTDOWN:
3820 ehci_suspend(sc);
3821 break;
3822 case USB_HW_POWER_RESUME:
3823 ehci_resume(sc);
3824 break;
3825 default:
3826 break;
3827 }
3828}
3829
3830static void
3831ehci_set_hw_power(struct usb_bus *bus)
3832{
3833 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3834 uint32_t temp;
3835 uint32_t flags;
3836
3837 DPRINTF("\n");
3838
3839 USB_BUS_LOCK(bus);
3840
3841 flags = bus->hw_power_state;
3842
3843 temp = EOREAD4(sc, EHCI_USBCMD);
3844
3845 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3846
3847 if (flags & (USB_HW_POWER_CONTROL |
3848 USB_HW_POWER_BULK)) {
3849 DPRINTF("Async is active\n");
3850 temp |= EHCI_CMD_ASE;
3851 }
3852 if (flags & (USB_HW_POWER_INTERRUPT |
3853 USB_HW_POWER_ISOC)) {
3854 DPRINTF("Periodic is active\n");
3855 temp |= EHCI_CMD_PSE;
3856 }
3857 EOWRITE4(sc, EHCI_USBCMD, temp);
3858
3859 USB_BUS_UNLOCK(bus);
3860
3861 return;
3862}
3863
3864struct usb_bus_methods ehci_bus_methods =
3865{
3866 .endpoint_init = ehci_ep_init,
3867 .xfer_setup = ehci_xfer_setup,
3868 .xfer_unsetup = ehci_xfer_unsetup,
3869 .get_dma_delay = ehci_get_dma_delay,
3870 .device_resume = ehci_device_resume,
3871 .device_suspend = ehci_device_suspend,
3872 .set_hw_power = ehci_set_hw_power,
3873 .set_hw_power_sleep = ehci_set_hw_power_sleep,
3874 .roothub_exec = ehci_roothub_exec,
3875 .xfer_poll = ehci_do_poll,
3876};