elcr: File relocate
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD
41#include "use_npx.h"
42#include "use_isa.h"
984263bc
MD
43#include "opt_atalk.h"
44#include "opt_compat.h"
45#include "opt_cpu.h"
46#include "opt_ddb.h"
47#include "opt_directio.h"
48#include "opt_inet.h"
49#include "opt_ipx.h"
50#include "opt_maxmem.h"
51#include "opt_msgbuf.h"
52#include "opt_perfmon.h"
53#include "opt_swap.h"
984263bc 54#include "opt_userconfig.h"
eac0bf8f 55#include "opt_apic.h"
984263bc
MD
56
57#include <sys/param.h>
58#include <sys/systm.h>
59#include <sys/sysproto.h>
60#include <sys/signalvar.h>
61#include <sys/kernel.h>
62#include <sys/linker.h>
63#include <sys/malloc.h>
64#include <sys/proc.h>
895c1f85 65#include <sys/priv.h>
984263bc
MD
66#include <sys/buf.h>
67#include <sys/reboot.h>
984263bc
MD
68#include <sys/mbuf.h>
69#include <sys/msgbuf.h>
70#include <sys/sysent.h>
71#include <sys/sysctl.h>
72#include <sys/vmmeter.h>
73#include <sys/bus.h>
a722be49 74#include <sys/upcall.h>
cb7f4ab1 75#include <sys/usched.h>
527fddf7 76#include <sys/reg.h>
984263bc
MD
77
78#include <vm/vm.h>
79#include <vm/vm_param.h>
80#include <sys/lock.h>
81#include <vm/vm_kern.h>
82#include <vm/vm_object.h>
83#include <vm/vm_page.h>
84#include <vm/vm_map.h>
85#include <vm/vm_pager.h>
86#include <vm/vm_extern.h>
87
4b5f931b 88#include <sys/thread2.h>
684a93c4 89#include <sys/mplock2.h>
4b5f931b 90
984263bc
MD
91#include <sys/user.h>
92#include <sys/exec.h>
93#include <sys/cons.h>
94
95#include <ddb/ddb.h>
96
984263bc 97#include <machine/cpu.h>
984263bc
MD
98#include <machine/clock.h>
99#include <machine/specialreg.h>
100#include <machine/bootinfo.h>
984263bc
MD
101#include <machine/md_var.h>
102#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 103#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 104#include <machine/smp.h>
984263bc
MD
105#ifdef PERFMON
106#include <machine/perfmon.h>
107#endif
108#include <machine/cputypes.h>
87cf6827 109#include <machine/intr_machdep.h>
984263bc
MD
110
111#ifdef OLD_BUS_ARCH
21ce0dfa 112#include <bus/isa/isa_device.h>
984263bc 113#endif
87cf6827 114#include <machine_base/isa/isa_intr.h>
1f2de5d4 115#include <bus/isa/rtc.h>
984263bc
MD
116#include <machine/vm86.h>
117#include <sys/random.h>
118#include <sys/ptrace.h>
119#include <machine/sigframe.h>
120
30c5f287 121#include <sys/machintr.h>
9284cddf 122#include <machine_base/icu/icu_abi.h>
7265a4fe 123#include <machine_base/icu/elcr_var.h>
a3dd9120 124#include <machine_base/apic/ioapic_abi.h>
30c5f287 125
ff1a75a1
MD
126#define PHYSMAP_ENTRIES 10
127
d678dc17
MN
128extern void init386(int first);
129extern void dblfault_handler(void);
984263bc
MD
130
131extern void printcpuinfo(void); /* XXX header file */
132extern void finishidentcpu(void);
133extern void panicifcpuunsupported(void);
134extern void initializecpu(void);
135
d678dc17 136static void cpu_startup(void *);
642a6e88 137#ifndef CPU_DISABLE_SSE
d678dc17
MN
138static void set_fpregs_xmm(struct save87 *, struct savexmm *);
139static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 140#endif /* CPU_DISABLE_SSE */
984263bc
MD
141#ifdef DIRECTIO
142extern void ffs_rawread_setup(void);
143#endif /* DIRECTIO */
8a8d5d85 144static void init_locks(void);
984263bc 145
ba39e2e0 146SYSINIT(cpu, SI_BOOT2_SMP, SI_ORDER_FIRST, cpu_startup, NULL)
984263bc 147
984263bc
MD
148int _udatasel, _ucodesel;
149u_int atdevbase;
c2751817
MD
150#ifdef SMP
151int64_t tsc_offsets[MAXCPU];
152#else
153int64_t tsc_offsets[1];
154#endif
984263bc
MD
155
156#if defined(SWTCH_OPTIM_STATS)
157extern int swtch_optim_stats;
158SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
159 CTLFLAG_RD, &swtch_optim_stats, 0, "");
160SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
161 CTLFLAG_RD, &tlb_flush_count, 0, "");
162#endif
163
39d69dae 164long physmem = 0;
984263bc 165
1876681a
SZ
166u_long ebda_addr = 0;
167
984263bc
MD
168static int
169sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
170{
39d69dae
AH
171 u_long pmem = ctob(physmem);
172
173 int error = sysctl_handle_long(oidp, &pmem, 0, req);
984263bc
MD
174 return (error);
175}
176
39d69dae 177SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 178 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
984263bc
MD
179
180static int
181sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
182{
183 int error = sysctl_handle_int(oidp, 0,
12e4aaff 184 ctob(physmem - vmstats.v_wire_count), req);
984263bc
MD
185 return (error);
186}
187
188SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
189 0, 0, sysctl_hw_usermem, "IU", "");
190
191static int
192sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
193{
194 int error = sysctl_handle_int(oidp, 0,
195 i386_btop(avail_end - avail_start), req);
196 return (error);
197}
198
199SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
200 0, 0, sysctl_hw_availpages, "I", "");
201
1bda0d3d
MD
202vm_paddr_t Maxmem;
203vm_paddr_t Realmem;
984263bc 204
ff1a75a1 205vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH
206vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
207
984263bc
MD
208
209static vm_offset_t buffer_sva, buffer_eva;
210vm_offset_t clean_sva, clean_eva;
211static vm_offset_t pager_sva, pager_eva;
212static struct trapframe proc0_tf;
213
214static void
f123d5a1 215cpu_startup(void *dummy)
984263bc 216{
c9faf524 217 caddr_t v;
984263bc 218 vm_size_t size = 0;
e4846942 219 vm_offset_t firstaddr;
984263bc 220
984263bc
MD
221 /*
222 * Good {morning,afternoon,evening,night}.
223 */
26be20a0 224 kprintf("%s", version);
984263bc
MD
225 startrtclock();
226 printcpuinfo();
227 panicifcpuunsupported();
228#ifdef PERFMON
229 perfmon_init();
230#endif
15dc6550 231 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
MD
232 (intmax_t)Realmem,
233 (intmax_t)Realmem / 1024 / 1024);
984263bc
MD
234 /*
235 * Display any holes after the first chunk of extended memory.
236 */
237 if (bootverbose) {
238 int indx;
239
26be20a0 240 kprintf("Physical memory chunk(s):\n");
984263bc 241 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 242 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 243
26be20a0 244 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
984263bc
MD
245 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
246 size1 / PAGE_SIZE);
247 }
248 }
249
984263bc
MD
250 /*
251 * Allocate space for system data structures.
252 * The first available kernel virtual address is in "v".
253 * As pages of kernel virtual memory are allocated, "v" is incremented.
254 * As pages of memory are allocated and cleared,
255 * "firstaddr" is incremented.
256 * An index into the kernel page table corresponding to the
257 * virtual memory address maintained in "v" is kept in "mapaddr".
258 */
259
260 /*
261 * Make two passes. The first pass calculates how much memory is
262 * needed and allocates it. The second pass assigns virtual
263 * addresses to the various data structures.
264 */
265 firstaddr = 0;
266again:
267 v = (caddr_t)firstaddr;
268
269#define valloc(name, type, num) \
270 (name) = (type *)v; v = (caddr_t)((name)+(num))
271#define valloclim(name, type, num, lim) \
272 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
273
984263bc
MD
274 /*
275 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
276 * For the first 64MB of ram nominally allocate sufficient buffers to
277 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
278 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
279 * the buffer cache we limit the eventual kva reservation to
280 * maxbcache bytes.
281 *
282 * factor represents the 1/4 x ram conversion.
283 */
284 if (nbuf == 0) {
285 int factor = 4 * BKVASIZE / 1024;
286 int kbytes = physmem * (PAGE_SIZE / 1024);
287
288 nbuf = 50;
289 if (kbytes > 4096)
290 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
291 if (kbytes > 65536)
292 nbuf += (kbytes - 65536) * 2 / (factor * 5);
293 if (maxbcache && nbuf > maxbcache / BKVASIZE)
294 nbuf = maxbcache / BKVASIZE;
295 }
296
297 /*
298 * Do not allow the buffer_map to be more then 1/2 the size of the
299 * kernel_map.
300 */
e4846942
MD
301 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
302 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
26be20a0 303 kprintf("Warning: nbufs capped at %d\n", nbuf);
984263bc
MD
304 }
305
948209ce
MD
306 /* limit to 128 on i386 */
307 nswbuf = max(min(nbuf/4, 128), 16);
984263bc
MD
308#ifdef NSWBUF_MIN
309 if (nswbuf < NSWBUF_MIN)
310 nswbuf = NSWBUF_MIN;
311#endif
312#ifdef DIRECTIO
313 ffs_rawread_setup();
314#endif
315
316 valloc(swbuf, struct buf, nswbuf);
317 valloc(buf, struct buf, nbuf);
984263bc
MD
318
319 /*
320 * End of first pass, size has been calculated so allocate memory
321 */
322 if (firstaddr == 0) {
323 size = (vm_size_t)(v - firstaddr);
e4846942 324 firstaddr = kmem_alloc(&kernel_map, round_page(size));
984263bc
MD
325 if (firstaddr == 0)
326 panic("startup: no room for tables");
327 goto again;
328 }
329
330 /*
331 * End of second pass, addresses have been assigned
332 */
333 if ((vm_size_t)(v - firstaddr) != size)
334 panic("startup: table size inconsistency");
335
e4846942
MD
336 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
337 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
338 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
339 (nbuf*BKVASIZE));
340 buffer_map.system_map = 1;
341 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
342 (nswbuf*MAXPHYS) + pager_map_size);
343 pager_map.system_map = 1;
984263bc 344
984263bc
MD
345#if defined(USERCONFIG)
346 userconfig();
347 cninit(); /* the preferred console may have changed */
348#endif
349
15dc6550 350 kprintf("avail memory = %ju (%ju MB)\n",
f9ab53b8 351 (intmax_t)ptoa(vmstats.v_free_count),
15dc6550 352 (intmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
984263bc
MD
353
354 /*
355 * Set up buffers, so they can be used to read disk labels.
356 */
357 bufinit();
358 vm_pager_bufferinit();
359
e24dd6e0
SZ
360 /* Log ELCR information */
361 elcr_dump();
362
984263bc
MD
363#ifdef SMP
364 /*
365 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
366 */
367 mp_start(); /* fire up the APs and APICs */
368 mp_announce();
7bf5fa56
SZ
369#else
370 MachIntrABI.finalize();
984263bc
MD
371#endif /* SMP */
372 cpu_setregs();
373}
374
984263bc
MD
375/*
376 * Send an interrupt to process.
377 *
378 * Stack is set up to allow sigcode stored
379 * at top to call routine, followed by kcall
380 * to sigreturn routine below. After sigreturn
381 * resets the signal mask, the stack, and the
382 * frame pointer, it returns to the user
383 * specified pc, psl.
384 */
984263bc 385void
f123d5a1 386sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 387{
065b709a
SS
388 struct lwp *lp = curthread->td_lwp;
389 struct proc *p = lp->lwp_proc;
984263bc
MD
390 struct trapframe *regs;
391 struct sigacts *psp = p->p_sigacts;
392 struct sigframe sf, *sfp;
393 int oonstack;
394
065b709a
SS
395 regs = lp->lwp_md.md_regs;
396 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
MD
397
398 /* save user context */
399 bzero(&sf, sizeof(struct sigframe));
400 sf.sf_uc.uc_sigmask = *mask;
065b709a 401 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 402 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 403 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 404
ce3d8c4d
MD
405 /* make the size of the saved context visible to userland */
406 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
407
4b486183
MD
408 /* save mailbox pending state for syscall interlock semantics */
409 if (p->p_flag & P_MAILBOX)
410 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
411
984263bc 412 /* Allocate and validate space for the signal handler context. */
08f2f1bb 413 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 414 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS
415 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
416 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
417 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 418 } else {
984263bc 419 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 420 }
984263bc
MD
421
422 /* Translate the signal is appropriate */
423 if (p->p_sysent->sv_sigtbl) {
424 if (sig <= p->p_sysent->sv_sigsize)
425 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
426 }
427
428 /* Build the argument list for the signal handler. */
429 sf.sf_signum = sig;
430 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 431 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
984263bc
MD
432 /* Signal handler installed with SA_SIGINFO. */
433 sf.sf_siginfo = (register_t)&sfp->sf_si;
434 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
435
436 /* fill siginfo structure */
437 sf.sf_si.si_signo = sig;
438 sf.sf_si.si_code = code;
439 sf.sf_si.si_addr = (void*)regs->tf_err;
440 }
441 else {
442 /* Old FreeBSD-style arguments. */
443 sf.sf_siginfo = code;
444 sf.sf_addr = regs->tf_err;
445 sf.sf_ahu.sf_handler = catcher;
446 }
447
448 /*
449 * If we're a vm86 process, we want to save the segment registers.
450 * We also change eflags to be our emulated eflags, not the actual
451 * eflags.
452 */
453 if (regs->tf_eflags & PSL_VM) {
454 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 455 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD
456
457 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
458 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
459 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
460 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
461
462 if (vm86->vm86_has_vme == 0)
463 sf.sf_uc.uc_mcontext.mc_eflags =
464 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
465 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
466
467 /*
468 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
469 * syscalls made by the signal handler. This just avoids
470 * wasting time for our lazy fixup of such faults. PSL_NT
471 * does nothing in vm86 mode, but vm86 programs can set it
472 * almost legitimately in probes for old cpu types.
473 */
474 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
475 }
476
1b251f0a
MD
477 /*
478 * Save the FPU state and reinit the FP unit
479 */
480 npxpush(&sf.sf_uc.uc_mcontext);
481
984263bc
MD
482 /*
483 * Copy the sigframe out to the user's stack.
484 */
485 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
486 /*
487 * Something is wrong with the stack pointer.
488 * ...Kill the process.
489 */
b276424c 490 sigexit(lp, SIGILL);
984263bc
MD
491 }
492
493 regs->tf_esp = (int)sfp;
494 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE
495
496 /*
497 * i386 abi specifies that the direction flag must be cleared
498 * on function entry
499 */
500 regs->tf_eflags &= ~(PSL_T|PSL_D);
501
984263bc
MD
502 regs->tf_cs = _ucodesel;
503 regs->tf_ds = _udatasel;
504 regs->tf_es = _udatasel;
dd4ad62d
MD
505
506 /*
507 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD
508 * the userland program might be using both.
509 *
510 * However, if a T_PROTFLT occured the segment registers could be
511 * totally broken. They must be reset in order to be able to
512 * return to userland.
dd4ad62d 513 */
4e7c41c5
MD
514 if (regs->tf_trapno == T_PROTFLT) {
515 regs->tf_fs = _udatasel;
516 regs->tf_gs = _udatasel;
517 }
984263bc
MD
518 regs->tf_ss = _udatasel;
519}
520
4a22e893
MD
521/*
522 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD
523 * VM context. Remove any items that would otherwise create a privilage
524 * issue.
4a22e893 525 *
4e7c41c5
MD
526 * XXX at the moment we allow userland to set the resume flag. Is this a
527 * bad idea?
4a22e893
MD
528 */
529int
530cpu_sanitize_frame(struct trapframe *frame)
531{
532 frame->tf_cs = _ucodesel;
533 frame->tf_ds = _udatasel;
4e7c41c5
MD
534 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
535#if 0
4a22e893 536 frame->tf_fs = _udatasel;
4e7c41c5
MD
537 frame->tf_gs = _udatasel;
538#endif
4a22e893 539 frame->tf_ss = _udatasel;
4e7c41c5 540 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD
541 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
542 return(0);
543}
544
4e7c41c5
MD
545int
546cpu_sanitize_tls(struct savetls *tls)
547{
548 struct segment_descriptor *desc;
549 int i;
550
551 for (i = 0; i < NGTLS; ++i) {
552 desc = &tls->tls[i];
553 if (desc->sd_dpl == 0 && desc->sd_type == 0)
554 continue;
555 if (desc->sd_def32 == 0)
556 return(ENXIO);
557 if (desc->sd_type != SDT_MEMRWA)
558 return(ENXIO);
559 if (desc->sd_dpl != SEL_UPL)
560 return(ENXIO);
561 if (desc->sd_xx != 0 || desc->sd_p != 1)
562 return(ENXIO);
563 }
564 return(0);
565}
566
984263bc 567/*
65957d54 568 * sigreturn(ucontext_t *sigcntxp)
41c20dac 569 *
984263bc
MD
570 * System call to cleanup state after a signal
571 * has been taken. Reset signal mask and
572 * stack state from context left by sendsig (above).
573 * Return to previous pc and psl as specified by
574 * context left by sendsig. Check carefully to
575 * make sure that the user has not modified the
576 * state to gain improper privileges.
3919ced0
MD
577 *
578 * MPSAFE
984263bc
MD
579 */
580#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
581#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
582
984263bc 583int
753fd850 584sys_sigreturn(struct sigreturn_args *uap)
984263bc 585{
065b709a 586 struct lwp *lp = curthread->td_lwp;
4b486183 587 struct proc *p = lp->lwp_proc;
984263bc 588 struct trapframe *regs;
1b251f0a 589 ucontext_t uc;
984263bc 590 ucontext_t *ucp;
1b251f0a
MD
591 int cs;
592 int eflags;
593 int error;
984263bc 594
1b251f0a
MD
595 /*
596 * We have to copy the information into kernel space so userland
597 * can't modify it while we are sniffing it.
598 */
065b709a 599 regs = lp->lwp_md.md_regs;
1b251f0a
MD
600 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
601 if (error)
602 return (error);
603 ucp = &uc;
984263bc
MD
604 eflags = ucp->uc_mcontext.mc_eflags;
605
606 if (eflags & PSL_VM) {
607 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
608 struct vm86_kernel *vm86;
609
610 /*
611 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
612 * set up the vm86 area, and we can't enter vm86 mode.
613 */
065b709a 614 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 615 return (EINVAL);
065b709a 616 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD
617 if (vm86->vm86_inited == 0)
618 return (EINVAL);
619
620 /* go back to user mode if both flags are set */
621 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 622 trapsignal(lp, SIGBUS, 0);
984263bc
MD
623
624 if (vm86->vm86_has_vme) {
625 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
626 (eflags & VME_USERCHANGE) | PSL_VM;
627 } else {
628 vm86->vm86_eflags = eflags; /* save VIF, VIP */
e2742650
MD
629 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
630 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 631 }
4e7c41c5 632 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
984263bc
MD
633 tf->tf_eflags = eflags;
634 tf->tf_vm86_ds = tf->tf_ds;
635 tf->tf_vm86_es = tf->tf_es;
636 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 637 tf->tf_vm86_gs = tf->tf_gs;
984263bc
MD
638 tf->tf_ds = _udatasel;
639 tf->tf_es = _udatasel;
4e7c41c5 640#if 0
984263bc 641 tf->tf_fs = _udatasel;
4e7c41c5
MD
642 tf->tf_gs = _udatasel;
643#endif
984263bc
MD
644 } else {
645 /*
646 * Don't allow users to change privileged or reserved flags.
647 */
648 /*
649 * XXX do allow users to change the privileged flag PSL_RF.
650 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
651 * should sometimes set it there too. tf_eflags is kept in
652 * the signal context during signal handling and there is no
653 * other place to remember it, so the PSL_RF bit may be
654 * corrupted by the signal handler without us knowing.
655 * Corruption of the PSL_RF bit at worst causes one more or
656 * one less debugger trap, so allowing it is fairly harmless.
657 */
658 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 659 kprintf("sigreturn: eflags = 0x%x\n", eflags);
984263bc
MD
660 return(EINVAL);
661 }
662
663 /*
664 * Don't allow users to load a valid privileged %cs. Let the
665 * hardware check for invalid selectors, excess privilege in
666 * other selectors, invalid %eip's and invalid %esp's.
667 */
668 cs = ucp->uc_mcontext.mc_cs;
669 if (!CS_SECURE(cs)) {
26be20a0 670 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 671 trapsignal(lp, SIGBUS, T_PROTFLT);
984263bc
MD
672 return(EINVAL);
673 }
4e7c41c5 674 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
MD
675 }
676
1b251f0a
MD
677 /*
678 * Restore the FPU state from the frame
679 */
3919ced0 680 crit_enter();
1b251f0a
MD
681 npxpop(&ucp->uc_mcontext);
682
4b486183
MD
683 /*
684 * Merge saved signal mailbox pending flag to maintain interlock
685 * semantics against system calls.
686 */
687 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
688 p->p_flag |= P_MAILBOX;
689
984263bc 690 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 691 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 692 else
065b709a 693 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 694
065b709a
SS
695 lp->lwp_sigmask = ucp->uc_sigmask;
696 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 697 crit_exit();
984263bc
MD
698 return(EJUSTRETURN);
699}
700
a722be49
MD
701/*
702 * Stack frame on entry to function. %eax will contain the function vector,
703 * %ecx will contain the function data. flags, ecx, and eax will have
704 * already been pushed on the stack.
705 */
706struct upc_frame {
707 register_t eax;
708 register_t ecx;
0a455ac5 709 register_t edx;
a722be49
MD
710 register_t flags;
711 register_t oldip;
712};
713
714void
715sendupcall(struct vmupcall *vu, int morepending)
716{
065b709a 717 struct lwp *lp = curthread->td_lwp;
a722be49
MD
718 struct trapframe *regs;
719 struct upcall upcall;
720 struct upc_frame upc_frame;
6e58b5df 721 int crit_count = 0;
a722be49 722
69c61fbe
MD
723 /*
724 * If we are a virtual kernel running an emulated user process
725 * context, switch back to the virtual kernel context before
726 * trying to post the signal.
727 */
39005e16 728 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 729 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 730 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD
731 }
732
a722be49
MD
733 /*
734 * Get the upcall data structure
735 */
065b709a 736 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD
737 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
738 ) {
a722be49 739 vu->vu_pending = 0;
26be20a0 740 kprintf("bad upcall address\n");
a722be49
MD
741 return;
742 }
743
744 /*
745 * If the data structure is already marked pending or has a critical
746 * section count, mark the data structure as pending and return
747 * without doing an upcall. vu_pending is left set.
748 */
6e58b5df
MD
749 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
750 if (upcall.upc_pending < vu->vu_pending) {
751 upcall.upc_pending = vu->vu_pending;
065b709a 752 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 753 sizeof(upcall.upc_pending));
a722be49
MD
754 }
755 return;
756 }
757
758 /*
759 * We can run this upcall now, clear vu_pending.
760 *
761 * Bump our critical section count and set or clear the
762 * user pending flag depending on whether more upcalls are
763 * pending. The user will be responsible for calling
764 * upc_dispatch(-1) to process remaining upcalls.
765 */
766 vu->vu_pending = 0;
6e58b5df 767 upcall.upc_pending = morepending;
f9235b6d 768 ++crit_count;
065b709a 769 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD
770 sizeof(upcall.upc_pending));
771 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
772 sizeof(int));
a722be49
MD
773
774 /*
775 * Construct a stack frame and issue the upcall
776 */
065b709a 777 regs = lp->lwp_md.md_regs;
a722be49
MD
778 upc_frame.eax = regs->tf_eax;
779 upc_frame.ecx = regs->tf_ecx;
0a455ac5 780 upc_frame.edx = regs->tf_edx;
a722be49
MD
781 upc_frame.flags = regs->tf_eflags;
782 upc_frame.oldip = regs->tf_eip;
783 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
784 sizeof(upc_frame)) != 0) {
26be20a0 785 kprintf("bad stack on upcall\n");
a722be49
MD
786 } else {
787 regs->tf_eax = (register_t)vu->vu_func;
788 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 789 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
790 regs->tf_eip = (register_t)vu->vu_ctx;
791 regs->tf_esp -= sizeof(upc_frame);
792 }
793}
794
795/*
796 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD
797 * we have to return EJUSTRETURN in order to prevent eax and edx from
798 * being overwritten by the syscall return value.
a722be49
MD
799 *
800 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
801 * and the function pointer in %eax.
802 */
803int
d678dc17 804fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD
805{
806 struct upc_frame upc_frame;
065b709a 807 struct lwp *lp = curthread->td_lwp;
a722be49
MD
808 struct trapframe *regs;
809 int error;
6e58b5df
MD
810 struct upcall upcall;
811 int crit_count;
a722be49 812
065b709a 813 regs = lp->lwp_md.md_regs;
a722be49 814
065b709a 815 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD
816 if (error == 0) {
817 if (vu) {
818 /*
819 * This jumps us to the next ready context.
820 */
821 vu->vu_pending = 0;
065b709a 822 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD
823 crit_count = 0;
824 if (error == 0)
825 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 826 ++crit_count;
a722be49 827 if (error == 0)
6e58b5df 828 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD
829 regs->tf_eax = (register_t)vu->vu_func;
830 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 831 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
832 regs->tf_eip = (register_t)vu->vu_ctx;
833 regs->tf_esp = (register_t)rsp;
834 } else {
835 /*
836 * This returns us to the originally interrupted code.
837 */
838 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
839 regs->tf_eax = upc_frame.eax;
840 regs->tf_ecx = upc_frame.ecx;
0a455ac5 841 regs->tf_edx = upc_frame.edx;
6e58b5df
MD
842 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
843 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD
844 regs->tf_eip = upc_frame.oldip;
845 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
846 }
847 }
848 if (error == 0)
849 error = EJUSTRETURN;
850 return(error);
851}
852
984263bc
MD
853/*
854 * Machine dependent boot() routine
855 *
856 * I haven't seen anything to put here yet
857 * Possibly some stuff might be grafted back here from boot()
858 */
859void
860cpu_boot(int howto)
861{
862}
863
864/*
865 * Shutdown the CPU as much as possible
866 */
867void
868cpu_halt(void)
869{
870 for (;;)
1184892f 871 __asm__ __volatile("hlt");
984263bc
MD
872}
873
874/*
8ad65e08
MD
875 * cpu_idle() represents the idle LWKT. You cannot return from this function
876 * (unless you want to blow things up!). Instead we look for runnable threads
877 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 878 *
26a0694b 879 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD
880 * the critical section before doing anything else. lwkt_switch() will
881 * check for pending interrupts due to entering and exiting its own
882 * critical section.
26a0694b 883 *
7d4d6fdb
MD
884 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
885 * However, there are cases where the idlethread will be entered with
886 * the possibility that no IPI will occur and in such cases
cbdd23b1
MD
887 * lwkt_switch() sets RQF_WAKEUP. We usually check
888 * RQF_IDLECHECK_WK_MASK.
7d4d6fdb 889 *
46e562ce
MD
890 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
891 * 1 to just use hlt and for debugging purposes.
984263bc 892 */
46e562ce 893static int cpu_idle_hlt = 2;
60f945af
MD
894static int cpu_idle_hltcnt;
895static int cpu_idle_spincnt;
be71787b 896static u_int cpu_idle_repeat = 4;
984263bc
MD
897SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
898 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD
899SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
900 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
901SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
902 &cpu_idle_spincnt, 0, "Idle loop entry spins");
be71787b
MD
903SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
904 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 905
f9d8cd12
MD
906static void
907cpu_idle_default_hook(void)
908{
909 /*
910 * We must guarentee that hlt is exactly the instruction
911 * following the sti.
912 */
913 __asm __volatile("sti; hlt");
914}
915
916/* Other subsystems (e.g., ACPI) can hook this later. */
917void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
918
984263bc
MD
919void
920cpu_idle(void)
921{
be71787b 922 globaldata_t gd = mycpu;
10662728 923 struct thread *td __debugvar = gd->gd_curthread;
be71787b
MD
924 int reqflags;
925 int quick;
a2a5ad0d 926
26a0694b 927 crit_exit();
f9235b6d 928 KKASSERT(td->td_critcount == 0);
8ad65e08 929 for (;;) {
a2a5ad0d
MD
930 /*
931 * See if there are any LWKTs ready to go.
932 */
8ad65e08 933 lwkt_switch();
a2a5ad0d
MD
934
935 /*
be71787b
MD
936 * When halting inside a cli we must check for reqflags
937 * races, particularly [re]schedule requests. Running
938 * splz() does the job.
939 *
940 * cpu_idle_hlt:
941 * 0 Never halt, just spin
942 *
943 * 1 Always use HLT (or MONITOR/MWAIT if avail).
944 * This typically eats more power than the
945 * ACPI halt.
946 *
947 * 2 Use HLT/MONITOR/MWAIT up to a point and then
948 * use the ACPI halt (default). This is a hybrid
949 * approach. See machdep.cpu_idle_repeat.
950 *
951 * 3 Always use the ACPI halt. This typically
952 * eats the least amount of power but the cpu
953 * will be slow waking up. Slows down e.g.
954 * compiles and other pipe/event oriented stuff.
955 *
956 *
957 * NOTE: Interrupts are enabled and we are not in a critical
958 * section.
959 *
960 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
961 * don't bother capping gd_idle_repeat, it is ok if
962 * it overflows.
a2a5ad0d 963 */
be71787b
MD
964 ++gd->gd_idle_repeat;
965 reqflags = gd->gd_reqflags;
966 quick = (cpu_idle_hlt == 1) ||
967 (cpu_idle_hlt < 3 &&
968 gd->gd_idle_repeat < cpu_idle_repeat);
969
970 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
971 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
972 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
973 ++cpu_idle_hltcnt;
974 } else if (cpu_idle_hlt) {
a2a5ad0d
MD
975 __asm __volatile("cli");
976 splz();
be71787b
MD
977 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
978 if (quick)
7d4d6fdb
MD
979 cpu_idle_default_hook();
980 else
981 cpu_idle_hook();
982 }
7d4d6fdb 983 __asm __volatile("sti");
60f945af 984 ++cpu_idle_hltcnt;
8ad65e08 985 } else {
60f945af 986 splz();
c5724852 987 __asm __volatile("sti");
60f945af 988 ++cpu_idle_spincnt;
8ad65e08 989 }
984263bc
MD
990 }
991}
992
7ad8cc6c
SW
993#ifdef SMP
994
06615ccb
MD
995/*
996 * This routine is called if a spinlock has been held through the
997 * exponential backoff period and is seriously contested. On a real cpu
998 * we let it spin.
999 */
1000void
1001cpu_spinlock_contested(void)
1002{
1003 cpu_pause();
1004}
1005
7ad8cc6c
SW
1006#endif
1007
984263bc
MD
1008/*
1009 * Clear registers on exec
1010 */
1011void
08f2f1bb 1012exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 1013{
08f2f1bb
SS
1014 struct thread *td = curthread;
1015 struct lwp *lp = td->td_lwp;
1016 struct pcb *pcb = td->td_pcb;
bb3cd951 1017 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 1018
984263bc
MD
1019 /* was i386_user_cleanup() in NetBSD */
1020 user_ldt_free(pcb);
984263bc
MD
1021
1022 bzero((char *)regs, sizeof(struct trapframe));
1023 regs->tf_eip = entry;
1024 regs->tf_esp = stack;
1025 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1026 regs->tf_ss = _udatasel;
1027 regs->tf_ds = _udatasel;
1028 regs->tf_es = _udatasel;
1029 regs->tf_fs = _udatasel;
4e7c41c5 1030 regs->tf_gs = _udatasel;
984263bc
MD
1031 regs->tf_cs = _ucodesel;
1032
1033 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1034 regs->tf_ebx = ps_strings;
1035
1036 /*
1037 * Reset the hardware debug registers if they were in use.
1038 * They won't have any meaning for the newly exec'd process.
1039 */
1040 if (pcb->pcb_flags & PCB_DBREGS) {
1041 pcb->pcb_dr0 = 0;
1042 pcb->pcb_dr1 = 0;
1043 pcb->pcb_dr2 = 0;
1044 pcb->pcb_dr3 = 0;
1045 pcb->pcb_dr6 = 0;
1046 pcb->pcb_dr7 = 0;
08f2f1bb 1047 if (pcb == td->td_pcb) {
984263bc
MD
1048 /*
1049 * Clear the debug registers on the running
1050 * CPU, otherwise they will end up affecting
1051 * the next process we switch to.
1052 */
1053 reset_dbregs();
1054 }
1055 pcb->pcb_flags &= ~PCB_DBREGS;
1056 }
1057
1058 /*
1059 * Initialize the math emulator (if any) for the current process.
1060 * Actually, just clear the bit that says that the emulator has
1061 * been initialized. Initialization is delayed until the process
1062 * traps to the emulator (if it is done at all) mainly because
1063 * emulators don't provide an entry point for initialization.
1064 */
08f2f1bb 1065 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD
1066
1067 /*
a02705a9
MD
1068 * note: do not set CR0_TS here. npxinit() must do it after clearing
1069 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1070 * in npxdna().
984263bc 1071 */
a02705a9
MD
1072 crit_enter();
1073 load_cr0(rcr0() | CR0_MP);
984263bc
MD
1074
1075#if NNPX > 0
1076 /* Initialize the npx (if any) for the current process. */
1077 npxinit(__INITIAL_NPXCW__);
1078#endif
a02705a9 1079 crit_exit();
984263bc 1080
90b9818c
MD
1081 /*
1082 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD
1083 * handled in execve simply by setting the 64 bit syscall
1084 * return value to 0.
90b9818c 1085 */
984263bc
MD
1086}
1087
1088void
1089cpu_setregs(void)
1090{
1091 unsigned int cr0;
1092
1093 cr0 = rcr0();
1094 cr0 |= CR0_NE; /* Done by npxinit() */
1095 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1096 cr0 |= CR0_WP | CR0_AM;
984263bc
MD
1097 load_cr0(cr0);
1098 load_gs(_udatasel);
1099}
1100
1101static int
1102sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1103{
1104 int error;
1105 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1106 req);
1107 if (!error && req->newptr)
1108 resettodr();
1109 return (error);
1110}
1111
1112SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1113 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1114
1115SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1116 CTLFLAG_RW, &disable_rtc_set, 0, "");
1117
1118SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1119 CTLFLAG_RD, &bootinfo, bootinfo, "");
1120
1121SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1122 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1123
b13267a5 1124extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1125SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1126 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD
1127
1128/*
1129 * Initialize 386 and configure to run kernel
1130 */
1131
1132/*
1133 * Initialize segments & interrupt table
1134 */
1135
1136int _default_ldt;
1137union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1138static struct gate_descriptor idt0[NIDT];
1139struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1140union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD
1141
1142/* table descriptors - used to load tables by cpu */
984263bc 1143struct region_descriptor r_gdt, r_idt;
984263bc 1144
984263bc
MD
1145#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1146extern int has_f00f_bug;
1147#endif
1148
1149static struct i386tss dblfault_tss;
1150static char dblfault_stack[PAGE_SIZE];
1151
1152extern struct user *proc0paddr;
1153
1154
1155/* software prototypes -- in more palatable form */
1156struct soft_segment_descriptor gdt_segs[] = {
1157/* GNULL_SEL 0 Null Descriptor */
1158{ 0x0, /* segment base address */
1159 0x0, /* length */
1160 0, /* segment type */
1161 0, /* segment descriptor priority level */
1162 0, /* segment descriptor present */
1163 0, 0,
1164 0, /* default 32 vs 16 bit size */
1165 0 /* limit granularity (byte/page units)*/ },
1166/* GCODE_SEL 1 Code Descriptor for kernel */
1167{ 0x0, /* segment base address */
1168 0xfffff, /* length - all address space */
1169 SDT_MEMERA, /* segment type */
1170 0, /* segment descriptor priority level */
1171 1, /* segment descriptor present */
1172 0, 0,
1173 1, /* default 32 vs 16 bit size */
1174 1 /* limit granularity (byte/page units)*/ },
1175/* GDATA_SEL 2 Data Descriptor for kernel */
1176{ 0x0, /* segment base address */
1177 0xfffff, /* length - all address space */
1178 SDT_MEMRWA, /* segment type */
1179 0, /* segment descriptor priority level */
1180 1, /* segment descriptor present */
1181 0, 0,
1182 1, /* default 32 vs 16 bit size */
1183 1 /* limit granularity (byte/page units)*/ },
1184/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1185{ 0x0, /* segment base address */
1186 0xfffff, /* length - all address space */
1187 SDT_MEMRWA, /* segment type */
1188 0, /* segment descriptor priority level */
1189 1, /* segment descriptor present */
1190 0, 0,
1191 1, /* default 32 vs 16 bit size */
1192 1 /* limit granularity (byte/page units)*/ },
1193/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1194{
1195 0x0, /* segment base address */
1196 sizeof(struct i386tss)-1,/* length - all address space */
1197 SDT_SYS386TSS, /* segment type */
1198 0, /* segment descriptor priority level */
1199 1, /* segment descriptor present */
1200 0, 0,
1201 0, /* unused - default 32 vs 16 bit size */
1202 0 /* limit granularity (byte/page units)*/ },
1203/* GLDT_SEL 5 LDT Descriptor */
1204{ (int) ldt, /* segment base address */
1205 sizeof(ldt)-1, /* length - all address space */
1206 SDT_SYSLDT, /* segment type */
1207 SEL_UPL, /* segment descriptor priority level */
1208 1, /* segment descriptor present */
1209 0, 0,
1210 0, /* unused - default 32 vs 16 bit size */
1211 0 /* limit granularity (byte/page units)*/ },
1212/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1213{ (int) ldt, /* segment base address */
1214 (512 * sizeof(union descriptor)-1), /* length */
1215 SDT_SYSLDT, /* segment type */
1216 0, /* segment descriptor priority level */
1217 1, /* segment descriptor present */
1218 0, 0,
1219 0, /* unused - default 32 vs 16 bit size */
1220 0 /* limit granularity (byte/page units)*/ },
1221/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1222{ 0x0, /* segment base address */
1223 0x0, /* length - all address space */
1224 0, /* segment type */
1225 0, /* segment descriptor priority level */
1226 0, /* segment descriptor present */
1227 0, 0,
1228 0, /* default 32 vs 16 bit size */
1229 0 /* limit granularity (byte/page units)*/ },
1230/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1231{ 0x400, /* segment base address */
1232 0xfffff, /* length */
1233 SDT_MEMRWA, /* segment type */
1234 0, /* segment descriptor priority level */
1235 1, /* segment descriptor present */
1236 0, 0,
1237 1, /* default 32 vs 16 bit size */
1238 1 /* limit granularity (byte/page units)*/ },
1239/* GPANIC_SEL 9 Panic Tss Descriptor */
1240{ (int) &dblfault_tss, /* segment base address */
1241 sizeof(struct i386tss)-1,/* length - all address space */
1242 SDT_SYS386TSS, /* segment type */
1243 0, /* segment descriptor priority level */
1244 1, /* segment descriptor present */
1245 0, 0,
1246 0, /* unused - default 32 vs 16 bit size */
1247 0 /* limit granularity (byte/page units)*/ },
1248/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1249{ 0, /* segment base address (overwritten) */
1250 0xfffff, /* length */
1251 SDT_MEMERA, /* segment type */
1252 0, /* segment descriptor priority level */
1253 1, /* segment descriptor present */
1254 0, 0,
1255 0, /* default 32 vs 16 bit size */
1256 1 /* limit granularity (byte/page units)*/ },
1257/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1258{ 0, /* segment base address (overwritten) */
1259 0xfffff, /* length */
1260 SDT_MEMERA, /* segment type */
1261 0, /* segment descriptor priority level */
1262 1, /* segment descriptor present */
1263 0, 0,
1264 0, /* default 32 vs 16 bit size */
1265 1 /* limit granularity (byte/page units)*/ },
1266/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1267{ 0, /* segment base address (overwritten) */
1268 0xfffff, /* length */
1269 SDT_MEMRWA, /* segment type */
1270 0, /* segment descriptor priority level */
1271 1, /* segment descriptor present */
1272 0, 0,
1273 1, /* default 32 vs 16 bit size */
1274 1 /* limit granularity (byte/page units)*/ },
1275/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1276{ 0, /* segment base address (overwritten) */
1277 0xfffff, /* length */
1278 SDT_MEMRWA, /* segment type */
1279 0, /* segment descriptor priority level */
1280 1, /* segment descriptor present */
1281 0, 0,
1282 0, /* default 32 vs 16 bit size */
1283 1 /* limit granularity (byte/page units)*/ },
1284/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1285{ 0, /* segment base address (overwritten) */
1286 0xfffff, /* length */
1287 SDT_MEMRWA, /* segment type */
1288 0, /* segment descriptor priority level */
1289 1, /* segment descriptor present */
1290 0, 0,
1291 0, /* default 32 vs 16 bit size */
1292 1 /* limit granularity (byte/page units)*/ },
806bf111
MD
1293/* GTLS_START 15 TLS */
1294{ 0x0, /* segment base address */
1295 0x0, /* length */
1296 0, /* segment type */
1297 0, /* segment descriptor priority level */
1298 0, /* segment descriptor present */
1299 0, 0,
1300 0, /* default 32 vs 16 bit size */
1301 0 /* limit granularity (byte/page units)*/ },
1302/* GTLS_START+1 16 TLS */
1303{ 0x0, /* segment base address */
1304 0x0, /* length */
1305 0, /* segment type */
1306 0, /* segment descriptor priority level */
1307 0, /* segment descriptor present */
1308 0, 0,
1309 0, /* default 32 vs 16 bit size */
1310 0 /* limit granularity (byte/page units)*/ },
1311/* GTLS_END 17 TLS */
1312{ 0x0, /* segment base address */
1313 0x0, /* length */
1314 0, /* segment type */
1315 0, /* segment descriptor priority level */
1316 0, /* segment descriptor present */
1317 0, 0,
1318 0, /* default 32 vs 16 bit size */
1319 0 /* limit granularity (byte/page units)*/ },
984263bc
MD
1320};
1321
1322static struct soft_segment_descriptor ldt_segs[] = {
1323 /* Null Descriptor - overwritten by call gate */
1324{ 0x0, /* segment base address */
1325 0x0, /* length - all address space */
1326 0, /* segment type */
1327 0, /* segment descriptor priority level */
1328 0, /* segment descriptor present */
1329 0, 0,
1330 0, /* default 32 vs 16 bit size */
1331 0 /* limit granularity (byte/page units)*/ },
1332 /* Null Descriptor - overwritten by call gate */
1333{ 0x0, /* segment base address */
1334 0x0, /* length - all address space */
1335 0, /* segment type */
1336 0, /* segment descriptor priority level */
1337 0, /* segment descriptor present */
1338 0, 0,
1339 0, /* default 32 vs 16 bit size */
1340 0 /* limit granularity (byte/page units)*/ },
1341 /* Null Descriptor - overwritten by call gate */
1342{ 0x0, /* segment base address */
1343 0x0, /* length - all address space */
1344 0, /* segment type */
1345 0, /* segment descriptor priority level */
1346 0, /* segment descriptor present */
1347 0, 0,
1348 0, /* default 32 vs 16 bit size */
1349 0 /* limit granularity (byte/page units)*/ },
1350 /* Code Descriptor for user */
1351{ 0x0, /* segment base address */
1352 0xfffff, /* length - all address space */
1353 SDT_MEMERA, /* segment type */
1354 SEL_UPL, /* segment descriptor priority level */
1355 1, /* segment descriptor present */
1356 0, 0,
1357 1, /* default 32 vs 16 bit size */
1358 1 /* limit granularity (byte/page units)*/ },
1359 /* Null Descriptor - overwritten by call gate */
1360{ 0x0, /* segment base address */
1361 0x0, /* length - all address space */
1362 0, /* segment type */
1363 0, /* segment descriptor priority level */
1364 0, /* segment descriptor present */
1365 0, 0,
1366 0, /* default 32 vs 16 bit size */
1367 0 /* limit granularity (byte/page units)*/ },
1368 /* Data Descriptor for user */
1369{ 0x0, /* segment base address */
1370 0xfffff, /* length - all address space */
1371 SDT_MEMRWA, /* segment type */
1372 SEL_UPL, /* segment descriptor priority level */
1373 1, /* segment descriptor present */
1374 0, 0,
1375 1, /* default 32 vs 16 bit size */
1376 1 /* limit granularity (byte/page units)*/ },
1377};
1378
1379void
f123d5a1 1380setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD
1381{
1382 struct gate_descriptor *ip;
1383
1384 ip = idt + idx;
1385 ip->gd_looffset = (int)func;
1386 ip->gd_selector = selec;
1387 ip->gd_stkcpy = 0;
1388 ip->gd_xx = 0;
1389 ip->gd_type = typ;
1390 ip->gd_dpl = dpl;
1391 ip->gd_p = 1;
1392 ip->gd_hioffset = ((int)func)>>16 ;
1393}
1394
1395#define IDTVEC(name) __CONCAT(X,name)
1396
1397extern inthand_t
1398 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1399 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1400 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1401 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1402 IDTVEC(xmm), IDTVEC(syscall),
1403 IDTVEC(rsvd0);
a64ba182 1404extern inthand_t
f9a13fc4 1405 IDTVEC(int0x80_syscall);
984263bc 1406
f7bc9806
MD
1407#ifdef DEBUG_INTERRUPTS
1408extern inthand_t *Xrsvdary[256];
1409#endif
1410
984263bc 1411void
f123d5a1 1412sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD
1413{
1414 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1415 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1416 ssd->ssd_type = sd->sd_type;
1417 ssd->ssd_dpl = sd->sd_dpl;
1418 ssd->ssd_p = sd->sd_p;
1419 ssd->ssd_def32 = sd->sd_def32;
1420 ssd->ssd_gran = sd->sd_gran;
1421}
1422
984263bc
MD
1423/*
1424 * Populate the (physmap) array with base/bound pairs describing the
1425 * available physical memory in the system, then test this memory and
1426 * build the phys_avail array describing the actually-available memory.
1427 *
1428 * If we cannot accurately determine the physical memory map, then use
1429 * value from the 0xE801 call, and failing that, the RTC.
1430 *
1431 * Total memory size may be set by the kernel environment variable
1432 * hw.physmem or the compile-time define MAXMEM.
1433 */
1434static void
1435getmemsize(int first)
1436{
b24cd69c 1437 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD
1438 int hasbrokenint12;
1439 u_int basemem, extmem;
1440 struct vm86frame vmf;
1441 struct vm86context vmc;
ff1a75a1
MD
1442 vm_offset_t pa;
1443 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1444 pt_entry_t *pte;
555da584 1445 quad_t maxmem;
984263bc
MD
1446 struct {
1447 u_int64_t base;
1448 u_int64_t length;
1449 u_int32_t type;
1450 } *smap;
28abdbbb 1451 quad_t dcons_addr, dcons_size;
984263bc 1452
984263bc
MD
1453 bzero(&vmf, sizeof(struct vm86frame));
1454 bzero(physmap, sizeof(physmap));
1455 basemem = 0;
1456
1457 /*
1458 * Some newer BIOSes has broken INT 12H implementation which cause
1459 * kernel panic immediately. In this case, we need to scan SMAP
1460 * with INT 15:E820 first, then determine base memory size.
1461 */
2ed482dc
MN
1462 hasbrokenint12 = 0;
1463 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD
1464 if (hasbrokenint12) {
1465 goto int15e820;
1466 }
1467
1468 /*
7febcc6e
MD
1469 * Perform "base memory" related probes & setup. If we get a crazy
1470 * value give the bios some scribble space just in case.
984263bc
MD
1471 */
1472 vm86_intcall(0x12, &vmf);
1473 basemem = vmf.vmf_ax;
1474 if (basemem > 640) {
26be20a0 1475 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD
1476 "truncating to < 640K\n", basemem);
1477 basemem = 636;
984263bc
MD
1478 }
1479
1480 /*
1481 * XXX if biosbasemem is now < 640, there is a `hole'
1482 * between the end of base memory and the start of
1483 * ISA memory. The hole may be empty or it may
1484 * contain BIOS code or data. Map it read/write so
1485 * that the BIOS can write to it. (Memory from 0 to
1486 * the physical end of the kernel is mapped read-only
1487 * to begin with and then parts of it are remapped.
1488 * The parts that aren't remapped form holes that
1489 * remain read-only and are unused by the kernel.
1490 * The base memory area is below the physical end of
1491 * the kernel and right now forms a read-only hole.
1492 * The part of it from PAGE_SIZE to
1493 * (trunc_page(biosbasemem * 1024) - 1) will be
1494 * remapped and used by the kernel later.)
1495 *
1496 * This code is similar to the code used in
1497 * pmap_mapdev, but since no memory needs to be
1498 * allocated we simply change the mapping.
1499 */
1500 for (pa = trunc_page(basemem * 1024);
1501 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1502 pte = vtopte(pa + KERNBASE);
984263bc
MD
1503 *pte = pa | PG_RW | PG_V;
1504 }
1505
1506 /*
1507 * if basemem != 640, map pages r/w into vm86 page table so
1508 * that the bios can scribble on it.
1509 */
b5b32410 1510 pte = vm86paddr;
984263bc
MD
1511 for (i = basemem / 4; i < 160; i++)
1512 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1513
1514int15e820:
1515 /*
1516 * map page 1 R/W into the kernel page table so we can use it
1517 * as a buffer. The kernel will unmap this page later.
1518 */
b5b32410 1519 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1520 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1521
1522 /*
1523 * get memory map with INT 15:E820
1524 */
1525#define SMAPSIZ sizeof(*smap)
1526#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1527
1528 vmc.npages = 0;
1529 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1530 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1531
1532 physmap_idx = 0;
1533 vmf.vmf_ebx = 0;
1534 do {
1535 vmf.vmf_eax = 0xE820;
1536 vmf.vmf_edx = SMAP_SIG;
1537 vmf.vmf_ecx = SMAPSIZ;
1538 i = vm86_datacall(0x15, &vmf, &vmc);
1539 if (i || vmf.vmf_eax != SMAP_SIG)
1540 break;
1541 if (boothowto & RB_VERBOSE)
26be20a0 1542 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD
1543 smap->type,
1544 *(u_int32_t *)((char *)&smap->base + 4),
1545 (u_int32_t)smap->base,
1546 *(u_int32_t *)((char *)&smap->length + 4),
1547 (u_int32_t)smap->length);
1548
1549 if (smap->type != 0x01)
1550 goto next_run;
1551
1552 if (smap->length == 0)
1553 goto next_run;
1554
1bda0d3d
MD
1555 Realmem += smap->length;
1556
1557 if (smap->base >= 0xffffffffLLU) {
9c3db322 1558 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1559 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD
1560 goto next_run;
1561 }
1562
1563 for (i = 0; i <= physmap_idx; i += 2) {
1564 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1565 if (boothowto & RB_VERBOSE) {
1566 kprintf("Overlapping or non-montonic "
1567 "memory region, ignoring "
1568 "second region\n");
1569 }
1570 Realmem -= smap->length;
984263bc
MD
1571 goto next_run;
1572 }
1573 }
1574
1575 if (smap->base == physmap[physmap_idx + 1]) {
1576 physmap[physmap_idx + 1] += smap->length;
1577 goto next_run;
1578 }
1579
1580 physmap_idx += 2;
ff1a75a1 1581 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD
1582 kprintf("Too many segments in the physical "
1583 "address map, giving up\n");
984263bc
MD
1584 break;
1585 }
1586 physmap[physmap_idx] = smap->base;
1587 physmap[physmap_idx + 1] = smap->base + smap->length;
1588next_run:
6b08710e 1589 ; /* fix GCC3.x warning */
984263bc
MD
1590 } while (vmf.vmf_ebx != 0);
1591
1592 /*
1593 * Perform "base memory" related probes & setup based on SMAP
1594 */
1595 if (basemem == 0) {
1596 for (i = 0; i <= physmap_idx; i += 2) {
1597 if (physmap[i] == 0x00000000) {
1598 basemem = physmap[i + 1] / 1024;
1599 break;
1600 }
1601 }
1602
1603 if (basemem == 0) {
1604 basemem = 640;
1605 }
1606
1607 if (basemem > 640) {
1bda0d3d
MD
1608 kprintf("Preposterous BIOS basemem of %uK, "
1609 "truncating to 640K\n", basemem);
984263bc
MD
1610 basemem = 640;
1611 }
1612
1613 for (pa = trunc_page(basemem * 1024);
1614 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1615 pte = vtopte(pa + KERNBASE);
984263bc
MD
1616 *pte = pa | PG_RW | PG_V;
1617 }
1618
b5b32410 1619 pte = vm86paddr;
984263bc
MD
1620 for (i = basemem / 4; i < 160; i++)
1621 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1622 }
1623
1624 if (physmap[1] != 0)
1625 goto physmap_done;
1626
1627 /*
1628 * If we failed above, try memory map with INT 15:E801
1629 */
1630 vmf.vmf_ax = 0xE801;
1631 if (vm86_intcall(0x15, &vmf) == 0) {
1632 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1633 } else {
1634#if 0
1635 vmf.vmf_ah = 0x88;
1636 vm86_intcall(0x15, &vmf);
1637 extmem = vmf.vmf_ax;
1638#else
1639 /*
1640 * Prefer the RTC value for extended memory.
1641 */
1642 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1643#endif
1644 }
1645
1646 /*
1647 * Special hack for chipsets that still remap the 384k hole when
1648 * there's 16MB of memory - this really confuses people that
1649 * are trying to use bus mastering ISA controllers with the
1650 * "16MB limit"; they only have 16MB, but the remapping puts
1651 * them beyond the limit.
1652 *
1653 * If extended memory is between 15-16MB (16-17MB phys address range),
1654 * chop it to 15MB.
1655 */
1656 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1657 extmem = 15 * 1024;
1658
1659 physmap[0] = 0;
1660 physmap[1] = basemem * 1024;
1661 physmap_idx = 2;
1662 physmap[physmap_idx] = 0x100000;
1663 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1664
1665physmap_done:
1666 /*
1667 * Now, physmap contains a map of physical memory.
1668 */
1669
1670#ifdef SMP
17a9f566 1671 /* make hole for AP bootstrap code YYY */
c0c5de70 1672 physmap[1] = mp_bootaddress(physmap[1]);
984263bc 1673
1876681a
SZ
1674 /* Save EBDA address, if any */
1675 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1676 ebda_addr <<= 4;
984263bc
MD
1677#endif
1678
1679 /*
1680 * Maxmem isn't the "maximum memory", it's one larger than the
1681 * highest page of the physical address space. It should be
1682 * called something like "Maxphyspage". We may adjust this
1683 * based on ``hw.physmem'' and the results of the memory test.
1684 */
1685 Maxmem = atop(physmap[physmap_idx + 1]);
1686
1687#ifdef MAXMEM
1688 Maxmem = MAXMEM / 4;
1689#endif
1690
555da584
MD
1691 if (kgetenv_quad("hw.physmem", &maxmem))
1692 Maxmem = atop(maxmem);
984263bc
MD
1693
1694 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1695 (boothowto & RB_VERBOSE))
26be20a0 1696 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1697
1698 /*
1699 * If Maxmem has been increased beyond what the system has detected,
1700 * extend the last memory segment to the new limit.
1701 */
1702 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1703 physmap[physmap_idx + 1] = ptoa(Maxmem);
1704
1705 /* call pmap initialization to make new kernel address space */
1706 pmap_bootstrap(first, 0);
1707
1708 /*
1709 * Size up each available chunk of physical memory.
1710 */
1711 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1712 pa_indx = 0;
b24cd69c 1713 da_indx = 1;
984263bc
MD
1714 phys_avail[pa_indx++] = physmap[0];
1715 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH
1716 dump_avail[da_indx] = physmap[0];
1717
b5b32410 1718 pte = CMAP1;
984263bc 1719
28abdbbb
HS
1720 /*
1721 * Get dcons buffer address
1722 */
bc01a404
MD
1723 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1724 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS
1725 dcons_addr = 0;
1726
984263bc
MD
1727 /*
1728 * physmap is in bytes, so when converting to page boundaries,
1729 * round up the start address and round down the end address.
1730 */
1731 for (i = 0; i <= physmap_idx; i += 2) {
1732 vm_offset_t end;
1733
1734 end = ptoa(Maxmem);
1735 if (physmap[i + 1] < end)
1736 end = trunc_page(physmap[i + 1]);
1737 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1738 int tmp, page_bad, full;
984263bc
MD
1739#if 0
1740 int *ptr = 0;
1741#else
1742 int *ptr = (int *)CADDR1;
1743#endif
b24cd69c 1744 full = FALSE;
984263bc
MD
1745
1746 /*
1747 * block out kernel memory as not available.
1748 */
1749 if (pa >= 0x100000 && pa < first)
b24cd69c 1750 goto do_dump_avail;
984263bc 1751
28abdbbb
HS
1752 /*
1753 * block out dcons buffer
1754 */
1755 if (dcons_addr > 0
1756 && pa >= trunc_page(dcons_addr)
1757 && pa < dcons_addr + dcons_size)
b24cd69c 1758 goto do_dump_avail;
28abdbbb 1759
984263bc
MD
1760 page_bad = FALSE;
1761
1762 /*
1763 * map page into kernel: valid, read/write,non-cacheable
1764 */
1765 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1766 cpu_invltlb();
984263bc
MD
1767
1768 tmp = *(int *)ptr;
1769 /*
1770 * Test for alternating 1's and 0's
1771 */
1772 *(volatile int *)ptr = 0xaaaaaaaa;
1773 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1774 page_bad = TRUE;
1775 }
1776 /*
1777 * Test for alternating 0's and 1's
1778 */
1779 *(volatile int *)ptr = 0x55555555;
1780 if (*(volatile int *)ptr != 0x55555555) {
1781 page_bad = TRUE;
1782 }
1783 /*
1784 * Test for all 1's
1785 */
1786 *(volatile int *)ptr = 0xffffffff;
1787 if (*(volatile int *)ptr != 0xffffffff) {
1788 page_bad = TRUE;
1789 }
1790 /*
1791 * Test for all 0's
1792 */
1793 *(volatile int *)ptr = 0x0;
1794 if (*(volatile int *)ptr != 0x0) {
1795 page_bad = TRUE;
1796 }
1797 /*
1798 * Restore original value.
1799 */
1800 *(int *)ptr = tmp;
1801
1802 /*
1803 * Adjust array of valid/good pages.
1804 */
1805 if (page_bad == TRUE) {
1806 continue;
1807 }
1808 /*
1809 * If this good page is a continuation of the
1810 * previous set of good pages, then just increase
1811 * the end pointer. Otherwise start a new chunk.
1812 * Note that "end" points one higher than end,
1813 * making the range >= start and < end.
1814 * If we're also doing a speculative memory
1815 * test and we at or past the end, bump up Maxmem
1816 * so that we keep going. The first bad page
1817 * will terminate the loop.
1818 */
1819 if (phys_avail[pa_indx] == pa) {
1820 phys_avail[pa_indx] += PAGE_SIZE;
1821 } else {
1822 pa_indx++;
ff1a75a1 1823 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1824 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1825 pa_indx--;
b24cd69c
AH
1826 full = TRUE;
1827 goto do_dump_avail;
984263bc
MD
1828 }
1829 phys_avail[pa_indx++] = pa; /* start */
1830 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1831 }
1832 physmem++;
b24cd69c
AH
1833do_dump_avail:
1834 if (dump_avail[da_indx] == pa) {
1835 dump_avail[da_indx] += PAGE_SIZE;
1836 } else {
1837 da_indx++;
1838 if (da_indx >= PHYSMAP_ENTRIES*2) {
1839 da_indx--;
1840 goto do_next;
1841 }
1842 dump_avail[da_indx++] = pa; /* start */
1843 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1844 }
1845do_next:
1846 if (full)
1847 break;
1848
984263bc
MD
1849 }
1850 }
1851 *pte = 0;
0f7a3396 1852 cpu_invltlb();
984263bc
MD
1853
1854 /*
1855 * XXX
1856 * The last chunk must contain at least one page plus the message
1857 * buffer to avoid complicating other code (message buffer address
1858 * calculation, etc.).
1859 */
1860 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1861 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1862 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1863 phys_avail[pa_indx--] = 0;
1864 phys_avail[pa_indx--] = 0;
1865 }
1866
1867 Maxmem = atop(phys_avail[pa_indx]);
1868
1869 /* Trim off space for the message buffer. */
1870 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1871
1872 avail_end = phys_avail[pa_indx];
1873}
1874
30c5f287 1875#ifdef SMP
6ceb272b 1876int ioapic_use_old = 0;
0d863fd0 1877
eac0bf8f
MD
1878#ifdef APIC_IO
1879int apic_io_enable = 1; /* Enabled by default for kernels compiled w/APIC_IO */
1880#else
1881int apic_io_enable = 0; /* Disabled by default for kernels compiled without */
1882#endif
30c5f287
MN
1883#endif
1884
30c5f287
MN
1885struct machintr_abi MachIntrABI;
1886
f7bc9806
MD
1887/*
1888 * IDT VECTORS:
1889 * 0 Divide by zero
1890 * 1 Debug
1891 * 2 NMI
1892 * 3 BreakPoint
1893 * 4 OverFlow
1894 * 5 Bound-Range
1895 * 6 Invalid OpCode
1896 * 7 Device Not Available (x87)
1897 * 8 Double-Fault
1898 * 9 Coprocessor Segment overrun (unsupported, reserved)
1899 * 10 Invalid-TSS
1900 * 11 Segment not present
1901 * 12 Stack
1902 * 13 General Protection
1903 * 14 Page Fault
1904 * 15 Reserved
1905 * 16 x87 FP Exception pending
1906 * 17 Alignment Check
1907 * 18 Machine Check
1908 * 19 SIMD floating point
1909 * 20-31 reserved
1910 * 32-255 INTn/external sources
1911 */
984263bc 1912void
17a9f566 1913init386(int first)
984263bc
MD
1914{
1915 struct gate_descriptor *gdp;
1916 int gsel_tss, metadata_missing, off, x;
85100692 1917 struct mdglobaldata *gd;
984263bc
MD
1918
1919 /*
1920 * Prevent lowering of the ipl if we call tsleep() early.
1921 */
85100692 1922 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1923 bzero(gd, sizeof(*gd));
984263bc 1924
85100692 1925 gd->mi.gd_curthread = &thread0;
4e7c41c5 1926 thread0.td_gd = &gd->mi;
984263bc
MD
1927
1928 atdevbase = ISA_HOLE_START + KERNBASE;
1929
1930 metadata_missing = 0;
1931 if (bootinfo.bi_modulep) {
1932 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1933 preload_bootstrap_relocate(KERNBASE);
1934 } else {
1935 metadata_missing = 1;
1936 }
1937 if (bootinfo.bi_envp)
1938 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1939
27af435a
SZ
1940 if (boothowto & RB_VERBOSE)
1941 bootverbose++;
1942
30c5f287 1943 /*
10db3cc6 1944 * Default MachIntrABI to ICU
30c5f287
MN
1945 */
1946 MachIntrABI = MachIntrABI_ICU;
1947#ifdef SMP
1948 TUNABLE_INT_FETCH("hw.apic_io_enable", &apic_io_enable);
0d863fd0 1949 TUNABLE_INT_FETCH("hw.ioapic_use_old", &ioapic_use_old);
30c5f287
MN
1950#endif
1951
c5cc06e3 1952 /*
b45759e1
MD
1953 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1954 * and ncpus_fit_mask remain 0.
c5cc06e3 1955 */
4e8e646b 1956 ncpus = 1;
c5cc06e3 1957 ncpus2 = 1;
b45759e1 1958 ncpus_fit = 1;
984263bc
MD
1959 /* Init basic tunables, hz etc */
1960 init_param1();
1961
1962 /*
1963 * make gdt memory segments, the code segment goes up to end of the
1964 * page with etext in it, the data segment goes to the end of
1965 * the address space
1966 */
1967 /*
1968 * XXX text protection is temporarily (?) disabled. The limit was
1969 * i386_btop(round_page(etext)) - 1.
1970 */
1971 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1972 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1973
984263bc
MD
1974 gdt_segs[GPRIV_SEL].ssd_limit =
1975 atop(sizeof(struct privatespace) - 1);
8ad65e08 1976 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1977 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1978 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1979
85100692 1980 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1981
84b592ba
MD
1982 /*
1983 * Note: on both UP and SMP curthread must be set non-NULL
1984 * early in the boot sequence because the system assumes
1985 * that 'curthread' is never NULL.
1986 */
984263bc
MD
1987
1988 for (x = 0; x < NGDT; x++) {
1989#ifdef BDE_DEBUGGER
1990 /* avoid overwriting db entries with APM ones */
1991 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1992 continue;
1993#endif
1994 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1995 }
1996
1997 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1998 r_gdt.rd_base = (int) gdt;
1999 lgdt(&r_gdt);
2000
73e4f7b9
MD
2001 mi_gdinit(&gd->mi, 0);
2002 cpu_gdinit(gd, 0);
6bf59cd2 2003 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 2004 safepri = TDPRI_MAX;
73e4f7b9 2005
984263bc
MD
2006 /* make ldt memory segments */
2007 /*
88181b08 2008 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD
2009 * should be spelled ...MAX_USER...
2010 */
88181b08
MD
2011 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
2012 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
984263bc
MD
2013 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
2014 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2015
2016 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2017 lldt(_default_ldt);
17a9f566 2018 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
2019 /* spinlocks and the BGL */
2020 init_locks();
984263bc 2021
2f839e54
MD
2022 /*
2023 * Setup the hardware exception table. Most exceptions use
2024 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
2025 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
2026 * an 'interrupt trap gate', which disables interrupts on entry,
2027 * in order to be able to poll the appropriate CRn register to
2028 * determine the fault address.
2029 */
f7bc9806
MD
2030 for (x = 0; x < NIDT; x++) {
2031#ifdef DEBUG_INTERRUPTS
2032 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2033#else
2034 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2035#endif
2036 }
984263bc
MD
2037 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2038 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2039 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2040 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2041 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2042 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2043 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2044 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2045 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2046 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2047 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2048 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2050 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2052 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
2053 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2054 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2055 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2056 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2057 setidt(0x80, &IDTVEC(int0x80_syscall),
2058 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2059
2060 r_idt.rd_limit = sizeof(idt0) - 1;
2061 r_idt.rd_base = (int) idt;
2062 lidt(&r_idt);
2063
2064 /*
2065 * Initialize the console before we print anything out.
2066 */
2067 cninit();
2068
2069 if (metadata_missing)
26be20a0 2070 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2071
984263bc 2072#if NISA >0
e24dd6e0 2073 elcr_probe();
984263bc
MD
2074 isa_defaultirq();
2075#endif
2076 rand_initialize();
2077
a3dd9120
SZ
2078 /*
2079 * Initialize IRQ mapping
2080 *
2081 * NOTE:
2082 * SHOULD be after elcr_probe()
2083 */
2084 MachIntrABI_ICU.initmap();
2085#ifdef SMP
2086 MachIntrABI_IOAPIC.initmap();
2087#endif
2088
984263bc
MD
2089#ifdef DDB
2090 kdb_init();
2091 if (boothowto & RB_KDB)
2092 Debugger("Boot flags requested debugger");
2093#endif
2094
2095 finishidentcpu(); /* Final stage of CPU initialization */
2096 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2097 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2098 initializecpu(); /* Initialize CPU registers */
2099
b7c628e4
MD
2100 /*
2101 * make an initial tss so cpu can get interrupt stack on syscall!
2102 * The 16 bytes is to save room for a VM86 context.
2103 */
17a9f566
MD
2104 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2105 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2106 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
2107 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2108 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2109 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
2110 ltr(gsel_tss);
2111
2112 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2113 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2114 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2115 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2116 dblfault_tss.tss_cr3 = (int)IdlePTD;
2117 dblfault_tss.tss_eip = (int) dblfault_handler;
2118 dblfault_tss.tss_eflags = PSL_KERNEL;
2119 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2120 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2121 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2122 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2123 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2124
2125 vm86_initialize();
2126 getmemsize(first);
2127 init_param2(physmem);
2128
2129 /* now running on new page tables, configured,and u/iom is accessible */
2130
2131 /* Map the message buffer. */
2132 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2133 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2134
2135 msgbufinit(msgbufp, MSGBUF_SIZE);
2136
2137 /* make a call gate to reenter kernel with */
2138 gdp = &ldt[LSYS5CALLS_SEL].gd;
2139
2140 x = (int) &IDTVEC(syscall);
2141 gdp->gd_looffset = x++;
2142 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2143 gdp->gd_stkcpy = 1;
2144 gdp->gd_type = SDT_SYS386CGT;
2145 gdp->gd_dpl = SEL_UPL;
2146 gdp->gd_p = 1;
2147 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2148
2149 /* XXX does this work? */
2150 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2151 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2152
2153 /* transfer to user mode */
2154
2155 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2156 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2157
2158 /* setup proc 0's pcb */
b7c628e4
MD
2159 thread0.td_pcb->pcb_flags = 0;
2160 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2161 thread0.td_pcb->pcb_ext = 0;
08f2f1bb 2162 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2163}
2164
8ad65e08 2165/*
17a9f566
MD
2166 * Initialize machine-dependant portions of the global data structure.
2167 * Note that the global data area and cpu0's idlestack in the private
2168 * data space were allocated in locore.
ef0fdad1
MD
2169 *
2170 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2171 *
2172 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2173 */
2174void
85100692 2175cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2176{
7d0bac62 2177 if (cpu)
a2a5ad0d 2178 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2179
f470d0c8
MD
2180 lwkt_init_thread(&gd->mi.gd_idlethread,
2181 gd->mi.gd_prvspace->idlestack,
d3d32139 2182 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2183 0, &gd->mi);
a2a5ad0d
MD
2184 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2185 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2186 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2187 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2188}
2189
0cd275af
MD
2190int
2191is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2192{
2193 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2194 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2195 return (TRUE);
2196 }
2197 return (FALSE);
2198}
2199
12e4aaff
MD
2200struct globaldata *
2201globaldata_find(int cpu)
2202{
2203 KKASSERT(cpu >= 0 && cpu < ncpus);
2204 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2205}
2206
984263bc
MD
2207#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2208static void f00f_hack(void *unused);
ba39e2e0 2209SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD
2210
2211static void
17a9f566
MD
2212f00f_hack(void *unused)
2213{
984263bc 2214 struct gate_descriptor *new_idt;
984263bc
MD
2215 vm_offset_t tmp;
2216
2217 if (!has_f00f_bug)
2218 return;
2219
26be20a0 2220 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD
2221
2222 r_idt.rd_limit = sizeof(idt0) - 1;
2223
e4846942 2224 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD
2225 if (tmp == 0)
2226 panic("kmem_alloc returned 0");
2227 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2228 panic("kmem_alloc returned non-page-aligned memory");
2229 /* Put the first seven entries in the lower page */
2230 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2231 bcopy(idt, new_idt, sizeof(idt0));
2232 r_idt.rd_base = (int)new_idt;
2233 lidt(&r_idt);
2234 idt = new_idt;
e4846942 2235 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD
2236 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2237 panic("vm_map_protect failed");
2238 return;
2239}
2240#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2241
2242int
08f2f1bb 2243ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2244{
08f2f1bb 2245 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD
2246 return (0);
2247}
2248
2249int
e9182c58 2250ptrace_single_step(struct lwp *lp)
984263bc 2251{
e9182c58 2252 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD
2253 return (0);
2254}
2255
984263bc 2256int
e9182c58 2257fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2258{
984263bc
MD
2259 struct trapframe *tp;
2260
e9182c58 2261 tp = lp->lwp_md.md_regs;
4e7c41c5 2262 regs->r_gs = tp->tf_gs;
984263bc
MD
2263 regs->r_fs = tp->tf_fs;
2264 regs->r_es = tp->tf_es;
2265 regs->r_ds = tp->tf_ds;
2266 regs->r_edi = tp->tf_edi;
2267 regs->r_esi = tp->tf_esi;
2268 regs->r_ebp = tp->tf_ebp;
2269 regs->r_ebx = tp->tf_ebx;
2270 regs->r_edx = tp->tf_edx;
2271 regs->r_ecx = tp->tf_ecx;
2272 regs->r_eax = tp->tf_eax;
2273 regs->r_eip = tp->tf_eip;
2274 regs->r_cs = tp->tf_cs;
2275 regs->r_eflags = tp->tf_eflags;
2276 regs->r_esp = tp->tf_esp;
2277 regs->r_ss = tp->tf_ss;
984263bc
MD
2278 return (0);
2279}
2280
2281int
e9182c58 2282set_regs(struct lwp *lp, struct reg *regs)
984263bc 2283{
984263bc
MD
2284 struct trapframe *tp;
2285
e9182c58 2286 tp = lp->lwp_md.md_regs;
984263bc
MD
2287 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2288 !CS_SECURE(regs->r_cs))
2289 return (EINVAL);
4e7c41c5 2290 tp->tf_gs = regs->r_gs;
984263bc
MD
2291 tp->tf_fs = regs->r_fs;
2292 tp->tf_es = regs->r_es;
2293 tp->tf_ds = regs->r_ds;
2294 tp->tf_edi = regs->r_edi;
2295 tp->tf_esi = regs->r_esi;
2296 tp->tf_ebp = regs->r_ebp;
2297 tp->tf_ebx = regs->r_ebx;
2298 tp->tf_edx = regs->r_edx;
2299 tp->tf_ecx = regs->r_ecx;
2300 tp->tf_eax = regs->r_eax;
2301 tp->tf_eip = regs->r_eip;
2302 tp->tf_cs = regs->r_cs;
2303 tp->tf_eflags = regs->r_eflags;
2304 tp->tf_esp = regs->r_esp;
2305 tp->tf_ss = regs->r_ss;
984263bc
MD
2306 return (0);
2307}
2308
642a6e88 2309#ifndef CPU_DISABLE_SSE
984263bc 2310static void
f123d5a1 2311fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2312{
c9faf524
RG
2313 struct env87 *penv_87 = &sv_87->sv_env;
2314 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2315 int i;
2316
2317 /* FPU control/status */
2318 penv_87->en_cw = penv_xmm->en_cw;
2319 penv_87->en_sw = penv_xmm->en_sw;
2320 penv_87->en_tw = penv_xmm->en_tw;
2321 penv_87->en_fip = penv_xmm->en_fip;
2322 penv_87->en_fcs = penv_xmm->en_fcs;
2323 penv_87->en_opcode = penv_xmm->en_opcode;
2324 penv_87->en_foo = penv_xmm->en_foo;
2325 penv_87->en_fos = penv_xmm->en_fos;
2326
2327 /* FPU registers */
2328 for (i = 0; i < 8; ++i)
2329 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD
2330}
2331
2332static void
f123d5a1 2333set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2334{
c9faf524
RG
2335 struct env87 *penv_87 = &sv_87->sv_env;
2336 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2337 int i;
2338
2339 /* FPU control/status */
2340 penv_xmm->en_cw = penv_87->en_cw;
2341 penv_xmm->en_sw = penv_87->en_sw;
2342 penv_xmm->en_tw = penv_87->en_tw;
2343 penv_xmm->en_fip = penv_87->en_fip;
2344 penv_xmm->en_fcs = penv_87->en_fcs;
2345 penv_xmm->en_opcode = penv_87->en_opcode;
2346 penv_xmm->en_foo = penv_87->en_foo;
2347 penv_xmm->en_fos = penv_87->en_fos;
2348
2349 /* FPU registers */
2350 for (i = 0; i < 8; ++i)
2351 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2352}
642a6e88 2353#endif /* CPU_DISABLE_SSE */
984263bc
MD
2354
2355int
e9182c58 2356fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2357{
642a6e88 2358#ifndef CPU_DISABLE_SSE
984263bc 2359 if (cpu_fxsr) {
e9182c58
SZ
2360 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2361 (struct save87 *)fpregs);
984263bc
MD
2362 return (0);
2363 }
642a6e88 2364#endif /* CPU_DISABLE_SSE */
e9182c58 2365 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2366 return (0);
2367}
2368
2369int
e9182c58 2370set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2371{
642a6e88 2372#ifndef CPU_DISABLE_SSE
984263bc
MD
2373 if (cpu_fxsr) {
2374 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2375 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2376 return (0);
2377 }
642a6e88 2378#endif /* CPU_DISABLE_SSE */
e9182c58 2379 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2380 return (0);
2381}
2382
2383int
e9182c58 2384fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2385{
e9182c58 2386 if (lp == NULL) {
984263bc
MD
2387 dbregs->dr0 = rdr0();
2388 dbregs->dr1 = rdr1();
2389 dbregs->dr2 = rdr2();
2390 dbregs->dr3 = rdr3();
2391 dbregs->dr4 = rdr4();
2392 dbregs->dr5 = rdr5();
2393 dbregs->dr6 = rdr6();
2394 dbregs->dr7 = rdr7();
e9182c58
SZ
2395 } else {
2396 struct pcb *pcb;
2397
2398 pcb = lp->lwp_thread->td_pcb;
984263bc
MD
2399 dbregs->dr0 = pcb->pcb_dr0;
2400 dbregs->dr1 = pcb->pcb_dr1;
2401 dbregs->dr2 = pcb->pcb_dr2;
2402 dbregs->dr3 = pcb->pcb_dr3;
2403 dbregs->dr4 = 0;
2404 dbregs->dr5 = 0;
2405 dbregs->dr6 = pcb->pcb_dr6;
2406 dbregs->dr7 = pcb->pcb_dr7;
2407 }
2408 return (0);
2409}
2410
2411int
e9182c58 2412set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2413{
e9182c58 2414 if (lp == NULL) {
984263bc
MD
2415 load_dr0(dbregs->dr0);
2416 load_dr1(dbregs->dr1);
2417 load_dr2(dbregs->dr2);
2418 load_dr3(dbregs->dr3);
2419 load_dr4(dbregs->dr4);
2420 load_dr5(dbregs->dr5);
2421 load_dr6(dbregs->dr6);
2422 load_dr7(dbregs->dr7);
e9182c58
SZ
2423 } else {
2424 struct pcb *pcb;
2425 struct ucred *ucred;
2426 int i;
2427 uint32_t mask1, mask2;
2428
984263bc
MD
2429 /*
2430 * Don't let an illegal value for dr7 get set. Specifically,
2431 * check for undefined settings. Setting these bit patterns
2432 * result in undefined behaviour and can lead to an unexpected
2433 * TRCTRAP.
2434 */
2435 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2436 i++, mask1 <<= 2, mask2 <<= 2)
2437 if ((dbregs->dr7 & mask1) == mask2)
2438 return (EINVAL);
2439
e9182c58
SZ
2440 pcb = lp->lwp_thread->td_pcb;
2441 ucred = lp->lwp_proc->p_ucred;
2442
984263bc
MD
2443 /*
2444 * Don't let a process set a breakpoint that is not within the
2445 * process's address space. If a process could do this, it
2446 * could halt the system by setting a breakpoint in the kernel
2447 * (if ddb was enabled). Thus, we need to check to make sure
2448 * that no breakpoints are being enabled for addresses outside
2449 * process's address space, unless, perhaps, we were called by
2450 * uid 0.
2451 *
2452 * XXX - what about when the watched area of the user's
2453 * address space is written into from within the kernel
2454 * ... wouldn't that still cause a breakpoint to be generated
2455 * from within kernel mode?
2456 */
e9182c58 2457
895c1f85 2458 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD
2459 if (dbregs->dr7 & 0x3) {
2460 /* dr0 is enabled */
88181b08 2461 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2462 return (EINVAL);
2463 }
e9182c58 2464
984263bc
MD
2465 if (dbregs->dr7 & (0x3<<2)) {
2466 /* dr1 is enabled */
88181b08 2467 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2468 return (EINVAL);
2469 }
e9182c58 2470
984263bc
MD
2471 if (dbregs->dr7 & (0x3<<4)) {
2472 /* dr2 is enabled */
88181b08 2473 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2474 return (EINVAL);
2475 }
e9182c58 2476
984263bc
MD
2477 if (dbregs->dr7 & (0x3<<6)) {
2478 /* dr3 is enabled */
88181b08 2479 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2480 return (EINVAL);
2481 }
2482 }
e9182c58 2483
984263bc
MD
2484 pcb->pcb_dr0 = dbregs->dr0;
2485 pcb->pcb_dr1 = dbregs->dr1;
2486 pcb->pcb_dr2 = dbregs->dr2;
2487 pcb->pcb_dr3 = dbregs->dr3;
2488 pcb->pcb_dr6 = dbregs->dr6;
2489 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2490
984263bc
MD
2491 pcb->pcb_flags |= PCB_DBREGS;
2492 }
2493
2494 return (0);
2495}
2496
2497/*
2498 * Return > 0 if a hardware breakpoint has been hit, and the
2499 * breakpoint was in user space. Return 0, otherwise.
2500 */
2501int
2502user_dbreg_trap(void)
2503{
2504 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2505 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2506 int nbp; /* number of breakpoints that triggered */
2507 caddr_t addr[4]; /* breakpoint addresses */
2508 int i;
2509
2510 dr7 = rdr7();
2511 if ((dr7 & 0x000000ff) == 0) {
2512 /*
2513 * all GE and LE bits in the dr7 register are zero,
2514 * thus the trap couldn't have been caused by the
2515 * hardware debug registers
2516 */
2517 return 0;
2518 }
2519
2520 nbp = 0;
2521 dr6 = rdr6();
2522 bp = dr6 & 0x0000000f;
2523
2524 if (!bp) {
2525 /*
2526 * None of the breakpoint bits are set meaning this
2527 * trap was not caused by any of the debug registers
2528 */
2529 return 0;
2530 }
2531
2532 /*
2533 * at least one of the breakpoints were hit, check to see
2534 * which ones and if any of them are user space addresses
2535 */
2536
2537 if (bp & 0x01) {
2538 addr[nbp++] = (caddr_t)rdr0();
2539 }
2540 if (bp & 0x02) {
2541 addr[nbp++] = (caddr_t)rdr1();
2542 }
2543 if (bp & 0x04) {
2544 addr[nbp++] = (caddr_t)rdr2();
2545 }
2546 if (bp & 0x08) {
2547 addr[nbp++] = (caddr_t)rdr3();
2548 }
2549
2550 for (i=0; i<nbp; i++) {
2551 if (addr[i] <
88181b08 2552 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD
2553 /*
2554 * addr[i] is in user space
2555 */
2556 return nbp;
2557 }
2558 }
2559
2560 /*
2561 * None of the breakpoints are in user space.
2562 */
2563 return 0;
2564}
2565
2566
2567#ifndef DDB
2568void
2569Debugger(const char *msg)
2570{
26be20a0 2571 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD
2572}
2573#endif /* no DDB */
2574
984263bc
MD
2575#ifdef DDB
2576
2577/*
2578 * Provide inb() and outb() as functions. They are normally only
2579 * available as macros calling inlined functions, thus cannot be
2580 * called inside DDB.
2581 *
2582 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2583 */
2584
2585#undef inb
2586#undef outb
2587
2588/* silence compiler warnings */
2589u_char inb(u_int);
2590void outb(u_int, u_char);
2591
2592u_char
2593inb(u_int port)
2594{
2595 u_char data;
2596 /*
2597 * We use %%dx and not %1 here because i/o is done at %dx and not at
2598 * %edx, while gcc generates inferior code (movw instead of movl)
2599 * if we tell it to load (u_short) port.
2600 */
2601 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2602 return (data);
2603}
2604
2605void
2606outb(u_int port, u_char data)
2607{
2608 u_char al;
2609 /*
2610 * Use an unnecessary assignment to help gcc's register allocator.
2611 * This make a large difference for gcc-1.40 and a tiny difference
2612 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2613 * best results. gcc-2.6.0 can't handle this.
2614 */
2615 al = data;
2616 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2617}
2618
2619#endif /* DDB */
8a8d5d85
MD
2620
2621
2622
2623#include "opt_cpu.h"
8a8d5d85
MD
2624
2625
2626/*
2627 * initialize all the SMP locks
2628 */
2629
97359a5b 2630/* critical region when masking or unmasking interupts */
b1af91cb 2631struct spinlock_deprecated imen_spinlock;
8a8d5d85 2632
8a8d5d85 2633/* critical region for old style disable_intr/enable_intr */
b1af91cb 2634struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2635
2636/* critical region around INTR() routines */
b1af91cb 2637struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2638
2639/* lock region used by kernel profiling */
b1af91cb 2640struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2641
2642/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2643struct spinlock_deprecated com_spinlock;
8a8d5d85 2644
8a8d5d85 2645/* lock regions around the clock hardware */
b1af91cb 2646struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2647
2648/* lock around the MP rendezvous */
b1af91cb 2649struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2650
2651static void
2652init_locks(void)
2653{
b5d16701 2654#ifdef SMP
8a8d5d85 2655 /*
b5d16701 2656 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD
2657 * This uses a LOGICAL cpu ID, ie BSP == 0.
2658 */
8a8d5d85
MD
2659 cpu_get_initial_mplock();
2660#endif
41a01a4d 2661 /* DEPRECATED */
8a8d5d85 2662 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD
2663 spin_lock_init(&intr_spinlock);
2664 spin_lock_init(&mpintr_spinlock);
2665 spin_lock_init(&imen_spinlock);
2666 spin_lock_init(&smp_rv_spinlock);
2667 spin_lock_init(&com_spinlock);
2668 spin_lock_init(&clock_spinlock);
41a01a4d
MD
2669
2670 /* our token pool needs to work early */
2671 lwkt_token_pool_init();
8a8d5d85 2672}