elcr: File relocate
[dragonfly.git] / sys / platform / pc64 / icu / icu_abi.c
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1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2005,2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * $DragonFly: src/sys/platform/pc64/icu/icu_abi.c,v 1.1 2008/08/29 17:07:16 dillon Exp $
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
57a9c56b 51#include <machine/intr_machdep.h>
c8fe38ae 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
56
7265a4fe 57#include <machine_base/icu/elcr_var.h>
9e0e3f85 58
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59#include <machine_base/icu/icu.h>
60#include <machine_base/icu/icu_ipl.h>
c8fe38ae 61
c8fe38ae 62extern inthand_t
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63 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
64 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
65 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
66 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
67 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
68 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
69 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
70 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
c8fe38ae 71
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72static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
73 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
74 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
75 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
76 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
77 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
78 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
79 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
80 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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81};
82
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83static struct icu_irqmap {
84 int im_type; /* ICU_IMT_ */
85 enum intr_trigger im_trig;
86} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
87
88#define ICU_IMT_UNUSED 0 /* KEEP THIS */
89#define ICU_IMT_RESERVED 1
90#define ICU_IMT_LINE 2
474ba684 91#define ICU_IMT_SYSCALL 3
a3dd9120 92
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93extern void ICU_INTREN(int);
94extern void ICU_INTRDIS(int);
95
96static int icu_vectorctl(int, int, int);
97static int icu_setvar(int, const void *);
98static int icu_getvar(int, void *);
99static void icu_finalize(void);
100static void icu_cleanup(void);
101static void icu_setdefault(void);
7bf5fa56 102static void icu_stabilize(void);
a3dd9120 103static void icu_initmap(void);
d1ae7328 104static void icu_intr_config(int, enum intr_trigger, enum intr_polarity);
10db3cc6 105
faaf4131 106struct machintr_abi MachIntrABI_ICU = {
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107 MACHINTR_ICU,
108 .intrdis = ICU_INTRDIS,
109 .intren = ICU_INTREN,
110 .vectorctl = icu_vectorctl,
111 .setvar = icu_setvar,
112 .getvar = icu_getvar,
113 .finalize = icu_finalize,
10db3cc6 114 .cleanup = icu_cleanup,
7bf5fa56 115 .setdefault = icu_setdefault,
a3dd9120 116 .stabilize = icu_stabilize,
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117 .initmap = icu_initmap,
118 .intr_config = icu_intr_config
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119};
120
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121/*
122 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
123 */
339478ac 124static int
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125icu_setvar(int varid, const void *buf)
126{
9d758cc4 127 return ENOENT;
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128}
129
339478ac 130static int
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131icu_getvar(int varid, void *buf)
132{
9d758cc4 133 return ENOENT;
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134}
135
136/*
137 * Called before interrupts are physically enabled
138 */
139static void
7bf5fa56 140icu_stabilize(void)
c8fe38ae 141{
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142 int intr;
143
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144 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
145 machintr_intrdis(intr);
146 machintr_intren(ICU_IRQ_SLAVE);
147}
148
149/*
150 * Called after interrupts physically enabled but before the
151 * critical section is released.
152 */
153static void
154icu_cleanup(void)
155{
156 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
157}
158
159/*
160 * Called after stablize and cleanup; critical section is not
161 * held and interrupts are not physically disabled.
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162 */
163static void
164icu_finalize(void)
165{
166 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
167
10db3cc6 168#ifdef SMP
e0918665 169 KKASSERT(!apic_io_enable);
339478ac 170
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171 /*
172 * If an IMCR is present, programming bit 0 disconnects the 8259
173 * from the BSP. The 8259 may still be connected to LINT0 on the
174 * BSP's LAPIC.
175 *
176 * If we are running SMP the LAPIC is active, try to use virtual
177 * wire mode so we can use other interrupt sources within the LAPIC
178 * in addition to the 8259.
179 */
9d758cc4 180 if (imcr_present) {
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181 outb(0x22, 0x70);
182 outb(0x23, 0x01);
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183 }
184#endif /* SMP */
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185}
186
339478ac 187static int
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188icu_vectorctl(int op, int intr, int flags)
189{
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190 int error;
191 register_t ef;
192
193 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
194 return EINVAL;
195
196 ef = read_rflags();
197 cpu_disable_intr();
198 error = 0;
199
200 switch(op) {
201 case MACHINTR_VECTOR_SETUP:
35e45e47 202 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
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203 SEL_KPL, 0);
204 machintr_intren(intr);
205 break;
206
207 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 208 machintr_intrdis(intr);
35e45e47 209 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
339478ac 210 SEL_KPL, 0);
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211 break;
212
213 default:
214 error = EOPNOTSUPP;
215 break;
216 }
217 write_rflags(ef);
218 return error;
c8fe38ae 219}
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220
221static void
222icu_setdefault(void)
223{
224 int intr;
225
226 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
227 if (intr == ICU_IRQ_SLAVE)
228 continue;
229 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
230 SEL_KPL, 0);
231 }
232}
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233
234static void
235icu_initmap(void)
236{
237 int i;
238
239 for (i = 0; i < ICU_HWI_VECTORS; ++i)
240 icu_irqmaps[i].im_type = ICU_IMT_LINE;
241 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
242
243 if (elcr_found) {
244 for (i = 0; i < ICU_HWI_VECTORS; ++i)
245 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
246 } else {
247 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
248 switch (i) {
249 case 0:
250 case 1:
251 case 2:
252 case 8:
253 case 13:
254 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
255 break;
256
257 default:
258 icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
259 break;
260 }
261 }
262 }
08c05167 263 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
a3dd9120 264}
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265
266static void
267icu_intr_config(int irq __unused, enum intr_trigger trig __unused,
268 enum intr_polarity pola __unused)
269{
270}