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bce: Add workaround for the lost of MSI on 5706/5708
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
CommitLineData
43c2aeb0
SZ		 1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
43c2aeb0
SZ		 31 */
32
33/*
34 * The following controllers are supported by this driver:
35 * BCM5706C A2, A3
d0092544 36 * BCM5706S A2, A3
43c2aeb0 37 * BCM5708C B1, B2
d0092544
SZ		 38 * BCM5708S B1, B2
39 * BCM5709C A1, C0
40 * BCM5716 C0
43c2aeb0
SZ		 41 *
42 * The following controllers are not supported by this driver:
43 * BCM5706C A0, A1
d0092544 44 * BCM5706S A0, A1
43c2aeb0 45 * BCM5708C A0, B0
d0092544
SZ		 46 * BCM5708S A0, B0
47 * BCM5709C A0, B0, B1
48 * BCM5709S A0, A1, B0, B1, B2, C0
43c2aeb0
SZ		 49 */
50
51#include "opt_bce.h"
52#include "opt_polling.h"
53
54#include <sys/param.h>
55#include <sys/bus.h>
56#include <sys/endian.h>
57#include <sys/kernel.h>
9db4b353 58#include <sys/interrupt.h>
43c2aeb0
SZ		 59#include <sys/mbuf.h>
60#include <sys/malloc.h>
61#include <sys/queue.h>
62#ifdef BCE_DEBUG
63#include <sys/random.h>
64#endif
65#include <sys/rman.h>
66#include <sys/serialize.h>
67#include <sys/socket.h>
68#include <sys/sockio.h>
69#include <sys/sysctl.h>
70
71#include <net/bpf.h>
72#include <net/ethernet.h>
73#include <net/if.h>
74#include <net/if_arp.h>
75#include <net/if_dl.h>
76#include <net/if_media.h>
77#include <net/if_types.h>
78#include <net/ifq_var.h>
79#include <net/vlan/if_vlan_var.h>
b637f170 80#include <net/vlan/if_vlan_ether.h>
43c2aeb0
SZ		 81
82#include <dev/netif/mii_layer/mii.h>
83#include <dev/netif/mii_layer/miivar.h>
84
85#include <bus/pci/pcireg.h>
86#include <bus/pci/pcivar.h>
87
88#include "miibus_if.h"
89
9382dc55
SZ		 90#include <dev/netif/bce/if_bcereg.h>
91#include <dev/netif/bce/if_bcefw.h>
43c2aeb0
SZ		 92
93/****************************************************************************/
94/* BCE Debug Options */
95/****************************************************************************/
96#ifdef BCE_DEBUG
97
98static uint32_t bce_debug = BCE_WARN;
99
100/*
101 * 0 = Never
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
107 * 268435456 = 1 in 8
108 * 536870912 = 1 in 4
109 * 1073741824 = 1 in 2
110 *
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
113 *
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
116 *
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
119 *
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
122 *
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
125 */
126static int bce_debug_l2fhdr_status_check = 0;
127static int bce_debug_unexpected_attention = 0;
128static int bce_debug_mbuf_allocation_failure = 0;
129static int bce_debug_dma_map_addr_failure = 0;
130static int bce_debug_bootcode_running_failure = 0;
131
132#endif /* BCE_DEBUG */
133
134
135/****************************************************************************/
136/* PCI Device ID Table */
137/* */
138/* Used by bce_probe() to identify the devices supported by this driver. */
139/****************************************************************************/
140#define BCE_DEVDESC_MAX 64
141
142static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
3482f06c
SZ		 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
43c2aeb0
SZ		 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
154
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
160
161 /* BCM5708C controllers and OEM boards. */
3482f06c
SZ		 162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
43c2aeb0
SZ		 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
170
171 /* BCM5708S controllers and OEM boards. */
3482f06c
SZ		 172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
43c2aeb0
SZ		 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
d0092544
SZ		 180
181 /* BCM5709C controllers and OEM boards. */
3482f06c
SZ		 182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
d0092544
SZ		 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
188
189 /* BCM5709S controllers and OEM boards. */
3482f06c
SZ		 190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
d0092544
SZ		 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
196
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
200
43c2aeb0
SZ		 201 { 0, 0, 0, 0, NULL }
202};
203
204
205/****************************************************************************/
206/* Supported Flash NVRAM device data. */
207/****************************************************************************/
208static const struct flash_spec flash_table[] =
209{
d0092544
SZ		 210#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211#define NONBUFFERED_FLAGS (BCE_NV_WREN)
212
43c2aeb0
SZ		 213 /* Slow EEPROM */
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
43c2aeb0
SZ		 216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217 "EEPROM - slow"},
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 "Entry 0001"},
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239 "Entry 0100"},
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
256 /* Fast EEPROM */
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
43c2aeb0
SZ		 259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
260 "EEPROM - fast"},
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265 "Entry 1001"},
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270 "Entry 1010"},
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280 "Entry 1100"},
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285 "Entry 1101"},
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
43c2aeb0
SZ		 294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
296};
297
d0092544
SZ		 298/*
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
303 * driver.
304 */
305static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
312};
313
43c2aeb0
SZ		 314
315/****************************************************************************/
316/* DragonFly device entry points. */
317/****************************************************************************/
318static int bce_probe(device_t);
319static int bce_attach(device_t);
320static int bce_detach(device_t);
321static void bce_shutdown(device_t);
322
323/****************************************************************************/
324/* BCE Debug Data Structure Dump Routines */
325/****************************************************************************/
326#ifdef BCE_DEBUG
327static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334static void bce_dump_tx_chain(struct bce_softc *, int, int);
335static void bce_dump_rx_chain(struct bce_softc *, int, int);
336static void bce_dump_status_block(struct bce_softc *);
337static void bce_dump_driver_state(struct bce_softc *);
338static void bce_dump_stats_block(struct bce_softc *) __unused;
339static void bce_dump_hw_state(struct bce_softc *);
340static void bce_dump_txp_state(struct bce_softc *);
341static void bce_dump_rxp_state(struct bce_softc *) __unused;
342static void bce_dump_tpat_state(struct bce_softc *) __unused;
343static void bce_freeze_controller(struct bce_softc *) __unused;
344static void bce_unfreeze_controller(struct bce_softc *) __unused;
345static void bce_breakpoint(struct bce_softc *);
346#endif /* BCE_DEBUG */
347
348
349/****************************************************************************/
350/* BCE Register/Memory Access Routines */
351/****************************************************************************/
352static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
bc30d40d
SZ		 354static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355static uint32_t bce_shmem_rd(struct bce_softc *, u32);
43c2aeb0
SZ		 356static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357static int bce_miibus_read_reg(device_t, int, int);
358static int bce_miibus_write_reg(device_t, int, int, int);
359static void bce_miibus_statchg(device_t);
360
361
362/****************************************************************************/
363/* BCE NVRAM Access Routines */
364/****************************************************************************/
365static int bce_acquire_nvram_lock(struct bce_softc *);
366static int bce_release_nvram_lock(struct bce_softc *);
367static void bce_enable_nvram_access(struct bce_softc *);
368static void bce_disable_nvram_access(struct bce_softc *);
369static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
370 uint32_t);
371static int bce_init_nvram(struct bce_softc *);
372static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373static int bce_nvram_test(struct bce_softc *);
43c2aeb0
SZ		 374
375/****************************************************************************/
376/* BCE DMA Allocate/Free Routines */
377/****************************************************************************/
378static int bce_dma_alloc(struct bce_softc *);
379static void bce_dma_free(struct bce_softc *);
380static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
43c2aeb0
SZ		 381
382/****************************************************************************/
383/* BCE Firmware Synchronization and Load */
384/****************************************************************************/
385static int bce_fw_sync(struct bce_softc *, uint32_t);
386static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
387 uint32_t, uint32_t);
388static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
389 struct fw_info *);
5d05a208
SZ		 390static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392static void bce_start_rxp_cpu(struct bce_softc *);
d0092544
SZ		 393static void bce_init_rxp_cpu(struct bce_softc *);
394static void bce_init_txp_cpu(struct bce_softc *);
395static void bce_init_tpat_cpu(struct bce_softc *);
396static void bce_init_cp_cpu(struct bce_softc *);
397static void bce_init_com_cpu(struct bce_softc *);
43c2aeb0
SZ		 398static void bce_init_cpus(struct bce_softc *);
399
400static void bce_stop(struct bce_softc *);
401static int bce_reset(struct bce_softc *, uint32_t);
402static int bce_chipinit(struct bce_softc *);
403static int bce_blockinit(struct bce_softc *);
c36fd9ee
SZ		 404static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
405 uint32_t *, int);
314a2fcc 406static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
d0092544
SZ		 407static void bce_probe_pci_caps(struct bce_softc *);
408static void bce_print_adapter_info(struct bce_softc *);
409static void bce_get_media(struct bce_softc *);
43c2aeb0 410
d0092544 411static void bce_init_tx_context(struct bce_softc *);
43c2aeb0 412static int bce_init_tx_chain(struct bce_softc *);
d0092544 413static void bce_init_rx_context(struct bce_softc *);
43c2aeb0
SZ		 414static int bce_init_rx_chain(struct bce_softc *);
415static void bce_free_rx_chain(struct bce_softc *);
416static void bce_free_tx_chain(struct bce_softc *);
417
418static int bce_encap(struct bce_softc *, struct mbuf **);
419static void bce_start(struct ifnet *);
420static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421static void bce_watchdog(struct ifnet *);
422static int bce_ifmedia_upd(struct ifnet *);
423static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424static void bce_init(void *);
425static void bce_mgmt_init(struct bce_softc *);
426
5b609aa3 427static int bce_init_ctx(struct bce_softc *);
43c2aeb0
SZ		 428static void bce_get_mac_addr(struct bce_softc *);
429static void bce_set_mac_addr(struct bce_softc *);
430static void bce_phy_intr(struct bce_softc *);
431static void bce_rx_intr(struct bce_softc *, int);
432static void bce_tx_intr(struct bce_softc *);
433static void bce_disable_intr(struct bce_softc *);
d0092544 434static void bce_enable_intr(struct bce_softc *, int);
43c2aeb0
SZ		 435
436#ifdef DEVICE_POLLING
437static void bce_poll(struct ifnet *, enum poll_cmd, int);
438#endif
eac57ffb
SZ		 439static void bce_intr(struct bce_softc *);
440static void bce_intr_legacy(void *);
441static void bce_intr_msi(void *);
442static void bce_intr_msi_oneshot(void *);
43c2aeb0
SZ		 443static void bce_set_rx_mode(struct bce_softc *);
444static void bce_stats_update(struct bce_softc *);
445static void bce_tick(void *);
446static void bce_tick_serialized(struct bce_softc *);
d0092544 447static void bce_pulse(void *);
733403d6 448static void bce_pulse_check_msi(struct bce_softc *);
43c2aeb0
SZ		 449static void bce_add_sysctls(struct bce_softc *);
450
bdeb8fff
SZ		 451static void bce_coal_change(struct bce_softc *);
452static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
453static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
454static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
455static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
456static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
457static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
458static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
459static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
460static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
461 uint32_t *, uint32_t);
462
3fb4bb6c
SZ		 463/*
464 * NOTE:
465 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
466 * takes 1023 as the TX ticks limit. However, using 1023 will
467 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
468 * there is _no_ network activity on the NIC.
3fb4bb6c
SZ		 469 */
470static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
471static uint32_t bce_tx_bds = 255; /* bcm: 20 */
472static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
473static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
1af951ab
SZ		 474static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
475static uint32_t bce_rx_bds = 128; /* bcm: 6 */
476static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
477static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
bdeb8fff 478
83ce3dce
SZ		 479static int bce_msi_enable = 1;
480
bdeb8fff
SZ		 481TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
482TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
483TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
484TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
485TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
486TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
487TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
488TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
83ce3dce 489TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
43c2aeb0
SZ		 490
491/****************************************************************************/
492/* DragonFly device dispatch table. */
493/****************************************************************************/
494static device_method_t bce_methods[] = {
495 /* Device interface */
496 DEVMETHOD(device_probe, bce_probe),
497 DEVMETHOD(device_attach, bce_attach),
498 DEVMETHOD(device_detach, bce_detach),
499 DEVMETHOD(device_shutdown, bce_shutdown),
500
501 /* bus interface */
502 DEVMETHOD(bus_print_child, bus_generic_print_child),
503 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
504
505 /* MII interface */
506 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
507 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
508 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
509
510 { 0, 0 }
511};
512
513static driver_t bce_driver = {
514 "bce",
515 bce_methods,
516 sizeof(struct bce_softc)
517};
518
519static devclass_t bce_devclass;
520
43c2aeb0 521
d0092544 522DECLARE_DUMMY_MODULE(if_bce);
1be78fa8 523MODULE_DEPEND(bce, miibus, 1, 1, 1);
aa2b9d05
SW		 524DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
525DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
43c2aeb0
SZ		 526
527
528/****************************************************************************/
529/* Device probe function. */
530/* */
531/* Compares the device to the driver's list of supported devices and */
532/* reports back to the OS whether this is the right driver for the device. */
533/* */
534/* Returns: */
535/* BUS_PROBE_DEFAULT on success, positive value on failure. */
536/****************************************************************************/
537static int
538bce_probe(device_t dev)
539{
540 struct bce_type *t;
541 uint16_t vid, did, svid, sdid;
542
543 /* Get the data for the device to be probed. */
544 vid = pci_get_vendor(dev);
545 did = pci_get_device(dev);
546 svid = pci_get_subvendor(dev);
547 sdid = pci_get_subdevice(dev);
548
549 /* Look through the list of known devices for a match. */
550 for (t = bce_devs; t->bce_name != NULL; ++t) {
551 if (vid == t->bce_vid && did == t->bce_did &&
552 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
553 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
554 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
555 char *descbuf;
556
557 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
558
559 /* Print out the device identity. */
560 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
561 t->bce_name,
562 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
563
564 device_set_desc_copy(dev, descbuf);
565 kfree(descbuf, M_TEMP);
566 return 0;
567 }
568 }
569 return ENXIO;
570}
571
572
573/****************************************************************************/
d0092544
SZ		 574/* PCI Capabilities Probe Function. */
575/* */
576/* Walks the PCI capabiites list for the device to find what features are */
577/* supported. */
578/* */
579/* Returns: */
580/* None. */
581/****************************************************************************/
582static void
583bce_print_adapter_info(struct bce_softc *sc)
584{
585 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
586
587 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
588 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
589
590 /* Bus info. */
591 if (sc->bce_flags & BCE_PCIE_FLAG) {
592 kprintf("Bus (PCIe x%d, ", sc->link_width);
593 switch (sc->link_speed) {
594 case 1:
595 kprintf("2.5Gbps); ");
596 break;
597 case 2:
598 kprintf("5Gbps); ");
599 break;
600 default:
601 kprintf("Unknown link speed); ");
602 break;
603 }
604 } else {
605 kprintf("Bus (PCI%s, %s, %dMHz); ",
606 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
607 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
608 sc->bus_speed_mhz);
609 }
610
611 /* Firmware version and device features. */
bc30d40d 612 kprintf("B/C (%s)", sc->bce_bc_ver);
cff16e71
SZ		 613
614 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
615 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
616 kprintf("; Flags(");
617 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
bc30d40d 618 kprintf("MFW[%s]", sc->bce_mfw_ver);
cff16e71
SZ		 619 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
620 kprintf(" 2.5G");
621 kprintf(")");
622 }
623 kprintf("\n");
d0092544
SZ		 624}
625
626
627/****************************************************************************/
628/* PCI Capabilities Probe Function. */
629/* */
630/* Walks the PCI capabiites list for the device to find what features are */
631/* supported. */
632/* */
633/* Returns: */
634/* None. */
635/****************************************************************************/
636static void
637bce_probe_pci_caps(struct bce_softc *sc)
638{
639 device_t dev = sc->bce_dev;
640 uint8_t ptr;
641
642 if (pci_is_pcix(dev))
643 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
644
645 ptr = pci_get_pciecap_ptr(dev);
646 if (ptr) {
647 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
648
649 sc->link_speed = link_status & 0xf;
650 sc->link_width = (link_status >> 4) & 0x3f;
651 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
652 sc->bce_flags |= BCE_PCIE_FLAG;
653 }
654}
655
656
657/****************************************************************************/
43c2aeb0
SZ		 658/* Device attach function. */
659/* */
660/* Allocates device resources, performs secondary chip identification, */
661/* resets and initializes the hardware, and initializes driver instance */
662/* variables. */
663/* */
664/* Returns: */
665/* 0 on success, positive value on failure. */
666/****************************************************************************/
667static int
668bce_attach(device_t dev)
669{
670 struct bce_softc *sc = device_get_softc(dev);
671 struct ifnet *ifp = &sc->arpcom.ac_if;
672 uint32_t val;
83ce3dce 673 u_int irq_flags;
eac57ffb 674 void (*irq_handle)(void *);
7fb43956 675 int rid, rc = 0;
bc30d40d 676 int i, j;
43c2aeb0
SZ		 677
678 sc->bce_dev = dev;
679 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
680
681 pci_enable_busmaster(dev);
682
d0092544
SZ		 683 bce_probe_pci_caps(sc);
684
43c2aeb0
SZ		 685 /* Allocate PCI memory resources. */
686 rid = PCIR_BAR(0);
687 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
688 RF_ACTIVE | PCI_RF_DENSE);
689 if (sc->bce_res_mem == NULL) {
690 device_printf(dev, "PCI memory allocation failed\n");
691 return ENXIO;
692 }
693 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
694 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
695
696 /* Allocate PCI IRQ resources. */
7fb43956
SZ		 697 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
698 &sc->bce_irq_rid, &irq_flags);
83ce3dce
SZ		 699
700 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
701 &sc->bce_irq_rid, irq_flags);
43c2aeb0
SZ		 702 if (sc->bce_res_irq == NULL) {
703 device_printf(dev, "PCI map interrupt failed\n");
704 rc = ENXIO;
705 goto fail;
706 }
707
708 /*
709 * Configure byte swap and enable indirect register access.
710 * Rely on CPU to do target byte swapping on big endian systems.
711 * Access to registers outside of PCI configurtion space are not
712 * valid until this is done.
713 */
714 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
715 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
716 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
717
718 /* Save ASIC revsion info. */
719 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
720
721 /* Weed out any non-production controller revisions. */
bc30d40d 722 switch (BCE_CHIP_ID(sc)) {
43c2aeb0
SZ		 723 case BCE_CHIP_ID_5706_A0:
724 case BCE_CHIP_ID_5706_A1:
725 case BCE_CHIP_ID_5708_A0:
726 case BCE_CHIP_ID_5708_B0:
d0092544
SZ		 727 case BCE_CHIP_ID_5709_A0:
728 case BCE_CHIP_ID_5709_B0:
729 case BCE_CHIP_ID_5709_B1:
730#ifdef foo
731 /* 5709C B2 seems to work fine */
732 case BCE_CHIP_ID_5709_B2:
733#endif
43c2aeb0
SZ		 734 device_printf(dev, "Unsupported chip id 0x%08x!\n",
735 BCE_CHIP_ID(sc));
736 rc = ENODEV;
737 goto fail;
738 }
739
eac57ffb
SZ		 740 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
741 irq_handle = bce_intr_legacy;
742 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
743 irq_handle = bce_intr_msi;
744 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
745 irq_handle = bce_intr_msi_oneshot;
746 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
747 }
748 } else {
749 panic("%s: unsupported intr type %d\n",
750 device_get_nameunit(dev), sc->bce_irq_type);
751 }
752
43c2aeb0
SZ		 753 /*
754 * Find the base address for shared memory access.
755 * Newer versions of bootcode use a signature and offset
756 * while older versions use a fixed address.
757 */
758 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
d0092544
SZ		 759 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
760 BCE_SHM_HDR_SIGNATURE_SIG) {
761 /* Multi-port devices use different offsets in shared memory. */
762 sc->bce_shmem_base = REG_RD_IND(sc,
763 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
764 } else {
43c2aeb0 765 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
d0092544 766 }
43c2aeb0
SZ		 767 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
768
d0092544 769 /* Fetch the bootcode revision. */
bc30d40d
SZ		 770 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
771 for (i = 0, j = 0; i < 3; i++) {
772 uint8_t num;
773 int k, skip0;
774
775 num = (uint8_t)(val >> (24 - (i * 8)));
776 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
777 if (num >= k || !skip0 || k == 1) {
778 sc->bce_bc_ver[j++] = (num / k) + '0';
779 skip0 = 0;
780 }
781 }
782 if (i != 2)
783 sc->bce_bc_ver[j++] = '.';
784 }
d0092544 785
bc30d40d
SZ		 786 /* Check if any management firwmare is running. */
787 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
788 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
d0092544
SZ		 789 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
790
bc30d40d
SZ		 791 /* Allow time for firmware to enter the running state. */
792 for (i = 0; i < 30; i++) {
793 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
794 if (val & BCE_CONDITION_MFW_RUN_MASK)
795 break;
796 DELAY(10000);
797 }
798 }
799
800 /* Check the current bootcode state. */
801 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
802 BCE_CONDITION_MFW_RUN_MASK;
803 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
804 val != BCE_CONDITION_MFW_RUN_NONE) {
805 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
806
807 for (i = 0, j = 0; j < 3; j++) {
808 val = bce_reg_rd_ind(sc, addr + j * 4);
809 val = bswap32(val);
810 memcpy(&sc->bce_mfw_ver[i], &val, 4);
811 i += 4;
812 }
813 }
814
43c2aeb0
SZ		 815 /* Get PCI bus information (speed and type). */
816 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
817 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
818 uint32_t clkreg;
819
820 sc->bce_flags |= BCE_PCIX_FLAG;
821
822 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
823 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
824 switch (clkreg) {
825 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
826 sc->bus_speed_mhz = 133;
827 break;
828
829 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
830 sc->bus_speed_mhz = 100;
831 break;
832
833 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
834 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
835 sc->bus_speed_mhz = 66;
836 break;
837
838 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
839 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
840 sc->bus_speed_mhz = 50;
841 break;
842
843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
844 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
845 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
846 sc->bus_speed_mhz = 33;
847 break;
848 }
849 } else {
850 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
851 sc->bus_speed_mhz = 66;
852 else
853 sc->bus_speed_mhz = 33;
854 }
855
856 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
857 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
858
43c2aeb0
SZ		 859 /* Reset the controller. */
860 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
861 if (rc != 0)
862 goto fail;
863
864 /* Initialize the controller. */
865 rc = bce_chipinit(sc);
866 if (rc != 0) {
867 device_printf(dev, "Controller initialization failed!\n");
868 goto fail;
869 }
870
871 /* Perform NVRAM test. */
872 rc = bce_nvram_test(sc);
873 if (rc != 0) {
874 device_printf(dev, "NVRAM test failed!\n");
875 goto fail;
876 }
877
878 /* Fetch the permanent Ethernet MAC address. */
879 bce_get_mac_addr(sc);
880
881 /*
882 * Trip points control how many BDs
883 * should be ready before generating an
884 * interrupt while ticks control how long
885 * a BD can sit in the chain before
886 * generating an interrupt. Set the default
887 * values for the RX and TX rings.
888 */
889
890#ifdef BCE_DRBUG
891 /* Force more frequent interrupts. */
892 sc->bce_tx_quick_cons_trip_int = 1;
893 sc->bce_tx_quick_cons_trip = 1;
894 sc->bce_tx_ticks_int = 0;
895 sc->bce_tx_ticks = 0;
896
897 sc->bce_rx_quick_cons_trip_int = 1;
898 sc->bce_rx_quick_cons_trip = 1;
899 sc->bce_rx_ticks_int = 0;
900 sc->bce_rx_ticks = 0;
901#else
bdeb8fff
SZ		 902 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
903 sc->bce_tx_quick_cons_trip = bce_tx_bds;
904 sc->bce_tx_ticks_int = bce_tx_ticks_int;
905 sc->bce_tx_ticks = bce_tx_ticks;
906
907 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
908 sc->bce_rx_quick_cons_trip = bce_rx_bds;
909 sc->bce_rx_ticks_int = bce_rx_ticks_int;
910 sc->bce_rx_ticks = bce_rx_ticks;
43c2aeb0
SZ		 911#endif
912
913 /* Update statistics once every second. */
914 sc->bce_stats_ticks = 1000000 & 0xffff00;
915
d0092544
SZ		 916 /* Find the media type for the adapter. */
917 bce_get_media(sc);
43c2aeb0
SZ		 918
919 /* Allocate DMA memory resources. */
920 rc = bce_dma_alloc(sc);
921 if (rc != 0) {
922 device_printf(dev, "DMA resource allocation failed!\n");
923 goto fail;
924 }
925
926 /* Initialize the ifnet interface. */
927 ifp->if_softc = sc;
928 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
929 ifp->if_ioctl = bce_ioctl;
930 ifp->if_start = bce_start;
931 ifp->if_init = bce_init;
932 ifp->if_watchdog = bce_watchdog;
933#ifdef DEVICE_POLLING
934 ifp->if_poll = bce_poll;
935#endif
936 ifp->if_mtu = ETHERMTU;
937 ifp->if_hwassist = BCE_IF_HWASSIST;
938 ifp->if_capabilities = BCE_IF_CAPABILITIES;
939 ifp->if_capenable = ifp->if_capabilities;
940 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
941 ifq_set_ready(&ifp->if_snd);
942
943 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
944 ifp->if_baudrate = IF_Gbps(2.5);
945 else
946 ifp->if_baudrate = IF_Gbps(1);
947
948 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
949 sc->mbuf_alloc_size = MCLBYTES;
950
951 /* Look for our PHY. */
952 rc = mii_phy_probe(dev, &sc->bce_miibus,
953 bce_ifmedia_upd, bce_ifmedia_sts);
954 if (rc != 0) {
955 device_printf(dev, "PHY probe failed!\n");
956 goto fail;
957 }
958
959 /* Attach to the Ethernet interface list. */
960 ether_ifattach(ifp, sc->eaddr, NULL);
961
6ac77363
SZ		 962 callout_init_mp(&sc->bce_tick_callout);
963 callout_init_mp(&sc->bce_pulse_callout);
43c2aeb0
SZ		 964
965 /* Hookup IRQ last. */
eac57ffb 966 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
43c2aeb0
SZ		 967 &sc->bce_intrhand, ifp->if_serializer);
968 if (rc != 0) {
969 device_printf(dev, "Failed to setup IRQ!\n");
970 ether_ifdetach(ifp);
971 goto fail;
972 }
973
733403d6 974 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
9db4b353
SZ		 975 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
976
43c2aeb0
SZ		 977 /* Print some important debugging info. */
978 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
979
980 /* Add the supported sysctls to the kernel. */
981 bce_add_sysctls(sc);
982
d0092544
SZ		 983 /*
984 * The chip reset earlier notified the bootcode that
985 * a driver is present. We now need to start our pulse
986 * routine so that the bootcode is reminded that we're
987 * still running.
988 */
989 bce_pulse(sc);
990
43c2aeb0
SZ		 991 /* Get the firmware running so IPMI still works */
992 bce_mgmt_init(sc);
993
b51a4d98
SZ		 994 if (bootverbose)
995 bce_print_adapter_info(sc);
d0092544 996
43c2aeb0
SZ		 997 return 0;
998fail:
999 bce_detach(dev);
1000 return(rc);
1001}
1002
1003
1004/****************************************************************************/
1005/* Device detach function. */
1006/* */
1007/* Stops the controller, resets the controller, and releases resources. */
1008/* */
1009/* Returns: */
1010/* 0 on success, positive value on failure. */
1011/****************************************************************************/
1012static int
1013bce_detach(device_t dev)
1014{
1015 struct bce_softc *sc = device_get_softc(dev);
1016
1017 if (device_is_attached(dev)) {
1018 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1019 uint32_t msg;
43c2aeb0
SZ		 1020
1021 /* Stop and reset the controller. */
1022 lwkt_serialize_enter(ifp->if_serializer);
d0092544 1023 callout_stop(&sc->bce_pulse_callout);
43c2aeb0 1024 bce_stop(sc);
d0092544
SZ		 1025 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1026 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1027 else
1028 msg = BCE_DRV_MSG_CODE_UNLOAD;
1029 bce_reset(sc, msg);
43c2aeb0
SZ		 1030 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1031 lwkt_serialize_exit(ifp->if_serializer);
1032
1033 ether_ifdetach(ifp);
1034 }
1035
1036 /* If we have a child device on the MII bus remove it too. */
1037 if (sc->bce_miibus)
1038 device_delete_child(dev, sc->bce_miibus);
1039 bus_generic_detach(dev);
1040
1041 if (sc->bce_res_irq != NULL) {
83ce3dce
SZ		 1042 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1043 sc->bce_res_irq);
43c2aeb0
SZ		 1044 }
1045
7fb43956 1046 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
43c2aeb0 1047 pci_release_msi(dev);
43c2aeb0
SZ		 1048
1049 if (sc->bce_res_mem != NULL) {
1050 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1051 sc->bce_res_mem);
1052 }
1053
1054 bce_dma_free(sc);
1055
1056 if (sc->bce_sysctl_tree != NULL)
1057 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1058
1059 return 0;
1060}
1061
1062
1063/****************************************************************************/
1064/* Device shutdown function. */
1065/* */
1066/* Stops and resets the controller. */
1067/* */
1068/* Returns: */
1069/* Nothing */
1070/****************************************************************************/
1071static void
1072bce_shutdown(device_t dev)
1073{
1074 struct bce_softc *sc = device_get_softc(dev);
1075 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1076 uint32_t msg;
43c2aeb0
SZ		 1077
1078 lwkt_serialize_enter(ifp->if_serializer);
1079 bce_stop(sc);
d0092544
SZ		 1080 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1081 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1082 else
1083 msg = BCE_DRV_MSG_CODE_UNLOAD;
1084 bce_reset(sc, msg);
43c2aeb0
SZ		 1085 lwkt_serialize_exit(ifp->if_serializer);
1086}
1087
1088
1089/****************************************************************************/
1090/* Indirect register read. */
1091/* */
1092/* Reads NetXtreme II registers using an index/data register pair in PCI */
1093/* configuration space. Using this mechanism avoids issues with posted */
1094/* reads but is much slower than memory-mapped I/O. */
1095/* */
1096/* Returns: */
1097/* The value of the register. */
1098/****************************************************************************/
1099static uint32_t
1100bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1101{
1102 device_t dev = sc->bce_dev;
1103
1104 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1105#ifdef BCE_DEBUG
1106 {
1107 uint32_t val;
1108 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1109 DBPRINT(sc, BCE_EXCESSIVE,
1110 "%s(); offset = 0x%08X, val = 0x%08X\n",
1111 __func__, offset, val);
1112 return val;
1113 }
1114#else
1115 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1116#endif
1117}
1118
1119
1120/****************************************************************************/
1121/* Indirect register write. */
1122/* */
1123/* Writes NetXtreme II registers using an index/data register pair in PCI */
1124/* configuration space. Using this mechanism avoids issues with posted */
1125/* writes but is muchh slower than memory-mapped I/O. */
1126/* */
1127/* Returns: */
1128/* Nothing. */
1129/****************************************************************************/
1130static void
1131bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1132{
1133 device_t dev = sc->bce_dev;
1134
1135 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1136 __func__, offset, val);
1137
1138 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1139 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1140}
1141
1142
1143/****************************************************************************/
bc30d40d
SZ		 1144/* Shared memory write. */
1145/* */
1146/* Writes NetXtreme II shared memory region. */
1147/* */
1148/* Returns: */
1149/* Nothing. */
1150/****************************************************************************/
1151static void
1152bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1153{
1154 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1155}
1156
1157
1158/****************************************************************************/
1159/* Shared memory read. */
1160/* */
1161/* Reads NetXtreme II shared memory region. */
1162/* */
1163/* Returns: */
1164/* The 32 bit value read. */
1165/****************************************************************************/
1166static u32
1167bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1168{
1169 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1170}
1171
1172
1173/****************************************************************************/
43c2aeb0
SZ		 1174/* Context memory write. */
1175/* */
1176/* The NetXtreme II controller uses context memory to track connection */
1177/* information for L2 and higher network protocols. */
1178/* */
1179/* Returns: */
1180/* Nothing. */
1181/****************************************************************************/
1182static void
d0092544
SZ		 1183bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1184 uint32_t ctx_val)
43c2aeb0 1185{
d0092544
SZ		 1186 uint32_t idx, offset = ctx_offset + cid_addr;
1187 uint32_t val, retry_cnt = 5;
43c2aeb0 1188
d0092544
SZ		 1189 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1190 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1191 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1192 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1193
1194 for (idx = 0; idx < retry_cnt; idx++) {
1195 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1196 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1197 break;
1198 DELAY(5);
1199 }
1200
1201 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1202 device_printf(sc->bce_dev,
1203 "Unable to write CTX memory: "
1204 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1205 cid_addr, ctx_offset);
1206 }
1207 } else {
1208 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1209 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1210 }
43c2aeb0
SZ		 1211}
1212
1213
1214/****************************************************************************/
1215/* PHY register read. */
1216/* */
1217/* Implements register reads on the MII bus. */
1218/* */
1219/* Returns: */
1220/* The value of the register. */
1221/****************************************************************************/
1222static int
1223bce_miibus_read_reg(device_t dev, int phy, int reg)
1224{
1225 struct bce_softc *sc = device_get_softc(dev);
1226 uint32_t val;
1227 int i;
1228
1229 /* Make sure we are accessing the correct PHY address. */
1230 if (phy != sc->bce_phy_addr) {
1231 DBPRINT(sc, BCE_VERBOSE,
1232 "Invalid PHY address %d for PHY read!\n", phy);
1233 return 0;
1234 }
1235
1236 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1237 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1238 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1239
1240 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1241 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1242
1243 DELAY(40);
1244 }
1245
1246 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1247 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1248 BCE_EMAC_MDIO_COMM_START_BUSY;
1249 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1250
1251 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1252 DELAY(10);
1253
1254 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1255 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1256 DELAY(5);
1257
1258 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1259 val &= BCE_EMAC_MDIO_COMM_DATA;
1260 break;
1261 }
1262 }
1263
1264 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1265 if_printf(&sc->arpcom.ac_if,
1266 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1267 phy, reg);
1268 val = 0x0;
1269 } else {
1270 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1271 }
1272
1273 DBPRINT(sc, BCE_EXCESSIVE,
1274 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1275 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1276
1277 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1278 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1279 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1280
1281 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1282 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1283
1284 DELAY(40);
1285 }
1286 return (val & 0xffff);
1287}
1288
1289
1290/****************************************************************************/
1291/* PHY register write. */
1292/* */
1293/* Implements register writes on the MII bus. */
1294/* */
1295/* Returns: */
1296/* The value of the register. */
1297/****************************************************************************/
1298static int
1299bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1300{
1301 struct bce_softc *sc = device_get_softc(dev);
1302 uint32_t val1;
1303 int i;
1304
1305 /* Make sure we are accessing the correct PHY address. */
1306 if (phy != sc->bce_phy_addr) {
1307 DBPRINT(sc, BCE_WARN,
1308 "Invalid PHY address %d for PHY write!\n", phy);
1309 return(0);
1310 }
1311
1312 DBPRINT(sc, BCE_EXCESSIVE,
1313 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1314 __func__, phy, (uint16_t)(reg & 0xffff),
1315 (uint16_t)(val & 0xffff));
1316
1317 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1318 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1319 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1320
1321 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1322 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1323
1324 DELAY(40);
1325 }
1326
1327 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1328 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1329 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1330 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1331
1332 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1333 DELAY(10);
1334
1335 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1336 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1337 DELAY(5);
1338 break;
1339 }
1340 }
1341
1342 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1343 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1344
1345 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1346 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1347 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1348
1349 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1350 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1351
1352 DELAY(40);
1353 }
1354 return 0;
1355}
1356
1357
1358/****************************************************************************/
1359/* MII bus status change. */
1360/* */
1361/* Called by the MII bus driver when the PHY establishes link to set the */
1362/* MAC interface registers. */
1363/* */
1364/* Returns: */
1365/* Nothing. */
1366/****************************************************************************/
1367static void
1368bce_miibus_statchg(device_t dev)
1369{
1370 struct bce_softc *sc = device_get_softc(dev);
1371 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1372
1373 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1374 mii->mii_media_active);
1375
1376#ifdef BCE_DEBUG
1377 /* Decode the interface media flags. */
1378 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1379 switch(IFM_TYPE(mii->mii_media_active)) {
1380 case IFM_ETHER:
1381 kprintf("Ethernet )");
1382 break;
1383 default:
1384 kprintf("Unknown )");
1385 break;
1386 }
1387
1388 kprintf(" Media Options: ( ");
1389 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1390 case IFM_AUTO:
1391 kprintf("Autoselect )");
1392 break;
1393 case IFM_MANUAL:
1394 kprintf("Manual )");
1395 break;
1396 case IFM_NONE:
1397 kprintf("None )");
1398 break;
1399 case IFM_10_T:
1400 kprintf("10Base-T )");
1401 break;
1402 case IFM_100_TX:
1403 kprintf("100Base-TX )");
1404 break;
1405 case IFM_1000_SX:
1406 kprintf("1000Base-SX )");
1407 break;
1408 case IFM_1000_T:
1409 kprintf("1000Base-T )");
1410 break;
1411 default:
1412 kprintf("Other )");
1413 break;
1414 }
1415
1416 kprintf(" Global Options: (");
1417 if (mii->mii_media_active & IFM_FDX)
1418 kprintf(" FullDuplex");
1419 if (mii->mii_media_active & IFM_HDX)
1420 kprintf(" HalfDuplex");
1421 if (mii->mii_media_active & IFM_LOOP)
1422 kprintf(" Loopback");
1423 if (mii->mii_media_active & IFM_FLAG0)
1424 kprintf(" Flag0");
1425 if (mii->mii_media_active & IFM_FLAG1)
1426 kprintf(" Flag1");
1427 if (mii->mii_media_active & IFM_FLAG2)
1428 kprintf(" Flag2");
1429 kprintf(" )\n");
1430#endif
1431
1432 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1433
1434 /*
1435 * Set MII or GMII interface based on the speed negotiated
1436 * by the PHY.
1437 */
1438 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1439 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1440 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1441 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1442 } else {
1443 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1444 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1445 }
1446
1447 /*
1448 * Set half or full duplex based on the duplicity negotiated
1449 * by the PHY.
1450 */
1451 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1452 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1453 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1454 } else {
1455 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1456 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1457 }
1458}
1459
1460
1461/****************************************************************************/
1462/* Acquire NVRAM lock. */
1463/* */
1464/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1465/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1466/* for use by the driver. */
1467/* */
1468/* Returns: */
1469/* 0 on success, positive value on failure. */
1470/****************************************************************************/
1471static int
1472bce_acquire_nvram_lock(struct bce_softc *sc)
1473{
1474 uint32_t val;
1475 int j;
1476
1477 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1478
1479 /* Request access to the flash interface. */
1480 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1481 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1482 val = REG_RD(sc, BCE_NVM_SW_ARB);
1483 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1484 break;
1485
1486 DELAY(5);
1487 }
1488
1489 if (j >= NVRAM_TIMEOUT_COUNT) {
1490 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1491 return EBUSY;
1492 }
1493 return 0;
1494}
1495
1496
1497/****************************************************************************/
1498/* Release NVRAM lock. */
1499/* */
1500/* When the caller is finished accessing NVRAM the lock must be released. */
1501/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1502/* for use by the driver. */
1503/* */
1504/* Returns: */
1505/* 0 on success, positive value on failure. */
1506/****************************************************************************/
1507static int
1508bce_release_nvram_lock(struct bce_softc *sc)
1509{
1510 int j;
1511 uint32_t val;
1512
1513 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1514
1515 /*
1516 * Relinquish nvram interface.
1517 */
1518 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1519
1520 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1521 val = REG_RD(sc, BCE_NVM_SW_ARB);
1522 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1523 break;
1524
1525 DELAY(5);
1526 }
1527
1528 if (j >= NVRAM_TIMEOUT_COUNT) {
1529 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1530 return EBUSY;
1531 }
1532 return 0;
1533}
1534
1535
43c2aeb0
SZ		 1536/****************************************************************************/
1537/* Enable NVRAM access. */
1538/* */
1539/* Before accessing NVRAM for read or write operations the caller must */
1540/* enabled NVRAM access. */
1541/* */
1542/* Returns: */
1543/* Nothing. */
1544/****************************************************************************/
1545static void
1546bce_enable_nvram_access(struct bce_softc *sc)
1547{
1548 uint32_t val;
1549
1550 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1551
1552 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1553 /* Enable both bits, even on read. */
1554 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1555 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1556}
1557
1558
1559/****************************************************************************/
1560/* Disable NVRAM access. */
1561/* */
1562/* When the caller is finished accessing NVRAM access must be disabled. */
1563/* */
1564/* Returns: */
1565/* Nothing. */
1566/****************************************************************************/
1567static void
1568bce_disable_nvram_access(struct bce_softc *sc)
1569{
1570 uint32_t val;
1571
1572 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1573
1574 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1575
1576 /* Disable both bits, even after read. */
1577 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1578 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1579}
1580
1581
43c2aeb0
SZ		 1582/****************************************************************************/
1583/* Read a dword (32 bits) from NVRAM. */
1584/* */
1585/* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1586/* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1587/* */
1588/* Returns: */
1589/* 0 on success and the 32 bit value read, positive value on failure. */
1590/****************************************************************************/
1591static int
1592bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1593 uint32_t cmd_flags)
1594{
1595 uint32_t cmd;
1596 int i, rc = 0;
1597
1598 /* Build the command word. */
1599 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1600
1601 /* Calculate the offset for buffered flash. */
d0092544 1602 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
43c2aeb0
SZ		 1603 offset = ((offset / sc->bce_flash_info->page_size) <<
1604 sc->bce_flash_info->page_bits) +
1605 (offset % sc->bce_flash_info->page_size);
1606 }
1607
1608 /*
1609 * Clear the DONE bit separately, set the address to read,
1610 * and issue the read.
1611 */
1612 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1613 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1614 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1615
1616 /* Wait for completion. */
1617 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1618 uint32_t val;
1619
1620 DELAY(5);
1621
1622 val = REG_RD(sc, BCE_NVM_COMMAND);
1623 if (val & BCE_NVM_COMMAND_DONE) {
1624 val = REG_RD(sc, BCE_NVM_READ);
1625
1626 val = be32toh(val);
1627 memcpy(ret_val, &val, 4);
1628 break;
1629 }
1630 }
1631
1632 /* Check for errors. */
1633 if (i >= NVRAM_TIMEOUT_COUNT) {
1634 if_printf(&sc->arpcom.ac_if,
1635 "Timeout error reading NVRAM at offset 0x%08X!\n",
1636 offset);
1637 rc = EBUSY;
1638 }
1639 return rc;
1640}
1641
1642
43c2aeb0
SZ		 1643/****************************************************************************/
1644/* Initialize NVRAM access. */
1645/* */
1646/* Identify the NVRAM device in use and prepare the NVRAM interface to */
1647/* access that device. */
1648/* */
1649/* Returns: */
1650/* 0 on success, positive value on failure. */
1651/****************************************************************************/
1652static int
1653bce_init_nvram(struct bce_softc *sc)
1654{
1655 uint32_t val;
1656 int j, entry_count, rc = 0;
1657 const struct flash_spec *flash;
1658
1659 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1660
d0092544
SZ		 1661 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1662 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1663 sc->bce_flash_info = &flash_5709;
1664 goto bce_init_nvram_get_flash_size;
1665 }
1666
43c2aeb0
SZ		 1667 /* Determine the selected interface. */
1668 val = REG_RD(sc, BCE_NVM_CFG1);
1669
1670 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1671
1672 /*
1673 * Flash reconfiguration is required to support additional
1674 * NVRAM devices not directly supported in hardware.
1675 * Check if the flash interface was reconfigured
1676 * by the bootcode.
1677 */
1678
1679 if (val & 0x40000000) {
1680 /* Flash interface reconfigured by bootcode. */
1681
1682 DBPRINT(sc, BCE_INFO_LOAD,
1683 "%s(): Flash WAS reconfigured.\n", __func__);
1684
1685 for (j = 0, flash = flash_table; j < entry_count;
1686 j++, flash++) {
1687 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1688 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1689 sc->bce_flash_info = flash;
1690 break;
1691 }
1692 }
1693 } else {
1694 /* Flash interface not yet reconfigured. */
1695 uint32_t mask;
1696
1697 DBPRINT(sc, BCE_INFO_LOAD,
1698 "%s(): Flash was NOT reconfigured.\n", __func__);
1699
1700 if (val & (1 << 23))
1701 mask = FLASH_BACKUP_STRAP_MASK;
1702 else
1703 mask = FLASH_STRAP_MASK;
1704
1705 /* Look for the matching NVRAM device configuration data. */
1706 for (j = 0, flash = flash_table; j < entry_count;
1707 j++, flash++) {
1708 /* Check if the device matches any of the known devices. */
1709 if ((val & mask) == (flash->strapping & mask)) {
1710 /* Found a device match. */
1711 sc->bce_flash_info = flash;
1712
1713 /* Request access to the flash interface. */
1714 rc = bce_acquire_nvram_lock(sc);
1715 if (rc != 0)
1716 return rc;
1717
1718 /* Reconfigure the flash interface. */
1719 bce_enable_nvram_access(sc);
1720 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1721 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1722 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1723 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1724 bce_disable_nvram_access(sc);
1725 bce_release_nvram_lock(sc);
1726 break;
1727 }
1728 }
1729 }
1730
1731 /* Check if a matching device was found. */
1732 if (j == entry_count) {
1733 sc->bce_flash_info = NULL;
1734 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
d819a615 1735 return ENODEV;
43c2aeb0
SZ		 1736 }
1737
d0092544 1738bce_init_nvram_get_flash_size:
43c2aeb0 1739 /* Write the flash config data to the shared memory interface. */
bc30d40d
SZ		 1740 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1741 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
43c2aeb0
SZ		 1742 if (val)
1743 sc->bce_flash_size = val;
1744 else
1745 sc->bce_flash_size = sc->bce_flash_info->total_size;
1746
1747 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1748 __func__, sc->bce_flash_info->total_size);
1749
1750 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1751
1752 return rc;
1753}
1754
1755
1756/****************************************************************************/
1757/* Read an arbitrary range of data from NVRAM. */
1758/* */
1759/* Prepares the NVRAM interface for access and reads the requested data */
1760/* into the supplied buffer. */
1761/* */
1762/* Returns: */
1763/* 0 on success and the data read, positive value on failure. */
1764/****************************************************************************/
1765static int
1766bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1767 int buf_size)
1768{
1769 uint32_t cmd_flags, offset32, len32, extra;
1770 int rc = 0;
1771
1772 if (buf_size == 0)
1773 return 0;
1774
1775 /* Request access to the flash interface. */
1776 rc = bce_acquire_nvram_lock(sc);
1777 if (rc != 0)
1778 return rc;
1779
1780 /* Enable access to flash interface */
1781 bce_enable_nvram_access(sc);
1782
1783 len32 = buf_size;
1784 offset32 = offset;
1785 extra = 0;
1786
1787 cmd_flags = 0;
1788
1789 /* XXX should we release nvram lock if read_dword() fails? */
1790 if (offset32 & 3) {
1791 uint8_t buf[4];
1792 uint32_t pre_len;
1793
1794 offset32 &= ~3;
1795 pre_len = 4 - (offset & 3);
1796
1797 if (pre_len >= len32) {
1798 pre_len = len32;
1799 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1800 } else {
1801 cmd_flags = BCE_NVM_COMMAND_FIRST;
1802 }
1803
1804 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1805 if (rc)
1806 return rc;
1807
1808 memcpy(ret_buf, buf + (offset & 3), pre_len);
1809
1810 offset32 += 4;
1811 ret_buf += pre_len;
1812 len32 -= pre_len;
1813 }
1814
1815 if (len32 & 3) {
1816 extra = 4 - (len32 & 3);
1817 len32 = (len32 + 4) & ~3;
1818 }
1819
1820 if (len32 == 4) {
1821 uint8_t buf[4];
1822
1823 if (cmd_flags)
1824 cmd_flags = BCE_NVM_COMMAND_LAST;
1825 else
1826 cmd_flags = BCE_NVM_COMMAND_FIRST |
1827 BCE_NVM_COMMAND_LAST;
1828
1829 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1830
1831 memcpy(ret_buf, buf, 4 - extra);
1832 } else if (len32 > 0) {
1833 uint8_t buf[4];
1834
1835 /* Read the first word. */
1836 if (cmd_flags)
1837 cmd_flags = 0;
1838 else
1839 cmd_flags = BCE_NVM_COMMAND_FIRST;
1840
1841 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1842
1843 /* Advance to the next dword. */
1844 offset32 += 4;
1845 ret_buf += 4;
1846 len32 -= 4;
1847
1848 while (len32 > 4 && rc == 0) {
1849 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1850
1851 /* Advance to the next dword. */
1852 offset32 += 4;
1853 ret_buf += 4;
1854 len32 -= 4;
1855 }
1856
1857 if (rc)
d0092544 1858 goto bce_nvram_read_locked_exit;
43c2aeb0
SZ		 1859
1860 cmd_flags = BCE_NVM_COMMAND_LAST;
1861 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1862
1863 memcpy(ret_buf, buf, 4 - extra);
1864 }
1865
d0092544 1866bce_nvram_read_locked_exit:
43c2aeb0
SZ		 1867 /* Disable access to flash interface and release the lock. */
1868 bce_disable_nvram_access(sc);
1869 bce_release_nvram_lock(sc);
1870
1871 return rc;
1872}
1873
1874
43c2aeb0
SZ		 1875/****************************************************************************/
1876/* Verifies that NVRAM is accessible and contains valid data. */
1877/* */
1878/* Reads the configuration data from NVRAM and verifies that the CRC is */
1879/* correct. */
1880/* */
1881/* Returns: */
1882/* 0 on success, positive value on failure. */
1883/****************************************************************************/
1884static int
1885bce_nvram_test(struct bce_softc *sc)
1886{
1887 uint32_t buf[BCE_NVRAM_SIZE / 4];
1888 uint32_t magic, csum;
1889 uint8_t *data = (uint8_t *)buf;
1890 int rc = 0;
1891
1892 /*
1893 * Check that the device NVRAM is valid by reading
1894 * the magic value at offset 0.
1895 */
1896 rc = bce_nvram_read(sc, 0, data, 4);
1897 if (rc != 0)
1898 return rc;
1899
1900 magic = be32toh(buf[0]);
1901 if (magic != BCE_NVRAM_MAGIC) {
1902 if_printf(&sc->arpcom.ac_if,
1903 "Invalid NVRAM magic value! Expected: 0x%08X, "
1904 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1905 return ENODEV;
1906 }
1907
1908 /*
1909 * Verify that the device NVRAM includes valid
1910 * configuration data.
1911 */
1912 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1913 if (rc != 0)
1914 return rc;
1915
1916 csum = ether_crc32_le(data, 0x100);
1917 if (csum != BCE_CRC32_RESIDUAL) {
1918 if_printf(&sc->arpcom.ac_if,
1919 "Invalid Manufacturing Information NVRAM CRC! "
1920 "Expected: 0x%08X, Found: 0x%08X\n",
1921 BCE_CRC32_RESIDUAL, csum);
1922 return ENODEV;
1923 }
1924
1925 csum = ether_crc32_le(data + 0x100, 0x100);
1926 if (csum != BCE_CRC32_RESIDUAL) {
1927 if_printf(&sc->arpcom.ac_if,
1928 "Invalid Feature Configuration Information "
1929 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1930 BCE_CRC32_RESIDUAL, csum);
1931 rc = ENODEV;
1932 }
1933 return rc;
1934}
1935
1936
1937/****************************************************************************/
d0092544
SZ		 1938/* Identifies the current media type of the controller and sets the PHY */
1939/* address. */
1940/* */
1941/* Returns: */
1942/* Nothing. */
1943/****************************************************************************/
1944static void
1945bce_get_media(struct bce_softc *sc)
1946{
1947 uint32_t val;
1948
1949 sc->bce_phy_addr = 1;
1950
1951 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1952 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1953 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1954 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1955 uint32_t strap;
1956
1957 /*
1958 * The BCM5709S is software configurable
1959 * for Copper or SerDes operation.
1960 */
1961 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1962 return;
1963 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1964 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1965 return;
1966 }
1967
1968 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1969 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1970 } else {
1971 strap =
1972 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1973 }
1974
1975 if (pci_get_function(sc->bce_dev) == 0) {
1976 switch (strap) {
1977 case 0x4:
1978 case 0x5:
1979 case 0x6:
1980 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1981 break;
1982 }
1983 } else {
1984 switch (strap) {
1985 case 0x1:
1986 case 0x2:
1987 case 0x4:
1988 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1989 break;
1990 }
1991 }
1992 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1993 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1994 }
1995
1996 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1997 sc->bce_flags |= BCE_NO_WOL_FLAG;
1998 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1999 sc->bce_phy_addr = 2;
bc30d40d 2000 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
d0092544
SZ		 2001 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2002 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2003 }
2004 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2005 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2006 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2007 }
2008}
2009
2010
2011/****************************************************************************/
43c2aeb0
SZ		 2012/* Free any DMA memory owned by the driver. */
2013/* */
2014/* Scans through each data structre that requires DMA memory and frees */
2015/* the memory if allocated. */
2016/* */
2017/* Returns: */
2018/* Nothing. */
2019/****************************************************************************/
2020static void
2021bce_dma_free(struct bce_softc *sc)
2022{
2023 int i;
2024
2025 /* Destroy the status block. */
2026 if (sc->status_tag != NULL) {
2027 if (sc->status_block != NULL) {
2028 bus_dmamap_unload(sc->status_tag, sc->status_map);
2029 bus_dmamem_free(sc->status_tag, sc->status_block,
2030 sc->status_map);
2031 }
2032 bus_dma_tag_destroy(sc->status_tag);
2033 }
2034
2035
2036 /* Destroy the statistics block. */
2037 if (sc->stats_tag != NULL) {
2038 if (sc->stats_block != NULL) {
2039 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2040 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2041 sc->stats_map);
2042 }
2043 bus_dma_tag_destroy(sc->stats_tag);
2044 }
2045
d0092544
SZ		 2046 /* Destroy the CTX DMA stuffs. */
2047 if (sc->ctx_tag != NULL) {
2048 for (i = 0; i < sc->ctx_pages; i++) {
2049 if (sc->ctx_block[i] != NULL) {
2050 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2051 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2052 sc->ctx_map[i]);
2053 }
2054 }
2055 bus_dma_tag_destroy(sc->ctx_tag);
2056 }
2057
43c2aeb0
SZ		 2058 /* Destroy the TX buffer descriptor DMA stuffs. */
2059 if (sc->tx_bd_chain_tag != NULL) {
2060 for (i = 0; i < TX_PAGES; i++) {
2061 if (sc->tx_bd_chain[i] != NULL) {
2062 bus_dmamap_unload(sc->tx_bd_chain_tag,
2063 sc->tx_bd_chain_map[i]);
2064 bus_dmamem_free(sc->tx_bd_chain_tag,
2065 sc->tx_bd_chain[i],
2066 sc->tx_bd_chain_map[i]);
2067 }
2068 }
2069 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2070 }
2071
2072 /* Destroy the RX buffer descriptor DMA stuffs. */
2073 if (sc->rx_bd_chain_tag != NULL) {
2074 for (i = 0; i < RX_PAGES; i++) {
2075 if (sc->rx_bd_chain[i] != NULL) {
2076 bus_dmamap_unload(sc->rx_bd_chain_tag,
2077 sc->rx_bd_chain_map[i]);
2078 bus_dmamem_free(sc->rx_bd_chain_tag,
2079 sc->rx_bd_chain[i],
2080 sc->rx_bd_chain_map[i]);
2081 }
2082 }
2083 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2084 }
2085
2086 /* Destroy the TX mbuf DMA stuffs. */
2087 if (sc->tx_mbuf_tag != NULL) {
2088 for (i = 0; i < TOTAL_TX_BD; i++) {
2089 /* Must have been unloaded in bce_stop() */
2090 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2091 bus_dmamap_destroy(sc->tx_mbuf_tag,
2092 sc->tx_mbuf_map[i]);
2093 }
2094 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2095 }
2096
2097 /* Destroy the RX mbuf DMA stuffs. */
2098 if (sc->rx_mbuf_tag != NULL) {
2099 for (i = 0; i < TOTAL_RX_BD; i++) {
2100 /* Must have been unloaded in bce_stop() */
2101 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2102 bus_dmamap_destroy(sc->rx_mbuf_tag,
2103 sc->rx_mbuf_map[i]);
2104 }
c36fd9ee 2105 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
43c2aeb0
SZ		 2106 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2107 }
2108
2109 /* Destroy the parent tag */
2110 if (sc->parent_tag != NULL)
2111 bus_dma_tag_destroy(sc->parent_tag);
2112}
2113
2114
2115/****************************************************************************/
2116/* Get DMA memory from the OS. */
2117/* */
2118/* Validates that the OS has provided DMA buffers in response to a */
2119/* bus_dmamap_load() call and saves the physical address of those buffers. */
2120/* When the callback is used the OS will return 0 for the mapping function */
2121/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2122/* failures back to the caller. */
2123/* */
2124/* Returns: */
2125/* Nothing. */
2126/****************************************************************************/
2127static void
2128bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2129{
2130 bus_addr_t *busaddr = arg;
2131
2132 /*
2133 * Simulate a mapping failure.
2134 * XXX not correct.
2135 */
2136 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2137 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2138 __FILE__, __LINE__);
2139 error = ENOMEM);
2140
2141 /* Check for an error and signal the caller that an error occurred. */
2142 if (error)
2143 return;
2144
2145 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2146 *busaddr = segs->ds_addr;
2147}
2148
2149
43c2aeb0
SZ		 2150/****************************************************************************/
2151/* Allocate any DMA memory needed by the driver. */
2152/* */
2153/* Allocates DMA memory needed for the various global structures needed by */
2154/* hardware. */
2155/* */
cffea833 2156/* Memory alignment requirements: */
d0092544
SZ		 2157/* -----------------+----------+----------+----------+----------+ */
2158/* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2159/* -----------------+----------+----------+----------+----------+ */
2160/* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2161/* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2162/* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2163/* PG Buffers | none | none | none | none | */
2164/* TX Buffers | none | none | none | none | */
2165/* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2166/* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2167/* -----------------+----------+----------+----------+----------+ */
cffea833
SZ		 2168/* */
2169/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2170/* */
43c2aeb0
SZ		 2171/* Returns: */
2172/* 0 for success, positive value for failure. */
2173/****************************************************************************/
2174static int
2175bce_dma_alloc(struct bce_softc *sc)
2176{
2177 struct ifnet *ifp = &sc->arpcom.ac_if;
2178 int i, j, rc = 0;
d0092544
SZ		 2179 bus_addr_t busaddr, max_busaddr;
2180 bus_size_t status_align, stats_align;
2181
2182 /*
2183 * The embedded PCIe to PCI-X bridge (EPB)
2184 * in the 5708 cannot address memory above
2185 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2186 */
2187 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2188 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2189 else
2190 max_busaddr = BUS_SPACE_MAXADDR;
2191
2192 /*
2193 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2194 */
2195 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2196 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2197 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2198 if (sc->ctx_pages == 0)
2199 sc->ctx_pages = 1;
2200 if (sc->ctx_pages > BCE_CTX_PAGES) {
2201 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2202 sc->ctx_pages);
2203 return ENOMEM;
2204 }
2205 status_align = 16;
2206 stats_align = 16;
2207 } else {
2208 status_align = 8;
2209 stats_align = 8;
2210 }
43c2aeb0
SZ		 2211
2212 /*
2213 * Allocate the parent bus DMA tag appropriate for PCI.
2214 */
2215 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
d0092544 2216 max_busaddr, BUS_SPACE_MAXADDR,
43c2aeb0 2217 NULL, NULL,
45010e4d 2218 BUS_SPACE_MAXSIZE_32BIT, 0,
43c2aeb0
SZ		 2219 BUS_SPACE_MAXSIZE_32BIT,
2220 0, &sc->parent_tag);
2221 if (rc != 0) {
2222 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2223 return rc;
2224 }
2225
2226 /*
4a458e9d 2227 * Allocate status block.
43c2aeb0 2228 */
4a458e9d 2229 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2230 status_align, BCE_STATUS_BLK_SZ,
4a458e9d
SZ		 2231 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2232 &sc->status_tag, &sc->status_map,
2233 &sc->status_block_paddr);
2234 if (sc->status_block == NULL) {
2235 if_printf(ifp, "Could not allocate status block!\n");
2236 return ENOMEM;
43c2aeb0
SZ		 2237 }
2238
43c2aeb0 2239 /*
4a458e9d 2240 * Allocate statistics block.
43c2aeb0 2241 */
4a458e9d 2242 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2243 stats_align, BCE_STATS_BLK_SZ,
4a458e9d
SZ		 2244 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2245 &sc->stats_tag, &sc->stats_map,
2246 &sc->stats_block_paddr);
2247 if (sc->stats_block == NULL) {
2248 if_printf(ifp, "Could not allocate statistics block!\n");
2249 return ENOMEM;
43c2aeb0
SZ		 2250 }
2251
43c2aeb0 2252 /*
d0092544
SZ		 2253 * Allocate context block, if needed
2254 */
2255 if (sc->ctx_pages != 0) {
2256 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2257 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2258 NULL, NULL,
2259 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2260 0, &sc->ctx_tag);
2261 if (rc != 0) {
2262 if_printf(ifp, "Could not allocate "
2263 "context block DMA tag!\n");
2264 return rc;
2265 }
2266
2267 for (i = 0; i < sc->ctx_pages; i++) {
2268 rc = bus_dmamem_alloc(sc->ctx_tag,
2269 (void **)&sc->ctx_block[i],
2270 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2271 BUS_DMA_COHERENT,
2272 &sc->ctx_map[i]);
2273 if (rc != 0) {
2274 if_printf(ifp, "Could not allocate %dth context "
2275 "DMA memory!\n", i);
2276 return rc;
2277 }
2278
2279 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2280 sc->ctx_block[i], BCM_PAGE_SIZE,
2281 bce_dma_map_addr, &busaddr,
2282 BUS_DMA_WAITOK);
2283 if (rc != 0) {
2284 if (rc == EINPROGRESS) {
2285 panic("%s coherent memory loading "
2286 "is still in progress!", ifp->if_xname);
2287 }
2288 if_printf(ifp, "Could not map %dth context "
2289 "DMA memory!\n", i);
2290 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2291 sc->ctx_map[i]);
2292 sc->ctx_block[i] = NULL;
2293 return rc;
2294 }
2295 sc->ctx_paddr[i] = busaddr;
2296 }
2297 }
2298
2299 /*
43c2aeb0
SZ		 2300 * Create a DMA tag for the TX buffer descriptor chain,
2301 * allocate and clear the memory, and fetch the
2302 * physical address of the block.
2303 */
4a458e9d
SZ		 2304 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2305 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ		 2306 NULL, NULL,
2307 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2308 0, &sc->tx_bd_chain_tag);
2309 if (rc != 0) {
2310 if_printf(ifp, "Could not allocate "
2311 "TX descriptor chain DMA tag!\n");
2312 return rc;
2313 }
2314
2315 for (i = 0; i < TX_PAGES; i++) {
2316 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2317 (void **)&sc->tx_bd_chain[i],
4a458e9d
SZ		 2318 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2319 BUS_DMA_COHERENT,
2320 &sc->tx_bd_chain_map[i]);
43c2aeb0
SZ		 2321 if (rc != 0) {
2322 if_printf(ifp, "Could not allocate %dth TX descriptor "
2323 "chain DMA memory!\n", i);
2324 return rc;
2325 }
2326
2327 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2328 sc->tx_bd_chain_map[i],
2329 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2330 bce_dma_map_addr, &busaddr,
2331 BUS_DMA_WAITOK);
2332 if (rc != 0) {
4a458e9d
SZ		 2333 if (rc == EINPROGRESS) {
2334 panic("%s coherent memory loading "
2335 "is still in progress!", ifp->if_xname);
2336 }
43c2aeb0
SZ		 2337 if_printf(ifp, "Could not map %dth TX descriptor "
2338 "chain DMA memory!\n", i);
2339 bus_dmamem_free(sc->tx_bd_chain_tag,
2340 sc->tx_bd_chain[i],
2341 sc->tx_bd_chain_map[i]);
2342 sc->tx_bd_chain[i] = NULL;
2343 return rc;
2344 }
2345
2346 sc->tx_bd_chain_paddr[i] = busaddr;
2347 /* DRC - Fix for 64 bit systems. */
2348 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2349 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2350 }
2351
2352 /* Create a DMA tag for TX mbufs. */
45010e4d
SZ		 2353 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2354 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2355 NULL, NULL,
45010e4d 2356 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
43c2aeb0 2357 BCE_MAX_SEGMENTS, MCLBYTES,
45010e4d
SZ		 2358 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2359 BUS_DMA_ONEBPAGE,
2360 &sc->tx_mbuf_tag);
43c2aeb0
SZ		 2361 if (rc != 0) {
2362 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2363 return rc;
2364 }
2365
2366 /* Create DMA maps for the TX mbufs clusters. */
2367 for (i = 0; i < TOTAL_TX_BD; i++) {
45010e4d
SZ		 2368 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2369 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
43c2aeb0
SZ		 2370 &sc->tx_mbuf_map[i]);
2371 if (rc != 0) {
2372 for (j = 0; j < i; ++j) {
2373 bus_dmamap_destroy(sc->tx_mbuf_tag,
2374 sc->tx_mbuf_map[i]);
2375 }
2376 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2377 sc->tx_mbuf_tag = NULL;
2378
2379 if_printf(ifp, "Unable to create "
2380 "%dth TX mbuf DMA map!\n", i);
2381 return rc;
2382 }
2383 }
2384
2385 /*
2386 * Create a DMA tag for the RX buffer descriptor chain,
2387 * allocate and clear the memory, and fetch the physical
2388 * address of the blocks.
2389 */
4a458e9d
SZ		 2390 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2391 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ		 2392 NULL, NULL,
2393 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2394 0, &sc->rx_bd_chain_tag);
2395 if (rc != 0) {
2396 if_printf(ifp, "Could not allocate "
2397 "RX descriptor chain DMA tag!\n");
2398 return rc;
2399 }
2400
2401 for (i = 0; i < RX_PAGES; i++) {
2402 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2403 (void **)&sc->rx_bd_chain[i],
4a458e9d
SZ		 2404 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2405 BUS_DMA_COHERENT,
43c2aeb0
SZ		 2406 &sc->rx_bd_chain_map[i]);
2407 if (rc != 0) {
2408 if_printf(ifp, "Could not allocate %dth RX descriptor "
2409 "chain DMA memory!\n", i);
2410 return rc;
2411 }
2412
2413 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2414 sc->rx_bd_chain_map[i],
2415 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2416 bce_dma_map_addr, &busaddr,
2417 BUS_DMA_WAITOK);
2418 if (rc != 0) {
4a458e9d
SZ		 2419 if (rc == EINPROGRESS) {
2420 panic("%s coherent memory loading "
2421 "is still in progress!", ifp->if_xname);
2422 }
43c2aeb0
SZ		 2423 if_printf(ifp, "Could not map %dth RX descriptor "
2424 "chain DMA memory!\n", i);
2425 bus_dmamem_free(sc->rx_bd_chain_tag,
2426 sc->rx_bd_chain[i],
2427 sc->rx_bd_chain_map[i]);
2428 sc->rx_bd_chain[i] = NULL;
2429 return rc;
2430 }
2431
2432 sc->rx_bd_chain_paddr[i] = busaddr;
2433 /* DRC - Fix for 64 bit systems. */
2434 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2435 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2436 }
2437
2438 /* Create a DMA tag for RX mbufs. */
cffea833 2439 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
45010e4d 2440 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2441 NULL, NULL,
45010e4d 2442 MCLBYTES, 1, MCLBYTES,
cffea833
SZ		 2443 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2444 BUS_DMA_WAITOK,
45010e4d 2445 &sc->rx_mbuf_tag);
43c2aeb0
SZ		 2446 if (rc != 0) {
2447 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2448 return rc;
2449 }
2450
c36fd9ee
SZ		 2451 /* Create tmp DMA map for RX mbuf clusters. */
2452 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2453 &sc->rx_mbuf_tmpmap);
2454 if (rc != 0) {
2455 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2456 sc->rx_mbuf_tag = NULL;
2457
2458 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2459 return rc;
2460 }
2461
43c2aeb0
SZ		 2462 /* Create DMA maps for the RX mbuf clusters. */
2463 for (i = 0; i < TOTAL_RX_BD; i++) {
2464 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2465 &sc->rx_mbuf_map[i]);
2466 if (rc != 0) {
2467 for (j = 0; j < i; ++j) {
2468 bus_dmamap_destroy(sc->rx_mbuf_tag,
2469 sc->rx_mbuf_map[j]);
2470 }
2471 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2472 sc->rx_mbuf_tag = NULL;
2473
2474 if_printf(ifp, "Unable to create "
2475 "%dth RX mbuf DMA map!\n", i);
2476 return rc;
2477 }
2478 }
2479 return 0;
2480}
2481
2482
2483/****************************************************************************/
2484/* Firmware synchronization. */
2485/* */
2486/* Before performing certain events such as a chip reset, synchronize with */
2487/* the firmware first. */
2488/* */
2489/* Returns: */
2490/* 0 for success, positive value for failure. */
2491/****************************************************************************/
2492static int
2493bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2494{
2495 int i, rc = 0;
2496 uint32_t val;
2497
2498 /* Don't waste any time if we've timed out before. */
2499 if (sc->bce_fw_timed_out)
2500 return EBUSY;
2501
2502 /* Increment the message sequence number. */
2503 sc->bce_fw_wr_seq++;
2504 msg_data |= sc->bce_fw_wr_seq;
2505
2506 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2507
2508 /* Send the message to the bootcode driver mailbox. */
bc30d40d 2509 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ		 2510
2511 /* Wait for the bootcode to acknowledge the message. */
2512 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2513 /* Check for a response in the bootcode firmware mailbox. */
bc30d40d 2514 val = bce_shmem_rd(sc, BCE_FW_MB);
43c2aeb0
SZ		 2515 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2516 break;
2517 DELAY(1000);
2518 }
2519
2520 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2521 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2522 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2523 if_printf(&sc->arpcom.ac_if,
2524 "Firmware synchronization timeout! "
2525 "msg_data = 0x%08X\n", msg_data);
2526
2527 msg_data &= ~BCE_DRV_MSG_CODE;
2528 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2529
bc30d40d 2530 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ		 2531
2532 sc->bce_fw_timed_out = 1;
2533 rc = EBUSY;
2534 }
2535 return rc;
2536}
2537
2538
2539/****************************************************************************/
2540/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2541/* */
2542/* Returns: */
2543/* Nothing. */
2544/****************************************************************************/
2545static void
2546bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2547 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2548{
2549 int i;
2550 uint32_t val;
2551
2552 for (i = 0; i < rv2p_code_len; i += 8) {
2553 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2554 rv2p_code++;
2555 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2556 rv2p_code++;
2557
2558 if (rv2p_proc == RV2P_PROC1) {
2559 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2560 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2561 } else {
2562 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2563 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2564 }
2565 }
2566
2567 /* Reset the processor, un-stall is done later. */
2568 if (rv2p_proc == RV2P_PROC1)
2569 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2570 else
2571 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2572}
2573
2574
2575/****************************************************************************/
2576/* Load RISC processor firmware. */
2577/* */
2578/* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2579/* associated with a particular processor. */
2580/* */
2581/* Returns: */
2582/* Nothing. */
2583/****************************************************************************/
2584static void
2585bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2586 struct fw_info *fw)
2587{
5d05a208 2588 uint32_t offset;
43c2aeb0
SZ		 2589 int j;
2590
5d05a208 2591 bce_halt_cpu(sc, cpu_reg);
43c2aeb0
SZ		 2592
2593 /* Load the Text area. */
2594 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2595 if (fw->text) {
2596 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2597 REG_WR_IND(sc, offset, fw->text[j]);
2598 }
2599
2600 /* Load the Data area. */
2601 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2602 if (fw->data) {
2603 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2604 REG_WR_IND(sc, offset, fw->data[j]);
2605 }
2606
2607 /* Load the SBSS area. */
2608 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2609 if (fw->sbss) {
2610 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2611 REG_WR_IND(sc, offset, fw->sbss[j]);
2612 }
2613
2614 /* Load the BSS area. */
2615 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2616 if (fw->bss) {
2617 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2618 REG_WR_IND(sc, offset, fw->bss[j]);
2619 }
2620
2621 /* Load the Read-Only area. */
2622 offset = cpu_reg->spad_base +
2623 (fw->rodata_addr - cpu_reg->mips_view_base);
2624 if (fw->rodata) {
2625 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2626 REG_WR_IND(sc, offset, fw->rodata[j]);
2627 }
2628
5d05a208 2629 /* Clear the pre-fetch instruction and set the FW start address. */
43c2aeb0
SZ		 2630 REG_WR_IND(sc, cpu_reg->inst, 0);
2631 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
5d05a208
SZ		 2632}
2633
2634
2635/****************************************************************************/
2636/* Starts the RISC processor. */
2637/* */
2638/* Assumes the CPU starting address has already been set. */
2639/* */
2640/* Returns: */
2641/* Nothing. */
2642/****************************************************************************/
2643static void
2644bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2645{
2646 uint32_t val;
43c2aeb0
SZ		 2647
2648 /* Start the CPU. */
2649 val = REG_RD_IND(sc, cpu_reg->mode);
2650 val &= ~cpu_reg->mode_value_halt;
2651 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2652 REG_WR_IND(sc, cpu_reg->mode, val);
2653}
2654
2655
2656/****************************************************************************/
5d05a208
SZ		 2657/* Halts the RISC processor. */
2658/* */
2659/* Returns: */
2660/* Nothing. */
2661/****************************************************************************/
2662static void
2663bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2664{
2665 uint32_t val;
2666
2667 /* Halt the CPU. */
2668 val = REG_RD_IND(sc, cpu_reg->mode);
2669 val |= cpu_reg->mode_value_halt;
2670 REG_WR_IND(sc, cpu_reg->mode, val);
2671 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2672}
2673
2674
2675/****************************************************************************/
2676/* Start the RX CPU. */
2677/* */
2678/* Returns: */
2679/* Nothing. */
2680/****************************************************************************/
2681static void
2682bce_start_rxp_cpu(struct bce_softc *sc)
2683{
2684 struct cpu_reg cpu_reg;
2685
2686 cpu_reg.mode = BCE_RXP_CPU_MODE;
2687 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2688 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2689 cpu_reg.state = BCE_RXP_CPU_STATE;
2690 cpu_reg.state_value_clear = 0xffffff;
2691 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2692 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2693 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2694 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2695 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2696 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2697 cpu_reg.mips_view_base = 0x8000000;
2698
2699 bce_start_cpu(sc, &cpu_reg);
2700}
2701
2702
2703/****************************************************************************/
d0092544 2704/* Initialize the RX CPU. */
43c2aeb0
SZ		 2705/* */
2706/* Returns: */
2707/* Nothing. */
2708/****************************************************************************/
2709static void
d0092544 2710bce_init_rxp_cpu(struct bce_softc *sc)
43c2aeb0
SZ		 2711{
2712 struct cpu_reg cpu_reg;
2713 struct fw_info fw;
2714
43c2aeb0
SZ		 2715 cpu_reg.mode = BCE_RXP_CPU_MODE;
2716 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2717 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2718 cpu_reg.state = BCE_RXP_CPU_STATE;
2719 cpu_reg.state_value_clear = 0xffffff;
2720 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2721 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2722 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2723 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2724 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2725 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2726 cpu_reg.mips_view_base = 0x8000000;
2727
d0092544
SZ		 2728 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2729 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2730 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2731 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2732 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2733 fw.start_addr = bce_RXP_b09FwStartAddr;
2734
2735 fw.text_addr = bce_RXP_b09FwTextAddr;
2736 fw.text_len = bce_RXP_b09FwTextLen;
2737 fw.text_index = 0;
2738 fw.text = bce_RXP_b09FwText;
2739
2740 fw.data_addr = bce_RXP_b09FwDataAddr;
2741 fw.data_len = bce_RXP_b09FwDataLen;
2742 fw.data_index = 0;
2743 fw.data = bce_RXP_b09FwData;
2744
2745 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2746 fw.sbss_len = bce_RXP_b09FwSbssLen;
2747 fw.sbss_index = 0;
2748 fw.sbss = bce_RXP_b09FwSbss;
2749
2750 fw.bss_addr = bce_RXP_b09FwBssAddr;
2751 fw.bss_len = bce_RXP_b09FwBssLen;
2752 fw.bss_index = 0;
2753 fw.bss = bce_RXP_b09FwBss;
2754
2755 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2756 fw.rodata_len = bce_RXP_b09FwRodataLen;
2757 fw.rodata_index = 0;
2758 fw.rodata = bce_RXP_b09FwRodata;
2759 } else {
2760 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2761 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2762 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2763 fw.start_addr = bce_RXP_b06FwStartAddr;
2764
2765 fw.text_addr = bce_RXP_b06FwTextAddr;
2766 fw.text_len = bce_RXP_b06FwTextLen;
2767 fw.text_index = 0;
2768 fw.text = bce_RXP_b06FwText;
2769
2770 fw.data_addr = bce_RXP_b06FwDataAddr;
2771 fw.data_len = bce_RXP_b06FwDataLen;
2772 fw.data_index = 0;
2773 fw.data = bce_RXP_b06FwData;
2774
2775 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2776 fw.sbss_len = bce_RXP_b06FwSbssLen;
2777 fw.sbss_index = 0;
2778 fw.sbss = bce_RXP_b06FwSbss;
2779
2780 fw.bss_addr = bce_RXP_b06FwBssAddr;
2781 fw.bss_len = bce_RXP_b06FwBssLen;
2782 fw.bss_index = 0;
2783 fw.bss = bce_RXP_b06FwBss;
2784
2785 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2786 fw.rodata_len = bce_RXP_b06FwRodataLen;
2787 fw.rodata_index = 0;
2788 fw.rodata = bce_RXP_b06FwRodata;
2789 }
43c2aeb0
SZ		 2790
2791 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2792 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2793 /* Delay RXP start until initialization is complete. */
d0092544
SZ		 2794}
2795
2796
2797/****************************************************************************/
2798/* Initialize the TX CPU. */
2799/* */
2800/* Returns: */
2801/* Nothing. */
2802/****************************************************************************/
2803static void
2804bce_init_txp_cpu(struct bce_softc *sc)
2805{
2806 struct cpu_reg cpu_reg;
2807 struct fw_info fw;
43c2aeb0 2808
43c2aeb0
SZ		 2809 cpu_reg.mode = BCE_TXP_CPU_MODE;
2810 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2811 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2812 cpu_reg.state = BCE_TXP_CPU_STATE;
2813 cpu_reg.state_value_clear = 0xffffff;
2814 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2815 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2816 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2817 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2818 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2819 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2820 cpu_reg.mips_view_base = 0x8000000;
2821
d0092544
SZ		 2822 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2823 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2824 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2825 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2826 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2827 fw.start_addr = bce_TXP_b09FwStartAddr;
2828
2829 fw.text_addr = bce_TXP_b09FwTextAddr;
2830 fw.text_len = bce_TXP_b09FwTextLen;
2831 fw.text_index = 0;
2832 fw.text = bce_TXP_b09FwText;
2833
2834 fw.data_addr = bce_TXP_b09FwDataAddr;
2835 fw.data_len = bce_TXP_b09FwDataLen;
2836 fw.data_index = 0;
2837 fw.data = bce_TXP_b09FwData;
2838
2839 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2840 fw.sbss_len = bce_TXP_b09FwSbssLen;
2841 fw.sbss_index = 0;
2842 fw.sbss = bce_TXP_b09FwSbss;
2843
2844 fw.bss_addr = bce_TXP_b09FwBssAddr;
2845 fw.bss_len = bce_TXP_b09FwBssLen;
2846 fw.bss_index = 0;
2847 fw.bss = bce_TXP_b09FwBss;
2848
2849 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2850 fw.rodata_len = bce_TXP_b09FwRodataLen;
2851 fw.rodata_index = 0;
2852 fw.rodata = bce_TXP_b09FwRodata;
2853 } else {
2854 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2855 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2856 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2857 fw.start_addr = bce_TXP_b06FwStartAddr;
2858
2859 fw.text_addr = bce_TXP_b06FwTextAddr;
2860 fw.text_len = bce_TXP_b06FwTextLen;
2861 fw.text_index = 0;
2862 fw.text = bce_TXP_b06FwText;
2863
2864 fw.data_addr = bce_TXP_b06FwDataAddr;
2865 fw.data_len = bce_TXP_b06FwDataLen;
2866 fw.data_index = 0;
2867 fw.data = bce_TXP_b06FwData;
2868
2869 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2870 fw.sbss_len = bce_TXP_b06FwSbssLen;
2871 fw.sbss_index = 0;
2872 fw.sbss = bce_TXP_b06FwSbss;
2873
2874 fw.bss_addr = bce_TXP_b06FwBssAddr;
2875 fw.bss_len = bce_TXP_b06FwBssLen;
2876 fw.bss_index = 0;
2877 fw.bss = bce_TXP_b06FwBss;
2878
2879 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2880 fw.rodata_len = bce_TXP_b06FwRodataLen;
2881 fw.rodata_index = 0;
2882 fw.rodata = bce_TXP_b06FwRodata;
2883 }
43c2aeb0
SZ		 2884
2885 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2886 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2887 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ		 2888}
2889
2890
2891/****************************************************************************/
2892/* Initialize the TPAT CPU. */
2893/* */
2894/* Returns: */
2895/* Nothing. */
2896/****************************************************************************/
2897static void
2898bce_init_tpat_cpu(struct bce_softc *sc)
2899{
2900 struct cpu_reg cpu_reg;
2901 struct fw_info fw;
43c2aeb0 2902
43c2aeb0
SZ		 2903 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2904 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2905 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2906 cpu_reg.state = BCE_TPAT_CPU_STATE;
2907 cpu_reg.state_value_clear = 0xffffff;
2908 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2909 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2910 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2911 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2912 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2913 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2914 cpu_reg.mips_view_base = 0x8000000;
2915
d0092544
SZ		 2916 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2917 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2918 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2919 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2920 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2921 fw.start_addr = bce_TPAT_b09FwStartAddr;
2922
2923 fw.text_addr = bce_TPAT_b09FwTextAddr;
2924 fw.text_len = bce_TPAT_b09FwTextLen;
2925 fw.text_index = 0;
2926 fw.text = bce_TPAT_b09FwText;
2927
2928 fw.data_addr = bce_TPAT_b09FwDataAddr;
2929 fw.data_len = bce_TPAT_b09FwDataLen;
2930 fw.data_index = 0;
2931 fw.data = bce_TPAT_b09FwData;
2932
2933 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2934 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2935 fw.sbss_index = 0;
2936 fw.sbss = bce_TPAT_b09FwSbss;
2937
2938 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2939 fw.bss_len = bce_TPAT_b09FwBssLen;
2940 fw.bss_index = 0;
2941 fw.bss = bce_TPAT_b09FwBss;
2942
2943 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2944 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2945 fw.rodata_index = 0;
2946 fw.rodata = bce_TPAT_b09FwRodata;
2947 } else {
2948 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2949 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2950 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2951 fw.start_addr = bce_TPAT_b06FwStartAddr;
2952
2953 fw.text_addr = bce_TPAT_b06FwTextAddr;
2954 fw.text_len = bce_TPAT_b06FwTextLen;
2955 fw.text_index = 0;
2956 fw.text = bce_TPAT_b06FwText;
2957
2958 fw.data_addr = bce_TPAT_b06FwDataAddr;
2959 fw.data_len = bce_TPAT_b06FwDataLen;
2960 fw.data_index = 0;
2961 fw.data = bce_TPAT_b06FwData;
2962
2963 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2964 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2965 fw.sbss_index = 0;
2966 fw.sbss = bce_TPAT_b06FwSbss;
2967
2968 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2969 fw.bss_len = bce_TPAT_b06FwBssLen;
2970 fw.bss_index = 0;
2971 fw.bss = bce_TPAT_b06FwBss;
2972
2973 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2974 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2975 fw.rodata_index = 0;
2976 fw.rodata = bce_TPAT_b06FwRodata;
2977 }
43c2aeb0 2978
d0092544
SZ		 2979 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2980 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2981 bce_start_cpu(sc, &cpu_reg);
d0092544 2982}
43c2aeb0 2983
43c2aeb0 2984
d0092544
SZ		 2985/****************************************************************************/
2986/* Initialize the CP CPU. */
2987/* */
2988/* Returns: */
2989/* Nothing. */
2990/****************************************************************************/
2991static void
2992bce_init_cp_cpu(struct bce_softc *sc)
2993{
2994 struct cpu_reg cpu_reg;
2995 struct fw_info fw;
43c2aeb0 2996
d0092544
SZ		 2997 cpu_reg.mode = BCE_CP_CPU_MODE;
2998 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2999 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3000 cpu_reg.state = BCE_CP_CPU_STATE;
3001 cpu_reg.state_value_clear = 0xffffff;
3002 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3003 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3004 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3005 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3006 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3007 cpu_reg.spad_base = BCE_CP_SCRATCH;
3008 cpu_reg.mips_view_base = 0x8000000;
43c2aeb0 3009
d0092544
SZ		 3010 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3011 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3012 fw.ver_major = bce_CP_b09FwReleaseMajor;
3013 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3014 fw.ver_fix = bce_CP_b09FwReleaseFix;
3015 fw.start_addr = bce_CP_b09FwStartAddr;
3016
3017 fw.text_addr = bce_CP_b09FwTextAddr;
3018 fw.text_len = bce_CP_b09FwTextLen;
3019 fw.text_index = 0;
3020 fw.text = bce_CP_b09FwText;
3021
3022 fw.data_addr = bce_CP_b09FwDataAddr;
3023 fw.data_len = bce_CP_b09FwDataLen;
3024 fw.data_index = 0;
3025 fw.data = bce_CP_b09FwData;
3026
3027 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3028 fw.sbss_len = bce_CP_b09FwSbssLen;
3029 fw.sbss_index = 0;
3030 fw.sbss = bce_CP_b09FwSbss;
3031
3032 fw.bss_addr = bce_CP_b09FwBssAddr;
3033 fw.bss_len = bce_CP_b09FwBssLen;
3034 fw.bss_index = 0;
3035 fw.bss = bce_CP_b09FwBss;
3036
3037 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3038 fw.rodata_len = bce_CP_b09FwRodataLen;
3039 fw.rodata_index = 0;
3040 fw.rodata = bce_CP_b09FwRodata;
3041 } else {
3042 fw.ver_major = bce_CP_b06FwReleaseMajor;
3043 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3044 fw.ver_fix = bce_CP_b06FwReleaseFix;
3045 fw.start_addr = bce_CP_b06FwStartAddr;
3046
3047 fw.text_addr = bce_CP_b06FwTextAddr;
3048 fw.text_len = bce_CP_b06FwTextLen;
3049 fw.text_index = 0;
3050 fw.text = bce_CP_b06FwText;
3051
3052 fw.data_addr = bce_CP_b06FwDataAddr;
3053 fw.data_len = bce_CP_b06FwDataLen;
3054 fw.data_index = 0;
3055 fw.data = bce_CP_b06FwData;
3056
3057 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3058 fw.sbss_len = bce_CP_b06FwSbssLen;
3059 fw.sbss_index = 0;
3060 fw.sbss = bce_CP_b06FwSbss;
3061
3062 fw.bss_addr = bce_CP_b06FwBssAddr;
3063 fw.bss_len = bce_CP_b06FwBssLen;
3064 fw.bss_index = 0;
3065 fw.bss = bce_CP_b06FwBss;
3066
3067 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3068 fw.rodata_len = bce_CP_b06FwRodataLen;
3069 fw.rodata_index = 0;
3070 fw.rodata = bce_CP_b06FwRodata;
3071 }
43c2aeb0 3072
d0092544 3073 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
43c2aeb0 3074 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3075 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ		 3076}
3077
3078
3079/****************************************************************************/
3080/* Initialize the COM CPU. */
3081/* */
3082/* Returns: */
3083/* Nothing. */
3084/****************************************************************************/
3085static void
3086bce_init_com_cpu(struct bce_softc *sc)
3087{
3088 struct cpu_reg cpu_reg;
3089 struct fw_info fw;
43c2aeb0 3090
43c2aeb0
SZ		 3091 cpu_reg.mode = BCE_COM_CPU_MODE;
3092 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3093 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3094 cpu_reg.state = BCE_COM_CPU_STATE;
3095 cpu_reg.state_value_clear = 0xffffff;
3096 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3097 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3098 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3099 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3100 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3101 cpu_reg.spad_base = BCE_COM_SCRATCH;
3102 cpu_reg.mips_view_base = 0x8000000;
3103
d0092544
SZ		 3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3105 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3106 fw.ver_major = bce_COM_b09FwReleaseMajor;
3107 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3108 fw.ver_fix = bce_COM_b09FwReleaseFix;
3109 fw.start_addr = bce_COM_b09FwStartAddr;
3110
3111 fw.text_addr = bce_COM_b09FwTextAddr;
3112 fw.text_len = bce_COM_b09FwTextLen;
3113 fw.text_index = 0;
3114 fw.text = bce_COM_b09FwText;
3115
3116 fw.data_addr = bce_COM_b09FwDataAddr;
3117 fw.data_len = bce_COM_b09FwDataLen;
3118 fw.data_index = 0;
3119 fw.data = bce_COM_b09FwData;
3120
3121 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3122 fw.sbss_len = bce_COM_b09FwSbssLen;
3123 fw.sbss_index = 0;
3124 fw.sbss = bce_COM_b09FwSbss;
3125
3126 fw.bss_addr = bce_COM_b09FwBssAddr;
3127 fw.bss_len = bce_COM_b09FwBssLen;
3128 fw.bss_index = 0;
3129 fw.bss = bce_COM_b09FwBss;
3130
3131 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3132 fw.rodata_len = bce_COM_b09FwRodataLen;
3133 fw.rodata_index = 0;
3134 fw.rodata = bce_COM_b09FwRodata;
3135 } else {
3136 fw.ver_major = bce_COM_b06FwReleaseMajor;
3137 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3138 fw.ver_fix = bce_COM_b06FwReleaseFix;
3139 fw.start_addr = bce_COM_b06FwStartAddr;
3140
3141 fw.text_addr = bce_COM_b06FwTextAddr;
3142 fw.text_len = bce_COM_b06FwTextLen;
3143 fw.text_index = 0;
3144 fw.text = bce_COM_b06FwText;
3145
3146 fw.data_addr = bce_COM_b06FwDataAddr;
3147 fw.data_len = bce_COM_b06FwDataLen;
3148 fw.data_index = 0;
3149 fw.data = bce_COM_b06FwData;
3150
3151 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3152 fw.sbss_len = bce_COM_b06FwSbssLen;
3153 fw.sbss_index = 0;
3154 fw.sbss = bce_COM_b06FwSbss;
3155
3156 fw.bss_addr = bce_COM_b06FwBssAddr;
3157 fw.bss_len = bce_COM_b06FwBssLen;
3158 fw.bss_index = 0;
3159 fw.bss = bce_COM_b06FwBss;
3160
3161 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3162 fw.rodata_len = bce_COM_b06FwRodataLen;
3163 fw.rodata_index = 0;
3164 fw.rodata = bce_COM_b06FwRodata;
3165 }
43c2aeb0 3166
d0092544
SZ		 3167 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3168 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3169 bce_start_cpu(sc, &cpu_reg);
d0092544 3170}
43c2aeb0 3171
43c2aeb0 3172
d0092544
SZ		 3173/****************************************************************************/
3174/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3175/* */
3176/* Loads the firmware for each CPU and starts the CPU. */
3177/* */
3178/* Returns: */
3179/* Nothing. */
3180/****************************************************************************/
3181static void
3182bce_init_cpus(struct bce_softc *sc)
3183{
3184 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3185 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
cff16e71
SZ		 3186 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3187 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3188 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3189 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3190 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3191 } else {
3192 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3193 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3194 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3195 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3196 }
d0092544 3197 } else {
cff16e71
SZ		 3198 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3199 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3200 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3201 sizeof(bce_rv2p_proc2), RV2P_PROC2);
d0092544 3202 }
43c2aeb0 3203
d0092544
SZ		 3204 bce_init_rxp_cpu(sc);
3205 bce_init_txp_cpu(sc);
3206 bce_init_tpat_cpu(sc);
3207 bce_init_com_cpu(sc);
3208 bce_init_cp_cpu(sc);
43c2aeb0
SZ		 3209}
3210
3211
3212/****************************************************************************/
3213/* Initialize context memory. */
3214/* */
3215/* Clears the memory associated with each Context ID (CID). */
3216/* */
3217/* Returns: */
3218/* Nothing. */
3219/****************************************************************************/
5b609aa3 3220static int
3a41a80b 3221bce_init_ctx(struct bce_softc *sc)
43c2aeb0 3222{
d0092544
SZ		 3223 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3224 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3225 /* DRC: Replace this constant value with a #define. */
3226 int i, retry_cnt = 10;
3227 uint32_t val;
3228
3229 /*
3230 * BCM5709 context memory may be cached
3231 * in host memory so prepare the host memory
3232 * for access.
3233 */
3234 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3235 (1 << 12);
3236 val |= (BCM_PAGE_BITS - 8) << 16;
3237 REG_WR(sc, BCE_CTX_COMMAND, val);
3238
3239 /* Wait for mem init command to complete. */
3240 for (i = 0; i < retry_cnt; i++) {
3241 val = REG_RD(sc, BCE_CTX_COMMAND);
3242 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3243 break;
3244 DELAY(2);
3245 }
5b609aa3
SZ		 3246 if (i == retry_cnt) {
3247 device_printf(sc->bce_dev,
3248 "Context memory initialization failed!\n");
3249 return ETIMEDOUT;
3250 }
d0092544
SZ		 3251
3252 for (i = 0; i < sc->ctx_pages; i++) {
3253 int j;
43c2aeb0 3254
d0092544
SZ		 3255 /*
3256 * Set the physical address of the context
3257 * memory cache.
3258 */
3259 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3260 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3261 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3262 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3263 BCE_ADDR_HI(sc->ctx_paddr[i]));
3264 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3265 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
43c2aeb0 3266
d0092544
SZ		 3267 /*
3268 * Verify that the context memory write was successful.
3269 */
3270 for (j = 0; j < retry_cnt; j++) {
3271 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3272 if ((val &
3273 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3274 break;
3275 DELAY(5);
3276 }
5b609aa3
SZ		 3277 if (j == retry_cnt) {
3278 device_printf(sc->bce_dev,
3279 "Failed to initialize context page!\n");
3280 return ETIMEDOUT;
3281 }
d0092544
SZ		 3282 }
3283 } else {
3284 uint32_t vcid_addr, offset;
43c2aeb0 3285
d0092544
SZ		 3286 /*
3287 * For the 5706/5708, context memory is local to
3288 * the controller, so initialize the controller
3289 * context memory.
3290 */
43c2aeb0 3291
d0092544
SZ		 3292 vcid_addr = GET_CID_ADDR(96);
3293 while (vcid_addr) {
3294 vcid_addr -= PHY_CTX_SIZE;
43c2aeb0 3295
d0092544
SZ		 3296 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3297 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
43c2aeb0 3298
3a41a80b 3299 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
d0092544
SZ		 3300 CTX_WR(sc, 0x00, offset, 0);
3301
3302 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3303 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3a41a80b 3304 }
43c2aeb0 3305 }
5b609aa3 3306 return 0;
43c2aeb0
SZ		 3307}
3308
3309
3310/****************************************************************************/
3311/* Fetch the permanent MAC address of the controller. */
3312/* */
3313/* Returns: */
3314/* Nothing. */
3315/****************************************************************************/
3316static void
3317bce_get_mac_addr(struct bce_softc *sc)
3318{
3319 uint32_t mac_lo = 0, mac_hi = 0;
3320
3321 /*
3322 * The NetXtreme II bootcode populates various NIC
3323 * power-on and runtime configuration items in a
3324 * shared memory area. The factory configured MAC
3325 * address is available from both NVRAM and the
3326 * shared memory area so we'll read the value from
3327 * shared memory for speed.
3328 */
3329
bc30d40d
SZ		 3330 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3331 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
43c2aeb0
SZ		 3332
3333 if (mac_lo == 0 && mac_hi == 0) {
3334 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3335 } else {
3336 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3337 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3338 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3339 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3340 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3341 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3342 }
3343
3344 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3345}
3346
3347
3348/****************************************************************************/
3349/* Program the MAC address. */
3350/* */
3351/* Returns: */
3352/* Nothing. */
3353/****************************************************************************/
3354static void
3355bce_set_mac_addr(struct bce_softc *sc)
3356{
3357 const uint8_t *mac_addr = sc->eaddr;
3358 uint32_t val;
3359
3360 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3361 sc->eaddr, ":");
3362
3363 val = (mac_addr[0] << 8) | mac_addr[1];
3364 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3365
3366 val = (mac_addr[2] << 24) |
3367 (mac_addr[3] << 16) |
3368 (mac_addr[4] << 8) |
3369 mac_addr[5];
3370 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3371}
3372
3373
3374/****************************************************************************/
3375/* Stop the controller. */
3376/* */
3377/* Returns: */
3378/* Nothing. */
3379/****************************************************************************/
3380static void
3381bce_stop(struct bce_softc *sc)
3382{
3383 struct ifnet *ifp = &sc->arpcom.ac_if;
43c2aeb0
SZ		 3384
3385 ASSERT_SERIALIZED(ifp->if_serializer);
3386
d0092544 3387 callout_stop(&sc->bce_tick_callout);
43c2aeb0
SZ		 3388
3389 /* Disable the transmit/receive blocks. */
d0092544 3390 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
43c2aeb0
SZ		 3391 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3392 DELAY(20);
3393
3394 bce_disable_intr(sc);
3395
43c2aeb0
SZ		 3396 /* Free the RX lists. */
3397 bce_free_rx_chain(sc);
3398
3399 /* Free TX buffers. */
3400 bce_free_tx_chain(sc);
3401
43c2aeb0 3402 sc->bce_link = 0;
bdeb8fff 3403 sc->bce_coalchg_mask = 0;
43c2aeb0
SZ		 3404
3405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3406 ifp->if_timer = 0;
43c2aeb0
SZ		 3407}
3408
3409
3410static int
3411bce_reset(struct bce_softc *sc, uint32_t reset_code)
3412{
3413 uint32_t val;
3414 int i, rc = 0;
3415
3416 /* Wait for pending PCI transactions to complete. */
3417 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3418 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3419 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3420 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3421 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3422 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3423 DELAY(5);
3424
d0092544
SZ		 3425 /* Disable DMA */
3426 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3427 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3428 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3429 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3430 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3431 }
3432
43c2aeb0
SZ		 3433 /* Assume bootcode is running. */
3434 sc->bce_fw_timed_out = 0;
d8870c52 3435 sc->bce_drv_cardiac_arrest = 0;
43c2aeb0
SZ		 3436
3437 /* Give the firmware a chance to prepare for the reset. */
3438 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3439 if (rc) {
3440 if_printf(&sc->arpcom.ac_if,
3441 "Firmware is not ready for reset\n");
3442 return rc;
3443 }
3444
3445 /* Set a firmware reminder that this is a soft reset. */
bc30d40d
SZ		 3446 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3447 BCE_DRV_RESET_SIGNATURE_MAGIC);
43c2aeb0
SZ		 3448
3449 /* Dummy read to force the chip to complete all current transactions. */
3450 val = REG_RD(sc, BCE_MISC_ID);
3451
3452 /* Chip reset. */
d0092544
SZ		 3453 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3454 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3455 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3456 REG_RD(sc, BCE_MISC_COMMAND);
3457 DELAY(5);
3458
3459 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3460 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3461
3462 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3463 } else {
3464 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3465 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3466 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3467 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3468
3469 /* Allow up to 30us for reset to complete. */
3470 for (i = 0; i < 10; i++) {
3471 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3472 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3473 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3474 break;
3475 DELAY(10);
43c2aeb0 3476 }
43c2aeb0 3477
d0092544
SZ		 3478 /* Check that reset completed successfully. */
3479 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3480 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3481 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3482 return EBUSY;
3483 }
43c2aeb0
SZ		 3484 }
3485
3486 /* Make sure byte swapping is properly configured. */
3487 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3488 if (val != 0x01020304) {
3489 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3490 return ENODEV;
3491 }
3492
3493 /* Just completed a reset, assume that firmware is running again. */
3494 sc->bce_fw_timed_out = 0;
d8870c52 3495 sc->bce_drv_cardiac_arrest = 0;
43c2aeb0
SZ		 3496
3497 /* Wait for the firmware to finish its initialization. */
3498 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3499 if (rc) {
3500 if_printf(&sc->arpcom.ac_if,
3501 "Firmware did not complete initialization!\n");
3502 }
3503 return rc;
3504}
3505
3506
3507static int
3508bce_chipinit(struct bce_softc *sc)
3509{
3510 uint32_t val;
3511 int rc = 0;
3512
3513 /* Make sure the interrupt is not active. */
3514 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
d0092544 3515 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
43c2aeb0
SZ		 3516
3517 /*
3518 * Initialize DMA byte/word swapping, configure the number of DMA
3519 * channels and PCI clock compensation delay.
3520 */
3521 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3522 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3523#if BYTE_ORDER == BIG_ENDIAN
3524 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3525#endif
3526 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3527 DMA_READ_CHANS << 12 |
3528 DMA_WRITE_CHANS << 16;
3529
3530 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3531
3532 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3533 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3534
3535 /*
3536 * This setting resolves a problem observed on certain Intel PCI
3537 * chipsets that cannot handle multiple outstanding DMA operations.
3538 * See errata E9_5706A1_65.
3539 */
3540 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3541 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3542 !(sc->bce_flags & BCE_PCIX_FLAG))
3543 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3544
3545 REG_WR(sc, BCE_DMA_CONFIG, val);
3546
43c2aeb0
SZ		 3547 /* Enable the RX_V2P and Context state machines before access. */
3548 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3549 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3550 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3551 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3552
3553 /* Initialize context mapping and zero out the quick contexts. */
5b609aa3
SZ		 3554 rc = bce_init_ctx(sc);
3555 if (rc != 0)
3556 return rc;
43c2aeb0
SZ		 3557
3558 /* Initialize the on-boards CPUs */
3559 bce_init_cpus(sc);
3560
5d05a208
SZ		 3561 /* Enable management frames (NC-SI) to flow to the MCP. */
3562 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3563 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3564 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3565 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3566 }
3567
43c2aeb0
SZ		 3568 /* Prepare NVRAM for access. */
3569 rc = bce_init_nvram(sc);
3570 if (rc != 0)
3571 return rc;
3572
3573 /* Set the kernel bypass block size */
3574 val = REG_RD(sc, BCE_MQ_CONFIG);
3575 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3576 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
d0092544
SZ		 3577
3578 /* Enable bins used on the 5709/5716. */
3579 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3580 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3581 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3582 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3583 val |= BCE_MQ_CONFIG_HALT_DIS;
3584 }
3585
43c2aeb0
SZ		 3586 REG_WR(sc, BCE_MQ_CONFIG, val);
3587
3588 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3589 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3590 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3591
3592 /* Set the page size and clear the RV2P processor stall bits. */
3593 val = (BCM_PAGE_BITS - 8) << 24;
3594 REG_WR(sc, BCE_RV2P_CONFIG, val);
3595
3596 /* Configure page size. */
3597 val = REG_RD(sc, BCE_TBDR_CONFIG);
3598 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3599 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3600 REG_WR(sc, BCE_TBDR_CONFIG, val);
3601
d0092544
SZ		 3602 /* Set the perfect match control register to default. */
3603 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3604
43c2aeb0
SZ		 3605 return 0;
3606}
3607
3608
3609/****************************************************************************/
3610/* Initialize the controller in preparation to send/receive traffic. */
3611/* */
3612/* Returns: */
3613/* 0 for success, positive value for failure. */
3614/****************************************************************************/
3615static int
3616bce_blockinit(struct bce_softc *sc)
3617{
3618 uint32_t reg, val;
3619 int rc = 0;
3620
3621 /* Load the hardware default MAC address. */
3622 bce_set_mac_addr(sc);
3623
3624 /* Set the Ethernet backoff seed value */
3625 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3626 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3627 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3628
3629 sc->last_status_idx = 0;
3630 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3631
733403d6
SZ		 3632 sc->pulse_check_status_idx = 0xffff;
3633
43c2aeb0
SZ		 3634 /* Set up link change interrupt generation. */
3635 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3636
3637 /* Program the physical address of the status block. */
3638 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3639 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3640
3641 /* Program the physical address of the statistics block. */
3642 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3643 BCE_ADDR_LO(sc->stats_block_paddr));
3644 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3645 BCE_ADDR_HI(sc->stats_block_paddr));
3646
3647 /* Program various host coalescing parameters. */
3648 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3649 (sc->bce_tx_quick_cons_trip_int << 16) |
3650 sc->bce_tx_quick_cons_trip);
3651 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3652 (sc->bce_rx_quick_cons_trip_int << 16) |
3653 sc->bce_rx_quick_cons_trip);
3654 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3655 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3656 REG_WR(sc, BCE_HC_TX_TICKS,
3657 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3658 REG_WR(sc, BCE_HC_RX_TICKS,
3659 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3660 REG_WR(sc, BCE_HC_COM_TICKS,
3661 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3662 REG_WR(sc, BCE_HC_CMD_TICKS,
3663 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3664 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3665 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
eac57ffb
SZ		 3666
3667 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3668 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3669 if (bootverbose)
3670 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3671 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3672 }
3673 REG_WR(sc, BCE_HC_CONFIG, val);
43c2aeb0
SZ		 3674
3675 /* Clear the internal statistics counters. */
3676 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3677
3678 /* Verify that bootcode is running. */
bc30d40d 3679 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
43c2aeb0
SZ		 3680
3681 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3682 if_printf(&sc->arpcom.ac_if,
3683 "%s(%d): Simulating bootcode failure.\n",
3684 __FILE__, __LINE__);
3685 reg = 0);
3686
3687 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3688 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3689 if_printf(&sc->arpcom.ac_if,
3690 "Bootcode not running! Found: 0x%08X, "
3691 "Expected: 08%08X\n",
3692 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3693 BCE_DEV_INFO_SIGNATURE_MAGIC);
3694 return ENODEV;
3695 }
3696
d0092544
SZ		 3697 /* Enable DMA */
3698 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3699 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3700 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3701 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3702 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
43c2aeb0
SZ		 3703 }
3704
43c2aeb0
SZ		 3705 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3706 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3707
3708 /* Enable link state change interrupt generation. */
3709 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3710
5d05a208
SZ		 3711 /* Enable the RXP. */
3712 bce_start_rxp_cpu(sc);
3713
3714 /* Disable management frames (NC-SI) from flowing to the MCP. */
3715 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3716 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3717 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3718 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3719 }
3720
43c2aeb0 3721 /* Enable all remaining blocks in the MAC. */
d0092544
SZ		 3722 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3723 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3724 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3725 BCE_MISC_ENABLE_DEFAULT_XI);
3726 } else {
3727 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3728 }
43c2aeb0
SZ		 3729 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3730 DELAY(20);
3731
d0092544
SZ		 3732 /* Save the current host coalescing block settings. */
3733 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3734
43c2aeb0
SZ		 3735 return 0;
3736}
3737
3738
3739/****************************************************************************/
3740/* Encapsulate an mbuf cluster into the rx_bd chain. */
3741/* */
3742/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3743/* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3744/* necessary. */
3745/* */
3746/* Returns: */
3747/* 0 for success, positive value for failure. */
3748/****************************************************************************/
3749static int
c36fd9ee
SZ		 3750bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3751 uint32_t *prod_bseq, int init)
43c2aeb0
SZ		 3752{
3753 bus_dmamap_t map;
43c2aeb0
SZ		 3754 bus_dma_segment_t seg;
3755 struct mbuf *m_new;
c36fd9ee 3756 int error, nseg;
43c2aeb0
SZ		 3757#ifdef BCE_DEBUG
3758 uint16_t debug_chain_prod = *chain_prod;
3759#endif
3760
3761 /* Make sure the inputs are valid. */
3762 DBRUNIF((*chain_prod > MAX_RX_BD),
3763 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3764 "RX producer out of range: 0x%04X > 0x%04X\n",
3765 __FILE__, __LINE__,
3766 *chain_prod, (uint16_t)MAX_RX_BD));
3767
3768 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3769 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3770
c36fd9ee
SZ		 3771 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3772 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3773 "Simulating mbuf allocation failure.\n",
3774 __FILE__, __LINE__);
3775 sc->mbuf_alloc_failed++;
3776 return ENOBUFS);
43c2aeb0 3777
c36fd9ee
SZ		 3778 /* This is a new mbuf allocation. */
3779 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3780 if (m_new == NULL)
3781 return ENOBUFS;
3782 DBRUNIF(1, sc->rx_mbuf_alloc++);
43c2aeb0 3783
c36fd9ee 3784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
43c2aeb0 3785
c36fd9ee
SZ		 3786 /* Map the mbuf cluster into device memory. */
3787 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3788 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3789 BUS_DMA_NOWAIT);
3790 if (error) {
3791 m_freem(m_new);
3792 if (init) {
3793 if_printf(&sc->arpcom.ac_if,
3794 "Error mapping mbuf into RX chain!\n");
3795 }
43c2aeb0 3796 DBRUNIF(1, sc->rx_mbuf_alloc--);
c36fd9ee 3797 return error;
43c2aeb0
SZ		 3798 }
3799
c36fd9ee
SZ		 3800 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3801 bus_dmamap_unload(sc->rx_mbuf_tag,
3802 sc->rx_mbuf_map[*chain_prod]);
3803 }
3804
3805 map = sc->rx_mbuf_map[*chain_prod];
3806 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3807 sc->rx_mbuf_tmpmap = map;
3808
43c2aeb0
SZ		 3809 /* Watch for overflow. */
3810 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3811 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3812 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3813 __FILE__, __LINE__, sc->free_rx_bd,
3814 (uint16_t)USABLE_RX_BD));
3815
3816 /* Update some debug statistic counters */
3817 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3818 sc->rx_low_watermark = sc->free_rx_bd);
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