tcp_syncache.cache_limit is a per-cpu limit, reserve enough space for all
[dragonfly.git] / sys / dev / netif / rl / if_rl.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
d2c71fa0 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.28 2005/11/22 00:24:33 dillon Exp $
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34 */
35
36/*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48/*
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
54 *
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
63 *
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
69 * levels.
70 *
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
74 *
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
79 * filter.
80 *
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
85 */
86
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87#include "opt_polling.h"
88
984263bc 89#include <sys/param.h>
ca59556a 90#include <sys/endian.h>
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91#include <sys/systm.h>
92#include <sys/sockio.h>
93#include <sys/mbuf.h>
94#include <sys/malloc.h>
95#include <sys/kernel.h>
ca59556a 96#include <sys/module.h>
984263bc 97#include <sys/socket.h>
a3fbe745 98#include <sys/thread2.h>
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99
100#include <net/if.h>
c2ffa639 101#include <net/ifq_var.h>
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102#include <net/if_arp.h>
103#include <net/ethernet.h>
104#include <net/if_dl.h>
105#include <net/if_media.h>
106
107#include <net/bpf.h>
108
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109#include <machine/bus_pio.h>
110#include <machine/bus_memio.h>
111#include <machine/bus.h>
112#include <machine/resource.h>
113#include <sys/bus.h>
114#include <sys/rman.h>
115
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116#include <dev/netif/mii_layer/mii.h>
117#include <dev/netif/mii_layer/miivar.h>
984263bc 118
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119#include <bus/pci/pcireg.h>
120#include <bus/pci/pcivar.h>
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121
122/* "controller miibus0" required. See GENERIC if you get errors here. */
123#include "miibus_if.h"
124
125/*
126 * Default to using PIO access for this driver. On SMP systems,
127 * there appear to be problems with memory mapped mode: it looks like
128 * doing too many memory mapped access back to back in rapid succession
129 * can hang the bus. I'm inclined to blame this on crummy design/construction
130 * on the part of RealTek. Memory mapped mode does appear to work on
131 * uniprocessor systems though.
132 */
133#define RL_USEIOSPACE
134
ca59556a 135#include <dev/netif/rl/if_rlreg.h>
984263bc 136
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137/*
138 * Various supported device vendors/types and their names.
139 */
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140static struct rl_type {
141 uint16_t rl_vid;
142 uint16_t rl_did;
143 const char *rl_name;
144} rl_devs[] = {
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145 { RT_VENDORID, RT_DEVICEID_8129,
146 "RealTek 8129 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8139,
148 "RealTek 8139 10/100BaseTX" },
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149 { RT_VENDORID, RT_DEVICEID_8138,
150 "RealTek 8139 10/100BaseTX CardBus" },
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151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
152 "Accton MPX 5030/5038 10/100BaseTX" },
153 { DELTA_VENDORID, DELTA_DEVICEID_8139,
154 "Delta Electronics 8139 10/100BaseTX" },
155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
156 "Addtron Technolgy 8139 10/100BaseTX" },
157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
158 "D-Link DFE-530TX+ 10/100BaseTX" },
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159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
160 "D-Link DFE-690TX 10/100BaseTX" },
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161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
162 "Nortel Networks 10/100BaseTX" },
163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
164 "Peppercon AG ROL/F" },
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165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
166 "Corega FEther CB-TXD" },
167 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
168 "Corega FEtherII CB-TXD" },
169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
170 "Planex FNW-3800-TX" },
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171 { 0, 0, NULL }
172};
173
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174static int rl_probe(device_t);
175static int rl_attach(device_t);
176static int rl_detach(device_t);
177
178static int rl_encap(struct rl_softc *, struct mbuf * );
179
180static void rl_rxeof(struct rl_softc *);
181static void rl_txeof(struct rl_softc *);
182static void rl_intr(void *);
183static void rl_tick(void *);
184static void rl_start(struct ifnet *);
185static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
186static void rl_init(void *);
187static void rl_stop (struct rl_softc *);
188static void rl_watchdog(struct ifnet *);
189static int rl_suspend(device_t);
190static int rl_resume(device_t);
191static void rl_shutdown(device_t);
192static int rl_ifmedia_upd(struct ifnet *);
193static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
194
195static void rl_eeprom_putbyte(struct rl_softc *, int);
196static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
197static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
198static void rl_mii_sync(struct rl_softc *);
199static void rl_mii_send(struct rl_softc *, uint32_t, int);
200static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
201static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
202
203static int rl_miibus_readreg(device_t, int, int);
204static int rl_miibus_writereg(device_t, int, int, int);
205static void rl_miibus_statchg(device_t);
206
207static void rl_setmulti(struct rl_softc *);
208static void rl_reset(struct rl_softc *);
209static void rl_list_tx_init(struct rl_softc *);
210
211static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
212static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
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213#ifdef DEVICE_POLLING
214static poll_handler_t rl_poll;
215#endif
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216
217#ifdef RL_USEIOSPACE
ca59556a
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218#define RL_RES SYS_RES_IOPORT
219#define RL_RID RL_PCI_LOIO
984263bc 220#else
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221#define RL_RES SYS_RES_MEMORY
222#define RL_RID RL_PCI_LOMEM
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223#endif
224
225static device_method_t rl_methods[] = {
226 /* Device interface */
227 DEVMETHOD(device_probe, rl_probe),
228 DEVMETHOD(device_attach, rl_attach),
229 DEVMETHOD(device_detach, rl_detach),
230 DEVMETHOD(device_suspend, rl_suspend),
231 DEVMETHOD(device_resume, rl_resume),
232 DEVMETHOD(device_shutdown, rl_shutdown),
233
234 /* bus interface */
235 DEVMETHOD(bus_print_child, bus_generic_print_child),
236 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
237
238 /* MII interface */
239 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
240 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
241 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
242
243 { 0, 0 }
244};
245
ca59556a 246static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
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247static devclass_t rl_devclass;
248
32832096 249DECLARE_DUMMY_MODULE(if_rl);
984263bc 250DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
ca59556a 251DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
984263bc 252DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
ca59556a 253MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
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254
255#define EE_SET(x) \
ca59556a 256 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
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257
258#define EE_CLR(x) \
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259 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
260
261static void
262rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
263{
264 struct rl_softc *sc = arg;
265
266 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
267}
268
269static void
270rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
271{
272 struct rl_softc *sc = arg;
273
274 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
275}
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276
277/*
278 * Send a read command and address to the EEPROM, check for ACK.
279 */
ca59556a
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280static void
281rl_eeprom_putbyte(struct rl_softc *sc, int addr)
984263bc 282{
ca59556a 283 int d, i;
984263bc 284
ca59556a 285 d = addr | sc->rl_eecmd_read;
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286
287 /*
288 * Feed in each bit and strobe the clock.
289 */
290 for (i = 0x400; i; i >>= 1) {
ca59556a 291 if (d & i)
984263bc 292 EE_SET(RL_EE_DATAIN);
ca59556a 293 else
984263bc 294 EE_CLR(RL_EE_DATAIN);
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295 DELAY(100);
296 EE_SET(RL_EE_CLK);
297 DELAY(150);
298 EE_CLR(RL_EE_CLK);
299 DELAY(100);
300 }
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301}
302
303/*
304 * Read a word of data stored in the EEPROM at address 'addr.'
305 */
ca59556a
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306static void
307rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
984263bc 308{
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309 int i;
310 uint16_t word = 0;
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311
312 /* Enter EEPROM access mode. */
313 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
314
315 /*
316 * Send address of word we want to read.
317 */
318 rl_eeprom_putbyte(sc, addr);
319
320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
321
322 /*
323 * Start reading bits from EEPROM.
324 */
325 for (i = 0x8000; i; i >>= 1) {
326 EE_SET(RL_EE_CLK);
327 DELAY(100);
328 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
329 word |= i;
330 EE_CLR(RL_EE_CLK);
331 DELAY(100);
332 }
333
334 /* Turn off EEPROM access mode. */
335 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
336
337 *dest = word;
984263bc
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338}
339
340/*
341 * Read a sequence of words from the EEPROM.
342 */
ca59556a
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343static void
344rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 345{
ca59556a
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346 int i;
347 u_int16_t word = 0, *ptr;
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348
349 for (i = 0; i < cnt; i++) {
350 rl_eeprom_getword(sc, off + i, &word);
351 ptr = (u_int16_t *)(dest + (i * 2));
352 if (swap)
353 *ptr = ntohs(word);
354 else
355 *ptr = word;
356 }
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357}
358
359
360/*
361 * MII access routines are provided for the 8129, which
362 * doesn't have a built-in PHY. For the 8139, we fake things
363 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
364 * direct access PHY registers.
365 */
ca59556a
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366#define MII_SET(x) \
367 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
984263bc 368
ca59556a
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369#define MII_CLR(x) \
370 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
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371
372/*
373 * Sync the PHYs by setting data bit and strobing the clock 32 times.
374 */
ca59556a
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375static void
376rl_mii_sync(struct rl_softc *sc)
984263bc 377{
ca59556a 378 int i;
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379
380 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
381
382 for (i = 0; i < 32; i++) {
383 MII_SET(RL_MII_CLK);
384 DELAY(1);
385 MII_CLR(RL_MII_CLK);
386 DELAY(1);
387 }
984263bc
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388}
389
390/*
391 * Clock a series of bits through the MII.
392 */
ca59556a
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393static void
394rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
984263bc 395{
ca59556a 396 int i;
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397
398 MII_CLR(RL_MII_CLK);
399
400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
ca59556a 401 if (bits & i)
984263bc 402 MII_SET(RL_MII_DATAOUT);
ca59556a 403 else
984263bc 404 MII_CLR(RL_MII_DATAOUT);
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MD
405 DELAY(1);
406 MII_CLR(RL_MII_CLK);
407 DELAY(1);
408 MII_SET(RL_MII_CLK);
409 }
410}
411
412/*
413 * Read an PHY register through the MII.
414 */
ca59556a
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415static int
416rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 417{
a3fbe745 418 int ack, i;
984263bc 419
a3fbe745 420 crit_enter();
984263bc
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421
422 /*
423 * Set up frame for RX.
424 */
425 frame->mii_stdelim = RL_MII_STARTDELIM;
426 frame->mii_opcode = RL_MII_READOP;
427 frame->mii_turnaround = 0;
428 frame->mii_data = 0;
429
430 CSR_WRITE_2(sc, RL_MII, 0);
431
432 /*
433 * Turn on data xmit.
434 */
435 MII_SET(RL_MII_DIR);
436
437 rl_mii_sync(sc);
438
439 /*
440 * Send command/address info.
441 */
442 rl_mii_send(sc, frame->mii_stdelim, 2);
443 rl_mii_send(sc, frame->mii_opcode, 2);
444 rl_mii_send(sc, frame->mii_phyaddr, 5);
445 rl_mii_send(sc, frame->mii_regaddr, 5);
446
447 /* Idle bit */
448 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
449 DELAY(1);
450 MII_SET(RL_MII_CLK);
451 DELAY(1);
452
453 /* Turn off xmit. */
454 MII_CLR(RL_MII_DIR);
455
456 /* Check for ack */
457 MII_CLR(RL_MII_CLK);
458 DELAY(1);
459 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
460 MII_SET(RL_MII_CLK);
461 DELAY(1);
462
463 /*
464 * Now try reading data bits. If the ack failed, we still
465 * need to clock through 16 cycles to keep the PHY(s) in sync.
466 */
467 if (ack) {
468 for(i = 0; i < 16; i++) {
469 MII_CLR(RL_MII_CLK);
470 DELAY(1);
471 MII_SET(RL_MII_CLK);
472 DELAY(1);
473 }
ca59556a
JS
474 } else {
475 for (i = 0x8000; i; i >>= 1) {
476 MII_CLR(RL_MII_CLK);
477 DELAY(1);
478 if (!ack) {
479 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
480 frame->mii_data |= i;
481 DELAY(1);
482 }
483 MII_SET(RL_MII_CLK);
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484 DELAY(1);
485 }
984263bc
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486 }
487
984263bc
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488 MII_CLR(RL_MII_CLK);
489 DELAY(1);
490 MII_SET(RL_MII_CLK);
491 DELAY(1);
492
a3fbe745 493 crit_exit();
984263bc 494
ca59556a 495 return(ack ? 1 : 0);
984263bc
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496}
497
498/*
499 * Write to a PHY register through the MII.
500 */
ca59556a
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501static int
502rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 503{
a3fbe745 504 crit_enter();
984263bc 505
984263bc
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506 /*
507 * Set up frame for TX.
508 */
984263bc
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509 frame->mii_stdelim = RL_MII_STARTDELIM;
510 frame->mii_opcode = RL_MII_WRITEOP;
511 frame->mii_turnaround = RL_MII_TURNAROUND;
512
513 /*
514 * Turn on data output.
515 */
516 MII_SET(RL_MII_DIR);
517
518 rl_mii_sync(sc);
519
520 rl_mii_send(sc, frame->mii_stdelim, 2);
521 rl_mii_send(sc, frame->mii_opcode, 2);
522 rl_mii_send(sc, frame->mii_phyaddr, 5);
523 rl_mii_send(sc, frame->mii_regaddr, 5);
524 rl_mii_send(sc, frame->mii_turnaround, 2);
525 rl_mii_send(sc, frame->mii_data, 16);
526
527 /* Idle bit. */
528 MII_SET(RL_MII_CLK);
529 DELAY(1);
530 MII_CLR(RL_MII_CLK);
531 DELAY(1);
532
533 /*
534 * Turn off xmit.
535 */
536 MII_CLR(RL_MII_DIR);
537
a3fbe745 538 crit_exit();
984263bc
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539
540 return(0);
541}
542
ca59556a
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543static int
544rl_miibus_readreg(device_t dev, int phy, int reg)
984263bc 545{
ca59556a
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546 struct rl_softc *sc;
547 struct rl_mii_frame frame;
548 uint16_t rval = 0;
549 uint16_t rl8139_reg = 0;
984263bc
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550
551 sc = device_get_softc(dev);
552
553 if (sc->rl_type == RL_8139) {
554 /* Pretend the internal PHY is only at address 0 */
555 if (phy)
556 return(0);
ca59556a 557 switch (reg) {
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558 case MII_BMCR:
559 rl8139_reg = RL_BMCR;
560 break;
561 case MII_BMSR:
562 rl8139_reg = RL_BMSR;
563 break;
564 case MII_ANAR:
565 rl8139_reg = RL_ANAR;
566 break;
567 case MII_ANER:
568 rl8139_reg = RL_ANER;
569 break;
570 case MII_ANLPAR:
571 rl8139_reg = RL_LPAR;
572 break;
573 case MII_PHYIDR1:
574 case MII_PHYIDR2:
575 return(0);
576 break;
577 /*
578 * Allow the rlphy driver to read the media status
579 * register. If we have a link partner which does not
580 * support NWAY, this is the register which will tell
581 * us the results of parallel detection.
582 */
583 case RL_MEDIASTAT:
584 rval = CSR_READ_1(sc, RL_MEDIASTAT);
585 return(rval);
984263bc 586 default:
ca59556a 587 device_printf(dev, "bad phy register\n");
984263bc
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588 return(0);
589 }
590 rval = CSR_READ_2(sc, rl8139_reg);
591 return(rval);
592 }
593
ca59556a 594 bzero(&frame, sizeof(frame));
984263bc
MD
595
596 frame.mii_phyaddr = phy;
597 frame.mii_regaddr = reg;
598 rl_mii_readreg(sc, &frame);
599
600 return(frame.mii_data);
601}
602
ca59556a
JS
603static int
604rl_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 605{
ca59556a
JS
606 struct rl_softc *sc;
607 struct rl_mii_frame frame;
608 u_int16_t rl8139_reg = 0;
984263bc
MD
609
610 sc = device_get_softc(dev);
611
612 if (sc->rl_type == RL_8139) {
613 /* Pretend the internal PHY is only at address 0 */
614 if (phy)
615 return(0);
ca59556a 616 switch (reg) {
984263bc
MD
617 case MII_BMCR:
618 rl8139_reg = RL_BMCR;
619 break;
620 case MII_BMSR:
621 rl8139_reg = RL_BMSR;
622 break;
623 case MII_ANAR:
624 rl8139_reg = RL_ANAR;
625 break;
626 case MII_ANER:
627 rl8139_reg = RL_ANER;
628 break;
629 case MII_ANLPAR:
630 rl8139_reg = RL_LPAR;
631 break;
632 case MII_PHYIDR1:
633 case MII_PHYIDR2:
634 return(0);
984263bc 635 default:
ca59556a 636 device_printf(dev, "bad phy register\n");
984263bc
MD
637 return(0);
638 }
639 CSR_WRITE_2(sc, rl8139_reg, data);
640 return(0);
641 }
642
ca59556a 643 bzero(&frame, sizeof(frame));
984263bc
MD
644
645 frame.mii_phyaddr = phy;
646 frame.mii_regaddr = reg;
647 frame.mii_data = data;
648
649 rl_mii_writereg(sc, &frame);
650
651 return(0);
652}
653
ca59556a
JS
654static void
655rl_miibus_statchg(device_t dev)
984263bc 656{
984263bc
MD
657}
658
659/*
660 * Program the 64-bit multicast hash filter.
661 */
ca59556a
JS
662static void
663rl_setmulti(struct rl_softc *sc)
984263bc 664{
ca59556a
JS
665 struct ifnet *ifp;
666 int h = 0;
667 uint32_t hashes[2] = { 0, 0 };
668 struct ifmultiaddr *ifma;
669 uint32_t rxfilt;
670 int mcnt = 0;
984263bc
MD
671
672 ifp = &sc->arpcom.ac_if;
673
674 rxfilt = CSR_READ_4(sc, RL_RXCFG);
675
676 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
677 rxfilt |= RL_RXCFG_RX_MULTI;
678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
679 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
680 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
681 return;
682 }
683
684 /* first, zot all the existing hash bits */
685 CSR_WRITE_4(sc, RL_MAR0, 0);
686 CSR_WRITE_4(sc, RL_MAR4, 0);
687
688 /* now program new ones */
ca59556a 689 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
690 if (ifma->ifma_addr->sa_family != AF_LINK)
691 continue;
ca59556a
JS
692 h = ether_crc32_be(
693 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
527b7d96 694 ETHER_ADDR_LEN) >> 26;
984263bc
MD
695 if (h < 32)
696 hashes[0] |= (1 << h);
697 else
698 hashes[1] |= (1 << (h - 32));
699 mcnt++;
700 }
701
702 if (mcnt)
703 rxfilt |= RL_RXCFG_RX_MULTI;
704 else
705 rxfilt &= ~RL_RXCFG_RX_MULTI;
706
707 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
708 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
709 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
984263bc
MD
710}
711
ca59556a
JS
712static void
713rl_reset(struct rl_softc *sc)
984263bc 714{
ca59556a 715 int i;
984263bc
MD
716
717 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
718
719 for (i = 0; i < RL_TIMEOUT; i++) {
720 DELAY(10);
721 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
722 break;
723 }
724 if (i == RL_TIMEOUT)
ca59556a 725 device_printf(sc->rl_dev, "reset never completed!\n");
984263bc
MD
726}
727
728/*
729 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
730 * IDs against our list and return a device name if we find a match.
49c37738
JS
731 *
732 * Return with a value < 0 to give re(4) a change to attach.
984263bc 733 */
ca59556a
JS
734static int
735rl_probe(device_t dev)
984263bc 736{
ca59556a
JS
737 struct rl_type *t;
738 uint16_t product = pci_get_device(dev);
739 uint16_t vendor = pci_get_vendor(dev);
984263bc 740
49c37738 741 for (t = rl_devs; t->rl_name != NULL; t++) {
ca59556a
JS
742 if (vendor == t->rl_vid && product == t->rl_did) {
743 device_set_desc(dev, t->rl_name);
49c37738 744 return(-100);
ca59556a 745 }
984263bc
MD
746 }
747
748 return(ENXIO);
749}
750
751/*
752 * Attach the interface. Allocate softc structures, do ifmedia
753 * setup and ethernet/BPF attach.
754 */
ca59556a
JS
755static int
756rl_attach(device_t dev)
984263bc 757{
ca59556a
JS
758 uint8_t eaddr[ETHER_ADDR_LEN];
759 uint16_t as[3];
760 struct rl_softc *sc;
761 struct ifnet *ifp;
762 uint16_t rl_did = 0;
763 int error = 0, rid, i;
984263bc
MD
764
765 sc = device_get_softc(dev);
ca59556a 766 sc->rl_dev = dev;
984263bc
MD
767
768 /*
769 * Handle power management nonsense.
770 */
771
ca59556a
JS
772 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
773 uint32_t iobase, membase, irq;
984263bc 774
ca59556a
JS
775 /* Save important PCI config data. */
776 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
777 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
778 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
984263bc 779
ca59556a
JS
780 /* Reset the power state. */
781 device_printf(dev, "chip is is in D%d power mode "
782 "-- setting to D0\n", pci_get_powerstate(dev));
783 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
984263bc 784
ca59556a
JS
785 /* Restore PCI config data. */
786 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
787 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
788 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
984263bc
MD
789 }
790
ca59556a 791 pci_enable_busmaster(dev);
984263bc
MD
792
793 rid = RL_RID;
4e6d744d 794 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
984263bc
MD
795
796 if (sc->rl_res == NULL) {
ca59556a 797 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
798 error = ENXIO;
799 goto fail;
800 }
801
802 sc->rl_btag = rman_get_bustag(sc->rl_res);
803 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
804
805 rid = 0;
ca59556a
JS
806 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
807 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
808
809 if (sc->rl_irq == NULL) {
ca59556a 810 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
811 error = ENXIO;
812 goto fail;
813 }
814
b3a81bea 815 callout_init(&sc->rl_stat_timer);
984263bc
MD
816
817 /* Reset the adapter. */
818 rl_reset(sc);
819
ca59556a
JS
820 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
821 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
822 if (rl_did != 0x8129)
823 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
824
984263bc
MD
825 /*
826 * Get station address from the EEPROM.
827 */
ca59556a
JS
828 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
829 for (i = 0; i < 3; i++) {
830 eaddr[(i * 2) + 0] = as[i] & 0xff;
831 eaddr[(i * 2) + 1] = as[i] >> 8;
832 }
984263bc
MD
833
834 /*
835 * Now read the exact device type from the EEPROM to find
836 * out if it's an 8129 or 8139.
837 */
838 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
839
840 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
841 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
ca59556a
JS
842 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 ||
843 rl_did == DLINK_DEVICEID_690TXD ||
844 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
845 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
846 rl_did == PLANEX_DEVICEID_FNW3800TX)
984263bc
MD
847 sc->rl_type = RL_8139;
848 else if (rl_did == RT_DEVICEID_8129)
849 sc->rl_type = RL_8129;
850 else {
ca59556a 851 device_printf(dev, "unknown device ID: %x\n", rl_did);
984263bc
MD
852 error = ENXIO;
853 goto fail;
854 }
855
ca59556a
JS
856#define RL_NSEG_NEW 32
857 error = bus_dma_tag_create(NULL, /* parent */
858 1, 0, /* alignment, boundary */
859 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
860 BUS_SPACE_MAXADDR, /* highaddr */
861 NULL, NULL, /* filter, filterarg */
862 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
863 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
864 BUS_DMA_ALLOCNOW, /* flags */
865 &sc->rl_parent_tag);
984263bc 866
ca59556a
JS
867 if (error) {
868 device_printf(dev, "can't create parent tag\n");
869 goto fail;
870 }
871
872 /*
873 * Now allocate a tag for the DMA descriptor lists.
874 * All of our lists are allocated as a contiguous block
875 * of memory.
876 */
877 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
878 1, 0, /* alignment, boundary */
879 BUS_SPACE_MAXADDR, /* lowaddr */
880 BUS_SPACE_MAXADDR, /* highaddr */
881 NULL, NULL, /* filter, filterarg */
882 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
883 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
884 0, /* flags */
885 &sc->rl_tag);
886
887 if (error) {
888 device_printf(dev, "can't create RX tag\n");
889 goto fail;
890 }
891
892 /*
893 * Now allocate a chunk of DMA-able memory based on the tag
894 * we just created.
895 */
896 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
897 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
898
899 if (error) {
900 device_printf(dev, "can't allocate RX memory!\n");
984263bc
MD
901 error = ENXIO;
902 goto fail;
903 }
904
905 /* Leave a few bytes before the start of the RX ring buffer. */
906 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
907 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
908
909 /* Do MII setup */
ca59556a
JS
910 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
911 rl_ifmedia_sts)) {
912 device_printf(dev, "MII without any phy!\n");
984263bc
MD
913 error = ENXIO;
914 goto fail;
915 }
916
917 ifp = &sc->arpcom.ac_if;
918 ifp->if_softc = sc;
ca59556a 919 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
920 ifp->if_mtu = ETHERMTU;
921 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
922 ifp->if_ioctl = rl_ioctl;
984263bc
MD
923 ifp->if_start = rl_start;
924 ifp->if_watchdog = rl_watchdog;
925 ifp->if_init = rl_init;
926 ifp->if_baudrate = 10000000;
ca59556a
JS
927 ifp->if_capabilities = IFCAP_VLAN_MTU;
928#ifdef DEVICE_POLLING
9c095379 929 ifp->if_poll = rl_poll;
ca59556a 930#endif
c2ffa639
JS
931 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
932 ifq_set_ready(&ifp->if_snd);
984263bc
MD
933
934 /*
935 * Call MI attach routine.
936 */
0a8b5977 937 ether_ifattach(ifp, eaddr);
984263bc 938
ee61f228 939 error = bus_setup_intr(dev, sc->rl_irq, 0, rl_intr,
e9cb6d99 940 sc, &sc->rl_intrhand, NULL);
ca59556a
JS
941
942 if (error) {
943 device_printf(dev, "couldn't set up irq\n");
944 ether_ifdetach(ifp);
945 goto fail;
946 }
947
948 return(0);
949
984263bc 950fail:
ca59556a 951 rl_detach(dev);
984263bc
MD
952 return(error);
953}
954
ca59556a
JS
955static int
956rl_detach(device_t dev)
984263bc 957{
ca59556a
JS
958 struct rl_softc *sc;
959 struct ifnet *ifp;
984263bc
MD
960
961 sc = device_get_softc(dev);
962 ifp = &sc->arpcom.ac_if;
963
a3fbe745 964 crit_enter();
ca59556a
JS
965
966 if (device_is_attached(dev)) {
967 rl_stop(sc);
968 ether_ifdetach(ifp);
969 }
984263bc 970
ca59556a
JS
971 if (sc->rl_miibus)
972 device_delete_child(dev, sc->rl_miibus);
984263bc 973 bus_generic_detach(dev);
984263bc 974
ca59556a
JS
975 if (sc->rl_intrhand)
976 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
a3fbe745
JS
977
978 crit_exit();
984263bc 979
ca59556a
JS
980 if (sc->rl_irq)
981 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
982 if (sc->rl_res)
983 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
984263bc 984
ca59556a
JS
985 if (sc->rl_cdata.rl_rx_buf) {
986 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
987 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
988 sc->rl_cdata.rl_rx_dmamap);
989 }
990 if (sc->rl_tag)
991 bus_dma_tag_destroy(sc->rl_tag);
992 if (sc->rl_parent_tag)
993 bus_dma_tag_destroy(sc->rl_parent_tag);
984263bc
MD
994
995 return(0);
996}
997
998/*
999 * Initialize the transmit descriptors.
1000 */
ca59556a
JS
1001static void
1002rl_list_tx_init(struct rl_softc *sc)
984263bc 1003{
ca59556a
JS
1004 struct rl_chain_data *cd;
1005 int i;
984263bc
MD
1006
1007 cd = &sc->rl_cdata;
1008 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1009 cd->rl_tx_chain[i] = NULL;
1010 CSR_WRITE_4(sc,
ca59556a 1011 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
984263bc
MD
1012 }
1013
1014 sc->rl_cdata.cur_tx = 0;
1015 sc->rl_cdata.last_tx = 0;
984263bc
MD
1016}
1017
1018/*
1019 * A frame has been uploaded: pass the resulting mbuf chain up to
1020 * the higher level protocols.
1021 *
1022 * You know there's something wrong with a PCI bus-master chip design
1023 * when you have to use m_devget().
1024 *
1025 * The receive operation is badly documented in the datasheet, so I'll
1026 * attempt to document it here. The driver provides a buffer area and
1027 * places its base address in the RX buffer start address register.
1028 * The chip then begins copying frames into the RX buffer. Each frame
ca59556a 1029 * is preceded by a 32-bit RX status word which specifies the length
984263bc
MD
1030 * of the frame and certain other status bits. Each frame (starting with
1031 * the status word) is also 32-bit aligned. The frame length is in the
1032 * first 16 bits of the status word; the lower 15 bits correspond with
1033 * the 'rx status register' mentioned in the datasheet.
1034 *
1035 * Note: to make the Alpha happy, the frame payload needs to be aligned
1036 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1037 * the ring buffer starting at an address two bytes before the actual
1038 * data location. We can then shave off the first two bytes using m_adj().
1039 * The reason we do this is because m_devget() doesn't let us specify an
1040 * offset into the mbuf storage space, so we have to artificially create
1041 * one. The ring is allocated in such a way that there are a few unused
1042 * bytes of space preceecing it so that it will be safe for us to do the
1043 * 2-byte backstep even if reading from the ring at offset 0.
1044 */
ca59556a
JS
1045static void
1046rl_rxeof(struct rl_softc *sc)
984263bc 1047{
ca59556a
JS
1048 struct mbuf *m;
1049 struct ifnet *ifp;
1050 int total_len = 0;
1051 uint32_t rxstat;
1052 caddr_t rxbufpos;
1053 int wrap = 0;
1054 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
984263bc
MD
1055
1056 ifp = &sc->arpcom.ac_if;
1057
ca59556a
JS
1058 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1059 BUS_DMASYNC_POSTREAD);
1060
984263bc
MD
1061 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1062
1063 /* Do not try to read past this point. */
1064 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1065
1066 if (limit < cur_rx)
1067 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1068 else
1069 max_bytes = limit - cur_rx;
1070
1071 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1072#ifdef DEVICE_POLLING
46f25451 1073 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1074 if (sc->rxcycles <= 0)
1075 break;
1076 sc->rxcycles--;
1077 }
1078#endif /* DEVICE_POLLING */
1079 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
ca59556a 1080 rxstat = le32toh(*(uint32_t *)rxbufpos);
984263bc
MD
1081
1082 /*
1083 * Here's a totally undocumented fact for you. When the
1084 * RealTek chip is in the process of copying a packet into
1085 * RAM for you, the length will be 0xfff0. If you spot a
1086 * packet header with this value, you need to stop. The
1087 * datasheet makes absolutely no mention of this and
1088 * RealTek should be shot for this.
1089 */
ca59556a 1090 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
984263bc
MD
1091 break;
1092
ca59556a 1093 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
984263bc
MD
1094 ifp->if_ierrors++;
1095 rl_init(sc);
1096 return;
1097 }
1098
1099 /* No errors; receive the packet. */
1100 total_len = rxstat >> 16;
1101 rx_bytes += total_len + 4;
1102
1103 /*
1104 * XXX The RealTek chip includes the CRC with every
1105 * received frame, and there's no way to turn this
1106 * behavior off (at least, I can't find anything in
1107 * the manual that explains how to do it) so we have
1108 * to trim off the CRC manually.
1109 */
1110 total_len -= ETHER_CRC_LEN;
1111
1112 /*
1113 * Avoid trying to read more bytes than we know
1114 * the chip has prepared for us.
1115 */
1116 if (rx_bytes > max_bytes)
1117 break;
1118
1119 rxbufpos = sc->rl_cdata.rl_rx_buf +
ca59556a 1120 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
984263bc
MD
1121
1122 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1123 rxbufpos = sc->rl_cdata.rl_rx_buf;
1124
1125 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1126
1127 if (total_len > wrap) {
1128 /*
1129 * Fool m_devget() into thinking we want to copy
1130 * the whole buffer so we don't end up fragmenting
1131 * the data.
1132 */
1133 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1134 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1135 if (m == NULL) {
1136 ifp->if_ierrors++;
1137 } else {
1138 m_adj(m, RL_ETHER_ALIGN);
1139 m_copyback(m, wrap, total_len - wrap,
1140 sc->rl_cdata.rl_rx_buf);
1141 }
1142 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1143 } else {
1144 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1145 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1146 if (m == NULL) {
1147 ifp->if_ierrors++;
1148 } else
1149 m_adj(m, RL_ETHER_ALIGN);
1150 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1151 }
1152
1153 /*
1154 * Round up to 32-bit boundary.
1155 */
1156 cur_rx = (cur_rx + 3) & ~3;
1157 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1158
1159 if (m == NULL)
1160 continue;
1161
984263bc
MD
1162 ifp->if_ipackets++;
1163
3013ac0e 1164 (*ifp->if_input)(ifp, m);
984263bc 1165 }
984263bc
MD
1166}
1167
1168/*
1169 * A frame was downloaded to the chip. It's safe for us to clean up
1170 * the list buffers.
1171 */
ca59556a
JS
1172static void
1173rl_txeof(struct rl_softc *sc)
984263bc 1174{
ca59556a
JS
1175 struct ifnet *ifp;
1176 uint32_t txstat;
984263bc
MD
1177
1178 ifp = &sc->arpcom.ac_if;
1179
1180 /*
1181 * Go through our tx list and free mbufs for those
1182 * frames that have been uploaded.
1183 */
1184 do {
ca59556a
JS
1185 if (RL_LAST_TXMBUF(sc) == NULL)
1186 break;
984263bc 1187 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
ca59556a
JS
1188 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1189 RL_TXSTAT_TXABRT)) == 0)
984263bc
MD
1190 break;
1191
1192 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1193
ca59556a
JS
1194 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1195 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1196 m_freem(RL_LAST_TXMBUF(sc));
1197 RL_LAST_TXMBUF(sc) = NULL;
ef042148 1198 RL_INC(sc->rl_cdata.last_tx);
ca59556a 1199
ef042148
JS
1200 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1201 sc->rl_txthresh += 32;
1202 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1203 sc->rl_txthresh = RL_TX_THRESH_MAX;
1204 }
ca59556a 1205
ef042148
JS
1206 if (txstat & RL_TXSTAT_TX_OK) {
1207 ifp->if_opackets++;
1208 } else {
984263bc 1209 ifp->if_oerrors++;
ef042148 1210 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
984263bc 1211 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
984263bc 1212 }
984263bc
MD
1213 ifp->if_flags &= ~IFF_OACTIVE;
1214 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1215
ca59556a
JS
1216 if (RL_LAST_TXMBUF(sc) == NULL)
1217 ifp->if_timer = 0;
1218 else if (ifp->if_timer == 0)
1219 ifp->if_timer = 5;
984263bc
MD
1220}
1221
ca59556a
JS
1222static void
1223rl_tick(void *xsc)
984263bc 1224{
ca59556a
JS
1225 struct rl_softc *sc = xsc;
1226 struct mii_data *mii;
984263bc 1227
a3fbe745 1228 crit_enter();
984263bc 1229
984263bc 1230 mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1231 mii_tick(mii);
1232
b3a81bea 1233 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
a3fbe745
JS
1234
1235 crit_exit();
984263bc
MD
1236}
1237
1238#ifdef DEVICE_POLLING
984263bc
MD
1239
1240static void
ca59556a 1241rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
984263bc
MD
1242{
1243 struct rl_softc *sc = ifp->if_softc;
1244
9c095379
MD
1245 switch(cmd) {
1246 case POLL_REGISTER:
1247 /* disable interrupts */
1248 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1249 break;
1250 case POLL_DEREGISTER:
1251 /* enable interrupts */
ca59556a 1252 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
9c095379
MD
1253 break;
1254 default:
1255 sc->rxcycles = count;
1256 rl_rxeof(sc);
1257 rl_txeof(sc);
1258 if (!ifq_is_empty(&ifp->if_snd))
1259 rl_start(ifp);
1260
1261 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1262 uint16_t status;
1263
1264 status = CSR_READ_2(sc, RL_ISR);
1265 if (status == 0xffff)
1266 return;
1267 if (status)
1268 CSR_WRITE_2(sc, RL_ISR, status);
1269
1270 /*
1271 * XXX check behaviour on receiver stalls.
1272 */
984263bc 1273
9c095379
MD
1274 if (status & RL_ISR_SYSTEM_ERR) {
1275 rl_reset(sc);
1276 rl_init(sc);
1277 }
984263bc 1278 }
9c095379 1279 break;
984263bc
MD
1280 }
1281}
1282#endif /* DEVICE_POLLING */
1283
ca59556a
JS
1284static void
1285rl_intr(void *arg)
984263bc 1286{
ca59556a
JS
1287 struct rl_softc *sc;
1288 struct ifnet *ifp;
1289 uint16_t status;
984263bc
MD
1290
1291 sc = arg;
1292
ca59556a 1293 if (sc->suspended)
984263bc 1294 return;
984263bc
MD
1295
1296 ifp = &sc->arpcom.ac_if;
984263bc
MD
1297
1298 for (;;) {
984263bc 1299 status = CSR_READ_2(sc, RL_ISR);
ca59556a
JS
1300 /* If the card has gone away, the read returns 0xffff. */
1301 if (status == 0xffff)
1302 break;
1303
1304 if (status != 0)
984263bc
MD
1305 CSR_WRITE_2(sc, RL_ISR, status);
1306
1307 if ((status & RL_INTRS) == 0)
1308 break;
1309
1310 if (status & RL_ISR_RX_OK)
1311 rl_rxeof(sc);
1312
1313 if (status & RL_ISR_RX_ERR)
1314 rl_rxeof(sc);
1315
1316 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1317 rl_txeof(sc);
1318
1319 if (status & RL_ISR_SYSTEM_ERR) {
1320 rl_reset(sc);
1321 rl_init(sc);
1322 }
1323
1324 }
ca59556a 1325
c2ffa639 1326 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1327 rl_start(ifp);
984263bc
MD
1328}
1329
1330/*
1331 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1332 * pointers to the fragment pointers.
1333 */
ca59556a
JS
1334static int
1335rl_encap(struct rl_softc *sc, struct mbuf *m_head)
984263bc 1336{
ca59556a 1337 struct mbuf *m_new = NULL;
984263bc
MD
1338
1339 /*
1340 * The RealTek is brain damaged and wants longword-aligned
1341 * TX buffers, plus we can only have one fragment buffer
1342 * per packet. We have to copy pretty much all the time.
1343 */
ca59556a 1344 m_new = m_defrag(m_head, MB_DONTWAIT);
984263bc 1345
ca59556a
JS
1346 if (m_new == NULL) {
1347 m_freem(m_head);
984263bc 1348 return(1);
984263bc 1349 }
984263bc
MD
1350 m_head = m_new;
1351
1352 /* Pad frames to at least 60 bytes. */
1353 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1354 /*
1355 * Make security concious people happy: zero out the
1356 * bytes in the pad area, since we don't know what
1357 * this mbuf cluster buffer's previous user might
1358 * have left in it.
1359 */
1360 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1361 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1362 m_head->m_pkthdr.len +=
1363 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1364 m_head->m_len = m_head->m_pkthdr.len;
1365 }
1366
1367 RL_CUR_TXMBUF(sc) = m_head;
1368
1369 return(0);
1370}
1371
1372/*
1373 * Main transmit routine.
1374 */
1375
ca59556a
JS
1376static void
1377rl_start(struct ifnet *ifp)
984263bc 1378{
ca59556a
JS
1379 struct rl_softc *sc;
1380 struct mbuf *m_head = NULL;
984263bc
MD
1381
1382 sc = ifp->if_softc;
1383
1384 while(RL_CUR_TXMBUF(sc) == NULL) {
d2c71fa0 1385 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1386 if (m_head == NULL)
1387 break;
1388
ca59556a 1389 if (rl_encap(sc, m_head))
984263bc 1390 break;
984263bc
MD
1391
1392 /*
1393 * If there's a BPF listener, bounce a copy of this frame
1394 * to him.
1395 */
ca59556a 1396 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
984263bc
MD
1397
1398 /*
1399 * Transmit the frame.
1400 */
ca59556a
JS
1401 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1402 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1403 mtod(RL_CUR_TXMBUF(sc), void *),
1404 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1405 rl_dma_map_txbuf, sc, 0);
1406 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1407 BUS_DMASYNC_PREREAD);
984263bc
MD
1408 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1409 RL_TXTHRESH(sc->rl_txthresh) |
1410 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1411
1412 RL_INC(sc->rl_cdata.cur_tx);
ca59556a
JS
1413
1414 /*
1415 * Set a timeout in case the chip goes out to lunch.
1416 */
1417 ifp->if_timer = 5;
984263bc
MD
1418 }
1419
1420 /*
1421 * We broke out of the loop because all our TX slots are
1422 * full. Mark the NIC as busy until it drains some of the
1423 * packets from the queue.
1424 */
1425 if (RL_CUR_TXMBUF(sc) != NULL)
1426 ifp->if_flags |= IFF_OACTIVE;
984263bc
MD
1427}
1428
ca59556a
JS
1429static void
1430rl_init(void *xsc)
984263bc 1431{
ca59556a
JS
1432 struct rl_softc *sc = xsc;
1433 struct ifnet *ifp = &sc->arpcom.ac_if;
1434 struct mii_data *mii;
ca59556a 1435 uint32_t rxcfg = 0;
984263bc 1436
a3fbe745 1437 crit_enter();
984263bc
MD
1438
1439 mii = device_get_softc(sc->rl_miibus);
1440
1441 /*
1442 * Cancel pending I/O and free all RX/TX buffers.
1443 */
1444 rl_stop(sc);
1445
ca59556a
JS
1446 /*
1447 * Init our MAC address. Even though the chipset documentation
1448 * doesn't mention it, we need to enter "Config register write enable"
1449 * mode to modify the ID registers.
1450 */
1451 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1452 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1453 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1454 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1455 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1456 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
984263bc
MD
1457
1458 /* Init the RX buffer pointer register. */
ca59556a
JS
1459 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1460 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1461 sc, 0);
1462 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1463 BUS_DMASYNC_PREWRITE);
984263bc
MD
1464
1465 /* Init TX descriptors. */
1466 rl_list_tx_init(sc);
1467
1468 /*
1469 * Enable transmit and receive.
1470 */
1471 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1472
1473 /*
1474 * Set the initial TX and RX configuration.
1475 */
1476 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1477 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1478
1479 /* Set the individual bit to receive frames for this host only. */
1480 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1481 rxcfg |= RL_RXCFG_RX_INDIV;
1482
1483 /* If we want promiscuous mode, set the allframes bit. */
1484 if (ifp->if_flags & IFF_PROMISC) {
1485 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1486 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1487 } else {
1488 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1489 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1490 }
1491
1492 /*
1493 * Set capture broadcast bit to capture broadcast frames.
1494 */
1495 if (ifp->if_flags & IFF_BROADCAST) {
1496 rxcfg |= RL_RXCFG_RX_BROAD;
1497 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1498 } else {
1499 rxcfg &= ~RL_RXCFG_RX_BROAD;
1500 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1501 }
1502
1503 /*
1504 * Program the multicast filter, if necessary.
1505 */
1506 rl_setmulti(sc);
1507
1508#ifdef DEVICE_POLLING
1509 /*
1510 * Only enable interrupts if we are polling, keep them off otherwise.
1511 */
46f25451 1512 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1513 CSR_WRITE_2(sc, RL_IMR, 0);
1514 else
1515#endif /* DEVICE_POLLING */
1516 /*
1517 * Enable interrupts.
1518 */
1519 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1520
1521 /* Set initial TX threshold */
1522 sc->rl_txthresh = RL_TX_THRESH_INIT;
1523
1524 /* Start RX/TX process. */
1525 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1526
1527 /* Enable receiver and transmitter. */
1528 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1529
1530 mii_mediachg(mii);
1531
1532 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1533
1534 ifp->if_flags |= IFF_RUNNING;
1535 ifp->if_flags &= ~IFF_OACTIVE;
1536
b3a81bea 1537 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
a3fbe745
JS
1538
1539 crit_exit();
984263bc
MD
1540}
1541
1542/*
1543 * Set media options.
1544 */
ca59556a
JS
1545static int
1546rl_ifmedia_upd(struct ifnet *ifp)
984263bc 1547{
ca59556a
JS
1548 struct rl_softc *sc;
1549 struct mii_data *mii;
984263bc
MD
1550
1551 sc = ifp->if_softc;
1552 mii = device_get_softc(sc->rl_miibus);
1553 mii_mediachg(mii);
1554
1555 return(0);
1556}
1557
1558/*
1559 * Report current media status.
1560 */
ca59556a
JS
1561static void
1562rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1563{
ca59556a
JS
1564 struct rl_softc *sc = ifp->if_softc;
1565 struct mii_data *mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1566
1567 mii_pollstat(mii);
1568 ifmr->ifm_active = mii->mii_media_active;
1569 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1570}
1571
ca59556a
JS
1572static int
1573rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1574{
ca59556a
JS
1575 struct rl_softc *sc = ifp->if_softc;
1576 struct ifreq *ifr = (struct ifreq *) data;
1577 struct mii_data *mii;
a3fbe745 1578 int error = 0;
984263bc 1579
a3fbe745 1580 crit_enter();
984263bc 1581
ca59556a 1582 switch (command) {
984263bc
MD
1583 case SIOCSIFFLAGS:
1584 if (ifp->if_flags & IFF_UP) {
1585 rl_init(sc);
1586 } else {
1587 if (ifp->if_flags & IFF_RUNNING)
1588 rl_stop(sc);
1589 }
1590 error = 0;
1591 break;
1592 case SIOCADDMULTI:
1593 case SIOCDELMULTI:
1594 rl_setmulti(sc);
1595 error = 0;
1596 break;
1597 case SIOCGIFMEDIA:
1598 case SIOCSIFMEDIA:
1599 mii = device_get_softc(sc->rl_miibus);
1600 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1601 break;
ca59556a 1602 case SIOCSIFCAP:
ca59556a 1603 break;
984263bc 1604 default:
ca59556a 1605 error = ether_ioctl(ifp, command, data);
984263bc
MD
1606 break;
1607 }
1608
a3fbe745 1609 crit_exit();
984263bc
MD
1610
1611 return(error);
1612}
1613
ca59556a
JS
1614static void
1615rl_watchdog(struct ifnet *ifp)
984263bc 1616{
ca59556a 1617 struct rl_softc *sc = ifp->if_softc;
984263bc 1618
ca59556a 1619 device_printf(sc->rl_dev, "watchdog timeout\n");
a3fbe745
JS
1620
1621 crit_enter();
1622
984263bc
MD
1623 ifp->if_oerrors++;
1624
1625 rl_txeof(sc);
1626 rl_rxeof(sc);
1627 rl_init(sc);
1628
a3fbe745 1629 crit_exit();
984263bc
MD
1630}
1631
1632/*
1633 * Stop the adapter and free any mbufs allocated to the
1634 * RX and TX lists.
1635 */
ca59556a
JS
1636static void
1637rl_stop(struct rl_softc *sc)
984263bc 1638{
ca59556a
JS
1639 struct ifnet *ifp = &sc->arpcom.ac_if;
1640 int i;
984263bc 1641
984263bc
MD
1642 ifp->if_timer = 0;
1643
b3a81bea 1644 callout_stop(&sc->rl_stat_timer);
984263bc 1645 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1646
1647 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1648 CSR_WRITE_2(sc, RL_IMR, 0x0000);
ca59556a 1649 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
984263bc
MD
1650
1651 /*
1652 * Free the TX list buffers.
1653 */
1654 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1655 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
ca59556a
JS
1656 bus_dmamap_unload(sc->rl_tag,
1657 sc->rl_cdata.rl_tx_dmamap[i]);
1658 bus_dmamap_destroy(sc->rl_tag,
1659 sc->rl_cdata.rl_tx_dmamap[i]);
984263bc
MD
1660 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1661 sc->rl_cdata.rl_tx_chain[i] = NULL;
ca59556a
JS
1662 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1663 0x0000000);
984263bc
MD
1664 }
1665 }
984263bc
MD
1666}
1667
1668/*
1669 * Stop all chip I/O so that the kernel's probe routines don't
1670 * get confused by errant DMAs when rebooting.
1671 */
ca59556a
JS
1672static void
1673rl_shutdown(device_t dev)
984263bc 1674{
ca59556a 1675 struct rl_softc *sc;
984263bc
MD
1676
1677 sc = device_get_softc(dev);
1678
1679 rl_stop(sc);
984263bc
MD
1680}
1681
1682/*
1683 * Device suspend routine. Stop the interface and save some PCI
1684 * settings in case the BIOS doesn't restore them properly on
1685 * resume.
1686 */
ca59556a
JS
1687static int
1688rl_suspend(device_t dev)
984263bc 1689{
ca59556a
JS
1690 struct rl_softc *sc = device_get_softc(dev);
1691 int i;
984263bc
MD
1692
1693 rl_stop(sc);
1694
1695 for (i = 0; i < 5; i++)
ca59556a 1696 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
984263bc
MD
1697 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1698 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1699 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1700 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1701
1702 sc->suspended = 1;
1703
1704 return (0);
1705}
1706
1707/*
1708 * Device resume routine. Restore some PCI settings in case the BIOS
1709 * doesn't, re-enable busmastering, and restart the interface if
1710 * appropriate.
1711 */
ca59556a 1712static int rl_resume(device_t dev)
984263bc 1713{
ca59556a
JS
1714 struct rl_softc *sc = device_get_softc(dev);
1715 struct ifnet *ifp = &sc->arpcom.ac_if;
3d0f5f54 1716 int i;
984263bc
MD
1717
1718 /* better way to do this? */
1719 for (i = 0; i < 5; i++)
ca59556a 1720 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
984263bc
MD
1721 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1722 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1723 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1724 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1725
1726 /* reenable busmastering */
1727 pci_enable_busmaster(dev);
1728 pci_enable_io(dev, RL_RES);
1729
1730 /* reinitialize interface if necessary */
1731 if (ifp->if_flags & IFF_UP)
1732 rl_init(sc);
1733
1734 sc->suspended = 0;
1735
1736 return (0);
1737}