igb: Change TXCSUM does not require reinitialize hardware
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
CommitLineData
1f7e3916
SZ
1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "opt_polling.h"
8d6600da 33#include "opt_igb.h"
1f7e3916
SZ
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/interrupt.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/serialize2.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <sys/sysctl.h>
49#include <sys/systm.h>
50
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/ifq_var.h>
58#include <net/toeplitz.h>
59#include <net/toeplitz2.h>
60#include <net/vlan/if_vlan_var.h>
61#include <net/vlan/if_vlan_ether.h>
62#include <net/if_poll.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <bus/pci/pcivar.h>
71#include <bus/pci/pcireg.h>
72
73#include <dev/netif/ig_hal/e1000_api.h>
74#include <dev/netif/ig_hal/e1000_82575.h>
75#include <dev/netif/igb/if_igb.h>
76
8d6600da
SZ
77#ifdef IGB_RSS_DEBUG
78#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79do { \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82} while (0)
83#else /* !IGB_RSS_DEBUG */
84#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85#endif /* IGB_RSS_DEBUG */
86
1f7e3916
SZ
87#define IGB_NAME "Intel(R) PRO/1000 "
88#define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90#define IGB_DEVICE_NULL { 0, 0, NULL }
91
92static struct igb_device {
93 uint16_t vid;
94 uint16_t did;
95 const char *desc;
96} igb_devices[] = {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
123 IGB_DEVICE(I350_VF),
124
125 /* required last entry */
126 IGB_DEVICE_NULL
127};
128
129static int igb_probe(device_t);
130static int igb_attach(device_t);
131static int igb_detach(device_t);
132static int igb_shutdown(device_t);
133static int igb_suspend(device_t);
134static int igb_resume(device_t);
135
136static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137static void igb_setup_ifp(struct igb_softc *);
48faa653 138static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
1f7e3916
SZ
139static void igb_add_sysctl(struct igb_softc *);
140static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
9c0ecdcc 141static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
b6220144 142static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
9c0ecdcc 143static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
1f7e3916
SZ
144
145static void igb_vf_init_stats(struct igb_softc *);
146static void igb_reset(struct igb_softc *);
147static void igb_update_stats_counters(struct igb_softc *);
148static void igb_update_vf_stats_counters(struct igb_softc *);
149static void igb_update_link_status(struct igb_softc *);
150static void igb_init_tx_unit(struct igb_softc *);
151static void igb_init_rx_unit(struct igb_softc *);
152
153static void igb_set_vlan(struct igb_softc *);
154static void igb_set_multi(struct igb_softc *);
155static void igb_set_promisc(struct igb_softc *);
156static void igb_disable_promisc(struct igb_softc *);
157
a619b256
SZ
158static int igb_alloc_rings(struct igb_softc *);
159static void igb_free_rings(struct igb_softc *);
1f7e3916
SZ
160static int igb_create_tx_ring(struct igb_tx_ring *);
161static int igb_create_rx_ring(struct igb_rx_ring *);
162static void igb_free_tx_ring(struct igb_tx_ring *);
163static void igb_free_rx_ring(struct igb_rx_ring *);
164static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
165static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
166static void igb_init_tx_ring(struct igb_tx_ring *);
167static int igb_init_rx_ring(struct igb_rx_ring *);
168static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
169static int igb_encap(struct igb_tx_ring *, struct mbuf **);
170
171static void igb_stop(struct igb_softc *);
172static void igb_init(void *);
173static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
174static void igb_media_status(struct ifnet *, struct ifmediareq *);
175static int igb_media_change(struct ifnet *);
176static void igb_timer(void *);
177static void igb_watchdog(struct ifnet *);
178static void igb_start(struct ifnet *);
179#ifdef DEVICE_POLLING
180static void igb_poll(struct ifnet *, enum poll_cmd, int);
181#endif
7d235eb5
SZ
182static void igb_serialize(struct ifnet *, enum ifnet_serialize);
183static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
184static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
185#ifdef INVARIANTS
186static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
187 boolean_t);
188#endif
1f7e3916
SZ
189
190static void igb_intr(void *);
9c0ecdcc 191static void igb_intr_shared(void *);
1f7e3916
SZ
192static void igb_rxeof(struct igb_rx_ring *, int);
193static void igb_txeof(struct igb_tx_ring *);
9c0ecdcc 194static void igb_set_eitr(struct igb_softc *, int, int);
1f7e3916
SZ
195static void igb_enable_intr(struct igb_softc *);
196static void igb_disable_intr(struct igb_softc *);
f6167a56
SZ
197static void igb_init_unshared_intr(struct igb_softc *);
198static void igb_init_intr(struct igb_softc *);
199static int igb_setup_intr(struct igb_softc *);
9c0ecdcc
SZ
200static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
201static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
be922da6 202static void igb_set_intr_mask(struct igb_softc *);
3c7cc5e2
SZ
203static int igb_alloc_intr(struct igb_softc *);
204static void igb_free_intr(struct igb_softc *);
9c0ecdcc
SZ
205static void igb_teardown_intr(struct igb_softc *);
206static void igb_msix_try_alloc(struct igb_softc *);
207static void igb_msix_free(struct igb_softc *, boolean_t);
208static int igb_msix_setup(struct igb_softc *);
209static void igb_msix_teardown(struct igb_softc *, int);
210static void igb_msix_rx(void *);
211static void igb_msix_tx(void *);
212static void igb_msix_status(void *);
1f7e3916
SZ
213
214/* Management and WOL Support */
215static void igb_get_mgmt(struct igb_softc *);
216static void igb_rel_mgmt(struct igb_softc *);
217static void igb_get_hw_control(struct igb_softc *);
73a4e8ed
SZ
218static void igb_rel_hw_control(struct igb_softc *);
219static void igb_enable_wol(device_t);
1f7e3916
SZ
220
221static device_method_t igb_methods[] = {
222 /* Device interface */
223 DEVMETHOD(device_probe, igb_probe),
224 DEVMETHOD(device_attach, igb_attach),
225 DEVMETHOD(device_detach, igb_detach),
226 DEVMETHOD(device_shutdown, igb_shutdown),
227 DEVMETHOD(device_suspend, igb_suspend),
228 DEVMETHOD(device_resume, igb_resume),
229 { 0, 0 }
230};
231
232static driver_t igb_driver = {
233 "igb",
234 igb_methods,
235 sizeof(struct igb_softc),
236};
237
238static devclass_t igb_devclass;
239
240DECLARE_DUMMY_MODULE(if_igb);
241MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
242DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
243
244static int igb_rxd = IGB_DEFAULT_RXD;
245static int igb_txd = IGB_DEFAULT_TXD;
8d6600da 246static int igb_rxr = 0;
1f7e3916
SZ
247static int igb_msi_enable = 1;
248static int igb_msix_enable = 1;
249static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
250static int igb_fc_setting = e1000_fc_full;
251
252/*
253 * DMA Coalescing, only for i350 - default to off,
254 * this feature is for power savings
255 */
256static int igb_dma_coalesce = 0;
257
258TUNABLE_INT("hw.igb.rxd", &igb_rxd);
259TUNABLE_INT("hw.igb.txd", &igb_txd);
8d6600da 260TUNABLE_INT("hw.igb.rxr", &igb_rxr);
1f7e3916
SZ
261TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
262TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
263TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
264
265/* i350 specific */
266TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
267TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
268
269static __inline void
270igb_rxcsum(uint32_t staterr, struct mbuf *mp)
271{
272 /* Ignore Checksum bit is set */
273 if (staterr & E1000_RXD_STAT_IXSM)
274 return;
275
276 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
277 E1000_RXD_STAT_IPCS)
278 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
279
280 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
281 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
282 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
283 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
284 mp->m_pkthdr.csum_data = htons(0xffff);
285 }
286 }
287}
288
8d6600da
SZ
289static __inline struct pktinfo *
290igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
291 uint32_t hash, uint32_t hashtype, uint32_t staterr)
292{
293 switch (hashtype) {
294 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
295 pi->pi_netisr = NETISR_IP;
296 pi->pi_flags = 0;
297 pi->pi_l3proto = IPPROTO_TCP;
298 break;
299
300 case E1000_RXDADV_RSSTYPE_IPV4:
301 if (staterr & E1000_RXD_STAT_IXSM)
302 return NULL;
303
304 if ((staterr &
305 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
306 E1000_RXD_STAT_TCPCS) {
307 pi->pi_netisr = NETISR_IP;
308 pi->pi_flags = 0;
309 pi->pi_l3proto = IPPROTO_UDP;
310 break;
311 }
312 /* FALL THROUGH */
313 default:
314 return NULL;
315 }
316
317 m->m_flags |= M_HASH;
318 m->m_pkthdr.hash = toeplitz_hash(hash);
319 return pi;
320}
321
1f7e3916
SZ
322static int
323igb_probe(device_t dev)
324{
325 const struct igb_device *d;
326 uint16_t vid, did;
327
328 vid = pci_get_vendor(dev);
329 did = pci_get_device(dev);
330
331 for (d = igb_devices; d->desc != NULL; ++d) {
332 if (vid == d->vid && did == d->did) {
333 device_set_desc(dev, d->desc);
334 return 0;
335 }
336 }
337 return ENXIO;
338}
339
340static int
341igb_attach(device_t dev)
342{
343 struct igb_softc *sc = device_get_softc(dev);
1f7e3916 344 uint16_t eeprom_data;
8d6600da 345 int error = 0, i, j, ring_max;
1f7e3916
SZ
346
347#ifdef notyet
348 /* SYSCTL stuff */
349 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
350 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
351 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
352 igb_sysctl_nvm_info, "I", "NVM Information");
353
354 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
355 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
356 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
357 &igb_enable_aim, 1, "Interrupt Moderation");
358
359 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
360 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
361 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
362 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
363#endif
364
365 callout_init_mp(&sc->timer);
9c0ecdcc 366 lwkt_serialize_init(&sc->main_serialize);
1f7e3916
SZ
367
368 sc->dev = sc->osdep.dev = dev;
369
370 /*
371 * Determine hardware and mac type
372 */
373 sc->hw.vendor_id = pci_get_vendor(dev);
374 sc->hw.device_id = pci_get_device(dev);
375 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
376 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
377 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
378
379 if (e1000_set_mac_type(&sc->hw))
380 return ENXIO;
381
382 /* Are we a VF device? */
383 if (sc->hw.mac.type == e1000_vfadapt ||
384 sc->hw.mac.type == e1000_vfadapt_i350)
385 sc->vf_ifp = 1;
386 else
387 sc->vf_ifp = 0;
388
9b7aa975
SZ
389 /*
390 * Configure total supported RX/TX ring count
391 */
392 switch (sc->hw.mac.type) {
393 case e1000_82575:
394 ring_max = IGB_MAX_RING_82575;
395 break;
396 case e1000_82580:
397 ring_max = IGB_MAX_RING_82580;
398 break;
399 case e1000_i350:
400 ring_max = IGB_MAX_RING_I350;
401 break;
402 case e1000_82576:
403 ring_max = IGB_MAX_RING_82576;
404 break;
405 default:
406 ring_max = IGB_MIN_RING;
407 break;
408 }
409 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
410 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
411#ifdef IGB_RSS_DEBUG
412 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
413#endif
414 sc->rx_ring_inuse = sc->rx_ring_cnt;
415 sc->tx_ring_cnt = 1; /* XXX */
416
1f7e3916
SZ
417 /* Enable bus mastering */
418 pci_enable_busmaster(dev);
419
420 /*
421 * Allocate IO memory
422 */
423 sc->mem_rid = PCIR_BAR(0);
424 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
425 RF_ACTIVE);
426 if (sc->mem_res == NULL) {
427 device_printf(dev, "Unable to allocate bus resource: memory\n");
428 error = ENXIO;
429 goto failed;
430 }
431 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
432 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
433
434 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
435
1f7e3916
SZ
436 /* Save PCI command register for Shared Code */
437 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
438 sc->hw.back = &sc->osdep;
439
1f7e3916
SZ
440 /* Do Shared Code initialization */
441 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
442 device_printf(dev, "Setup of Shared code failed\n");
443 error = ENXIO;
444 goto failed;
445 }
446
447 e1000_get_bus_info(&sc->hw);
448
449 sc->hw.mac.autoneg = DO_AUTO_NEG;
450 sc->hw.phy.autoneg_wait_to_complete = FALSE;
451 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
452
453 /* Copper options */
454 if (sc->hw.phy.media_type == e1000_media_type_copper) {
455 sc->hw.phy.mdix = AUTO_ALL_MODES;
456 sc->hw.phy.disable_polarity_correction = FALSE;
457 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
458 }
459
460 /* Set the frame limits assuming standard ethernet sized frames. */
461 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
1f7e3916 462
a619b256
SZ
463 /* Allocate RX/TX rings */
464 error = igb_alloc_rings(sc);
1f7e3916
SZ
465 if (error)
466 goto failed;
467
3c7cc5e2
SZ
468 /* Allocate interrupt */
469 error = igb_alloc_intr(sc);
470 if (error)
a1647e40 471 goto failed;
a1647e40
SZ
472
473 /*
7d235eb5
SZ
474 * Setup serializers
475 */
7d235eb5
SZ
476 i = 0;
477 sc->serializes[i++] = &sc->main_serialize;
478
479 sc->tx_serialize = i;
480 for (j = 0; j < sc->tx_ring_cnt; ++j)
481 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
482
483 sc->rx_serialize = i;
484 for (j = 0; j < sc->rx_ring_cnt; ++j)
485 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
486
487 sc->serialize_cnt = i;
488 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
489
1f7e3916
SZ
490 /* Allocate the appropriate stats memory */
491 if (sc->vf_ifp) {
492 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
493 M_WAITOK | M_ZERO);
494 igb_vf_init_stats(sc);
495 } else {
496 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
497 M_WAITOK | M_ZERO);
498 }
499
500 /* Allocate multicast array memory. */
501 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
502 M_DEVBUF, M_WAITOK);
503
504 /* Some adapter-specific advanced features */
505 if (sc->hw.mac.type >= e1000_i350) {
506#ifdef notyet
507 igb_set_sysctl_value(adapter, "dma_coalesce",
508 "configure dma coalesce",
509 &adapter->dma_coalesce, igb_dma_coalesce);
510 igb_set_sysctl_value(adapter, "eee_disabled",
511 "enable Energy Efficient Ethernet",
512 &adapter->hw.dev_spec._82575.eee_disable,
513 igb_eee_disabled);
514#else
515 sc->dma_coalesce = igb_dma_coalesce;
516 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
517#endif
518 e1000_set_eee_i350(&sc->hw);
519 }
520
521 /*
522 * Start from a known state, this is important in reading the nvm and
523 * mac from that.
524 */
525 e1000_reset_hw(&sc->hw);
526
527 /* Make sure we have a good EEPROM before we read from it */
528 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
529 /*
530 * Some PCI-E parts fail the first check due to
531 * the link being in sleep state, call it again,
532 * if it fails a second time its a real issue.
533 */
534 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
535 device_printf(dev,
536 "The EEPROM Checksum Is Not Valid\n");
537 error = EIO;
538 goto failed;
539 }
540 }
541
542 /* Copy the permanent MAC address out of the EEPROM */
543 if (e1000_read_mac_addr(&sc->hw) < 0) {
544 device_printf(dev, "EEPROM read error while reading MAC"
545 " address\n");
546 error = EIO;
547 goto failed;
548 }
549 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
550 device_printf(dev, "Invalid MAC address\n");
551 error = EIO;
552 goto failed;
553 }
554
555#ifdef notyet
556 /*
557 ** Configure Interrupts
558 */
559 if ((adapter->msix > 1) && (igb_enable_msix))
560 error = igb_allocate_msix(adapter);
561 else /* MSI or Legacy */
562 error = igb_allocate_legacy(adapter);
563 if (error)
564 goto err_late;
565#endif
566
567 /* Setup OS specific network interface */
568 igb_setup_ifp(sc);
569
570 /* Add sysctl tree, must after igb_setup_ifp() */
571 igb_add_sysctl(sc);
572
573 /* Now get a good starting state */
574 igb_reset(sc);
575
576 /* Initialize statistics */
577 igb_update_stats_counters(sc);
578
579 sc->hw.mac.get_link_status = 1;
580 igb_update_link_status(sc);
581
582 /* Indicate SOL/IDER usage */
583 if (e1000_check_reset_block(&sc->hw)) {
584 device_printf(dev,
585 "PHY reset is blocked due to SOL/IDER session.\n");
586 }
587
588 /* Determine if we have to control management hardware */
396b7048
SZ
589 if (e1000_enable_mng_pass_thru(&sc->hw))
590 sc->flags |= IGB_FLAG_HAS_MGMT;
1f7e3916
SZ
591
592 /*
593 * Setup Wake-on-Lan
594 */
595 /* APME bit in EEPROM is mapped to WUC.APME */
596 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
597 if (eeprom_data)
598 sc->wol = E1000_WUFC_MAG;
599 /* XXX disable WOL */
600 sc->wol = 0;
601
602#ifdef notyet
603 /* Register for VLAN events */
604 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
605 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
606 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
607 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
608#endif
609
610#ifdef notyet
611 igb_add_hw_stats(adapter);
612#endif
613
f6167a56 614 error = igb_setup_intr(sc);
1f7e3916 615 if (error) {
1f7e3916
SZ
616 ether_ifdetach(&sc->arpcom.ac_if);
617 goto failed;
618 }
1f7e3916
SZ
619 return 0;
620
621failed:
622 igb_detach(dev);
623 return error;
624}
625
626static int
627igb_detach(device_t dev)
628{
629 struct igb_softc *sc = device_get_softc(dev);
630
631 if (device_is_attached(dev)) {
632 struct ifnet *ifp = &sc->arpcom.ac_if;
633
634 ifnet_serialize_all(ifp);
635
636 igb_stop(sc);
637
638 e1000_phy_hw_reset(&sc->hw);
639
640 /* Give control back to firmware */
641 igb_rel_mgmt(sc);
642 igb_rel_hw_control(sc);
643
644 if (sc->wol) {
645 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
646 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
647 igb_enable_wol(dev);
648 }
649
9c0ecdcc 650 igb_teardown_intr(sc);
1f7e3916
SZ
651
652 ifnet_deserialize_all(ifp);
653
654 ether_ifdetach(ifp);
655 } else if (sc->mem_res != NULL) {
656 igb_rel_hw_control(sc);
657 }
658 bus_generic_detach(dev);
659
9c0ecdcc
SZ
660 if (sc->sysctl_tree != NULL)
661 sysctl_ctx_free(&sc->sysctl_ctx);
662
3c7cc5e2 663 igb_free_intr(sc);
1f7e3916 664
9c0ecdcc
SZ
665 if (sc->msix_mem_res != NULL) {
666 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
667 sc->msix_mem_res);
668 }
1f7e3916
SZ
669 if (sc->mem_res != NULL) {
670 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
671 sc->mem_res);
672 }
673
a619b256 674 igb_free_rings(sc);
1f7e3916
SZ
675
676 if (sc->mta != NULL)
677 kfree(sc->mta, M_DEVBUF);
678 if (sc->stats != NULL)
679 kfree(sc->stats, M_DEVBUF);
680
1f7e3916
SZ
681 return 0;
682}
683
684static int
685igb_shutdown(device_t dev)
686{
687 return igb_suspend(dev);
688}
689
690static int
691igb_suspend(device_t dev)
692{
693 struct igb_softc *sc = device_get_softc(dev);
694 struct ifnet *ifp = &sc->arpcom.ac_if;
695
696 ifnet_serialize_all(ifp);
697
698 igb_stop(sc);
699
700 igb_rel_mgmt(sc);
701 igb_rel_hw_control(sc);
702
703 if (sc->wol) {
704 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
705 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
706 igb_enable_wol(dev);
707 }
708
709 ifnet_deserialize_all(ifp);
710
711 return bus_generic_suspend(dev);
712}
713
714static int
715igb_resume(device_t dev)
716{
717 struct igb_softc *sc = device_get_softc(dev);
718 struct ifnet *ifp = &sc->arpcom.ac_if;
719
720 ifnet_serialize_all(ifp);
721
722 igb_init(sc);
723 igb_get_mgmt(sc);
724
725 if_devstart(ifp);
726
727 ifnet_deserialize_all(ifp);
728
729 return bus_generic_resume(dev);
730}
731
732static int
733igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
734{
735 struct igb_softc *sc = ifp->if_softc;
736 struct ifreq *ifr = (struct ifreq *)data;
737 int max_frame_size, mask, reinit;
738 int error = 0;
739
740 ASSERT_IFNET_SERIALIZED_ALL(ifp);
741
742 switch (command) {
743 case SIOCSIFMTU:
744 max_frame_size = 9234;
745 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
746 ETHER_CRC_LEN) {
747 error = EINVAL;
748 break;
749 }
750
751 ifp->if_mtu = ifr->ifr_mtu;
752 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
753 ETHER_CRC_LEN;
754
755 if (ifp->if_flags & IFF_RUNNING)
756 igb_init(sc);
757 break;
758
759 case SIOCSIFFLAGS:
760 if (ifp->if_flags & IFF_UP) {
761 if (ifp->if_flags & IFF_RUNNING) {
762 if ((ifp->if_flags ^ sc->if_flags) &
763 (IFF_PROMISC | IFF_ALLMULTI)) {
764 igb_disable_promisc(sc);
765 igb_set_promisc(sc);
766 }
767 } else {
768 igb_init(sc);
769 }
770 } else if (ifp->if_flags & IFF_RUNNING) {
771 igb_stop(sc);
772 }
773 sc->if_flags = ifp->if_flags;
774 break;
775
776 case SIOCADDMULTI:
777 case SIOCDELMULTI:
778 if (ifp->if_flags & IFF_RUNNING) {
779 igb_disable_intr(sc);
780 igb_set_multi(sc);
781#ifdef DEVICE_POLLING
782 if (!(ifp->if_flags & IFF_POLLING))
783#endif
784 igb_enable_intr(sc);
785 }
786 break;
787
788 case SIOCSIFMEDIA:
789 /*
790 * As the speed/duplex settings are being
791 * changed, we need toreset the PHY.
792 */
793 sc->hw.phy.reset_disable = FALSE;
794
795 /* Check SOL/IDER usage */
796 if (e1000_check_reset_block(&sc->hw)) {
797 if_printf(ifp, "Media change is "
798 "blocked due to SOL/IDER session.\n");
799 break;
800 }
801 /* FALL THROUGH */
802
803 case SIOCGIFMEDIA:
804 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
805 break;
806
807 case SIOCSIFCAP:
808 reinit = 0;
809 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
77d8cab9
SZ
810 if (mask & IFCAP_RXCSUM) {
811 ifp->if_capenable ^= IFCAP_RXCSUM;
1f7e3916
SZ
812 reinit = 1;
813 }
814 if (mask & IFCAP_VLAN_HWTAGGING) {
815 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
816 reinit = 1;
817 }
77d8cab9
SZ
818 if (mask & IFCAP_TXCSUM) {
819 ifp->if_capenable ^= IFCAP_TXCSUM;
820 if (ifp->if_capenable & IFCAP_TXCSUM)
821 ifp->if_hwassist |= IGB_CSUM_FEATURES;
822 else
823 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
824 }
8d6600da
SZ
825 if (mask & IFCAP_RSS)
826 ifp->if_capenable ^= IFCAP_RSS;
1f7e3916
SZ
827 if (reinit && (ifp->if_flags & IFF_RUNNING))
828 igb_init(sc);
829 break;
830
831 default:
832 error = ether_ioctl(ifp, command, data);
833 break;
834 }
835 return error;
836}
837
838static void
839igb_init(void *xsc)
840{
841 struct igb_softc *sc = xsc;
842 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 843 boolean_t polling;
1f7e3916
SZ
844 int i;
845
846 ASSERT_IFNET_SERIALIZED_ALL(ifp);
847
848 igb_stop(sc);
849
850 /* Get the latest mac address, User can use a LAA */
851 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
852
853 /* Put the address into the Receive Address Array */
854 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
855
856 igb_reset(sc);
857 igb_update_link_status(sc);
858
859 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
860
1f7e3916
SZ
861 /* Configure for OS presence */
862 igb_get_mgmt(sc);
863
9c0ecdcc 864 polling = FALSE;
be922da6 865#ifdef DEVICE_POLLING
9c0ecdcc
SZ
866 if (ifp->if_flags & IFF_POLLING)
867 polling = TRUE;
be922da6 868#endif
9c0ecdcc
SZ
869
870 /* Configured used RX/TX rings */
871 igb_set_ring_inuse(sc, polling);
872
873 /* Initialize interrupt */
874 igb_init_intr(sc);
be922da6 875
1f7e3916 876 /* Prepare transmit descriptors and buffers */
27866bf1 877 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916
SZ
878 igb_init_tx_ring(&sc->tx_rings[i]);
879 igb_init_tx_unit(sc);
880
881 /* Setup Multicast table */
882 igb_set_multi(sc);
883
884#if 0
885 /*
886 * Figure out the desired mbuf pool
887 * for doing jumbo/packetsplit
888 */
889 if (adapter->max_frame_size <= 2048)
890 adapter->rx_mbuf_sz = MCLBYTES;
891 else if (adapter->max_frame_size <= 4096)
892 adapter->rx_mbuf_sz = MJUMPAGESIZE;
893 else
894 adapter->rx_mbuf_sz = MJUM9BYTES;
1f7e3916
SZ
895#endif
896
897 /* Prepare receive descriptors and buffers */
be922da6 898 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
899 int error;
900
901 error = igb_init_rx_ring(&sc->rx_rings[i]);
902 if (error) {
903 if_printf(ifp, "Could not setup receive structures\n");
904 igb_stop(sc);
905 return;
906 }
907 }
908 igb_init_rx_unit(sc);
909
910 /* Enable VLAN support */
911 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
912 igb_set_vlan(sc);
913
914 /* Don't lose promiscuous settings */
915 igb_set_promisc(sc);
916
1f7e3916
SZ
917 ifp->if_flags |= IFF_RUNNING;
918 ifp->if_flags &= ~IFF_OACTIVE;
919
920 callout_reset(&sc->timer, hz, igb_timer, sc);
921 e1000_clear_hw_cntrs_base_generic(&sc->hw);
922
923#if 0
924 if (adapter->msix > 1) /* Set up queue routing */
925 igb_configure_queues(adapter);
926#endif
927
9c0ecdcc 928 /* This clears any pending interrupts */
1f7e3916 929 E1000_READ_REG(&sc->hw, E1000_ICR);
9c0ecdcc 930
1f7e3916
SZ
931 /*
932 * Only enable interrupts if we are not polling, make sure
933 * they are off otherwise.
934 */
9c0ecdcc 935 if (polling) {
1f7e3916 936 igb_disable_intr(sc);
9c0ecdcc 937 } else {
1f7e3916
SZ
938 igb_enable_intr(sc);
939 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
940 }
941
942 /* Set Energy Efficient Ethernet */
943 e1000_set_eee_i350(&sc->hw);
944
945 /* Don't reset the phy next time init gets called */
946 sc->hw.phy.reset_disable = TRUE;
947}
948
949static void
950igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
951{
952 struct igb_softc *sc = ifp->if_softc;
953 u_char fiber_type = IFM_1000_SX;
954
955 ASSERT_IFNET_SERIALIZED_ALL(ifp);
956
957 igb_update_link_status(sc);
958
959 ifmr->ifm_status = IFM_AVALID;
960 ifmr->ifm_active = IFM_ETHER;
961
962 if (!sc->link_active)
963 return;
964
965 ifmr->ifm_status |= IFM_ACTIVE;
966
967 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
968 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
969 ifmr->ifm_active |= fiber_type | IFM_FDX;
970 } else {
971 switch (sc->link_speed) {
972 case 10:
973 ifmr->ifm_active |= IFM_10_T;
974 break;
975
976 case 100:
977 ifmr->ifm_active |= IFM_100_TX;
978 break;
979
980 case 1000:
981 ifmr->ifm_active |= IFM_1000_T;
982 break;
983 }
984 if (sc->link_duplex == FULL_DUPLEX)
985 ifmr->ifm_active |= IFM_FDX;
986 else
987 ifmr->ifm_active |= IFM_HDX;
988 }
989}
990
991static int
992igb_media_change(struct ifnet *ifp)
993{
994 struct igb_softc *sc = ifp->if_softc;
995 struct ifmedia *ifm = &sc->media;
996
997 ASSERT_IFNET_SERIALIZED_ALL(ifp);
998
999 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1000 return EINVAL;
1001
1002 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1003 case IFM_AUTO:
1004 sc->hw.mac.autoneg = DO_AUTO_NEG;
1005 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1006 break;
1007
1008 case IFM_1000_LX:
1009 case IFM_1000_SX:
1010 case IFM_1000_T:
1011 sc->hw.mac.autoneg = DO_AUTO_NEG;
1012 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1013 break;
1014
1015 case IFM_100_TX:
1016 sc->hw.mac.autoneg = FALSE;
1017 sc->hw.phy.autoneg_advertised = 0;
1018 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1019 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1020 else
1021 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1022 break;
1023
1024 case IFM_10_T:
1025 sc->hw.mac.autoneg = FALSE;
1026 sc->hw.phy.autoneg_advertised = 0;
1027 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1028 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1029 else
1030 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1031 break;
1032
1033 default:
1034 if_printf(ifp, "Unsupported media type\n");
1035 break;
1036 }
1037
1038 igb_init(sc);
1039
1040 return 0;
1041}
1042
1043static void
1044igb_set_promisc(struct igb_softc *sc)
1045{
1046 struct ifnet *ifp = &sc->arpcom.ac_if;
1047 struct e1000_hw *hw = &sc->hw;
1048 uint32_t reg;
1049
1050 if (sc->vf_ifp) {
1051 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1052 return;
1053 }
1054
1055 reg = E1000_READ_REG(hw, E1000_RCTL);
1056 if (ifp->if_flags & IFF_PROMISC) {
1057 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1058 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1059 } else if (ifp->if_flags & IFF_ALLMULTI) {
1060 reg |= E1000_RCTL_MPE;
1061 reg &= ~E1000_RCTL_UPE;
1062 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1063 }
1064}
1065
1066static void
1067igb_disable_promisc(struct igb_softc *sc)
1068{
1069 struct e1000_hw *hw = &sc->hw;
1070 uint32_t reg;
1071
1072 if (sc->vf_ifp) {
1073 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1074 return;
1075 }
1076 reg = E1000_READ_REG(hw, E1000_RCTL);
1077 reg &= ~E1000_RCTL_UPE;
1078 reg &= ~E1000_RCTL_MPE;
1079 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1080}
1081
1082static void
1083igb_set_multi(struct igb_softc *sc)
1084{
1085 struct ifnet *ifp = &sc->arpcom.ac_if;
1086 struct ifmultiaddr *ifma;
1087 uint32_t reg_rctl = 0;
1088 uint8_t *mta;
1089 int mcnt = 0;
1090
1091 mta = sc->mta;
1092 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1093
1094 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1095 if (ifma->ifma_addr->sa_family != AF_LINK)
1096 continue;
1097
1098 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1099 break;
1100
1101 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1102 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1103 mcnt++;
1104 }
1105
1106 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1107 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1108 reg_rctl |= E1000_RCTL_MPE;
1109 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1110 } else {
1111 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1112 }
1113}
1114
1115static void
1116igb_timer(void *xsc)
1117{
1118 struct igb_softc *sc = xsc;
1f7e3916 1119
27dd00d6 1120 lwkt_serialize_enter(&sc->main_serialize);
1f7e3916
SZ
1121
1122 igb_update_link_status(sc);
1123 igb_update_stats_counters(sc);
1124
1125 callout_reset(&sc->timer, hz, igb_timer, sc);
1126
27dd00d6 1127 lwkt_serialize_exit(&sc->main_serialize);
1f7e3916
SZ
1128}
1129
1130static void
1131igb_update_link_status(struct igb_softc *sc)
1132{
1133 struct ifnet *ifp = &sc->arpcom.ac_if;
1134 struct e1000_hw *hw = &sc->hw;
1135 uint32_t link_check, thstat, ctrl;
1136
1137 link_check = thstat = ctrl = 0;
1138
1139 /* Get the cached link value or read for real */
1140 switch (hw->phy.media_type) {
1141 case e1000_media_type_copper:
1142 if (hw->mac.get_link_status) {
1143 /* Do the work to read phy */
1144 e1000_check_for_link(hw);
1145 link_check = !hw->mac.get_link_status;
1146 } else {
1147 link_check = TRUE;
1148 }
1149 break;
1150
1151 case e1000_media_type_fiber:
1152 e1000_check_for_link(hw);
1153 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1154 break;
1155
1156 case e1000_media_type_internal_serdes:
1157 e1000_check_for_link(hw);
1158 link_check = hw->mac.serdes_has_link;
1159 break;
1160
1161 /* VF device is type_unknown */
1162 case e1000_media_type_unknown:
1163 e1000_check_for_link(hw);
1164 link_check = !hw->mac.get_link_status;
1165 /* Fall thru */
1166 default:
1167 break;
1168 }
1169
1170 /* Check for thermal downshift or shutdown */
1171 if (hw->mac.type == e1000_i350) {
1172 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1173 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1174 }
1175
1176 /* Now we check if a transition has happened */
1177 if (link_check && sc->link_active == 0) {
1178 e1000_get_speed_and_duplex(hw,
1179 &sc->link_speed, &sc->link_duplex);
1180 if (bootverbose) {
1181 if_printf(ifp, "Link is up %d Mbps %s\n",
1182 sc->link_speed,
1183 sc->link_duplex == FULL_DUPLEX ?
1184 "Full Duplex" : "Half Duplex");
1185 }
1186 sc->link_active = 1;
1187
1188 ifp->if_baudrate = sc->link_speed * 1000000;
1189 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1190 (thstat & E1000_THSTAT_LINK_THROTTLE))
1191 if_printf(ifp, "Link: thermal downshift\n");
1192 /* This can sleep */
1193 ifp->if_link_state = LINK_STATE_UP;
1194 if_link_state_change(ifp);
1195 } else if (!link_check && sc->link_active == 1) {
1196 ifp->if_baudrate = sc->link_speed = 0;
1197 sc->link_duplex = 0;
1198 if (bootverbose)
1199 if_printf(ifp, "Link is Down\n");
1200 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1201 (thstat & E1000_THSTAT_PWR_DOWN))
1202 if_printf(ifp, "Link: thermal shutdown\n");
1203 sc->link_active = 0;
1204 /* This can sleep */
1205 ifp->if_link_state = LINK_STATE_DOWN;
1206 if_link_state_change(ifp);
1207 }
1208}
1209
1210static void
1211igb_stop(struct igb_softc *sc)
1212{
1213 struct ifnet *ifp = &sc->arpcom.ac_if;
1214 int i;
1215
1216 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1217
1218 igb_disable_intr(sc);
1219
1220 callout_stop(&sc->timer);
1221
1222 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1223 ifp->if_timer = 0;
1224
1225 e1000_reset_hw(&sc->hw);
1226 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1227
1228 e1000_led_off(&sc->hw);
1229 e1000_cleanup_led(&sc->hw);
1230
27866bf1 1231 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916 1232 igb_free_tx_ring(&sc->tx_rings[i]);
27866bf1 1233 for (i = 0; i < sc->rx_ring_cnt; ++i)
1f7e3916
SZ
1234 igb_free_rx_ring(&sc->rx_rings[i]);
1235}
1236
1237static void
1238igb_reset(struct igb_softc *sc)
1239{
1240 struct ifnet *ifp = &sc->arpcom.ac_if;
1241 struct e1000_hw *hw = &sc->hw;
1242 struct e1000_fc_info *fc = &hw->fc;
1243 uint32_t pba = 0;
1244 uint16_t hwm;
1245
1246 /* Let the firmware know the OS is in control */
1247 igb_get_hw_control(sc);
1248
1249 /*
1250 * Packet Buffer Allocation (PBA)
1251 * Writing PBA sets the receive portion of the buffer
1252 * the remainder is used for the transmit buffer.
1253 */
1254 switch (hw->mac.type) {
1255 case e1000_82575:
1256 pba = E1000_PBA_32K;
1257 break;
1258
1259 case e1000_82576:
1260 case e1000_vfadapt:
1261 pba = E1000_READ_REG(hw, E1000_RXPBS);
1262 pba &= E1000_RXPBS_SIZE_MASK_82576;
1263 break;
1264
1265 case e1000_82580:
1266 case e1000_i350:
1267 case e1000_vfadapt_i350:
1268 pba = E1000_READ_REG(hw, E1000_RXPBS);
1269 pba = e1000_rxpbs_adjust_82580(pba);
1270 break;
1271 /* XXX pba = E1000_PBA_35K; */
1272
1273 default:
1274 break;
1275 }
1276
1277 /* Special needs in case of Jumbo frames */
1278 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1279 uint32_t tx_space, min_tx, min_rx;
1280
1281 pba = E1000_READ_REG(hw, E1000_PBA);
1282 tx_space = pba >> 16;
1283 pba &= 0xffff;
1284
1285 min_tx = (sc->max_frame_size +
1286 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1287 min_tx = roundup2(min_tx, 1024);
1288 min_tx >>= 10;
1289 min_rx = sc->max_frame_size;
1290 min_rx = roundup2(min_rx, 1024);
1291 min_rx >>= 10;
1292 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1293 pba = pba - (min_tx - tx_space);
1294 /*
1295 * if short on rx space, rx wins
1296 * and must trump tx adjustment
1297 */
1298 if (pba < min_rx)
1299 pba = min_rx;
1300 }
1301 E1000_WRITE_REG(hw, E1000_PBA, pba);
1302 }
1303
1304 /*
1305 * These parameters control the automatic generation (Tx) and
1306 * response (Rx) to Ethernet PAUSE frames.
1307 * - High water mark should allow for at least two frames to be
1308 * received after sending an XOFF.
1309 * - Low water mark works best when it is very near the high water mark.
1310 * This allows the receiver to restart by sending XON when it has
1311 * drained a bit.
1312 */
1313 hwm = min(((pba << 10) * 9 / 10),
1314 ((pba << 10) - 2 * sc->max_frame_size));
1315
1316 if (hw->mac.type < e1000_82576) {
1317 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1318 fc->low_water = fc->high_water - 8;
1319 } else {
1320 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1321 fc->low_water = fc->high_water - 16;
1322 }
1323 fc->pause_time = IGB_FC_PAUSE_TIME;
1324 fc->send_xon = TRUE;
1325
1326 /* Issue a global reset */
1327 e1000_reset_hw(hw);
1328 E1000_WRITE_REG(hw, E1000_WUC, 0);
1329
1330 if (e1000_init_hw(hw) < 0)
1331 if_printf(ifp, "Hardware Initialization Failed\n");
1332
1333 /* Setup DMA Coalescing */
1334 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1335 uint32_t reg;
1336
1337 hwm = (pba - 4) << 10;
1338 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1339 & E1000_DMACR_DMACTHR_MASK;
1340
1341 /* transition to L0x or L1 if available..*/
1342 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1343
1344 /* timer = +-1000 usec in 32usec intervals */
1345 reg |= (1000 >> 5);
1346 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1347
1348 /* No lower threshold */
1349 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1350
1351 /* set hwm to PBA - 2 * max frame size */
1352 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1353
1354 /* Set the interval before transition */
1355 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1356 reg |= 0x800000FF; /* 255 usec */
1357 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1358
1359 /* free space in tx packet buffer to wake from DMA coal */
1360 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1361 (20480 - (2 * sc->max_frame_size)) >> 6);
1362
1363 /* make low power state decision controlled by DMA coal */
1364 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1365 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1366 reg | E1000_PCIEMISC_LX_DECISION);
1367 if_printf(ifp, "DMA Coalescing enabled\n");
1368 }
1369
1370 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1371 e1000_get_phy_info(hw);
1372 e1000_check_for_link(hw);
1373}
1374
1375static void
1376igb_setup_ifp(struct igb_softc *sc)
1377{
1378 struct ifnet *ifp = &sc->arpcom.ac_if;
1379
1380 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1381 ifp->if_softc = sc;
1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c0ecdcc 1383 ifp->if_init = igb_init;
1f7e3916
SZ
1384 ifp->if_ioctl = igb_ioctl;
1385 ifp->if_start = igb_start;
7d235eb5
SZ
1386 ifp->if_serialize = igb_serialize;
1387 ifp->if_deserialize = igb_deserialize;
1388 ifp->if_tryserialize = igb_tryserialize;
1389#ifdef INVARIANTS
1390 ifp->if_serialize_assert = igb_serialize_assert;
1391#endif
1f7e3916
SZ
1392#ifdef DEVICE_POLLING
1393 ifp->if_poll = igb_poll;
1394#endif
1395 ifp->if_watchdog = igb_watchdog;
1396
91b8700a 1397 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1f7e3916
SZ
1398 ifq_set_ready(&ifp->if_snd);
1399
1400 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1401
1402 ifp->if_capabilities =
1403 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
8d6600da
SZ
1404 if (IGB_ENABLE_HWRSS(sc))
1405 ifp->if_capabilities |= IFCAP_RSS;
1f7e3916
SZ
1406 ifp->if_capenable = ifp->if_capabilities;
1407 ifp->if_hwassist = IGB_CSUM_FEATURES;
1408
1409 /*
1410 * Tell the upper layer(s) we support long frames
1411 */
1412 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1413
1414 /*
1415 * Specify the media types supported by this adapter and register
1416 * callbacks to update media and link information
1417 */
1418 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1419 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1420 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1421 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1422 0, NULL);
1423 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1424 } else {
1425 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1426 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1427 0, NULL);
1428 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1429 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1430 0, NULL);
1431 if (sc->hw.phy.type != e1000_phy_ife) {
1432 ifmedia_add(&sc->media,
1433 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1434 ifmedia_add(&sc->media,
1435 IFM_ETHER | IFM_1000_T, 0, NULL);
1436 }
1437 }
1438 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1439 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1440}
1441
1442static void
1443igb_add_sysctl(struct igb_softc *sc)
1444{
9c0ecdcc 1445 char node[32];
8d6600da 1446 int i;
8d6600da 1447
1f7e3916
SZ
1448 sysctl_ctx_init(&sc->sysctl_ctx);
1449 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1450 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1451 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1452 if (sc->sysctl_tree == NULL) {
1453 device_printf(sc->dev, "can't add sysctl node\n");
1454 return;
1455 }
1456
1457 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1458 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1459 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
be922da6
SZ
1460 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1461 "# of RX rings used");
1462 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1463 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1464 "# of RX descs");
1f7e3916 1465 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1466 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1467 "# of TX descs");
1f7e3916 1468
9c0ecdcc
SZ
1469 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1470 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1471 SYSCTL_CHILDREN(sc->sysctl_tree),
1472 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1473 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1474 } else {
1475 for (i = 0; i < sc->msix_cnt; ++i) {
1476 struct igb_msix_data *msix = &sc->msix_data[i];
1477
1478 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1479 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1480 SYSCTL_CHILDREN(sc->sysctl_tree),
1481 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1482 msix, 0, igb_sysctl_msix_rate, "I",
1483 msix->msix_rate_desc);
1484 }
1485 }
b6220144
SZ
1486
1487 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1488 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1489 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
8d6600da
SZ
1490 "# of segments per TX interrupt");
1491
1492#ifdef IGB_RSS_DEBUG
1493 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1495 "RSS debug level");
1496 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9c0ecdcc 1497 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
8d6600da 1498 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
9c0ecdcc 1499 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
8d6600da
SZ
1500 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1501 }
1502#endif
1f7e3916
SZ
1503}
1504
1505static int
a619b256 1506igb_alloc_rings(struct igb_softc *sc)
1f7e3916
SZ
1507{
1508 int error, i;
1509
1f7e3916
SZ
1510 /*
1511 * Create top level busdma tag
1512 */
1513 error = bus_dma_tag_create(NULL, 1, 0,
1514 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1515 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1516 &sc->parent_tag);
1517 if (error) {
1518 device_printf(sc->dev, "could not create top level DMA tag\n");
1519 return error;
1520 }
1521
1522 /*
1523 * Allocate TX descriptor rings and buffers
1524 */
27866bf1 1525 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1f7e3916 1526 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1527 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1528 struct igb_tx_ring *txr = &sc->tx_rings[i];
1529
1530 /* Set up some basics */
1531 txr->sc = sc;
1532 txr->me = i;
7d235eb5 1533 lwkt_serialize_init(&txr->tx_serialize);
1f7e3916
SZ
1534
1535 error = igb_create_tx_ring(txr);
1536 if (error)
1537 return error;
1538 }
1539
1540 /*
1541 * Allocate RX descriptor rings and buffers
1542 */
27866bf1 1543 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1f7e3916 1544 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1545 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1f7e3916
SZ
1546 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1547
1548 /* Set up some basics */
1549 rxr->sc = sc;
1550 rxr->me = i;
7d235eb5 1551 lwkt_serialize_init(&rxr->rx_serialize);
1f7e3916
SZ
1552
1553 error = igb_create_rx_ring(rxr);
1554 if (error)
1555 return error;
1556 }
1557
1f7e3916
SZ
1558 return 0;
1559}
1560
1561static void
a619b256 1562igb_free_rings(struct igb_softc *sc)
1f7e3916
SZ
1563{
1564 int i;
1565
1f7e3916 1566 if (sc->tx_rings != NULL) {
91b8700a
SZ
1567 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1568 struct igb_tx_ring *txr = &sc->tx_rings[i];
1569
1570 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1571 }
1f7e3916
SZ
1572 kfree(sc->tx_rings, M_DEVBUF);
1573 }
1574
1575 if (sc->rx_rings != NULL) {
91b8700a
SZ
1576 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1577 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1578
1579 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1580 }
1f7e3916
SZ
1581 kfree(sc->rx_rings, M_DEVBUF);
1582 }
1583}
1584
1585static int
1586igb_create_tx_ring(struct igb_tx_ring *txr)
1587{
1588 int tsize, error, i;
1589
1590 /*
1591 * Validate number of transmit descriptors. It must not exceed
1592 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1593 */
1594 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1595 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1596 device_printf(txr->sc->dev,
1597 "Using %d TX descriptors instead of %d!\n",
1598 IGB_DEFAULT_TXD, igb_txd);
91b8700a 1599 txr->num_tx_desc = IGB_DEFAULT_TXD;
1f7e3916 1600 } else {
91b8700a 1601 txr->num_tx_desc = igb_txd;
1f7e3916
SZ
1602 }
1603
1604 /*
1605 * Allocate TX descriptor ring
1606 */
91b8700a 1607 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1f7e3916
SZ
1608 IGB_DBA_ALIGN);
1609 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1610 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1611 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1612 if (txr->txdma.dma_vaddr == NULL) {
1613 device_printf(txr->sc->dev,
1614 "Unable to allocate TX Descriptor memory\n");
1615 return ENOMEM;
1616 }
1617 txr->tx_base = txr->txdma.dma_vaddr;
1618 bzero(txr->tx_base, tsize);
1619
91b8700a 1620 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1f7e3916
SZ
1621 M_DEVBUF, M_WAITOK | M_ZERO);
1622
1623 /*
b6220144
SZ
1624 * Allocate TX head write-back buffer
1625 */
1626 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1627 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1628 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1629 if (txr->tx_hdr == NULL) {
1630 device_printf(txr->sc->dev,
1631 "Unable to allocate TX head write-back buffer\n");
1632 return ENOMEM;
1633 }
1634
1635 /*
1f7e3916
SZ
1636 * Create DMA tag for TX buffers
1637 */
1638 error = bus_dma_tag_create(txr->sc->parent_tag,
1639 1, 0, /* alignment, bounds */
1640 BUS_SPACE_MAXADDR, /* lowaddr */
1641 BUS_SPACE_MAXADDR, /* highaddr */
1642 NULL, NULL, /* filter, filterarg */
1643 IGB_TSO_SIZE, /* maxsize */
1644 IGB_MAX_SCATTER, /* nsegments */
1645 PAGE_SIZE, /* maxsegsize */
1646 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1647 BUS_DMA_ONEBPAGE, /* flags */
1648 &txr->tx_tag);
1649 if (error) {
1650 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1651 kfree(txr->tx_buf, M_DEVBUF);
1652 txr->tx_buf = NULL;
1653 return error;
1654 }
1655
1656 /*
1657 * Create DMA maps for TX buffers
1658 */
91b8700a 1659 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1660 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1661
1662 error = bus_dmamap_create(txr->tx_tag,
1663 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1664 if (error) {
1665 device_printf(txr->sc->dev,
1666 "Unable to create TX DMA map\n");
1667 igb_destroy_tx_ring(txr, i);
1668 return error;
1669 }
1670 }
b6220144
SZ
1671
1672 /*
1673 * Initialize various watermark
1674 */
1675 txr->spare_desc = IGB_TX_SPARE;
91b8700a
SZ
1676 txr->intr_nsegs = txr->num_tx_desc / 16;
1677 txr->oact_hi_desc = txr->num_tx_desc / 2;
1678 txr->oact_lo_desc = txr->num_tx_desc / 8;
b6220144
SZ
1679 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1680 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1681 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1682 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1683
1f7e3916
SZ
1684 return 0;
1685}
1686
1687static void
1688igb_free_tx_ring(struct igb_tx_ring *txr)
1689{
1690 int i;
1691
91b8700a 1692 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1693 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1694
1695 if (txbuf->m_head != NULL) {
1696 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1697 m_freem(txbuf->m_head);
1698 txbuf->m_head = NULL;
1699 }
1700 }
1701}
1702
1703static void
1704igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1705{
1706 int i;
1707
1708 if (txr->txdma.dma_vaddr != NULL) {
1709 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1710 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1711 txr->txdma.dma_map);
1712 bus_dma_tag_destroy(txr->txdma.dma_tag);
1713 txr->txdma.dma_vaddr = NULL;
1714 }
1715
b6220144
SZ
1716 if (txr->tx_hdr != NULL) {
1717 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1718 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1719 txr->tx_hdr_dmap);
1720 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1721 txr->tx_hdr = NULL;
1722 }
1723
1f7e3916
SZ
1724 if (txr->tx_buf == NULL)
1725 return;
1726
1727 for (i = 0; i < ndesc; ++i) {
1728 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1729
1730 KKASSERT(txbuf->m_head == NULL);
1731 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1732 }
1733 bus_dma_tag_destroy(txr->tx_tag);
1734
1735 kfree(txr->tx_buf, M_DEVBUF);
1736 txr->tx_buf = NULL;
1737}
1738
1739static void
1740igb_init_tx_ring(struct igb_tx_ring *txr)
1741{
1f7e3916
SZ
1742 /* Clear the old descriptor contents */
1743 bzero(txr->tx_base,
91b8700a 1744 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1f7e3916 1745
b6220144
SZ
1746 /* Clear TX head write-back buffer */
1747 *(txr->tx_hdr) = 0;
1748
1f7e3916
SZ
1749 /* Reset indices */
1750 txr->next_avail_desc = 0;
1751 txr->next_to_clean = 0;
b6220144 1752 txr->tx_nsegs = 0;
1f7e3916
SZ
1753
1754 /* Set number of descriptors available */
91b8700a 1755 txr->tx_avail = txr->num_tx_desc;
1f7e3916
SZ
1756}
1757
1758static void
1759igb_init_tx_unit(struct igb_softc *sc)
1760{
1761 struct e1000_hw *hw = &sc->hw;
1762 uint32_t tctl;
1763 int i;
1764
1765 /* Setup the Tx Descriptor Rings */
27866bf1 1766 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1767 struct igb_tx_ring *txr = &sc->tx_rings[i];
1768 uint64_t bus_addr = txr->txdma.dma_paddr;
c3162c4e 1769 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1f7e3916 1770 uint32_t txdctl = 0;
b6220144 1771 uint32_t dca_txctrl;
1f7e3916
SZ
1772
1773 E1000_WRITE_REG(hw, E1000_TDLEN(i),
91b8700a 1774 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1f7e3916
SZ
1775 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1776 (uint32_t)(bus_addr >> 32));
1777 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1778 (uint32_t)bus_addr);
1779
1780 /* Setup the HW Tx Head and Tail descriptor pointers */
1781 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1782 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1783
54691ff1
SZ
1784 /*
1785 * WTHRESH is ignored by the hardware, since header
1786 * write back mode is used.
1787 */
1f7e3916
SZ
1788 txdctl |= IGB_TX_PTHRESH;
1789 txdctl |= IGB_TX_HTHRESH << 8;
1790 txdctl |= IGB_TX_WTHRESH << 16;
1791 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1792 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
b6220144
SZ
1793
1794 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1795 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1796 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1797
54691ff1
SZ
1798 /*
1799 * Don't set WB_on_EITR:
1800 * - 82575 does not have it
1801 * - It almost has no effect on 82576, see:
1802 * 82576 specification update errata #26
1803 * - It causes unnecessary bus traffic
1804 */
b6220144 1805 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
c3162c4e 1806 (uint32_t)(hdr_paddr >> 32));
b6220144 1807 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
c3162c4e 1808 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1f7e3916
SZ
1809 }
1810
1811 if (sc->vf_ifp)
1812 return;
1813
1814 e1000_config_collision_dist(hw);
1815
1816 /* Program the Transmit Control Register */
1817 tctl = E1000_READ_REG(hw, E1000_TCTL);
1818 tctl &= ~E1000_TCTL_CT;
1819 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1820 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1821
1822 /* This write will effectively turn on the transmit unit. */
1823 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1824}
1825
1826static boolean_t
48faa653 1827igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1f7e3916
SZ
1828{
1829 struct e1000_adv_tx_context_desc *TXD;
1f7e3916 1830 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1f7e3916 1831 int ehdrlen, ctxd, ip_hlen = 0;
48faa653 1832 uint16_t vlantag = 0;
1f7e3916
SZ
1833 boolean_t offload = TRUE;
1834
1835 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1836 offload = FALSE;
1837
1838 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
48faa653 1839
1f7e3916 1840 ctxd = txr->next_avail_desc;
1f7e3916
SZ
1841 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1842
1843 /*
1844 * In advanced descriptors the vlan tag must
1845 * be placed into the context descriptor, thus
1846 * we need to be here just for that setup.
1847 */
1848 if (mp->m_flags & M_VLANTAG) {
1849 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1850 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1851 } else if (!offload) {
1852 return FALSE;
1853 }
1854
48faa653
SZ
1855 ehdrlen = mp->m_pkthdr.csum_lhlen;
1856 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1f7e3916
SZ
1857
1858 /* Set the ether header length */
1859 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1860
48faa653
SZ
1861 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1862 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1863 ip_hlen = mp->m_pkthdr.csum_iphlen;
1864 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1f7e3916
SZ
1865 }
1866
1867 vlan_macip_lens |= ip_hlen;
1868 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1869
1870 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1871 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1872 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1873 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1874
1875 /* 82575 needs the queue index added */
1876 if (txr->sc->hw.mac.type == e1000_82575)
1877 mss_l4len_idx = txr->me << 4;
1878
1879 /* Now copy bits into descriptor */
1880 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1881 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1882 TXD->seqnum_seed = htole32(0);
1883 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1884
1f7e3916 1885 /* We've consumed the first desc, adjust counters */
91b8700a 1886 if (++ctxd == txr->num_tx_desc)
1f7e3916
SZ
1887 ctxd = 0;
1888 txr->next_avail_desc = ctxd;
1889 --txr->tx_avail;
1890
1891 return offload;
1892}
1893
1894static void
1895igb_txeof(struct igb_tx_ring *txr)
1896{
1897 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
b6220144 1898 int first, hdr, avail;
1f7e3916 1899
91b8700a 1900 if (txr->tx_avail == txr->num_tx_desc)
1f7e3916
SZ
1901 return;
1902
1903 first = txr->next_to_clean;
b6220144 1904 hdr = *(txr->tx_hdr);
1f7e3916 1905
b6220144
SZ
1906 if (first == hdr)
1907 return;
1f7e3916 1908
b6220144
SZ
1909 avail = txr->tx_avail;
1910 while (first != hdr) {
1911 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1f7e3916 1912
b6220144
SZ
1913 ++avail;
1914 if (txbuf->m_head) {
1915 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1916 m_freem(txbuf->m_head);
1917 txbuf->m_head = NULL;
1918 ++ifp->if_opackets;
1f7e3916 1919 }
91b8700a 1920 if (++first == txr->num_tx_desc)
b6220144 1921 first = 0;
1f7e3916
SZ
1922 }
1923 txr->next_to_clean = first;
b6220144 1924 txr->tx_avail = avail;
1f7e3916
SZ
1925
1926 /*
1927 * If we have a minimum free, clear IFF_OACTIVE
1928 * to tell the stack that it is OK to send packets.
1929 */
b6220144 1930 if (IGB_IS_NOT_OACTIVE(txr)) {
1f7e3916
SZ
1931 ifp->if_flags &= ~IFF_OACTIVE;
1932
1f7e3916
SZ
1933 /*
1934 * We have enough TX descriptors, turn off
b6220144
SZ
1935 * the watchdog. We allow small amount of
1936 * packets (roughly intr_nsegs) pending on
1937 * the transmit ring.
1f7e3916
SZ
1938 */
1939 ifp->if_timer = 0;
1f7e3916
SZ
1940 }
1941}
1942
1943static int
1944igb_create_rx_ring(struct igb_rx_ring *rxr)
1945{
1946 int rsize, i, error;
1947
1948 /*
1949 * Validate number of receive descriptors. It must not exceed
1950 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1951 */
1952 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1953 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1954 device_printf(rxr->sc->dev,
1955 "Using %d RX descriptors instead of %d!\n",
1956 IGB_DEFAULT_RXD, igb_rxd);
91b8700a 1957 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1f7e3916 1958 } else {
91b8700a 1959 rxr->num_rx_desc = igb_rxd;
1f7e3916
SZ
1960 }
1961
1962 /*
1963 * Allocate RX descriptor ring
1964 */
91b8700a 1965 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1f7e3916
SZ
1966 IGB_DBA_ALIGN);
1967 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1968 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1969 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1970 &rxr->rxdma.dma_paddr);
1971 if (rxr->rxdma.dma_vaddr == NULL) {
1972 device_printf(rxr->sc->dev,
1973 "Unable to allocate RxDescriptor memory\n");
1974 return ENOMEM;
1975 }
1976 rxr->rx_base = rxr->rxdma.dma_vaddr;
1977 bzero(rxr->rx_base, rsize);
1978
91b8700a 1979 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1f7e3916
SZ
1980 M_DEVBUF, M_WAITOK | M_ZERO);
1981
1982 /*
1983 * Create DMA tag for RX buffers
1984 */
1985 error = bus_dma_tag_create(rxr->sc->parent_tag,
1986 1, 0, /* alignment, bounds */
1987 BUS_SPACE_MAXADDR, /* lowaddr */
1988 BUS_SPACE_MAXADDR, /* highaddr */
1989 NULL, NULL, /* filter, filterarg */
1990 MCLBYTES, /* maxsize */
1991 1, /* nsegments */
1992 MCLBYTES, /* maxsegsize */
1993 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1994 &rxr->rx_tag);
1995 if (error) {
1996 device_printf(rxr->sc->dev,
1997 "Unable to create RX payload DMA tag\n");
1998 kfree(rxr->rx_buf, M_DEVBUF);
1999 rxr->rx_buf = NULL;
2000 return error;
2001 }
2002
2003 /*
2004 * Create spare DMA map for RX buffers
2005 */
2006 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2007 &rxr->rx_sparemap);
2008 if (error) {
2009 device_printf(rxr->sc->dev,
2010 "Unable to create spare RX DMA maps\n");
2011 bus_dma_tag_destroy(rxr->rx_tag);
2012 kfree(rxr->rx_buf, M_DEVBUF);
2013 rxr->rx_buf = NULL;
2014 return error;
2015 }
2016
2017 /*
2018 * Create DMA maps for RX buffers
2019 */
91b8700a 2020 for (i = 0; i < rxr->num_rx_desc; i++) {
1f7e3916
SZ
2021 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2022
2023 error = bus_dmamap_create(rxr->rx_tag,
2024 BUS_DMA_WAITOK, &rxbuf->map);
2025 if (error) {
2026 device_printf(rxr->sc->dev,
2027 "Unable to create RX DMA maps\n");
2028 igb_destroy_rx_ring(rxr, i);
2029 return error;
2030 }
2031 }
2032 return 0;
2033}
2034
2035static void
2036igb_free_rx_ring(struct igb_rx_ring *rxr)
2037{
2038 int i;
2039
91b8700a 2040 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2041 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2042
2043 if (rxbuf->m_head != NULL) {
2044 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2045 m_freem(rxbuf->m_head);
2046 rxbuf->m_head = NULL;
2047 }
2048 }
2049
2050 if (rxr->fmp != NULL)
2051 m_freem(rxr->fmp);
2052 rxr->fmp = NULL;
2053 rxr->lmp = NULL;
2054}
2055
2056static void
2057igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2058{
2059 int i;
2060
2061 if (rxr->rxdma.dma_vaddr != NULL) {
2062 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2063 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2064 rxr->rxdma.dma_map);
2065 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2066 rxr->rxdma.dma_vaddr = NULL;
2067 }
2068
2069 if (rxr->rx_buf == NULL)
2070 return;
2071
2072 for (i = 0; i < ndesc; ++i) {
2073 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2074
2075 KKASSERT(rxbuf->m_head == NULL);
2076 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2077 }
2078 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2079 bus_dma_tag_destroy(rxr->rx_tag);
2080
2081 kfree(rxr->rx_buf, M_DEVBUF);
2082 rxr->rx_buf = NULL;
2083}
2084
2085static void
2086igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2087{
2088 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2089 rxd->wb.upper.status_error = 0;
2090}
2091
2092static int
2093igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2094{
2095 struct mbuf *m;
2096 bus_dma_segment_t seg;
2097 bus_dmamap_t map;
2098 struct igb_rx_buf *rxbuf;
2099 int error, nseg;
2100
2101 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2102 if (m == NULL) {
2103 if (wait) {
2104 if_printf(&rxr->sc->arpcom.ac_if,
2105 "Unable to allocate RX mbuf\n");
2106 }
2107 return ENOBUFS;
2108 }
2109 m->m_len = m->m_pkthdr.len = MCLBYTES;
2110
2111 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2112 m_adj(m, ETHER_ALIGN);
2113
2114 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2115 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2116 if (error) {
2117 m_freem(m);
2118 if (wait) {
2119 if_printf(&rxr->sc->arpcom.ac_if,
2120 "Unable to load RX mbuf\n");
2121 }
2122 return error;
2123 }
2124
2125 rxbuf = &rxr->rx_buf[i];
2126 if (rxbuf->m_head != NULL)
2127 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2128
2129 map = rxbuf->map;
2130 rxbuf->map = rxr->rx_sparemap;
2131 rxr->rx_sparemap = map;
2132
2133 rxbuf->m_head = m;
2134 rxbuf->paddr = seg.ds_addr;
2135
2136 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2137 return 0;
2138}
2139
2140static int
2141igb_init_rx_ring(struct igb_rx_ring *rxr)
2142{
2143 int i;
2144
2145 /* Clear the ring contents */
2146 bzero(rxr->rx_base,
91b8700a 2147 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
1f7e3916
SZ
2148
2149 /* Now replenish the ring mbufs */
91b8700a 2150 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2151 int error;
2152
2153 error = igb_newbuf(rxr, i, TRUE);
2154 if (error)
2155 return error;
2156 }
2157
2158 /* Setup our descriptor indices */
2159 rxr->next_to_check = 0;
2160
2161 rxr->fmp = NULL;
2162 rxr->lmp = NULL;
2163 rxr->discard = FALSE;
2164
2165 return 0;
2166}
2167
2168static void
2169igb_init_rx_unit(struct igb_softc *sc)
2170{
2171 struct ifnet *ifp = &sc->arpcom.ac_if;
2172 struct e1000_hw *hw = &sc->hw;
2173 uint32_t rctl, rxcsum, srrctl = 0;
2174 int i;
2175
2176 /*
2177 * Make sure receives are disabled while setting
2178 * up the descriptor ring
2179 */
2180 rctl = E1000_READ_REG(hw, E1000_RCTL);
2181 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2182
2183#if 0
2184 /*
2185 ** Set up for header split
2186 */
2187 if (igb_header_split) {
2188 /* Use a standard mbuf for the header */
2189 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2190 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2191 } else
2192#endif
2193 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2194
2195 /*
2196 ** Set up for jumbo frames
2197 */
2198 if (ifp->if_mtu > ETHERMTU) {
2199 rctl |= E1000_RCTL_LPE;
2200#if 0
2201 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2202 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2203 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2204 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2205 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2206 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2207 }
2208 /* Set maximum packet len */
2209 psize = adapter->max_frame_size;
2210 /* are we on a vlan? */
2211 if (adapter->ifp->if_vlantrunk != NULL)
2212 psize += VLAN_TAG_SIZE;
2213 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2214#else
2215 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2216 rctl |= E1000_RCTL_SZ_2048;
2217#endif
2218 } else {
2219 rctl &= ~E1000_RCTL_LPE;
2220 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2221 rctl |= E1000_RCTL_SZ_2048;
2222 }
2223
2224 /* Setup the Base and Length of the Rx Descriptor Rings */
be922da6 2225 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2226 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2227 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2228 uint32_t rxdctl;
2229
2230 E1000_WRITE_REG(hw, E1000_RDLEN(i),
91b8700a 2231 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
1f7e3916
SZ
2232 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2233 (uint32_t)(bus_addr >> 32));
2234 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2235 (uint32_t)bus_addr);
2236 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2237 /* Enable this Queue */
2238 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2239 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2240 rxdctl &= 0xFFF00000;
2241 rxdctl |= IGB_RX_PTHRESH;
2242 rxdctl |= IGB_RX_HTHRESH << 8;
54691ff1
SZ
2243 /*
2244 * Don't set WTHRESH to a value above 1 on 82576, see:
2245 * 82576 specification update errata #26
2246 */
1f7e3916
SZ
2247 rxdctl |= IGB_RX_WTHRESH << 16;
2248 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2249 }
2250
8d6600da
SZ
2251 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2252 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2253
1f7e3916 2254 /*
8d6600da
SZ
2255 * Receive Checksum Offload for TCP and UDP
2256 *
2257 * Checksum offloading is also enabled if multiple receive
2258 * queue is to be supported, since we need it to figure out
2259 * fragments.
1f7e3916 2260 */
8d6600da
SZ
2261 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2262 /*
2263 * NOTE:
2264 * PCSD must be enabled to enable multiple
2265 * receive queues.
2266 */
2267 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2268 E1000_RXCSUM_PCSD;
2269 } else {
2270 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2271 E1000_RXCSUM_PCSD);
2272 }
2273 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2274
2275 if (IGB_ENABLE_HWRSS(sc)) {
2276 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
d1218435
SZ
2277 uint32_t reta_shift;
2278 int j, r;
8d6600da
SZ
2279
2280 /*
2281 * NOTE:
2282 * When we reach here, RSS has already been disabled
2283 * in igb_stop(), so we could safely configure RSS key
2284 * and redirect table.
2285 */
2286
2287 /*
2288 * Configure RSS key
2289 */
2290 toeplitz_get_key(key, sizeof(key));
2291 for (i = 0; i < IGB_NRSSRK; ++i) {
2292 uint32_t rssrk;
2293
2294 rssrk = IGB_RSSRK_VAL(key, i);
2295 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2296
2297 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
1f7e3916 2298 }
1f7e3916
SZ
2299
2300 /*
8d6600da
SZ
2301 * Configure RSS redirect table in following fashion:
2302 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2303 */
2304 reta_shift = IGB_RETA_SHIFT;
2305 if (hw->mac.type == e1000_82575)
2306 reta_shift = IGB_RETA_SHIFT_82575;
8d6600da 2307
d1218435
SZ
2308 r = 0;
2309 for (j = 0; j < IGB_NRETA; ++j) {
2310 uint32_t reta = 0;
8d6600da 2311
d1218435
SZ
2312 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2313 uint32_t q;
2314
be922da6 2315 q = (r % sc->rx_ring_inuse) << reta_shift;
d1218435
SZ
2316 reta |= q << (8 * i);
2317 ++r;
2318 }
2319 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2320 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2321 }
8d6600da
SZ
2322
2323 /*
2324 * Enable multiple receive queues.
2325 * Enable IPv4 RSS standard hash functions.
2326 * Disable RSS interrupt on 82575
2327 */
2328 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2329 E1000_MRQC_ENABLE_RSS_4Q |
2330 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2331 E1000_MRQC_RSS_FIELD_IPV4);
1f7e3916 2332 }
1f7e3916
SZ
2333
2334 /* Setup the Receive Control Register */
2335 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2336 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2337 E1000_RCTL_RDMTS_HALF |
2338 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2339 /* Strip CRC bytes. */
2340 rctl |= E1000_RCTL_SECRC;
2341 /* Make sure VLAN Filters are off */
2342 rctl &= ~E1000_RCTL_VFE;
2343 /* Don't store bad packets */
2344 rctl &= ~E1000_RCTL_SBP;
2345
2346 /* Enable Receives */
2347 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2348
2349 /*
2350 * Setup the HW Rx Head and Tail Descriptor Pointers
2351 * - needs to be after enable
2352 */
be922da6 2353 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2354 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2355
2356 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
91b8700a 2357 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
1f7e3916
SZ
2358 }
2359}
2360
2361static void
2362igb_rxeof(struct igb_rx_ring *rxr, int count)
2363{
2364 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2365 union e1000_adv_rx_desc *cur;
2366 uint32_t staterr;
2367 int i;
2368
2369 i = rxr->next_to_check;
2370 cur = &rxr->rx_base[i];
2371 staterr = le32toh(cur->wb.upper.status_error);
2372
2373 if ((staterr & E1000_RXD_STAT_DD) == 0)
2374 return;
2375
2376 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
8d6600da 2377 struct pktinfo *pi = NULL, pi0;
1f7e3916
SZ
2378 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2379 struct mbuf *m = NULL;
2380 boolean_t eop;
2381
2382 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2383 if (eop)
2384 --count;
2385
2386 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2387 !rxr->discard) {
2388 struct mbuf *mp = rxbuf->m_head;
8d6600da 2389 uint32_t hash, hashtype;
1f7e3916
SZ
2390 uint16_t vlan;
2391 int len;
2392
2393 len = le16toh(cur->wb.upper.length);
2394 if (rxr->sc->hw.mac.type == e1000_i350 &&
2395 (staterr & E1000_RXDEXT_STATERR_LB))
2396 vlan = be16toh(cur->wb.upper.vlan);
2397 else
2398 vlan = le16toh(cur->wb.upper.vlan);
2399
8d6600da
SZ
2400 hash = le32toh(cur->wb.lower.hi_dword.rss);
2401 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2402 E1000_RXDADV_RSSTYPE_MASK;
2403
2404 IGB_RSS_DPRINTF(rxr->sc, 10,
2405 "ring%d, hash 0x%08x, hashtype %u\n",
2406 rxr->me, hash, hashtype);
2407
1f7e3916
SZ
2408 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2409 BUS_DMASYNC_POSTREAD);
2410
2411 if (igb_newbuf(rxr, i, FALSE) != 0) {
2412 ifp->if_iqdrops++;
2413 goto discard;
2414 }
2415
2416 mp->m_len = len;
2417 if (rxr->fmp == NULL) {
2418 mp->m_pkthdr.len = len;
2419 rxr->fmp = mp;
2420 rxr->lmp = mp;
2421 } else {
2422 rxr->lmp->m_next = mp;
2423 rxr->lmp = rxr->lmp->m_next;
2424 rxr->fmp->m_pkthdr.len += len;
2425 }
2426
2427 if (eop) {
2428 m = rxr->fmp;
2429 rxr->fmp = NULL;
2430 rxr->lmp = NULL;
2431
2432 m->m_pkthdr.rcvif = ifp;
2433 ifp->if_ipackets++;
2434
2435 if (ifp->if_capenable & IFCAP_RXCSUM)
2436 igb_rxcsum(staterr, m);
2437
2438 if (staterr & E1000_RXD_STAT_VP) {
2439 m->m_pkthdr.ether_vlantag = vlan;
2440 m->m_flags |= M_VLANTAG;
2441 }
2442
1f7e3916 2443 if (ifp->if_capenable & IFCAP_RSS) {
8d6600da
SZ
2444 pi = igb_rssinfo(m, &pi0,
2445 hash, hashtype, staterr);
1f7e3916 2446 }
8d6600da
SZ
2447#ifdef IGB_RSS_DEBUG
2448 rxr->rx_packets++;
1f7e3916
SZ
2449#endif
2450 }
2451 } else {
2452 ifp->if_ierrors++;
2453discard:
2454 igb_setup_rxdesc(cur, rxbuf);
2455 if (!eop)
2456 rxr->discard = TRUE;
2457 else
2458 rxr->discard = FALSE;
2459 if (rxr->fmp != NULL) {
2460 m_freem(rxr->fmp);
2461 rxr->fmp = NULL;
2462 rxr->lmp = NULL;
2463 }
2464 m = NULL;
2465 }
2466
2467 if (m != NULL)
8d6600da 2468 ether_input_pkt(ifp, m, pi);
1f7e3916
SZ
2469
2470 /* Advance our pointers to the next descriptor. */
91b8700a 2471 if (++i == rxr->num_rx_desc)
1f7e3916
SZ
2472 i = 0;
2473
2474 cur = &rxr->rx_base[i];
2475 staterr = le32toh(cur->wb.upper.status_error);
2476 }
2477 rxr->next_to_check = i;
2478
2479 if (--i < 0)
91b8700a 2480 i = rxr->num_rx_desc - 1;
1f7e3916
SZ
2481 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2482}
2483
2484
2485static void
2486igb_set_vlan(struct igb_softc *sc)
2487{
2488 struct e1000_hw *hw = &sc->hw;
2489 uint32_t reg;
2490#if 0
2491 struct ifnet *ifp = sc->arpcom.ac_if;
2492#endif
2493
2494 if (sc->vf_ifp) {
2495 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2496 return;
2497 }
2498
2499 reg = E1000_READ_REG(hw, E1000_CTRL);
2500 reg |= E1000_CTRL_VME;
2501 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2502
2503#if 0
2504 /* Enable the Filter Table */
2505 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2506 reg = E1000_READ_REG(hw, E1000_RCTL);
2507 reg &= ~E1000_RCTL_CFIEN;
2508 reg |= E1000_RCTL_VFE;
2509 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2510 }
2511#endif
2512
2513 /* Update the frame size */
2514 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2515 sc->max_frame_size + VLAN_TAG_SIZE);
2516
2517#if 0
2518 /* Don't bother with table if no vlans */
2519 if ((adapter->num_vlans == 0) ||
2520 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2521 return;
2522 /*
2523 ** A soft reset zero's out the VFTA, so
2524 ** we need to repopulate it now.
2525 */
2526 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2527 if (adapter->shadow_vfta[i] != 0) {
2528 if (adapter->vf_ifp)
2529 e1000_vfta_set_vf(hw,
2530 adapter->shadow_vfta[i], TRUE);
2531 else
2532 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2533 i, adapter->shadow_vfta[i]);
2534 }
2535#endif
2536}
2537
2538static void
2539igb_enable_intr(struct igb_softc *sc)
2540{
9c0ecdcc
SZ
2541 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2542 lwkt_serialize_handler_enable(&sc->main_serialize);
2543 } else {
2544 int i;
2545
2546 for (i = 0; i < sc->msix_cnt; ++i) {
2547 lwkt_serialize_handler_enable(
2548 sc->msix_data[i].msix_serialize);
2549 }
2550 }
1f7e3916 2551
f6167a56 2552 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
9c0ecdcc
SZ
2553 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2554 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2555 else
2556 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56
SZ
2557 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2558 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
1f7e3916
SZ
2559 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2560 } else {
2561 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2562 }
2563 E1000_WRITE_FLUSH(&sc->hw);
2564}
2565
2566static void
2567igb_disable_intr(struct igb_softc *sc)
2568{
f6167a56 2569 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
1f7e3916
SZ
2570 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2571 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56 2572 }
1f7e3916
SZ
2573 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2574 E1000_WRITE_FLUSH(&sc->hw);
2575
9c0ecdcc
SZ
2576 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2577 lwkt_serialize_handler_disable(&sc->main_serialize);
2578 } else {
2579 int i;
2580
2581 for (i = 0; i < sc->msix_cnt; ++i) {
2582 lwkt_serialize_handler_disable(
2583 sc->msix_data[i].msix_serialize);
2584 }
2585 }
1f7e3916
SZ
2586}
2587
2588/*
2589 * Bit of a misnomer, what this really means is
2590 * to enable OS management of the system... aka
2591 * to disable special hardware management features
2592 */
2593static void
2594igb_get_mgmt(struct igb_softc *sc)
2595{
396b7048 2596 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2597 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2598 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2599
2600 /* disable hardware interception of ARP */
2601 manc &= ~E1000_MANC_ARP_EN;
2602
2603 /* enable receiving management packets to the host */
2604 manc |= E1000_MANC_EN_MNG2HOST;
2605 manc2h |= 1 << 5; /* Mng Port 623 */
2606 manc2h |= 1 << 6; /* Mng Port 664 */
2607 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2608 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2609 }
2610}
2611
2612/*
2613 * Give control back to hardware management controller
2614 * if there is one.
2615 */
2616static void
2617igb_rel_mgmt(struct igb_softc *sc)
2618{
396b7048 2619 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2620 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2621
2622 /* Re-enable hardware interception of ARP */
2623 manc |= E1000_MANC_ARP_EN;
2624 manc &= ~E1000_MANC_EN_MNG2HOST;
2625
2626 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2627 }
2628}
2629
2630/*
2631 * Sets CTRL_EXT:DRV_LOAD bit.
2632 *
2633 * For ASF and Pass Through versions of f/w this means that
2634 * the driver is loaded.
2635 */
2636static void
2637igb_get_hw_control(struct igb_softc *sc)
2638{
2639 uint32_t ctrl_ext;
2640
2641 if (sc->vf_ifp)
2642 return;
2643
2644 /* Let firmware know the driver has taken over */
2645 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2646 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2647 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2648}
2649
2650/*
2651 * Resets CTRL_EXT:DRV_LOAD bit.
2652 *
2653 * For ASF and Pass Through versions of f/w this means that the
2654 * driver is no longer loaded.
2655 */
2656static void
2657igb_rel_hw_control(struct igb_softc *sc)
2658{
2659 uint32_t ctrl_ext;
2660
2661 if (sc->vf_ifp)
2662 return;
2663
2664 /* Let firmware taken over control of h/w */
2665 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2666 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2667 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2668}
2669
2670static int
2671igb_is_valid_ether_addr(const uint8_t *addr)
2672{
2673 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2674
2675 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2676 return FALSE;
2677 return TRUE;
2678}
2679
2680/*
2681 * Enable PCI Wake On Lan capability
2682 */
2683static void
2684igb_enable_wol(device_t dev)
2685{
2686 uint16_t cap, status;
2687 uint8_t id;
2688
2689 /* First find the capabilities pointer*/
2690 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2691
2692 /* Read the PM Capabilities */
2693 id = pci_read_config(dev, cap, 1);
2694 if (id != PCIY_PMG) /* Something wrong */
2695 return;
2696
2697 /*
2698 * OK, we have the power capabilities,
2699 * so now get the status register
2700 */
2701 cap += PCIR_POWER_STATUS;
2702 status = pci_read_config(dev, cap, 2);
2703 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2704 pci_write_config(dev, cap, status, 2);
2705}
2706
2707static void
2708igb_update_stats_counters(struct igb_softc *sc)
2709{
2710 struct e1000_hw *hw = &sc->hw;
2711 struct e1000_hw_stats *stats;
2712 struct ifnet *ifp = &sc->arpcom.ac_if;
2713
2714 /*
2715 * The virtual function adapter has only a
2716 * small controlled set of stats, do only
2717 * those and return.
2718 */
2719 if (sc->vf_ifp) {
2720 igb_update_vf_stats_counters(sc);
2721 return;
2722 }
2723 stats = sc->stats;
2724
2725 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2726 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2727 stats->symerrs +=
2728 E1000_READ_REG(hw,E1000_SYMERRS);
2729 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2730 }
2731
2732 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2733 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2734 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2735 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2736
2737 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2738 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2739 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2740 stats->dc += E1000_READ_REG(hw, E1000_DC);
2741 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2742 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2743 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2744
2745 /*
2746 * For watchdog management we need to know if we have been
2747 * paused during the last interval, so capture that here.
2748 */
2749 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2750 stats->xoffrxc += sc->pause_frames;
2751 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2752 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2753 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2754 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2755 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2756 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2757 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2758 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2759 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2760 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2761 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2762 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2763
2764 /* For the 64-bit byte counters the low dword must be read first. */
2765 /* Both registers clear on the read of the high dword */
2766
2767 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2768 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2769 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2770 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2771
2772 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2773 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2774 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2775 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2776 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2777
2778 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2779 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2780
2781 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2782 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2783 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2784 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2785 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2786 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2787 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2788 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2789 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2790 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2791
2792 /* Interrupt Counts */
2793
2794 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2795 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2796 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2797 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2798 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2799 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2800 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2801 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2802 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2803
2804 /* Host to Card Statistics */
2805
2806 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2807 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2808 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2809 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2810 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2811 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2812 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2813 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2814 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2815 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2816 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2817 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2818 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2819 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2820
2821 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2822 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2823 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2824 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2825 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2826 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2827
2828 ifp->if_collisions = stats->colc;
2829
2830 /* Rx Errors */
2831 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2832 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2833
2834 /* Tx Errors */
2835 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2836
2837 /* Driver specific counters */
2838 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2839 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2840 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2841 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2842 sc->packet_buf_alloc_tx =
2843 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2844 sc->packet_buf_alloc_rx =
2845 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2846}
2847
2848static void
2849igb_vf_init_stats(struct igb_softc *sc)
2850{
2851 struct e1000_hw *hw = &sc->hw;
2852 struct e1000_vf_stats *stats;
2853
2854 stats = sc->stats;
2855 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2856 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2857 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2858 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2859 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2860}
2861
2862static void
2863igb_update_vf_stats_counters(struct igb_softc *sc)
2864{
2865 struct e1000_hw *hw = &sc->hw;
2866 struct e1000_vf_stats *stats;
2867
2868 if (sc->link_speed == 0)
2869 return;
2870
2871 stats = sc->stats;
2872 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2873 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2874 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2875 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2876 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2877}
2878
2879#ifdef DEVICE_POLLING
2880
2881static void
2882igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2883{
2884 struct igb_softc *sc = ifp->if_softc;
2885 uint32_t reg_icr;
2886
1f7e3916
SZ
2887 switch (cmd) {
2888 case POLL_REGISTER:
1f7e3916 2889 case POLL_DEREGISTER:
9c0ecdcc
SZ
2890 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2891 igb_init(sc);
1f7e3916
SZ
2892 break;
2893
2894 case POLL_AND_CHECK_STATUS:
9c0ecdcc 2895 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2896 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2897 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2898 sc->hw.mac.get_link_status = 1;
2899 igb_update_link_status(sc);
2900 }
2901 /* FALL THROUGH */
2902 case POLL_ONLY:
9c0ecdcc 2903 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916 2904 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2905 struct igb_tx_ring *txr;
2906 int i;
2907
be922da6 2908 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2909 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2910
2911 lwkt_serialize_enter(&rxr->rx_serialize);
2912 igb_rxeof(rxr, count);
2913 lwkt_serialize_exit(&rxr->rx_serialize);
2914 }
1f7e3916 2915
7d235eb5
SZ
2916 txr = &sc->tx_rings[0];
2917 lwkt_serialize_enter(&txr->tx_serialize);
2918 igb_txeof(txr);
1f7e3916
SZ
2919 if (!ifq_is_empty(&ifp->if_snd))
2920 if_devstart(ifp);
7d235eb5 2921 lwkt_serialize_exit(&txr->tx_serialize);
1f7e3916
SZ
2922 }
2923 break;
2924 }
2925}
2926
2927#endif /* DEVICE_POLLING */
2928
2929static void
2930igb_intr(void *xsc)
2931{
2932 struct igb_softc *sc = xsc;
2933 struct ifnet *ifp = &sc->arpcom.ac_if;
f6167a56
SZ
2934 uint32_t eicr;
2935
7d235eb5 2936 ASSERT_SERIALIZED(&sc->main_serialize);
f6167a56
SZ
2937
2938 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2939
2940 if (eicr == 0)
2941 return;
2942
2943 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2944 struct igb_tx_ring *txr;
2945 int i;
f6167a56 2946
be922da6 2947 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2948 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2949
2950 if (eicr & rxr->rx_intr_mask) {
2951 lwkt_serialize_enter(&rxr->rx_serialize);
2952 igb_rxeof(rxr, -1);
2953 lwkt_serialize_exit(&rxr->rx_serialize);
2954 }
2955 }
2956
2957 txr = &sc->tx_rings[0];
2958 if (eicr & txr->tx_intr_mask) {
2959 lwkt_serialize_enter(&txr->tx_serialize);
2960 igb_txeof(txr);
f6167a56
SZ
2961 if (!ifq_is_empty(&ifp->if_snd))
2962 if_devstart(ifp);
7d235eb5 2963 lwkt_serialize_exit(&txr->tx_serialize);
f6167a56
SZ
2964 }
2965 }
2966
2967 if (eicr & E1000_EICR_OTHER) {
2968 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2969
2970 /* Link status change */
2971 if (icr & E1000_ICR_LSC) {
2972 sc->hw.mac.get_link_status = 1;
2973 igb_update_link_status(sc);
2974 }
2975 }
2976
2977 /*
2978 * Reading EICR has the side effect to clear interrupt mask,
2979 * so all interrupts need to be enabled here.
2980 */
2981 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2982}
2983
2984static void
9c0ecdcc 2985igb_intr_shared(void *xsc)
f6167a56
SZ
2986{
2987 struct igb_softc *sc = xsc;
2988 struct ifnet *ifp = &sc->arpcom.ac_if;
1f7e3916
SZ
2989 uint32_t reg_icr;
2990
7d235eb5 2991 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2992
2993 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2994
2995 /* Hot eject? */
2996 if (reg_icr == 0xffffffff)
2997 return;
2998
2999 /* Definitely not our interrupt. */
3000 if (reg_icr == 0x0)
3001 return;
3002
3003 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3004 return;
3005
3006 if (ifp->if_flags & IFF_RUNNING) {
71b8b086
SZ
3007 if (reg_icr &
3008 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3009 int i;
7d235eb5 3010
71b8b086
SZ
3011 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3012 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1f7e3916 3013
71b8b086
SZ
3014 lwkt_serialize_enter(&rxr->rx_serialize);
3015 igb_rxeof(rxr, -1);
3016 lwkt_serialize_exit(&rxr->rx_serialize);
3017 }
7d235eb5
SZ
3018 }
3019
71b8b086
SZ
3020 if (reg_icr & E1000_ICR_TXDW) {
3021 struct igb_tx_ring *txr = &sc->tx_rings[0];
3022
3023 lwkt_serialize_enter(&txr->tx_serialize);
3024 igb_txeof(txr);
3025 if (!ifq_is_empty(&ifp->if_snd))
3026 if_devstart(ifp);
3027 lwkt_serialize_exit(&txr->tx_serialize);
3028 }
1f7e3916
SZ
3029 }
3030
3031 /* Link status change */
3032 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3033 sc->hw.mac.get_link_status = 1;
3034 igb_update_link_status(sc);
3035 }
3036
3037 if (reg_icr & E1000_ICR_RXO)
3038 sc->rx_overruns++;
3039}
3040
3041static int
1f7e3916
SZ
3042igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3043{
3044 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3045 bus_dmamap_t map;
3046 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3047 union e1000_adv_tx_desc *txd = NULL;
3048 struct mbuf *m_head = *m_headp;
b6220144
SZ
3049 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3050 int maxsegs, nsegs, i, j, error, last = 0;
1f7e3916
SZ
3051 uint32_t hdrlen = 0;
3052
1f7e3916
SZ
3053 /* Set basic descriptor constants */
3054 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3055 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3056 if (m_head->m_flags & M_VLANTAG)
3057 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3058
3059 /*
3060 * Map the packet for DMA.
1f7e3916 3061 */
b6220144 3062 tx_buf = &txr->tx_buf[txr->next_avail_desc];
1f7e3916
SZ
3063 tx_buf_mapped = tx_buf;
3064 map = tx_buf->map;
3065
b6220144
SZ
3066 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3067 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
1f7e3916
SZ
3068 if (maxsegs > IGB_MAX_SCATTER)
3069 maxsegs = IGB_MAX_SCATTER;
3070
3071 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3072 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3073 if (error) {
3074 if (error == ENOBUFS)
3075 txr->sc->mbuf_defrag_failed++;
3076 else
3077 txr->sc->no_tx_dma_setup++;
3078
3079 m_freem(*m_headp);
3080 *m_headp = NULL;
3081 return error;
3082 }
3083 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3084
3085 m_head = *m_headp;
3086
3087#if 0
3088 /*
3089 * Set up the context descriptor:
3090 * used when any hardware offload is done.
3091 * This includes CSUM, VLAN, and TSO. It
3092 * will use the first descriptor.
3093 */
3094 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3095 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3096 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3097 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3098 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3099 } else
3100 return (ENXIO);
3101 } else if (igb_tx_ctx_setup(txr, m_head))
3102 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3103#else
48faa653
SZ
3104 if (igb_txcsum_ctx(txr, m_head)) {
3105 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3106 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
1f7e3916
SZ
3107 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3108 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
b6220144 3109 txr->tx_nsegs++;
1f7e3916
SZ
3110 }
3111#endif
3112
b6220144
SZ
3113 txr->tx_nsegs += nsegs;
3114 if (txr->tx_nsegs >= txr->intr_nsegs) {
3115 /*
3116 * Report Status (RS) is turned on every intr_nsegs
3117 * descriptors (roughly).
3118 */
3119 txr->tx_nsegs = 0;
3120 cmd_rs = E1000_ADVTXD_DCMD_RS;
3121 }
3122
1f7e3916
SZ
3123 /* Calculate payload length */
3124 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3125 << E1000_ADVTXD_PAYLEN_SHIFT);
3126
3127 /* 82575 needs the queue index added */
3128 if (txr->sc->hw.mac.type == e1000_82575)
3129 olinfo_status |= txr->me << 4;
3130
3131 /* Set up our transmit descriptors */
3132 i = txr->next_avail_desc;
3133 for (j = 0; j < nsegs; j++) {
3134 bus_size_t seg_len;
3135 bus_addr_t seg_addr;
3136
3137 tx_buf = &txr->tx_buf[i];
3138 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3139 seg_addr = segs[j].ds_addr;
3140 seg_len = segs[j].ds_len;
3141
3142 txd->read.buffer_addr = htole64(seg_addr);
3143 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3144 txd->read.olinfo_status = htole32(olinfo_status);
3145 last = i;
91b8700a 3146 if (++i == txr->num_tx_desc)
1f7e3916
SZ
3147 i = 0;
3148 tx_buf->m_head = NULL;
1f7e3916
SZ
3149 }
3150
3151 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3152 txr->next_avail_desc = i;
3153 txr->tx_avail -= nsegs;
3154
3155 tx_buf->m_head = m_head;
3156 tx_buf_mapped->map = tx_buf->map;
3157 tx_buf->map = map;
3158
3159 /*
b6220144 3160 * Last Descriptor of Packet needs End Of Packet (EOP)
1f7e3916 3161 */
b6220144 3162 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
1f7e3916
SZ
3163
3164 /*
3165 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3166 * that this frame is available to transmit.
3167 */
3168 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3169 ++txr->tx_packets;
3170
3171 return 0;
3172}
3173
3174static void
3175igb_start(struct ifnet *ifp)
3176{
3177 struct igb_softc *sc = ifp->if_softc;
27866bf1 3178 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3179 struct mbuf *m_head;
3180
7d235eb5 3181 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3182
9c0ecdcc 3183 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1f7e3916
SZ
3184 return;
3185
3186 if (!sc->link_active) {
3187 ifq_purge(&ifp->if_snd);
3188 return;
3189 }
3190
b6220144 3191 if (!IGB_IS_NOT_OACTIVE(txr))
1f7e3916
SZ
3192 igb_txeof(txr);
3193
3194 while (!ifq_is_empty(&ifp->if_snd)) {
b6220144 3195 if (IGB_IS_OACTIVE(txr)) {
1f7e3916
SZ
3196 ifp->if_flags |= IFF_OACTIVE;
3197 /* Set watchdog on */
3198 ifp->if_timer = 5;
3199 break;
3200 }
3201
3202 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3203 if (m_head == NULL)
3204 break;
3205
3206 if (igb_encap(txr, &m_head)) {
3207 ifp->if_oerrors++;
3208 continue;
3209 }
3210
3211 /* Send a copy of the frame to the BPF listener */
3212 ETHER_BPF_MTAP(ifp, m_head);
3213 }
3214}
3215
3216static void
3217igb_watchdog(struct ifnet *ifp)
3218{
3219 struct igb_softc *sc = ifp->if_softc;
27866bf1 3220 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3221
3222 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3223
3224 /*
3225 * If flow control has paused us since last checking
3226 * it invalidates the watchdog timing, so dont run it.
3227 */
3228 if (sc->pause_frames) {
3229 sc->pause_frames = 0;
3230 ifp->if_timer = 5;
3231 return;
3232 }
3233
3234 if_printf(ifp, "Watchdog timeout -- resetting\n");
3235 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3236 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3237 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3238 if_printf(ifp, "TX(%d) desc avail = %d, "
3239 "Next TX to Clean = %d\n",
3240 txr->me, txr->tx_avail, txr->next_to_clean);
3241
3242 ifp->if_oerrors++;
3243 sc->watchdog_events++;
3244
3245 igb_init(sc);
3246 if (!ifq_is_empty(&ifp->if_snd))
3247 if_devstart(ifp);
3248}
3249
3250static void
9c0ecdcc 3251igb_set_eitr(struct igb_softc *sc, int idx, int rate)
1f7e3916 3252{
9c0ecdcc 3253 uint32_t eitr = 0;
1f7e3916 3254
9c0ecdcc 3255 if (rate > 0) {
1f7e3916 3256 if (sc->hw.mac.type == e1000_82575) {
9c0ecdcc 3257 eitr = 1000000000 / 256 / rate;
1f7e3916
SZ
3258 /*
3259 * NOTE:
3260 * Document is wrong on the 2 bits left shift
3261 */
3262 } else {
9c0ecdcc 3263 eitr = 1000000 / rate;
d4beffa9
SZ
3264 eitr <<= IGB_EITR_INTVL_SHIFT;
3265 }
3266
3267 if (eitr == 0) {
3268 /* Don't disable it */
3269 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3270 } else if (eitr > IGB_EITR_INTVL_MASK) {
3271 /* Don't allow it to be too large */
3272 eitr = IGB_EITR_INTVL_MASK;
1f7e3916 3273 }
1f7e3916
SZ
3274 }
3275 if (sc->hw.mac.type == e1000_82575)
9c0ecdcc 3276 eitr |= eitr << 16;
1f7e3916 3277 else
9c0ecdcc
SZ
3278 eitr |= E1000_EITR_CNT_IGNR;
3279 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
1f7e3916
SZ
3280}
3281
3282static int
3283igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3284{
3285 struct igb_softc *sc = (void *)arg1;
3286 struct ifnet *ifp = &sc->arpcom.ac_if;
3287 int error, intr_rate;
3288
3289 intr_rate = sc->intr_rate;
3290 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3291 if (error || req->newptr == NULL)
3292 return error;
3293 if (intr_rate < 0)
3294 return EINVAL;
3295
3296 ifnet_serialize_all(ifp);
3297
3298 sc->intr_rate = intr_rate;
3299 if (ifp->if_flags & IFF_RUNNING)
9c0ecdcc
SZ
3300 igb_set_eitr(sc, 0, sc->intr_rate);
3301
3302 if (bootverbose)
3303 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
1f7e3916
SZ
3304
3305 ifnet_deserialize_all(ifp);
3306
9c0ecdcc
SZ
3307 return 0;
3308}
3309
3310static int
3311igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3312{
3313 struct igb_msix_data *msix = (void *)arg1;
3314 struct igb_softc *sc = msix->msix_sc;
3315 struct ifnet *ifp = &sc->arpcom.ac_if;
3316 int error, msix_rate;
3317
3318 msix_rate = msix->msix_rate;
3319 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3320 if (error || req->newptr == NULL)
3321 return error;
3322 if (msix_rate < 0)
3323 return EINVAL;
3324
3325 lwkt_serialize_enter(msix->msix_serialize);
3326
3327 msix->msix_rate = msix_rate;
3328 if (ifp->if_flags & IFF_RUNNING)
3329 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3330
3331 if (bootverbose) {
3332 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3333 msix->msix_rate);
3334 }
3335
3336 lwkt_serialize_exit(msix->msix_serialize);
3337
1f7e3916
SZ
3338 return 0;
3339}
b6220144
SZ
3340
3341static int
3342igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3343{
3344 struct igb_softc *sc = (void *)arg1;
3345 struct ifnet *ifp = &sc->arpcom.ac_if;
27866bf1 3346 struct igb_tx_ring *txr = &sc->tx_rings[0];
b6220144
SZ
3347 int error, nsegs;
3348
3349 nsegs = txr->intr_nsegs;
3350 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3351 if (error || req->newptr == NULL)
3352 return error;
3353 if (nsegs <= 0)
3354 return EINVAL;
3355
3356 ifnet_serialize_all(ifp);
3357
91b8700a 3358 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
b6220144
SZ
3359 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3360 error = EINVAL;
3361 } else {
3362 error = 0;
3363 txr->intr_nsegs = nsegs;
3364 }
3365
3366 ifnet_deserialize_all(ifp);
3367
3368 return error;
3369}
f6167a56
SZ
3370
3371static void
3372igb_init_intr(struct igb_softc *sc)
3373{
be922da6 3374 igb_set_intr_mask(sc);
9c0ecdcc
SZ
3375
3376 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
f6167a56 3377 igb_init_unshared_intr(sc);
9c0ecdcc
SZ
3378
3379 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3380 igb_set_eitr(sc, 0, sc->intr_rate);
3381 } else {
3382 int i;
3383
3384 for (i = 0; i < sc->msix_cnt; ++i)
3385 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3386 }
f6167a56
SZ
3387}
3388
3389static void
3390igb_init_unshared_intr(struct igb_softc *sc)
3391{
3392 struct e1000_hw *hw = &sc->hw;
3393 const struct igb_rx_ring *rxr;
3394 const struct igb_tx_ring *txr;
3395 uint32_t ivar, index;
3396 int i;
3397
3398 /*
3399 * Enable extended mode
3400 */
3401 if (sc->hw.mac.type != e1000_82575) {
9c0ecdcc
SZ
3402 uint32_t gpie;
3403 int ivar_max;
3404
3405 gpie = E1000_GPIE_NSICR;
3406 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3407 gpie |= E1000_GPIE_MSIX_MODE |
3408 E1000_GPIE_EIAME |
3409 E1000_GPIE_PBA;
3410 }
3411 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3412
3413 /*
3414 * Clear IVARs
3415 */
3416 switch (sc->hw.mac.type) {
3417 case e1000_82580:
3418 ivar_max = IGB_MAX_IVAR_82580;
3419 break;
3420
3421 case e1000_i350:
3422 ivar_max = IGB_MAX_IVAR_I350;
3423 break;
3424
3425 case e1000_vfadapt:
3426 case e1000_vfadapt_i350:
3427 ivar_max = IGB_MAX_IVAR_VF;
3428 break;
3429
3430 case e1000_82576:
3431 ivar_max = IGB_MAX_IVAR_82576;
3432 break;
3433
3434 default:
3435 panic("unknown mac type %d\n", sc->hw.mac.type);
3436 }
3437 for (i = 0; i < ivar_max; ++i)
3438 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3439 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
f6167a56
SZ
3440 } else {
3441 uint32_t tmp;
3442
9c0ecdcc
SZ
3443 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3444 ("82575 w/ MSI-X"));
f6167a56
SZ
3445 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3446 tmp |= E1000_CTRL_EXT_IRCA;
3447 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3448 }
3449
3450 /*
3451 * Map TX/RX interrupts to EICR
3452 */
3453 switch (sc->hw.mac.type) {
3454 case e1000_82580:
3455 case e1000_i350:
3456 case e1000_vfadapt:
3457 case e1000_vfadapt_i350:
3458 /* RX entries */
be922da6 3459 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3460 rxr = &sc->rx_rings[i];
3461
3462 index = i >> 1;
3463 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3464
3465 if (i & 1) {
3466 ivar &= 0xff00ffff;
3467 ivar |=
3468 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3469 } else {
3470 ivar &= 0xffffff00;
3471 ivar |=
3472 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3473 }
3474 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3475 }
3476 /* TX entries */
27866bf1 3477 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3478 txr = &sc->tx_rings[i];
3479
3480 index = i >> 1;
3481 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3482
3483 if (i & 1) {
3484 ivar &= 0x00ffffff;
3485 ivar |=
3486 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3487 } else {
3488 ivar &= 0xffff00ff;
3489 ivar |=
3490 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3491 }
3492 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3493 }
9c0ecdcc
SZ
3494 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3495 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3496 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3497 }
f6167a56
SZ
3498 break;
3499
3500 case e1000_82576:
3501 /* RX entries */
be922da6 3502 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3503 rxr = &sc->rx_rings[i];
3504
3505 index = i & 0x7; /* Each IVAR has two entries */
3506 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3507
3508 if (i < 8) {
3509 ivar &= 0xffffff00;
3510 ivar |=
3511 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3512 } else {
3513 ivar &= 0xff00ffff;
3514 ivar |=
3515 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3516 }
3517 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3518 }
3519 /* TX entries */
27866bf1 3520 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3521 txr = &sc->tx_rings[i];
3522
3523 index = i & 0x7; /* Each IVAR has two entries */
3524 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3525
3526 if (i < 8) {
3527 ivar &= 0xffff00ff;
3528 ivar |=
3529 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3530 } else {
3531 ivar &= 0x00ffffff;
3532 ivar |=
3533 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3534 }
3535 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3536 }
9c0ecdcc
SZ
3537 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3538 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3539 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3540 }
f6167a56
SZ
3541 break;
3542
3543 case e1000_82575:
3544 /*
3545 * Enable necessary interrupt bits.
3546 *
3547 * The name of the register is confusing; in addition to
3548 * configuring the first vector of MSI-X, it also configures
3549 * which bits of EICR could be set by the hardware even when
3550 * MSI or line interrupt is used; it thus controls interrupt
3551 * generation. It MUST be configured explicitly; the default
3552 * value mentioned in the datasheet is wrong: RX queue0 and
3553 * TX queue0 are NOT enabled by default.
3554 */
3555 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3556 break;
3557
3558 default:
9c0ecdcc 3559 panic("unknown mac type %d\n", sc->hw.mac.type);
f6167a56 3560 }
f6167a56
SZ
3561}
3562
3563static int
3564igb_setup_intr(struct igb_softc *sc)
3565{
3566 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 3567 int error;
f6167a56 3568
9c0ecdcc
SZ
3569 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3570 return igb_msix_setup(sc);
f6167a56 3571
f6167a56 3572 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
9c0ecdcc 3573 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
7d235eb5 3574 sc, &sc->intr_tag, &sc->main_serialize);
f6167a56
SZ
3575 if (error) {
3576 device_printf(sc->dev, "Failed to register interrupt handler");
3577 return error;
3578 }
3579
3580 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3581 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3582
3583 return 0;
3584}
3585
3586static void
9c0ecdcc 3587igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3588{
3589 if (txr->sc->hw.mac.type == e1000_82575) {
3590 txr->tx_intr_bit = 0; /* unused */
3591 switch (txr->me) {
3592 case 0:
3593 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3594 break;
3595 case 1:
3596 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3597 break;
3598 case 2:
3599 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3600 break;
3601 case 3:
3602 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3603 break;
3604 default:
3605 panic("unsupported # of TX ring, %d\n", txr->me);
3606 }
3607 } else {
8d6600da
SZ
3608 int intr_bit = *intr_bit0;
3609
3610 txr->tx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3611 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
8d6600da
SZ
3612
3613 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3614 }
3615}
3616
3617static void
9c0ecdcc 3618igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3619{
3620 if (rxr->sc->hw.mac.type == e1000_82575) {
3621 rxr->rx_intr_bit = 0; /* unused */
3622 switch (rxr->me) {
3623 case 0:
3624 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3625 break;
3626 case 1:
3627 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3628 break;
3629 case 2:
3630 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3631 break;
3632 case 3:
3633 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3634 break;
3635 default:
3636 panic("unsupported # of RX ring, %d\n", rxr->me);
3637 }
3638 } else {
8d6600da
SZ
3639 int intr_bit = *intr_bit0;
3640
3641 rxr->rx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3642 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
8d6600da
SZ
3643
3644 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3645 }
3646}
7d235eb5
SZ
3647
3648static void
3649igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3650{
3651 struct igb_softc *sc = ifp->if_softc;
3652
3653 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3654 sc->tx_serialize, sc->rx_serialize, slz);
3655}
3656
3657static void
3658igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3659{
3660 struct igb_softc *sc = ifp->if_softc;
3661
3662 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3663 sc->tx_serialize, sc->rx_serialize, slz);
3664}
3665
3666static int
3667igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3668{
3669 struct igb_softc *sc = ifp->if_softc;
3670
3671 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3672 sc->tx_serialize, sc->rx_serialize, slz);
3673}
3674
7d235eb5
SZ
3675#ifdef INVARIANTS
3676
3677static void
3678igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3679 boolean_t serialized)
3680{
3681 struct igb_softc *sc = ifp->if_softc;
3682
3683 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3684 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3685}
3686
3687#endif /* INVARIANTS */
be922da6
SZ
3688
3689static void
3690igb_set_intr_mask(struct igb_softc *sc)
3691{
3692 int i;
3693
9c0ecdcc 3694 sc->intr_mask = sc->sts_intr_mask;
be922da6
SZ
3695 for (i = 0; i < sc->rx_ring_inuse; ++i)
3696 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3697 for (i = 0; i < sc->tx_ring_cnt; ++i)
3698 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
9c0ecdcc
SZ
3699 if (bootverbose)
3700 device_printf(sc->dev, "intr mask 0x%08x\n", sc->intr_mask);
be922da6 3701}
3c7cc5e2
SZ
3702
3703static int
3704igb_alloc_intr(struct igb_softc *sc)
3705{
9c0ecdcc 3706 int i, intr_bit, intr_bitmax;
3c7cc5e2
SZ
3707 u_int intr_flags;
3708
9c0ecdcc
SZ
3709 igb_msix_try_alloc(sc);
3710 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3711 goto done;
3712
3713 /*
3714 * Allocate MSI/legacy interrupt resource
3715 */
3c7cc5e2
SZ
3716 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3717 &sc->intr_rid, &intr_flags);
3718
677d7b99
SZ
3719 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3720 int unshared;
3721
3722 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3723 if (!unshared) {
3724 sc->flags |= IGB_FLAG_SHARED_INTR;
3725 if (bootverbose)
3726 device_printf(sc->dev, "IRQ shared\n");
3727 } else {
3728 intr_flags &= ~RF_SHAREABLE;
3729 if (bootverbose)
3730 device_printf(sc->dev, "IRQ unshared\n");
3731 }
3732 }
3733
3c7cc5e2
SZ
3734 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3735 &sc->intr_rid, intr_flags);
3736 if (sc->intr_res == NULL) {
3737 device_printf(sc->dev, "Unable to allocate bus resource: "
3738 "interrupt\n");
3739 return ENXIO;
3740 }
9c0ecdcc
SZ
3741
3742 /*
3743 * Setup MSI/legacy interrupt mask
3744 */
3745 switch (sc->hw.mac.type) {
3746 case e1000_82575:
3747 intr_bitmax = IGB_MAX_TXRXINT_82575;
3748 break;
3749 case e1000_82580:
3750 intr_bitmax = IGB_MAX_TXRXINT_82580;
3751 break;
3752 case e1000_i350:
3753 intr_bitmax = IGB_MAX_TXRXINT_I350;
3754 break;
3755 case e1000_82576:
3756 intr_bitmax = IGB_MAX_TXRXINT_82576;
3757 break;
3758 default:
3759 intr_bitmax = IGB_MIN_TXRXINT;
3760 break;
3761 }
3762 intr_bit = 0;
3763 for (i = 0; i < sc->tx_ring_cnt; ++i)
3764 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3765 for (i = 0; i < sc->rx_ring_cnt; ++i)
3766 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3767 sc->sts_intr_bit = 0;
3768 sc->sts_intr_mask = E1000_EICR_OTHER;
3769
3770 /* Initialize interrupt rate */
3771 sc->intr_rate = IGB_INTR_RATE;
3772done:
3773 igb_set_ring_inuse(sc, FALSE);
3774 igb_set_intr_mask(sc);
3c7cc5e2
SZ
3775 return 0;
3776}
3777
3778static void
3779igb_free_intr(struct igb_softc *sc)
3780{
9c0ecdcc
SZ
3781 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3782 if (sc->intr_res != NULL) {
3783 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3784 sc->intr_res);
3785 }
3786 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3787 pci_release_msi(sc->dev);
3788 } else {
3789 igb_msix_free(sc, TRUE);
3790 }
3791}
3792
3793static void
3794igb_teardown_intr(struct igb_softc *sc)
3795{
3796 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3797 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3798 else
3799 igb_msix_teardown(sc, sc->msix_cnt);
3800}
3801
3802static void
3803igb_msix_try_alloc(struct igb_softc *sc)
3804{
3805 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3806 int i, x, error;
3807 struct igb_msix_data *msix;
3808 boolean_t aggregate, setup = FALSE;
3809
3810 /*
fea3f48a
SZ
3811 * Don't enable MSI-X on 82575, see:
3812 * 82575 specification update errata #25
9c0ecdcc
SZ
3813 */
3814 if (sc->hw.mac.type == e1000_82575)
3815 return;
3816
3817 /* Don't enable MSI-X on VF */
3818 if (sc->vf_ifp)
3819 return;
3820
3821 msix_enable = device_getenv_int(sc->dev, "msix.enable",
3822 igb_msix_enable);
3823 if (!msix_enable)
3824 return;
3825
3826 msix_cnt = pci_msix_count(sc->dev);
3827#ifdef IGB_MSIX_DEBUG
3828 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3829#endif
3830 if (msix_cnt <= 1) {
3831 /* One MSI-X model does not make sense */
3832 return;
3833 }
3834
3835 i = 0;
3836 while ((1 << (i + 1)) <= msix_cnt)
3837 ++i;
3838 msix_cnt2 = 1 << i;
3839
3840 if (bootverbose) {
3841 device_printf(sc->dev, "MSI-X count %d/%d\n",
3842 msix_cnt2, msix_cnt);
3843 }
3844
3845 KKASSERT(msix_cnt2 <= msix_cnt);
3846 if (msix_cnt == msix_cnt2) {
3847 /* We need at least one MSI-X for link status */
3848 msix_cnt2 >>= 1;
3849 if (msix_cnt2 <= 1) {
3850 /* One MSI-X for RX/TX does not make sense */
3851 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3852 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3853 return;
3854 }
3855 KKASSERT(msix_cnt > msix_cnt2);
3856
3857 if (bootverbose) {
3858 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
3859 msix_cnt2, msix_cnt);
3860 }
3861 }
3862
3863 sc->rx_ring_msix = sc->rx_ring_cnt;
3864 if (sc->rx_ring_msix > msix_cnt2)
3865 sc->rx_ring_msix = msix_cnt2;
3866
3867 if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
3868 /*
3869 * Independent TX/RX MSI-X
3870 */
3871 aggregate = FALSE;
3872 if (bootverbose)
3873 device_printf(sc->dev, "independent TX/RX MSI-X\n");
3874 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
3875 } else {
3876 /*
3877 * Aggregate TX/RX MSI-X
3878 */
3879 aggregate = TRUE;
3880 if (bootverbose)
3881 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
3882 alloc_cnt = msix_cnt2;
3883 if (alloc_cnt > ncpus2)
3884 alloc_cnt = ncpus2;
3885