Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / ed / if_ed.c
CommitLineData
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1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1f18ea8c 27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
78195a76 28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.28 2005/11/28 17:13:42 dillon Exp $
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29 */
30
31/*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
1f18ea8c
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41#include "opt_ed.h"
42
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43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/syslog.h>
888ab9b7 50#include <sys/thread2.h>
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51
52#include <sys/module.h>
53#include <sys/bus.h>
54
55#include <machine/bus.h>
56#include <sys/rman.h>
57#include <machine/resource.h>
58
59#include <net/ethernet.h>
60#include <net/if.h>
68adc7bf 61#include <net/ifq_var.h>
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62#include <net/if_arp.h>
63#include <net/if_dl.h>
64#include <net/if_mib.h>
65#include <net/if_media.h>
66
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67#ifndef ED_NO_MIIBUS
68#include <dev/netif/mii_layer/mii.h>
69#include <dev/netif/mii_layer/miivar.h>
70#endif
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71
72#include <net/bpf.h>
73#include "opt_bdg.h"
1f2de5d4 74#include <net/bridge/bridge.h>
984263bc 75
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76#include <machine/md_var.h>
77
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78#include "if_edreg.h"
79#include "if_edvar.h"
984263bc 80
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81devclass_t ed_devclass;
82
b5101a88 83static void ed_init (void *);
bd4539cc 84static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
b5101a88
RG
85static void ed_start (struct ifnet *);
86static void ed_reset (struct ifnet *);
87static void ed_watchdog (struct ifnet *);
1f18ea8c 88#ifndef ED_NO_MIIBUS
b5101a88 89static void ed_tick (void *);
1f18ea8c 90#endif
984263bc 91
b5101a88 92static void ds_getmcaf (struct ed_softc *, u_int32_t *);
984263bc 93
27b16ba9 94static void ed_get_packet (struct ed_softc *, char *, u_short);
984263bc 95
b5101a88
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96static __inline void ed_rint (struct ed_softc *);
97static __inline void ed_xmit (struct ed_softc *);
98static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
27b16ba9 99 u_short);
b5101a88 100static void ed_hpp_set_physical_link (struct ed_softc *);
27b16ba9
SZ
101static void ed_hpp_readmem (struct ed_softc *, u_short, u_char *, u_short);
102static void ed_hpp_writemem (struct ed_softc *, u_char *, u_short, u_short);
103static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *, int);
984263bc 104
27b16ba9 105static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *, int);
984263bc 106
b5101a88 107static void ed_setrcr (struct ed_softc *);
984263bc 108
1f18ea8c 109static uint32_t ds_mchash (const uint8_t *);
984263bc 110
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111DECLARE_DUMMY_MODULE(if_ed);
112
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113/*
114 * Interrupt conversion table for WD/SMC ASIC/83C584
115 */
27b16ba9 116static u_short ed_intr_val[] = {
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117 9,
118 3,
119 5,
120 7,
121 10,
122 11,
123 15,
124 4
125};
126
127/*
128 * Interrupt conversion table for 83C790
129 */
27b16ba9 130static u_short ed_790_intr_val[] = {
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131 0,
132 9,
133 3,
134 5,
135 7,
136 10,
137 11,
138 15
139};
140
141/*
142 * Interrupt conversion table for the HP PC LAN+
143 */
144
27b16ba9 145static u_short ed_hpp_intr_val[] = {
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146 0, /* 0 */
147 0, /* 1 */
148 0, /* 2 */
149 3, /* 3 */
150 4, /* 4 */
151 5, /* 5 */
152 6, /* 6 */
153 7, /* 7 */
154 0, /* 8 */
155 9, /* 9 */
156 10, /* 10 */
157 11, /* 11 */
158 12, /* 12 */
159 0, /* 13 */
160 0, /* 14 */
161 15 /* 15 */
162};
163
164/*
165 * Generic probe routine for testing for the existance of a DS8390.
166 * Must be called after the NIC has just been reset. This routine
167 * works by looking at certain register values that are guaranteed
168 * to be initialized a certain way after power-up or reset. Seems
169 * not to currently work on the 83C690.
170 *
171 * Specifically:
172 *
173 * Register reset bits set bits
174 * Command Register (CR) TXP, STA RD2, STP
175 * Interrupt Status (ISR) RST
176 * Interrupt Mask (IMR) All bits
177 * Data Control (DCR) LAS
178 * Transmit Config. (TCR) LB1, LB0
179 *
180 * We only look at the CR and ISR registers, however, because looking at
181 * the others would require changing register pages (which would be
182 * intrusive if this isn't an 8390).
183 *
184 * Return 1 if 8390 was found, 0 if not.
185 */
186
187int
27b16ba9 188ed_probe_generic8390(struct ed_softc *sc)
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189{
190 if ((ed_nic_inb(sc, ED_P0_CR) &
191 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
192 (ED_CR_RD2 | ED_CR_STP))
193 return (0);
194 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
195 return (0);
196
197 return (1);
198}
199
200/*
201 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
202 */
203int
27b16ba9 204ed_probe_WD80x3_generic(device_t dev, int flags, u_short *intr_vals[])
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205{
206 struct ed_softc *sc = device_get_softc(dev);
207 int error;
208 int i;
209 u_int memsize, maddr;
210 u_char iptr, isa16bit, sum, totalsum;
211 u_long conf_maddr, conf_msize, irq, junk;
212
213 sc->chip_type = ED_CHIP_TYPE_DP8390;
214
215 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
216 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
217 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
218 DELAY(10000);
219 }
220 else
221 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
222
223 /*
224 * Attempt to do a checksum over the station address PROM. If it
225 * fails, it's probably not a SMC/WD board. There is a problem with
226 * this, though: some clone WD boards don't pass the checksum test.
227 * Danpex boards for one.
228 */
229 for (sum = 0, i = 0; i < 8; ++i)
230 sum += ed_asic_inb(sc, ED_WD_PROM + i);
231
232 if (sum != totalsum) {
233
234 /*
235 * Checksum is invalid. This often happens with cheap WD8003E
236 * clones. In this case, the checksum byte (the eighth byte)
237 * seems to always be zero.
238 */
239 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
240 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
241 return (ENXIO);
242 }
243 /* reset card to force it into a known state. */
244 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
245 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
246 else
247 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
248
249 DELAY(100);
250 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
251 /* wait in the case this card is reading its EEROM */
252 DELAY(5000);
253
254 sc->vendor = ED_VENDOR_WD_SMC;
255 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
256
257 /*
258 * Set initial values for width/size.
259 */
260 memsize = 8192;
261 isa16bit = 0;
262 switch (sc->type) {
263 case ED_TYPE_WD8003S:
264 sc->type_str = "WD8003S";
265 break;
266 case ED_TYPE_WD8003E:
267 sc->type_str = "WD8003E";
268 break;
269 case ED_TYPE_WD8003EB:
270 sc->type_str = "WD8003EB";
271 break;
272 case ED_TYPE_WD8003W:
273 sc->type_str = "WD8003W";
274 break;
275 case ED_TYPE_WD8013EBT:
276 sc->type_str = "WD8013EBT";
277 memsize = 16384;
278 isa16bit = 1;
279 break;
280 case ED_TYPE_WD8013W:
281 sc->type_str = "WD8013W";
282 memsize = 16384;
283 isa16bit = 1;
284 break;
285 case ED_TYPE_WD8013EP: /* also WD8003EP */
286 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
287 isa16bit = 1;
288 memsize = 16384;
289 sc->type_str = "WD8013EP";
290 } else {
291 sc->type_str = "WD8003EP";
292 }
293 break;
294 case ED_TYPE_WD8013WC:
295 sc->type_str = "WD8013WC";
296 memsize = 16384;
297 isa16bit = 1;
298 break;
299 case ED_TYPE_WD8013EBP:
300 sc->type_str = "WD8013EBP";
301 memsize = 16384;
302 isa16bit = 1;
303 break;
304 case ED_TYPE_WD8013EPC:
305 sc->type_str = "WD8013EPC";
306 memsize = 16384;
307 isa16bit = 1;
308 break;
309 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
310 case ED_TYPE_SMC8216T:
311 if (sc->type == ED_TYPE_SMC8216C) {
312 sc->type_str = "SMC8216/SMC8216C";
313 } else {
314 sc->type_str = "SMC8216T";
315 }
316
317 ed_asic_outb(sc, ED_WD790_HWR,
318 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
319 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
320 case ED_WD790_RAR_SZ64:
321 memsize = 65536;
322 break;
323 case ED_WD790_RAR_SZ32:
324 memsize = 32768;
325 break;
326 case ED_WD790_RAR_SZ16:
327 memsize = 16384;
328 break;
329 case ED_WD790_RAR_SZ8:
330 /* 8216 has 16K shared mem -- 8416 has 8K */
331 if (sc->type == ED_TYPE_SMC8216C) {
332 sc->type_str = "SMC8416C/SMC8416BT";
333 } else {
334 sc->type_str = "SMC8416T";
335 }
336 memsize = 8192;
337 break;
338 }
339 ed_asic_outb(sc, ED_WD790_HWR,
340 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
341
342 isa16bit = 1;
343 sc->chip_type = ED_CHIP_TYPE_WD790;
344 break;
345 case ED_TYPE_TOSHIBA1:
346 sc->type_str = "Toshiba1";
347 memsize = 32768;
348 isa16bit = 1;
349 break;
350 case ED_TYPE_TOSHIBA4:
351 sc->type_str = "Toshiba4";
352 memsize = 32768;
353 isa16bit = 1;
354 break;
355 default:
356 sc->type_str = "";
357 break;
358 }
359
360 /*
361 * Make some adjustments to initial values depending on what is found
362 * in the ICR.
363 */
364 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
365 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
366 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
367 isa16bit = 0;
368 memsize = 8192;
369 }
370
371 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
372 &conf_maddr, &conf_msize);
373 if (error)
374 return (error);
375
376#if ED_DEBUG
377 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
378 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
379 for (i = 0; i < 8; i++)
380 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
381#endif
382
383 /*
384 * Allow the user to override the autoconfiguration
385 */
386 if (conf_msize > 1)
387 memsize = conf_msize;
388
389 maddr = conf_maddr;
390 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
391 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
392 maddr, maddr + memsize);
393 return (ENXIO);
394 }
395
396 /*
397 * (note that if the user specifies both of the following flags that
398 * '8bit' mode intentionally has precedence)
399 */
400 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
401 isa16bit = 1;
402 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
403 isa16bit = 0;
404
405 /*
406 * If possible, get the assigned interrupt number from the card and
407 * use it.
408 */
409 if ((sc->type & ED_WD_SOFTCONFIG) &&
410 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
411
412 /*
413 * Assemble together the encoded interrupt number.
414 */
415 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
416 ((ed_asic_inb(sc, ED_WD_IRR) &
417 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
418
419 /*
420 * If no interrupt specified (or "?"), use what the board tells us.
421 */
422 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
423 &irq, &junk);
424 if (error && intr_vals[0] != NULL) {
425 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
426 intr_vals[0][iptr], 1);
427 }
428 if (error)
429 return (error);
430
431 /*
432 * Enable the interrupt.
433 */
434 ed_asic_outb(sc, ED_WD_IRR,
435 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
436 }
437 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
438 ed_asic_outb(sc, ED_WD790_HWR,
439 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
440 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
441 (ed_asic_inb(sc, ED_WD790_GCR) &
442 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
443 ed_asic_outb(sc, ED_WD790_HWR,
444 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
445
446 /*
447 * If no interrupt specified (or "?"), use what the board tells us.
448 */
449 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
450 &irq, &junk);
451 if (error && intr_vals[1] != NULL) {
452 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
453 intr_vals[1][iptr], 1);
454 }
455 if (error)
456 return (error);
457
458 /*
459 * Enable interrupts.
460 */
461 ed_asic_outb(sc, ED_WD790_ICR,
462 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
463 }
464 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
465 &irq, &junk);
466 if (error) {
467 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
468 sc->type_str);
469 return (ENXIO);
470 }
471 sc->isa16bit = isa16bit;
472 sc->mem_shared = 1;
473
474 error = ed_alloc_memory(dev, 0, memsize);
475 if (error) {
476 printf("*** ed_alloc_memory() failed! (%d)\n", error);
477 return (error);
478 }
479 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
480
481 /*
482 * allocate one xmit buffer if < 16k, two buffers otherwise
483 */
484 if ((memsize < 16384) ||
485 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
486 sc->txb_cnt = 1;
487 } else {
488 sc->txb_cnt = 2;
489 }
490 sc->tx_page_start = ED_WD_PAGE_OFFSET;
491 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
492 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
493 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
494 sc->mem_size = memsize;
495 sc->mem_end = sc->mem_start + memsize;
496
497 /*
498 * Get station address from on-board ROM
499 */
500 for (i = 0; i < ETHER_ADDR_LEN; ++i)
501 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
502
503 /*
504 * Set upper address bits and 8/16 bit access to shared memory.
505 */
506 if (isa16bit) {
507 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
508 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
509 } else {
510 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
511 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
512 }
513 /*
514 * Enable 16bit access
515 */
516 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
517 ED_WD_LAAR_M16EN);
518 } else {
519 if (((sc->type & ED_WD_SOFTCONFIG) ||
520 (sc->type == ED_TYPE_TOSHIBA1) ||
521 (sc->type == ED_TYPE_TOSHIBA4) ||
522 (sc->type == ED_TYPE_WD8013EBT)) &&
523 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
524 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
525 ED_WD_LAAR_ADDRHI;
526 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
527 }
528 }
529
530 /*
531 * Set address and enable interface shared memory.
532 */
533 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
534 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
535 ed_asic_outb(sc, ED_WD_MSR + 1,
536 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
537 ed_asic_outb(sc, ED_WD_MSR + 2,
538 ((kvtop(sc->mem_start) >> 16) & 0x0f));
539 ed_asic_outb(sc, ED_WD_MSR,
540 ED_WD_MSR_MENB | ED_WD_MSR_POW);
541 } else {
542 ed_asic_outb(sc, ED_WD_MSR,
543 ((kvtop(sc->mem_start) >> 13) &
544 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
545 }
546 sc->cr_proto = ED_CR_RD2;
547 } else {
548 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
549 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
550 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
551 ((kvtop(sc->mem_start) >> 11) & 0x40) |
552 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
553 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
554 sc->cr_proto = 0;
555 }
556
557#if 0
558 printf("starting memory performance test at 0x%x, size %d...\n",
559 sc->mem_start, memsize*16384);
560 for (i = 0; i < 16384; i++)
561 bzero(sc->mem_start, memsize);
562 printf("***DONE***\n");
563#endif
564
565 /*
566 * Now zero memory and verify that it is clear
567 */
568 bzero(sc->mem_start, memsize);
569
570 for (i = 0; i < memsize; ++i) {
571 if (sc->mem_start[i]) {
79d1f4a5 572 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
1f18ea8c 573 (long long)kvtop(sc->mem_start + i));
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574
575 /*
576 * Disable 16 bit access to shared memory
577 */
578 if (isa16bit) {
579 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
580 ed_asic_outb(sc, ED_WD_MSR, 0x00);
581 }
582 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
583 ~ED_WD_LAAR_M16EN);
584 }
585 return (ENXIO);
586 }
587 }
588
589 /*
590 * Disable 16bit access to shared memory - we leave it
591 * disabled so that 1) machines reboot properly when the board
592 * is set 16 bit mode and there are conflicting 8bit
593 * devices/ROMS in the same 128k address space as this boards
594 * shared memory. and 2) so that other 8 bit devices with
595 * shared memory can be used in this 128k region, too.
596 */
597 if (isa16bit) {
598 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
599 ed_asic_outb(sc, ED_WD_MSR, 0x00);
600 }
601 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
602 ~ED_WD_LAAR_M16EN);
603 }
604 return (0);
605}
606
607int
27b16ba9 608ed_probe_WD80x3(device_t dev, int port_rid, int flags)
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609{
610 struct ed_softc *sc = device_get_softc(dev);
611 int error;
27b16ba9 612 static u_short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
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613
614 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
615 if (error)
616 return (error);
617
618 sc->asic_offset = ED_WD_ASIC_OFFSET;
619 sc->nic_offset = ED_WD_NIC_OFFSET;
620
621 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
622}
623
624/*
625 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
626 */
627int
27b16ba9 628ed_probe_3Com(device_t dev, int port_rid, int flags)
984263bc
MD
629{
630 struct ed_softc *sc = device_get_softc(dev);
631 int error;
632 int i;
633 u_int memsize;
634 u_char isa16bit;
635 u_long conf_maddr, conf_msize, irq, junk;
636
637 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
638 if (error)
639 return (error);
640
641 sc->asic_offset = ED_3COM_ASIC_OFFSET;
642 sc->nic_offset = ED_3COM_NIC_OFFSET;
643
644 /*
645 * Verify that the kernel configured I/O address matches the board
646 * configured address
647 */
648 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
649 case ED_3COM_BCFR_300:
650 if (rman_get_start(sc->port_res) != 0x300)
651 return (ENXIO);
652 break;
653 case ED_3COM_BCFR_310:
654 if (rman_get_start(sc->port_res) != 0x310)
655 return (ENXIO);
656 break;
657 case ED_3COM_BCFR_330:
658 if (rman_get_start(sc->port_res) != 0x330)
659 return (ENXIO);
660 break;
661 case ED_3COM_BCFR_350:
662 if (rman_get_start(sc->port_res) != 0x350)
663 return (ENXIO);
664 break;
665 case ED_3COM_BCFR_250:
666 if (rman_get_start(sc->port_res) != 0x250)
667 return (ENXIO);
668 break;
669 case ED_3COM_BCFR_280:
670 if (rman_get_start(sc->port_res) != 0x280)
671 return (ENXIO);
672 break;
673 case ED_3COM_BCFR_2A0:
674 if (rman_get_start(sc->port_res) != 0x2a0)
675 return (ENXIO);
676 break;
677 case ED_3COM_BCFR_2E0:
678 if (rman_get_start(sc->port_res) != 0x2e0)
679 return (ENXIO);
680 break;
681 default:
682 return (ENXIO);
683 }
684
685 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
686 &conf_maddr, &conf_msize);
687 if (error)
688 return (error);
689
690 /*
691 * Verify that the kernel shared memory address matches the board
692 * configured address.
693 */
694 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
695 case ED_3COM_PCFR_DC000:
696 if (conf_maddr != 0xdc000)
697 return (ENXIO);
698 break;
699 case ED_3COM_PCFR_D8000:
700 if (conf_maddr != 0xd8000)
701 return (ENXIO);
702 break;
703 case ED_3COM_PCFR_CC000:
704 if (conf_maddr != 0xcc000)
705 return (ENXIO);
706 break;
707 case ED_3COM_PCFR_C8000:
708 if (conf_maddr != 0xc8000)
709 return (ENXIO);
710 break;
711 default:
712 return (ENXIO);
713 }
714
715
716 /*
717 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
718 * sequence because it'll lock up if the cable isn't connected if we
719 * don't.
720 */
721 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
722
723 /*
724 * Wait for a while, then un-reset it
725 */
726 DELAY(50);
727
728 /*
729 * The 3Com ASIC defaults to rather strange settings for the CR after
730 * a reset - it's important to set it again after the following outb
731 * (this is done when we map the PROM below).
732 */
733 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
734
735 /*
736 * Wait a bit for the NIC to recover from the reset
737 */
738 DELAY(5000);
739
740 sc->vendor = ED_VENDOR_3COM;
741 sc->type_str = "3c503";
742 sc->mem_shared = 1;
743 sc->cr_proto = ED_CR_RD2;
744
745 /*
746 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
747 * to it.
748 */
749 memsize = 8192;
750
751 /*
752 * Get station address from on-board ROM
753 */
754
755 /*
756 * First, map ethernet address PROM over the top of where the NIC
757 * registers normally appear.
758 */
759 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
760
761 for (i = 0; i < ETHER_ADDR_LEN; ++i)
762 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
763
764 /*
765 * Unmap PROM - select NIC registers. The proper setting of the
766 * tranceiver is set in ed_init so that the attach code is given a
767 * chance to set the default based on a compile-time config option
768 */
769 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
770
771 /*
772 * Determine if this is an 8bit or 16bit board
773 */
774
775 /*
776 * select page 0 registers
777 */
778 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
779
780 /*
781 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
782 * board.
783 */
784 ed_nic_outb(sc, ED_P0_DCR, 0);
785
786 /*
787 * select page 2 registers
788 */
789 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
790
791 /*
792 * The 3c503 forces the WTS bit to a one if this is a 16bit board
793 */
794 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
795 isa16bit = 1;
796 else
797 isa16bit = 0;
798
799 /*
800 * select page 0 registers
801 */
802 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
803
804 error = ed_alloc_memory(dev, 0, memsize);
805 if (error)
806 return (error);
807
808 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
809 sc->mem_size = memsize;
810 sc->mem_end = sc->mem_start + memsize;
811
812 /*
813 * We have an entire 8k window to put the transmit buffers on the
814 * 16bit boards. But since the 16bit 3c503's shared memory is only
815 * fast enough to overlap the loading of one full-size packet, trying
816 * to load more than 2 buffers can actually leave the transmitter idle
817 * during the load. So 2 seems the best value. (Although a mix of
818 * variable-sized packets might change this assumption. Nonetheless,
819 * we optimize for linear transfers of same-size packets.)
820 */
821 if (isa16bit) {
822 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
823 sc->txb_cnt = 1;
824 else
825 sc->txb_cnt = 2;
826
827 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
828 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
829 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
830 ED_3COM_RX_PAGE_OFFSET_16BIT;
831 sc->mem_ring = sc->mem_start;
832 } else {
833 sc->txb_cnt = 1;
834 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
835 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
836 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
837 ED_3COM_TX_PAGE_OFFSET_8BIT;
838 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
839 }
840
841 sc->isa16bit = isa16bit;
842
843 /*
844 * Initialize GA page start/stop registers. Probably only needed if
845 * doing DMA, but what the hell.
846 */
847 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
848 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
849
850 /*
851 * Set IRQ. 3c503 only allows a choice of irq 2-5.
852 */
853 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
854 if (error)
855 return (error);
856
857 switch (irq) {
858 case 2:
859 case 9:
860 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
861 break;
862 case 3:
863 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
864 break;
865 case 4:
866 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
867 break;
868 case 5:
869 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
870 break;
871 default:
872 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
873 irq);
874 return (ENXIO);
875 }
876
877 /*
878 * Initialize GA configuration register. Set bank and enable shared
879 * mem.
880 */
881 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
882 ED_3COM_GACFR_MBS0);
883
884 /*
885 * Initialize "Vector Pointer" registers. These gawd-awful things are
886 * compared to 20 bits of the address on ISA, and if they match, the
887 * shared memory is disabled. We set them to 0xffff0...allegedly the
888 * reset vector.
889 */
890 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
891 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
892 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
893
894 /*
895 * Zero memory and verify that it is clear
896 */
897 bzero(sc->mem_start, memsize);
898
899 for (i = 0; i < memsize; ++i)
900 if (sc->mem_start[i]) {
27b16ba9
SZ
901 device_printf(dev, "failed to clear shared memory "
902 "at %llx - check configuration\n",
903 (unsigned long long)kvtop(sc->mem_start + i));
984263bc
MD
904 return (ENXIO);
905 }
906 return (0);
907}
908
79d1f4a5
HP
909/*
910 * Probe and vendor-specific initialization routine for SIC boards
911 */
912int
27b16ba9 913ed_probe_SIC(device_t dev, int port_rid, int flags)
79d1f4a5
HP
914{
915 struct ed_softc *sc = device_get_softc(dev);
916 int error;
917 int i;
918 u_int memsize;
919 u_long conf_maddr, conf_msize;
920 u_char sum;
921
922 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
923 if (error)
924 return (error);
925
926 sc->asic_offset = ED_SIC_ASIC_OFFSET;
927 sc->nic_offset = ED_SIC_NIC_OFFSET;
928
929 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
930 &conf_maddr, &conf_msize);
931 if (error)
932 return (error);
933
934 memsize = 16384;
935 if (conf_msize > 1)
936 memsize = conf_msize;
937
938 error = ed_alloc_memory(dev, 0, memsize);
939 if (error)
940 return (error);
941
942 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
943 sc->mem_size = memsize;
944
945 /* Reset card to force it into a known state. */
946 ed_asic_outb(sc, 0, 0x00);
947 DELAY(100);
948
949 /*
950 * Here we check the card ROM, if the checksum passes, and the
951 * type code and ethernet address check out, then we know we have
952 * an SIC card.
953 */
954 ed_asic_outb(sc, 0, 0x81);
955 DELAY(100);
956
957 sum = sc->mem_start[6];
958 for (i = 0; i < ETHER_ADDR_LEN; i++) {
959 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
960 }
961#ifdef ED_DEBUG
962 device_printf(dev, "ed_probe_sic: got address %6D\n",
963 sc->arpcom.ac_enaddr, ":");
964#endif
965 if (sum != 0) {
966 return (ENXIO);
967 }
968 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
969 sc->arpcom.ac_enaddr[2]) == 0) {
970 return (ENXIO);
971 }
972
973 sc->vendor = ED_VENDOR_SIC;
974 sc->type_str = "SIC";
975 sc->isa16bit = 0;
976 sc->cr_proto = 0;
977
978 /*
979 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
980 */
981 ed_asic_outb(sc, 0, 0x80);
982 DELAY(100);
983
984 /*
985 * Now zero memory and verify that it is clear
986 */
987 bzero(sc->mem_start, sc->mem_size);
988
989 for (i = 0; i < sc->mem_size; i++) {
990 if (sc->mem_start[i]) {
991 device_printf(dev, "failed to clear shared memory "
992 "at %llx - check configuration\n",
1f18ea8c 993 (long long)kvtop(sc->mem_start + i));
79d1f4a5
HP
994
995 return (ENXIO);
996 }
997 }
998
999 sc->mem_shared = 1;
1000 sc->mem_end = sc->mem_start + sc->mem_size;
1001
1002 /*
1003 * allocate one xmit buffer if < 16k, two buffers otherwise
1004 */
1005 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1006 sc->txb_cnt = 1;
1007 } else {
1008 sc->txb_cnt = 2;
1009 }
1010 sc->tx_page_start = 0;
1011
1012 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1013 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1014
1015 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1016
1017 return (0);
1018}
1019
984263bc
MD
1020/*
1021 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1022 */
1023int
27b16ba9 1024ed_probe_Novell_generic(device_t dev, int flags)
984263bc
MD
1025{
1026 struct ed_softc *sc = device_get_softc(dev);
1027 u_int memsize, n;
1028 u_char romdata[16], tmp;
1029 static char test_pattern[32] = "THIS is A memory TEST pattern";
1030 char test_buffer[32];
1031
1032 /* XXX - do Novell-specific probe here */
1033
1034 /* Reset the board */
1035 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1036 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1037 DELAY(200);
1038 }
1039 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1040
1041 /*
1042 * I don't know if this is necessary; probably cruft leftover from
1043 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1f18ea8c 1044 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
984263bc
MD
1045 * non-invasive...but some boards don't seem to reset and I don't have
1046 * complete documentation on what the 'right' thing to do is...so we
1047 * do the invasive thing for now. Yuck.]
1048 */
1049 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1050 DELAY(5000);
1051
1052 /*
1053 * This is needed because some NE clones apparently don't reset the
1054 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1055 * - this makes the probe invasive! ...Done against my better
1056 * judgement. -DLG
1057 */
1058 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1059
1060 DELAY(5000);
1061
1062 /* Make sure that we really have an 8390 based board */
1063 if (!ed_probe_generic8390(sc))
1064 return (ENXIO);
1065
1066 sc->vendor = ED_VENDOR_NOVELL;
1067 sc->mem_shared = 0;
1068 sc->cr_proto = ED_CR_RD2;
1069
1070 /*
1071 * Test the ability to read and write to the NIC memory. This has the
1072 * side affect of determining if this is an NE1000 or an NE2000.
1073 */
1074
1075 /*
1076 * This prevents packets from being stored in the NIC memory when the
1077 * readmem routine turns on the start bit in the CR.
1078 */
1079 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1080
1081 /* Temporarily initialize DCR for byte operations */
1082 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1083
1084 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1085 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1086
1087 sc->isa16bit = 0;
1088
1089 /*
1090 * Write a test pattern in byte mode. If this fails, then there
1091 * probably isn't any memory at 8k - which likely means that the board
1092 * is an NE2000.
1093 */
1094 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1095 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1096
1097 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1098 sc->type = ED_TYPE_NE1000;
1099 sc->type_str = "NE1000";
1100 } else {
1101
1102 /* neither an NE1000 nor a Linksys - try NE2000 */
1103 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1104 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1105 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1106
1107 sc->isa16bit = 1;
1108
1109 /*
1110 * Write a test pattern in word mode. If this also fails, then
1111 * we don't know what this board is.
1112 */
1113 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1114 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1115 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1116 sc->type = ED_TYPE_NE2000;
1117 sc->type_str = "NE2000";
1118 } else {
1119 return (ENXIO);
1120 }
1121 }
1122
1123
1124 /* 8k of memory plus an additional 8k if 16bit */
1125 memsize = 8192 + sc->isa16bit * 8192;
1126
1127#if 0 /* probably not useful - NE boards only come two ways */
1128 /* allow kernel config file overrides */
1129 if (isa_dev->id_msize)
1130 memsize = isa_dev->id_msize;
1131#endif
1132
1133 sc->mem_size = memsize;
1134
1135 /* NIC memory doesn't start at zero on an NE board */
1136 /* The start address is tied to the bus width */
1137 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1138 sc->mem_end = sc->mem_start + memsize;
1139 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1140
1141 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1142 int x, i, mstart = 0, msize = 0;
1143 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1144
1145 for (i = 0; i < ED_PAGE_SIZE; i++)
1146 pbuf0[i] = 0;
1147
1148 /* Clear all the memory. */
1149 for (x = 1; x < 256; x++)
1150 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1151
1152 /* Search for the start of RAM. */
1153 for (x = 1; x < 256; x++) {
1154 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1155 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1156 for (i = 0; i < ED_PAGE_SIZE; i++)
1157 pbuf[i] = 255 - x;
1158 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1159 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1160 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1161 mstart = x * ED_PAGE_SIZE;
1162 msize = ED_PAGE_SIZE;
1163 break;
1164 }
1165 }
1166 }
1167
1168 if (mstart == 0) {
1169 device_printf(dev, "Cannot find start of RAM.\n");
1170 return (ENXIO);
1171 }
1172 /* Search for the start of RAM. */
1173 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1174 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1175 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1176 for (i = 0; i < ED_PAGE_SIZE; i++)
1177 pbuf[i] = 255 - x;
1178 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1179 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1180 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1181 msize += ED_PAGE_SIZE;
1182 else {
1183 break;
1184 }
1185 } else {
1186 break;
1187 }
1188 }
1189
1190 if (msize == 0) {
1191 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1192 return (ENXIO);
1193 }
1194 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1195
1196 sc->mem_size = msize;
1197 sc->mem_start = (caddr_t) mstart;
1198 sc->mem_end = (caddr_t) (msize + mstart);
1199 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1200 }
1201
1202 /*
1203 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1204 * otherwise).
1205 */
1206 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1207 sc->txb_cnt = 1;
1208 else
1209 sc->txb_cnt = 2;
1210
1211 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1212 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1213
1214 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1215
1216 ed_pio_readmem(sc, 0, romdata, 16);
1217 for (n = 0; n < ETHER_ADDR_LEN; n++)
1218 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1219
1220 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1221 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1222 sc->type_str = "Gateway AT";
1223 }
1224
1225 /* clear any pending interrupts that might have occurred above */
1226 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1227
1228 return (0);
1229}
1230
1231int
27b16ba9 1232ed_probe_Novell(device_t dev, int port_rid, int flags)
984263bc
MD
1233{
1234 struct ed_softc *sc = device_get_softc(dev);
1235 int error;
1236
1237 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1238 if (error)
1239 return (error);
1240
1241 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1242 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1243
1244 return ed_probe_Novell_generic(dev, flags);
1245}
1246
1247#define ED_HPP_TEST_SIZE 16
1248
1249/*
1250 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1251 * (HP Part nos: 27247B and 27252A).
1252 *
1253 * The card has an asic wrapper around a DS8390 core. The asic handles
1254 * host accesses and offers both standard register IO and memory mapped
1255 * IO. Memory mapped I/O allows better performance at the expense of greater
1256 * chance of an incompatibility with existing ISA cards.
1257 *
1258 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1259 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1260 * don't allow 32 bit accesses; these are indicated by a bit in the software
1261 * ID register (see if_edreg.h).
1262 *
1263 * Other caveats are: we should read the MAC address only when the card
1264 * is inactive.
1265 *
1266 * For more information; please consult the CRYNWR packet driver.
1267 *
1268 * The AUI port is turned on using the "link2" option on the ifconfig
1269 * command line.
1270 */
1271int
27b16ba9 1272ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
984263bc
MD
1273{
1274 struct ed_softc *sc = device_get_softc(dev);
1275 int error;
1276 int n; /* temp var */
1277 int memsize; /* mem on board */
1278 u_char checksum; /* checksum of board address */
1279 u_char irq; /* board configured IRQ */
1280 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1281 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1282 u_long conf_maddr, conf_msize, conf_irq, junk;
1283
1284 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1285 if (error)
1286 return (error);
1287
1288 /* Fill in basic information */
1289 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1290 sc->nic_offset = ED_HPP_NIC_OFFSET;
1291
1292 sc->chip_type = ED_CHIP_TYPE_DP8390;
1293 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1294
1295 /*
1296 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1297 */
1298
1299 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1300 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1301 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1302 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1303 return ENXIO;
1304
1305 /*
1306 * Read the MAC address and verify checksum on the address.
1307 */
1308
1309 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1310 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1311 checksum += (sc->arpcom.ac_enaddr[n] =
1312 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1313
1314 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1315
1316 if (checksum != 0xFF)
1317 return ENXIO;
1318
1319 /*
1320 * Verify that the software model number is 0.
1321 */
1322
1323 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1324 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1325 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1326 return ENXIO;
1327
1328 /*
1329 * Read in and save the current options configured on card.
1330 */
1331
1332 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1333
1334 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1335 ED_HPP_OPTION_CHIP_RESET |
1336 ED_HPP_OPTION_ENABLE_IRQ);
1337
1338 /*
1339 * Reset the chip. This requires writing to the option register
1340 * so take care to preserve the other bits.
1341 */
1342
1343 ed_asic_outw(sc, ED_HPP_OPTION,
1344 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1345 ED_HPP_OPTION_CHIP_RESET)));
1346
1347 DELAY(5000); /* wait for chip reset to complete */
1348
1349 ed_asic_outw(sc, ED_HPP_OPTION,
1350 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1351 ED_HPP_OPTION_CHIP_RESET |
1352 ED_HPP_OPTION_ENABLE_IRQ)));
1353
1354 DELAY(5000);
1355
1356 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1357 return ENXIO; /* reset did not complete */
1358
1359 /*
1360 * Read out configuration information.
1361 */
1362
1363 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1364
1365 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1366
1367 /*
1368 * Check for impossible IRQ.
1369 */
1370
1371 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1372 return ENXIO;
1373
1374 /*
1375 * If the kernel IRQ was specified with a '?' use the cards idea
1376 * of the IRQ. If the kernel IRQ was explicitly specified, it
1377 * should match that of the hardware.
1378 */
1379 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1380 &conf_irq, &junk);
1381 if (error) {
1382 bus_set_resource(dev, SYS_RES_IRQ, 0,
1383 ed_hpp_intr_val[irq], 1);
1384 } else {
1385 if (conf_irq != ed_hpp_intr_val[irq])
1386 return (ENXIO);
1387 }
1388
1389 /*
1390 * Fill in softconfig info.
1391 */
1392
1393 sc->vendor = ED_VENDOR_HP;
1394 sc->type = ED_TYPE_HP_PCLANPLUS;
1395 sc->type_str = "HP-PCLAN+";
1396
1397 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1398 sc->mem_start = 0; /* we use offsets inside the card RAM */
1399
1400 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1401
1402 /*
1403 * The board has 32KB of memory. Is there a way to determine
1404 * this programmatically?
1405 */
1406
1407 memsize = 32768;
1408
1409 /*
1410 * Check if memory mapping of the I/O registers possible.
1411 */
1412
1413 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1414 {
1415 u_long mem_addr;
1416
1417 /*
1418 * determine the memory address from the board.
1419 */
1420
1421 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1422 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1423
1424 /*
1425 * Check that the kernel specified start of memory and
1426 * hardware's idea of it match.
1427 */
1428 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1429 &conf_maddr, &conf_msize);
1430 if (error)
1431 return (error);
1432
1433 if (mem_addr != conf_maddr)
1434 return ENXIO;
1435
1436 error = ed_alloc_memory(dev, 0, memsize);
1437 if (error)
1438 return (error);
1439
1440 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1441 }
1442
1443 /*
1444 * Fill in the rest of the soft config structure.
1445 */
1446
1447 /*
1448 * The transmit page index.
1449 */
1450
1451 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1452
1453 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1454 sc->txb_cnt = 1;
1455 else
1456 sc->txb_cnt = 2;
1457
1458 /*
1459 * Memory description
1460 */
1461
1462 sc->mem_size = memsize;
1463 sc->mem_ring = sc->mem_start +
1464 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1465 sc->mem_end = sc->mem_start + sc->mem_size;
1466
1467 /*
1468 * Receive area starts after the transmit area and
1469 * continues till the end of memory.
1470 */
1471
1472 sc->rec_page_start = sc->tx_page_start +
1473 (sc->txb_cnt * ED_TXBUF_SIZE);
1474 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1475
1476
1477 sc->cr_proto = 0; /* value works */
1478
1479 /*
1480 * Set the wrap registers for string I/O reads.
1481 */
1482
1483 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1484 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1485 ((sc->rec_page_start / ED_PAGE_SIZE) |
1486 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1487
1488 /*
1489 * Reset the register page to normal operation.
1490 */
1491
1492 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1493
1494 /*
1495 * Verify that we can read/write from adapter memory.
1496 * Create test pattern.
1497 */
1498
1499 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1500 {
1501 test_pattern[n] = (n*n) ^ ~n;
1502 }
1503
1504#undef ED_HPP_TEST_SIZE
1505
1506 /*
1507 * Check that the memory is accessible thru the I/O ports.
1508 * Write out the contents of "test_pattern", read back
1509 * into "test_buffer" and compare the two for any
1510 * mismatch.
1511 */
1512
1513 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1514
1515 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1516 sizeof(test_pattern));
1517 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1518 test_buffer, sizeof(test_pattern));
1519
1520 if (bcmp(test_pattern, test_buffer,
1521 sizeof(test_pattern)))
1522 return ENXIO;
1523 }
1524
1525 return (0);
1526
1527}
1528
1529/*
1530 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1531 */
1532
1f18ea8c 1533static void
984263bc
MD
1534ed_hpp_set_physical_link(struct ed_softc *sc)
1535{
1536 struct ifnet *ifp = &sc->arpcom.ac_if;
1537 int lan_page;
1538
1539 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1540 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1541
1542 if (ifp->if_flags & IFF_ALTPHYS) {
1543
1544 /*
1545 * Use the AUI port.
1546 */
1547
1548 lan_page |= ED_HPP_LAN_AUI;
1549
1550 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1551 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1552
1553
1554 } else {
1555
1556 /*
1557 * Use the ThinLan interface
1558 */
1559
1560 lan_page &= ~ED_HPP_LAN_AUI;
1561
1562 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1563 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1564
1565 }
1566
1567 /*
1568 * Wait for the lan card to re-initialize itself
1569 */
1570
1571 DELAY(150000); /* wait 150 ms */
1572
1573 /*
1574 * Restore normal pages.
1575 */
1576
1577 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1578
1579}
1580
1581/*
1582 * Allocate a port resource with the given resource id.
1583 */
1584int
27b16ba9 1585ed_alloc_port(device_t dev, int rid, int size)
984263bc
MD
1586{
1587 struct ed_softc *sc = device_get_softc(dev);
1588 struct resource *res;
1589
1590 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1591 0ul, ~0ul, size, RF_ACTIVE);
1592 if (res) {
1593 sc->port_rid = rid;
1594 sc->port_res = res;
1595 sc->port_used = size;
1596 return (0);
1597 } else {
1598 return (ENOENT);
1599 }
1600}
1601
1602/*
1603 * Allocate a memory resource with the given resource id.
1604 */
1605int
27b16ba9 1606ed_alloc_memory(device_t dev, int rid, int size)
984263bc
MD
1607{
1608 struct ed_softc *sc = device_get_softc(dev);
1609 struct resource *res;
1610
1611 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1612 0ul, ~0ul, size, RF_ACTIVE);
1613 if (res) {
1614 sc->mem_rid = rid;
1615 sc->mem_res = res;
1616 sc->mem_used = size;
1617 return (0);
1618 } else {
1619 return (ENOENT);
1620 }
1621}
1622
1623/*
1624 * Allocate an irq resource with the given resource id.
1625 */
1626int
27b16ba9 1627ed_alloc_irq(device_t dev, int rid, int flags)
984263bc
MD
1628{
1629 struct ed_softc *sc = device_get_softc(dev);
1630 struct resource *res;
1631
4e6d744d
JS
1632 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1633 (RF_ACTIVE | flags));
984263bc
MD
1634 if (res) {
1635 sc->irq_rid = rid;
1636 sc->irq_res = res;
1637 return (0);
1638 } else {
1639 return (ENOENT);
1640 }
1641}
1642
1643/*
1644 * Release all resources
1645 */
1646void
27b16ba9 1647ed_release_resources(device_t dev)
984263bc
MD
1648{
1649 struct ed_softc *sc = device_get_softc(dev);
1650
1651 if (sc->port_res) {
1f18ea8c
JS
1652 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1653 sc->port_rid, sc->port_res);
984263bc
MD
1654 bus_release_resource(dev, SYS_RES_IOPORT,
1655 sc->port_rid, sc->port_res);
1656 sc->port_res = 0;
1657 }
1658 if (sc->mem_res) {
1f18ea8c
JS
1659 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1660 sc->mem_rid, sc->mem_res);
984263bc
MD
1661 bus_release_resource(dev, SYS_RES_MEMORY,
1662 sc->mem_rid, sc->mem_res);
1663 sc->mem_res = 0;
1664 }
1665 if (sc->irq_res) {
1f18ea8c
JS
1666 bus_deactivate_resource(dev, SYS_RES_IRQ,
1667 sc->irq_rid, sc->irq_res);
984263bc
MD
1668 bus_release_resource(dev, SYS_RES_IRQ,
1669 sc->irq_rid, sc->irq_res);
1670 sc->irq_res = 0;
1671 }
1672}
1673
1674/*
1675 * Install interface into kernel networking data structures
1676 */
1677int
1f18ea8c 1678ed_attach(device_t dev)
984263bc 1679{
1f18ea8c 1680 struct ed_softc *sc = device_get_softc(dev);
984263bc
MD
1681 struct ifnet *ifp = &sc->arpcom.ac_if;
1682
4f65d502 1683 callout_init(&sc->ed_timer);
984263bc
MD
1684 /*
1685 * Set interface to stopped condition (reset)
1686 */
1687 ed_stop(sc);
1688
3e4a09e7
MD
1689 /*
1690 * Initialize ifnet structure
1691 */
1692 ifp->if_softc = sc;
1f18ea8c 1693 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1f18ea8c 1694 ifp->if_mtu = ETHERMTU;
3e4a09e7
MD
1695 ifp->if_start = ed_start;
1696 ifp->if_ioctl = ed_ioctl;
1697 ifp->if_watchdog = ed_watchdog;
1698 ifp->if_init = ed_init;
68adc7bf
JS
1699 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1700 ifq_set_ready(&ifp->if_snd);
3e4a09e7
MD
1701 ifp->if_linkmib = &sc->mibdata;
1702 ifp->if_linkmiblen = sizeof sc->mibdata;
1f18ea8c 1703 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3e4a09e7
MD
1704 /*
1705 * XXX - should do a better job.
1706 */
1707 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1708 sc->mibdata.dot3StatsEtherChipSet =
1709 DOT3CHIPSET(dot3VendorWesternDigital,
1710 dot3ChipSetWesternDigital83C790);
1711 else
1712 sc->mibdata.dot3StatsEtherChipSet =
1713 DOT3CHIPSET(dot3VendorNational,
1714 dot3ChipSetNational8390);
1715 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
984263bc 1716
3e4a09e7
MD
1717 /*
1718 * Set default state for ALTPHYS flag (used to disable the
1719 * tranceiver for AUI operation), based on compile-time
1720 * config option.
1721 */
1f18ea8c
JS
1722 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1723 ifp->if_flags |= IFF_ALTPHYS;
3e4a09e7
MD
1724
1725 /*
1726 * Attach the interface
1727 */
78195a76 1728 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
984263bc 1729
984263bc
MD
1730 /* device attach does transition from UNCONFIGURED to IDLE state */
1731
984263bc
MD
1732 if (sc->type_str && (*sc->type_str != 0))
1733 printf("type %s ", sc->type_str);
1734 else
1735 printf("type unknown (0x%x) ", sc->type);
1736
1737 if (sc->vendor == ED_VENDOR_HP)
1738 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1739 "16-bit" : "32-bit",
1740 sc->hpp_mem_start ? "memory mapped" : "regular");
1741 else
1742 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1743
1744 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1745 (sc->vendor == ED_VENDOR_HP)) &&
1746 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1747
1748 return (0);
1749}
1750
1751/*
1752 * Reset interface.
1753 */
1754static void
27b16ba9 1755ed_reset(struct ifnet *ifp)
984263bc
MD
1756{
1757 struct ed_softc *sc = ifp->if_softc;
984263bc 1758
888ab9b7
JS
1759 crit_enter();
1760
1761 if (sc->gone) {
1762 crit_exit();
984263bc 1763 return;
888ab9b7 1764 }
984263bc
MD
1765
1766 /*
1767 * Stop interface and re-initialize.
1768 */
1769 ed_stop(sc);
1770 ed_init(sc);
1771
888ab9b7 1772 crit_exit();
984263bc
MD
1773}
1774
1775/*
1776 * Take interface offline.
1777 */
1778void
27b16ba9 1779ed_stop(struct ed_softc *sc)
984263bc
MD
1780{
1781 int n = 5000;
1782
1f18ea8c 1783#ifndef ED_NO_MIIBUS
4f65d502 1784 callout_stop(&sc->ed_timer);
1f18ea8c 1785#endif
984263bc
MD
1786 if (sc->gone)
1787 return;
1788 /*
1789 * Stop everything on the interface, and select page 0 registers.
1790 */
1791 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1792
1793 /*
1794 * Wait for interface to enter stopped state, but limit # of checks to
1795 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1796 * just in case it's an old one.
1797 */
1798 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1799 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1800}
1801
1802/*
1803 * Device timeout/watchdog routine. Entered if the device neglects to
1804 * generate an interrupt after a transmit has been started on it.
1805 */
1806static void
27b16ba9 1807ed_watchdog(struct ifnet *ifp)
984263bc
MD
1808{
1809 struct ed_softc *sc = ifp->if_softc;
1810
1811 if (sc->gone)
1812 return;
3e4a09e7 1813 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
984263bc
MD
1814 ifp->if_oerrors++;
1815
1816 ed_reset(ifp);
1817}
1818
1f18ea8c 1819#ifndef ED_NO_MIIBUS
984263bc 1820static void
27b16ba9 1821ed_tick(void *arg)
984263bc
MD
1822{
1823 struct ed_softc *sc = arg;
1824 struct mii_data *mii;
78195a76 1825 struct ifnet *ifp;
984263bc 1826
78195a76
MD
1827 ifp = &sc->arpcom.ac_if;
1828 lwkt_serialize_enter(ifp->if_serializer);
888ab9b7
JS
1829
1830 if (sc->gone) {
1831 crit_exit();
984263bc 1832 return;
888ab9b7
JS
1833 }
1834
984263bc
MD
1835 if (sc->miibus != NULL) {
1836 mii = device_get_softc(sc->miibus);
1837 mii_tick(mii);
1838 }
888ab9b7 1839
4f65d502 1840 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
78195a76 1841 lwkt_serialize_exit(ifp->if_serializer);
984263bc 1842}
1f18ea8c 1843#endif
984263bc
MD
1844
1845/*
1846 * Initialize device.
1847 */
1848static void
27b16ba9 1849ed_init(void *xsc)
984263bc
MD
1850{
1851 struct ed_softc *sc = xsc;
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
888ab9b7 1853 int i;
984263bc 1854
888ab9b7
JS
1855 crit_enter();
1856
1857 if (sc->gone) {
1858 crit_exit();
984263bc 1859 return;
888ab9b7 1860 }
984263bc 1861
984263bc
MD
1862 /*
1863 * Initialize the NIC in the exact order outlined in the NS manual.
1864 * This init procedure is "mandatory"...don't change what or when
1865 * things happen.
1866 */
984263bc
MD
1867
1868 /* reset transmitter flags */
1869 sc->xmit_busy = 0;
1870 ifp->if_timer = 0;
1871
1872 sc->txb_inuse = 0;
1873 sc->txb_new = 0;
1874 sc->txb_next_tx = 0;
1875
1876 /* This variable is used below - don't move this assignment */
1877 sc->next_packet = sc->rec_page_start + 1;
1878
1879 /*
1880 * Set interface for page 0, Remote DMA complete, Stopped
1881 */
1882 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1883
1884 if (sc->isa16bit) {
1885
1886 /*
1887 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1888 * order=80x86, word-wide DMA xfers,
1889 */
1890 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1891 } else {
1892
1893 /*
1894 * Same as above, but byte-wide DMA xfers
1895 */
1896 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1897 }
1898
1899 /*
1900 * Clear Remote Byte Count Registers
1901 */
1902 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1903 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1904
1905 /*
1906 * For the moment, don't store incoming packets in memory.
1907 */
1908 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1909
1910 /*
1911 * Place NIC in internal loopback mode
1912 */
1913 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1914
1915 /*
1916 * Initialize transmit/receive (ring-buffer) Page Start
1917 */
1918 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1919 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1920 /* Set lower bits of byte addressable framing to 0 */
1921 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1922 ed_nic_outb(sc, 0x09, 0);
1923
1924 /*
1925 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1926 */
1927 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1928 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1929
1930 /*
1931 * Clear all interrupts. A '1' in each bit position clears the
1932 * corresponding flag.
1933 */
1934 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1935
1936 /*
1937 * Enable the following interrupts: receive/transmit complete,
1938 * receive/transmit error, and Receiver OverWrite.
1939 *
1940 * Counter overflow and Remote DMA complete are *not* enabled.
1941 */
1942 ed_nic_outb(sc, ED_P0_IMR,
1943 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1944
1945 /*
1946 * Program Command Register for page 1
1947 */
1948 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1949
1950 /*
1951 * Copy out our station address
1952 */
1953 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1954 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1955
1956 /*
1957 * Set Current Page pointer to next_packet (initialized above)
1958 */
1959 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1960
1961 /*
1962 * Program Receiver Configuration Register and multicast filter. CR is
1963 * set to page 0 on return.
1964 */
1965 ed_setrcr(sc);
1966
1967 /*
1968 * Take interface out of loopback
1969 */
1970 ed_nic_outb(sc, ED_P0_TCR, 0);
1971
1972 /*
1973 * If this is a 3Com board, the tranceiver must be software enabled
1974 * (there is no settable hardware default).
1975 */
1976 if (sc->vendor == ED_VENDOR_3COM) {
1977 if (ifp->if_flags & IFF_ALTPHYS) {
1978 ed_asic_outb(sc, ED_3COM_CR, 0);
1979 } else {
1980 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1981 }
1982 }
1983
1f18ea8c 1984#ifndef ED_NO_MIIBUS
984263bc
MD
1985 if (sc->miibus != NULL) {
1986 struct mii_data *mii;
1987 mii = device_get_softc(sc->miibus);
1988 mii_mediachg(mii);
1989 }
1f18ea8c 1990#endif
984263bc
MD
1991 /*
1992 * Set 'running' flag, and clear output active flag.
1993 */
1994 ifp->if_flags |= IFF_RUNNING;
1995 ifp->if_flags &= ~IFF_OACTIVE;
1996
1997 /*
1998 * ...and attempt to start output
1999 */
2000 ed_start(ifp);
2001
1f18ea8c 2002#ifndef ED_NO_MIIBUS
4f65d502 2003 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1f18ea8c 2004#endif
888ab9b7
JS
2005
2006 crit_exit();
984263bc
MD
2007}
2008
2009/*
2010 * This routine actually starts the transmission on the interface
2011 */
2012static __inline void
27b16ba9 2013ed_xmit(struct ed_softc *sc)
984263bc
MD
2014{
2015 struct ifnet *ifp = (struct ifnet *)sc;
27b16ba9 2016 u_short len;
984263bc
MD
2017
2018 if (sc->gone)
2019 return;
2020 len = sc->txb_len[sc->txb_next_tx];
2021
2022 /*
2023 * Set NIC for page 0 register access
2024 */
2025 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2026
2027 /*
2028 * Set TX buffer start page
2029 */
2030 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2031 sc->txb_next_tx * ED_TXBUF_SIZE);
2032
2033 /*
2034 * Set TX length
2035 */
2036 ed_nic_outb(sc, ED_P0_TBCR0, len);
2037 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2038
2039 /*
2040 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2041 */
2042 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2043 sc->xmit_busy = 1;
2044
2045 /*
2046 * Point to next transmit buffer slot and wrap if necessary.
2047 */
2048 sc->txb_next_tx++;
2049 if (sc->txb_next_tx == sc->txb_cnt)
2050 sc->txb_next_tx = 0;
2051
2052 /*
2053 * Set a timer just in case we never hear from the board again
2054 */
2055 ifp->if_timer = 2;
2056}
2057
2058/*
2059 * Start output on interface.
2060 * We make two assumptions here:
2061 * 1) that the current priority is set to splimp _before_ this code
2062 * is called *and* is returned to the appropriate priority after
2063 * return
2064 * 2) that the IFF_OACTIVE flag is checked before this code is called
2065 * (i.e. that the output part of the interface is idle)
2066 */
2067static void
27b16ba9 2068ed_start(struct ifnet *ifp)
984263bc
MD
2069{
2070 struct ed_softc *sc = ifp->if_softc;
2071 struct mbuf *m0, *m;
2072 caddr_t buffer;
2073 int len;
2074
2075 if (sc->gone) {
2076 printf("ed_start(%p) GONE\n",ifp);
2077 return;
2078 }
2079outloop:
2080
2081 /*
2082 * First, see if there are buffered packets and an idle transmitter -
2083 * should never happen at this point.
2084 */
2085 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2086 printf("ed: packets buffered, but transmitter idle\n");
2087 ed_xmit(sc);
2088 }
2089
2090 /*
2091 * See if there is room to put another packet in the buffer.
2092 */
2093 if (sc->txb_inuse == sc->txb_cnt) {
2094
2095 /*
2096 * No room. Indicate this to the outside world and exit.
2097 */
2098 ifp->if_flags |= IFF_OACTIVE;
2099 return;
2100 }
d2c71fa0 2101 m = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
2102 if (m == 0) {
2103
2104 /*
2105 * We are using the !OACTIVE flag to indicate to the outside
2106 * world that we can accept an additional packet rather than
2107 * that the transmitter is _actually_ active. Indeed, the
2108 * transmitter may be active, but if we haven't filled all the
2109 * buffers with data then we still want to accept more.
2110 */
2111 ifp->if_flags &= ~IFF_OACTIVE;
2112 return;
2113 }
2114
2115 /*
2116 * Copy the mbuf chain into the transmit buffer
2117 */
2118
2119 m0 = m;
2120
2121 /* txb_new points to next open buffer slot */
2122 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2123
2124 if (sc->mem_shared) {
2125
2126 /*
2127 * Special case setup for 16 bit boards...
2128 */
2129 if (sc->isa16bit) {
2130 switch (sc->vendor) {
2131
2132 /*
2133 * For 16bit 3Com boards (which have 16k of
2134 * memory), we have the xmit buffers in a
2135 * different page of memory ('page 0') - so
2136 * change pages.
2137 */
2138 case ED_VENDOR_3COM:
2139 ed_asic_outb(sc, ED_3COM_GACFR,
2140 ED_3COM_GACFR_RSEL);
2141 break;
2142
2143 /*
2144 * Enable 16bit access to shared memory on
2145 * WD/SMC boards.
2146 */
2147 case ED_VENDOR_WD_SMC:
2148 ed_asic_outb(sc, ED_WD_LAAR,
2149 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2150 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2151 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2152 }
2153 break;
2154 }
2155 }
2156 for (len = 0; m != 0; m = m->m_next) {
2157 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2158 buffer += m->m_len;
2159 len += m->m_len;
2160 }
2161
2162 /*
2163 * Restore previous shared memory access
2164 */
2165 if (sc->isa16bit) {
2166 switch (sc->vendor) {
2167 case ED_VENDOR_3COM:
2168 ed_asic_outb(sc, ED_3COM_GACFR,
2169 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2170 break;
2171 case ED_VENDOR_WD_SMC:
2172 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2173 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2174 }
2175 ed_asic_outb(sc, ED_WD_LAAR,
2176 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2177 break;
2178 }
2179 }
2180 } else {
2181 len = ed_pio_write_mbufs(sc, m, (int)buffer);
1f18ea8c
JS
2182 if (len == 0) {
2183 m_freem(m0);
984263bc 2184 goto outloop;
1f18ea8c 2185 }
984263bc
MD
2186 }
2187
2188 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2189
2190 sc->txb_inuse++;
2191
2192 /*
2193 * Point to next buffer slot and wrap if necessary.
2194 */
2195 sc->txb_new++;
2196 if (sc->txb_new == sc->txb_cnt)
2197 sc->txb_new = 0;
2198
2199 if (sc->xmit_busy == 0)
2200 ed_xmit(sc);
2201
7600679e 2202 BPF_MTAP(ifp, m0);
984263bc
MD
2203
2204 m_freem(m0);
2205
2206 /*
2207 * Loop back to the top to possibly buffer more packets
2208 */
2209 goto outloop;
2210}
2211
2212/*
2213 * Ethernet interface receiver interrupt.
2214 */
2215static __inline void
27b16ba9 2216ed_rint(struct ed_softc *sc)
984263bc
MD
2217{
2218 struct ifnet *ifp = &sc->arpcom.ac_if;
2219 u_char boundry;
2220 u_short len;
2221 struct ed_ring packet_hdr;
2222 char *packet_ptr;
2223
2224 if (sc->gone)
2225 return;
2226
2227 /*
2228 * Set NIC to page 1 registers to get 'current' pointer
2229 */
2230 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2231
2232 /*
2233 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2234 * i.e. it points to where new data has been buffered. The 'CURR'
2235 * (current) register points to the logical end of the ring-buffer -
2236 * i.e. it points to where additional new data will be added. We loop
2237 * here until the logical beginning equals the logical end (or in
2238 * other words, until the ring-buffer is empty).
2239 */
2240 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2241
2242 /* get pointer to this buffer's header structure */
2243 packet_ptr = sc->mem_ring +
2244 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2245
2246 /*
2247 * The byte count includes a 4 byte header that was added by
2248 * the NIC.
2249 */
2250 if (sc->mem_shared)
2251 packet_hdr = *(struct ed_ring *) packet_ptr;
2252 else
2253 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2254 sizeof(packet_hdr));
2255 len = packet_hdr.count;
2256 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2257 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2258 /*
2259 * Length is a wild value. There's a good chance that
2260 * this was caused by the NIC being old and buggy.
2261 * The bug is that the length low byte is duplicated in
2262 * the high byte. Try to recalculate the length based on
2263 * the pointer to the next packet.
2264 */
2265 /*
2266 * NOTE: sc->next_packet is pointing at the current packet.
2267 */
2268 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2269 if (packet_hdr.next_packet >= sc->next_packet) {
2270 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2271 } else {
2272 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2273 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2274 }
2275 /*
2276 * because buffers are aligned on 256-byte boundary,
2277 * the length computed above is off by 256 in almost
2278 * all cases. Fix it...
2279 */
2280 if (len & 0xff)
2281 len -= 256 ;
2282 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2283 + sizeof(struct ed_ring)))
2284 sc->mibdata.dot3StatsFrameTooLongs++;
2285 }
2286 /*
2287 * Be fairly liberal about what we allow as a "reasonable" length
2288 * so that a [crufty] packet will make it to BPF (and can thus
2289 * be analyzed). Note that all that is really important is that
2290 * we have a length that will fit into one mbuf cluster or less;
2291 * the upper layer protocols can then figure out the length from
2292 * their own length field(s).
2293 * But make sure that we have at least a full ethernet header
2294 * or we would be unable to call ether_input() later.
2295 */
2296 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2297 (len <= MCLBYTES) &&
2298 (packet_hdr.next_packet >= sc->rec_page_start) &&
2299 (packet_hdr.next_packet < sc->rec_page_stop)) {
2300 /*
2301 * Go get packet.
2302 */
2303 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2304 len - sizeof(struct ed_ring));
2305 ifp->if_ipackets++;
2306 } else {
2307 /*
2308 * Really BAD. The ring pointers are corrupted.
2309 */
2310 log(LOG_ERR,
3e4a09e7
MD
2311 "%s: NIC memory corrupt - invalid packet length %d\n",
2312 ifp->if_xname, len);
984263bc
MD
2313 ifp->if_ierrors++;
2314 ed_reset(ifp);
2315 return;
2316 }
2317
2318 /*
2319 * Update next packet pointer
2320 */
2321 sc->next_packet = packet_hdr.next_packet;
2322
2323 /*
2324 * Update NIC boundry pointer - being careful to keep it one
2325 * buffer behind. (as recommended by NS databook)
2326 */
2327 boundry = sc->next_packet - 1;
2328 if (boundry < sc->rec_page_start)
2329 boundry = sc->rec_page_stop - 1;
2330
2331 /*
2332 * Set NIC to page 0 registers to update boundry register
2333 */
2334 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2335
2336 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2337
2338 /*
2339 * Set NIC to page 1 registers before looping to top (prepare
2340 * to get 'CURR' current pointer)
2341 */
2342 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2343 }
2344}
2345
2346/*
2347 * Ethernet interface interrupt processor
2348 */
2349void
27b16ba9 2350edintr(void *arg)
984263bc
MD
2351{
2352 struct ed_softc *sc = (struct ed_softc*) arg;
2353 struct ifnet *ifp = (struct ifnet *)sc;
2354 u_char isr;
1f18ea8c 2355 int count;
984263bc
MD
2356
2357 if (sc->gone)
2358 return;
2359 /*
2360 * Set NIC to page 0 registers
2361 */
2362 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2363
2364 /*
1f18ea8c
JS
2365 * loop until there are no more new interrupts. When the card
2366 * goes away, the hardware will read back 0xff. Looking at
2367 * the interrupts, it would appear that 0xff is impossible,
2368 * or at least extremely unlikely.
984263bc 2369 */
1f18ea8c 2370 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
984263bc
MD
2371
2372 /*
2373 * reset all the bits that we are 'acknowledging' by writing a
2374 * '1' to each bit position that was set (writing a '1'
2375 * *clears* the bit)
2376 */
2377 ed_nic_outb(sc, ED_P0_ISR, isr);
2378
1f18ea8c
JS
2379 /*
2380 * XXX workaround for AX88190
2381 * We limit this to 5000 iterations. At 1us per inb/outb,
2382 * this translates to about 15ms, which should be plenty
2383 * of time, and also gives protection in the card eject
2384 * case.
2385 */
984263bc 2386 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
1f18ea8c
JS
2387 count = 5000; /* 15ms */
2388 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2389 ed_nic_outb(sc, ED_P0_ISR,0);
2390 ed_nic_outb(sc, ED_P0_ISR,isr);
2391 }
2392 if (count == 0)
2393 break;
984263bc
MD
2394 }
2395
2396 /*
2397 * Handle transmitter interrupts. Handle these first because
2398 * the receiver will reset the board under some conditions.
2399 */
2400 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2401 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2402
2403 /*
2404 * Check for transmit error. If a TX completed with an
2405 * error, we end up throwing the packet away. Really
2406 * the only error that is possible is excessive
2407 * collisions, and in this case it is best to allow
2408 * the automatic mechanisms of TCP to backoff the
2409 * flow. Of course, with UDP we're screwed, but this
2410 * is expected when a network is heavily loaded.
2411 */
2412 (void) ed_nic_inb(sc, ED_P0_TSR);
2413 if (isr & ED_ISR_TXE) {
2414 u_char tsr;
2415
2416 /*
2417 * Excessive collisions (16)
2418 */
2419 tsr = ed_nic_inb(sc, ED_P0_TSR);
2420 if ((tsr & ED_TSR_ABT)
2421 && (collisions == 0)) {
2422
2423 /*
2424 * When collisions total 16, the
2425 * P0_NCR will indicate 0, and the
2426 * TSR_ABT is set.
2427 */
2428 collisions = 16;
2429 sc->mibdata.dot3StatsExcessiveCollisions++;
2430 sc->mibdata.dot3StatsCollFrequencies[15]++;
2431 }
2432 if (tsr & ED_TSR_OWC)
2433 sc->mibdata.dot3StatsLateCollisions++;
2434 if (tsr & ED_TSR_CDH)
2435 sc->mibdata.dot3StatsSQETestErrors++;
2436 if (tsr & ED_TSR_CRS)
2437 sc->mibdata.dot3StatsCarrierSenseErrors++;
2438 if (tsr & ED_TSR_FU)
2439 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2440
2441 /*
2442 * update output errors counter
2443 */
2444 ifp->if_oerrors++;
2445 } else {
2446
2447 /*
2448 * Update total number of successfully
2449 * transmitted packets.
2450 */
2451 ifp->if_opackets++;
2452 }
2453
2454 /*
2455 * reset tx busy and output active flags
2456 */
2457 sc->xmit_busy = 0;
2458 ifp->if_flags &= ~IFF_OACTIVE;
2459
2460 /*
2461 * clear watchdog timer
2462 */
2463 ifp->if_timer = 0;
2464
2465 /*
2466 * Add in total number of collisions on last
2467 * transmission.
2468 */
2469 ifp->if_collisions += collisions;
2470 switch(collisions) {
2471 case 0:
2472 case 16:
2473 break;
2474 case 1:
2475 sc->mibdata.dot3StatsSingleCollisionFrames++;
2476 sc->mibdata.dot3StatsCollFrequencies[0]++;
2477 break;
2478 default:
2479 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2480 sc->mibdata.
2481 dot3StatsCollFrequencies[collisions-1]
2482 ++;
2483 break;
2484 }
2485
2486 /*
2487 * Decrement buffer in-use count if not zero (can only
2488 * be zero if a transmitter interrupt occured while
2489 * not actually transmitting). If data is ready to
2490 * transmit, start it transmitting, otherwise defer
2491 * until after handling receiver
2492 */
2493 if (sc->txb_inuse && --sc->txb_inuse)
2494 ed_xmit(sc);
2495 }
2496
2497 /*
2498 * Handle receiver interrupts
2499 */
2500 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2501
2502 /*
2503 * Overwrite warning. In order to make sure that a
2504 * lockup of the local DMA hasn't occurred, we reset
2505 * and re-init the NIC. The NSC manual suggests only a
2506 * partial reset/re-init is necessary - but some chips
2507 * seem to want more. The DMA lockup has been seen
2508 * only with early rev chips - Methinks this bug was
2509 * fixed in later revs. -DG
2510 */
2511 if (isr & ED_ISR_OVW) {
2512 ifp->if_ierrors++;
2513#ifdef DIAGNOSTIC
2514 log(LOG_WARNING,
3e4a09e7
MD
2515 "%s: warning - receiver ring buffer overrun\n",
2516 ifp->if_xname);
984263bc
MD
2517#endif
2518
2519 /*
2520 * Stop/reset/re-init NIC
2521 */
2522 ed_reset(ifp);
2523 } else {
2524
2525 /*
2526 * Receiver Error. One or more of: CRC error,
2527 * frame alignment error FIFO overrun, or
2528 * missed packet.
2529 */
2530 if (isr & ED_ISR_RXE) {
2531 u_char rsr;
2532 rsr = ed_nic_inb(sc, ED_P0_RSR);
2533 if (rsr & ED_RSR_CRC)
2534 sc->mibdata.dot3StatsFCSErrors++;
2535 if (rsr & ED_RSR_FAE)
2536 sc->mibdata.dot3StatsAlignmentErrors++;
2537 if (rsr & ED_RSR_FO)
2538 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2539 ifp->if_ierrors++;
2540#ifdef ED_DEBUG
1f18ea8c 2541 if_printf("receive error %x\n",
984263bc
MD
2542 ed_nic_inb(sc, ED_P0_RSR));
2543#endif
2544 }
2545
2546 /*
2547 * Go get the packet(s) XXX - Doing this on an
2548 * error is dubious because there shouldn't be
2549 * any data to get (we've configured the
2550 * interface to not accept packets with
2551 * errors).
2552 */
2553
2554 /*
2555 * Enable 16bit access to shared memory first
2556 * on WD/SMC boards.
2557 */
2558 if (sc->isa16bit &&
2559 (sc->vendor == ED_VENDOR_WD_SMC)) {
2560
2561 ed_asic_outb(sc, ED_WD_LAAR,
2562 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2563 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2564 ed_asic_outb(sc, ED_WD_MSR,
2565 ED_WD_MSR_MENB);
2566 }
2567 }
2568 ed_rint(sc);
2569
2570 /* disable 16bit access */
2571 if (sc->isa16bit &&
2572 (sc->vendor == ED_VENDOR_WD_SMC)) {
2573
2574 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2575 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2576 }
2577 ed_asic_outb(sc, ED_WD_LAAR,
2578 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2579 }
2580 }
2581 }
2582
2583 /*
2584 * If it looks like the transmitter can take more data,
2585 * attempt to start output on the interface. This is done
2586 * after handling the receiver to give the receiver priority.
2587 */
2588 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2589 ed_start(ifp);
2590
2591 /*
2592 * return NIC CR to standard state: page 0, remote DMA
2593 * complete, start (toggling the TXP bit off, even if was just
2594 * set in the transmit routine, is *okay* - it is 'edge'
2595 * triggered from low to high)
2596 */
2597 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2598
2599 /*
2600 * If the Network Talley Counters overflow, read them to reset
2601 * them. It appears that old 8390's won't clear the ISR flag
2602 * otherwise - resulting in an infinite loop.
2603 */
2604 if (isr & ED_ISR_CNT) {
2605 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2606 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2607 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2608 }
2609 }
2610}
2611
2612/*
2613 * Process an ioctl request. This code needs some work - it looks
2614 * pretty ugly.
2615 */
2616static int
27b16ba9 2617ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
2618{
2619 struct ed_softc *sc = ifp->if_softc;
1f18ea8c 2620#ifndef ED_NO_MIIBUS
984263bc
MD
2621 struct ifreq *ifr = (struct ifreq *)data;
2622 struct mii_data *mii;
1f18ea8c 2623#endif
888ab9b7
JS
2624 int error = 0;
2625
2626 crit_enter();
984263bc
MD
2627
2628 if (sc == NULL || sc->gone) {
2629 ifp->if_flags &= ~IFF_RUNNING;
888ab9b7 2630 crit_exit();
984263bc
MD
2631 return ENXIO;
2632 }
984263bc
MD
2633
2634 switch (command) {
984263bc
MD
2635 case SIOCSIFFLAGS:
2636
2637 /*
2638 * If the interface is marked up and stopped, then start it.
2639 * If it is marked down and running, then stop it.
2640 */
2641 if (ifp->if_flags & IFF_UP) {
2642 if ((ifp->if_flags & IFF_RUNNING) == 0)
2643 ed_init(sc);
2644 } else {
2645 if (ifp->if_flags & IFF_RUNNING) {
2646 ed_stop(sc);
2647 ifp->if_flags &= ~IFF_RUNNING;
2648 }
2649 }
2650
2651 /*
2652 * Promiscuous flag may have changed, so reprogram the RCR.
2653 */
2654 ed_setrcr(sc);
2655
2656 /*
2657 * An unfortunate hack to provide the (required) software
2658 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2659 * disables the tranceiver if set.
2660 */
2661 if (sc->vendor == ED_VENDOR_3COM) {
2662 if (ifp->if_flags & IFF_ALTPHYS) {
2663 ed_asic_outb(sc, ED_3COM_CR, 0);
2664 } else {
2665 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2666 }
2667 } else if (sc->vendor == ED_VENDOR_HP)
2668 ed_hpp_set_physical_link(sc);
2669 break;
2670
2671 case SIOCADDMULTI:
2672 case SIOCDELMULTI:
2673 /*
2674 * Multicast list has changed; set the hardware filter
2675 * accordingly.
2676 */
2677 ed_setrcr(sc);
2678 error = 0;
2679 break;
2680
1f18ea8c 2681#ifndef ED_NO_MIIBUS
984263bc
MD
2682 case SIOCGIFMEDIA:
2683 case SIOCSIFMEDIA:
2684 if (sc->miibus == NULL) {
2685 error = EINVAL;
2686 break;
2687 }
2688 mii = device_get_softc(sc->miibus);
2689 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2690 break;
1f18ea8c 2691#endif
984263bc
MD
2692
2693 default:
4cde4dd5
JS
2694 error = ether_ioctl(ifp, command, data);
2695 break;
984263bc 2696 }
888ab9b7
JS
2697
2698 crit_exit();
2699
984263bc
MD
2700 return (error);
2701}
2702
2703/*
2704 * Given a source and destination address, copy 'amount' of a packet from
2705 * the ring buffer into a linear destination buffer. Takes into account
2706 * ring-wrap.
2707 */
2708static __inline char *
27b16ba9 2709ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
984263bc
MD
2710{
2711 u_short tmp_amount;
2712
2713 /* does copy wrap to lower addr in ring buffer? */
2714 if (src + amount > sc->mem_end) {
2715 tmp_amount = sc->mem_end - src;
2716
2717 /* copy amount up to end of NIC memory */
2718 if (sc->mem_shared)
2719 bcopy(src, dst, tmp_amount);
2720 else
2721 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2722
2723 amount -= tmp_amount;
2724 src = sc->mem_ring;
2725 dst += tmp_amount;
2726 }
2727 if (sc->mem_shared)
2728 bcopy(src, dst, amount);
2729 else
2730 ed_pio_readmem(sc, (int)src, dst, amount);
2731
2732 return (src + amount);
2733}
2734
2735/*
2736 * Retreive packet from shared memory and send to the next level up via
2737 * ether_input().
2738 */
2739static void
27b16ba9 2740ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
984263bc 2741{
1f18ea8c 2742 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
2743 struct ether_header *eh;
2744 struct mbuf *m;
2745
984263bc 2746 /*
17b71a59 2747 * Allocate a header mbuf.
984263bc
MD
2748 * We always put the received packet in a single buffer -
2749 * either with just an mbuf header or in a cluster attached
2750 * to the header. The +2 is to compensate for the alignment
2751 * fixup below.
2752 */
17b71a59
JH
2753 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
2754 if (m == NULL)
2755 return;
2756 m->m_pkthdr.rcvif = ifp;
2757 m->m_pkthdr.len = m->m_len = len;
984263bc
MD
2758
2759 /*
2760 * The +2 is to longword align the start of the real packet.
2761 * This is important for NFS.
2762 */
2763 m->m_data += 2;
2764 eh = mtod(m, struct ether_header *);
2765
2766 /*
2767 * Don't read in the entire packet if we know we're going to drop it
2768 * and no bpf is active.
2769 */
1f18ea8c 2770 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
984263bc
MD
2771 struct ifnet *bif;
2772
2773 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
1f18ea8c 2774 bif = bridge_in_ptr(ifp, eh) ;
984263bc
MD
2775 if (bif == BDG_DROP) {
2776 m_freem(m);
2777 return;
2778 }
2779 if (len > ETHER_HDR_LEN)
2780 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2781 (char *)(eh + 1), len - ETHER_HDR_LEN);
2782 } else
2783 /*
2784 * Get packet, including link layer address, from interface.
2785 */
2786 ed_ring_copy(sc, buf, (char *)eh, len);
2787
3013ac0e 2788 m->m_pkthdr.len = m->m_len = len;
984263bc 2789
78195a76 2790 ifp->if_input(ifp, m);
984263bc
MD
2791}
2792
2793/*
2794 * Supporting routines
2795 */
2796
2797/*
2798 * Given a NIC memory source address and a host memory destination
2799 * address, copy 'amount' from NIC to host using Programmed I/O.
2800 * The 'amount' is rounded up to a word - okay as long as mbufs
2801 * are word sized.
2802 * This routine is currently Novell-specific.
2803 */
2804void
27b16ba9 2805ed_pio_readmem(struct ed_softc *sc, int src, u_char *dst, u_short amount)
984263bc
MD
2806{
2807 /* HP PC Lan+ cards need special handling */
2808 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2809 ed_hpp_readmem(sc, src, dst, amount);
2810 return;
2811 }
2812
2813 /* Regular Novell cards */
2814 /* select page 0 registers */
2815 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2816
2817 /* round up to a word */
2818 if (amount & 1)
2819 ++amount;
2820
2821 /* set up DMA byte count */
2822 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2823 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2824
2825 /* set up source address in NIC mem */
2826 ed_nic_outb(sc, ED_P0_RSAR0, src);
2827 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2828
2829 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2830
2831 if (sc->isa16bit) {
2832 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2833 } else {
2834 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2835 }
2836}
2837
2838/*
2839 * Stripped down routine for writing a linear buffer to NIC memory.
2840 * Only used in the probe routine to test the memory. 'len' must
2841 * be even.
2842 */
2843void
27b16ba9 2844ed_pio_writemem(struct ed_softc *sc, char *src, u_short dst, u_short len)
984263bc
MD
2845{
2846 int maxwait = 200; /* about 240us */
2847
2848 /* select page 0 registers */
2849 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2850
2851 /* reset remote DMA complete flag */
2852 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2853
2854 /* set up DMA byte count */
2855 ed_nic_outb(sc, ED_P0_RBCR0, len);
2856 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2857
2858 /* set up destination address in NIC mem */
2859 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2860 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2861
2862 /* set remote DMA write */
2863 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2864
2865 if (sc->isa16bit) {
2866 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2867 } else {
2868 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2869 }
2870
2871 /*
2872 * Wait for remote DMA complete. This is necessary because on the
2873 * transmit side, data is handled internally by the NIC in bursts and
2874 * we can't start another remote DMA until this one completes. Not
2875 * waiting causes really bad things to happen - like the NIC
2876 * irrecoverably jamming the ISA bus.
2877 */
2878 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2879}
2880
2881/*
2882 * Write an mbuf chain to the destination NIC memory address using
2883 * programmed I/O.
2884 */
2885static u_short
27b16ba9 2886ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
984263bc
MD
2887{
2888 struct ifnet *ifp = (struct ifnet *)sc;
27b16ba9 2889 u_short total_len, dma_len;
984263bc
MD
2890 struct mbuf *mp;
2891 int maxwait = 200; /* about 240us */
2892
2893 /* HP PC Lan+ cards need special handling */
2894 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2895 return ed_hpp_write_mbufs(sc, m, dst);
2896 }
2897
2898 /* Regular Novell cards */
2899 /* First, count up the total number of bytes to copy */
2900 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2901 total_len += mp->m_len;
2902
2903 dma_len = total_len;
2904 if (sc->isa16bit && (dma_len & 1))
2905 dma_len++;
2906
2907 /* select page 0 registers */
2908 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2909
2910 /* reset remote DMA complete flag */
2911 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2912
2913 /* set up DMA byte count */
2914 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2915 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2916
2917 /* set up destination address in NIC mem */
2918 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2919 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2920
2921 /* set remote DMA write */
2922 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2923
2924 /*
2925 * Transfer the mbuf chain to the NIC memory.
2926 * 16-bit cards require that data be transferred as words, and only words.
2927 * So that case requires some extra code to patch over odd-length mbufs.
2928 */
2929
2930 if (!sc->isa16bit) {
2931 /* NE1000s are easy */
2932 while (m) {
2933 if (m->m_len) {
2934 ed_asic_outsb(sc, ED_NOVELL_DATA,
2935 m->m_data, m->m_len);
2936 }
2937 m = m->m_next;
2938 }
2939 } else {
2940 /* NE2000s are a pain */
27b16ba9 2941 u_char *data;
984263bc 2942 int len, wantbyte;
27b16ba9 2943 u_char savebyte[2];
984263bc
MD
2944
2945 wantbyte = 0;
2946
2947 while (m) {
2948 len = m->m_len;
2949 if (len) {
2950 data = mtod(m, caddr_t);
2951 /* finish the last word */
2952 if (wantbyte) {
2953 savebyte[1] = *data;
2954 ed_asic_outw(sc, ED_NOVELL_DATA,
2955 *(u_short *)savebyte);
2956 data++;
2957 len--;
2958 wantbyte = 0;
2959 }
2960 /* output contiguous words */
2961 if (len > 1) {
2962 ed_asic_outsw(sc, ED_NOVELL_DATA,
2963 data, len >> 1);
2964 data += len & ~1;
2965 len &= 1;
2966 }
2967 /* save last byte, if necessary */
2968 if (len == 1) {
2969 savebyte[0] = *data;
2970 wantbyte = 1;
2971 }
2972 }
2973 m = m->m_next;
2974 }
2975 /* spit last byte */
2976 if (wantbyte) {
2977 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2978 }
2979 }
2980
2981 /*
2982 * Wait for remote DMA complete. This is necessary because on the
2983 * transmit side, data is handled internally by the NIC in bursts and
2984 * we can't start another remote DMA until this one completes. Not
2985 * waiting causes really bad things to happen - like the NIC
2986 * irrecoverably jamming the ISA bus.
2987 */
2988 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2989
2990 if (!maxwait) {
3e4a09e7
MD
2991 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
2992 ifp->if_xname);
984263bc
MD
2993 ed_reset(ifp);
2994 return(0);
2995 }
2996 return (total_len);
2997}
2998
2999/*
3000 * Support routines to handle the HP PC Lan+ card.
3001 */
3002
3003/*
3004 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3005 * IO.
3006 */
3007
3008static void
27b16ba9 3009ed_hpp_readmem(struct ed_softc *sc, u_short src, u_char *dst, u_short amount)
984263bc
MD
3010{
3011
3012 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3013
3014
3015 /* Program the source address in RAM */
3016 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3017
3018 /*
3019 * The HP PC Lan+ card supports word reads as well as
3020 * a memory mapped i/o port that is aliased to every
3021 * even address on the board.
3022 */
3023
3024 if (sc->hpp_mem_start) {
3025
3026 /* Enable memory mapped access. */
3027 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3028 ~(ED_HPP_OPTION_MEM_DISABLE |
3029 ED_HPP_OPTION_BOOT_ROM_ENB));
3030
3031 if (use_32bit_access && (amount > 3)) {
3032 u_int32_t *dl = (u_int32_t *) dst;
3033 volatile u_int32_t *const sl =
3034 (u_int32_t *) sc->hpp_mem_start;
3035 u_int32_t *const fence = dl + (amount >> 2);
3036
3037 /* Copy out NIC data. We could probably write this
3038 as a `movsl'. The currently generated code is lousy.
3039 */
3040
3041 while (dl < fence)
3042 *dl++ = *sl;
3043
3044 dst += (amount & ~3);
3045 amount &= 3;
3046
3047 }
3048
3049 /* Finish off any words left, as a series of short reads */
3050 if (amount > 1) {
3051 u_short *d = (u_short *) dst;
3052 volatile u_short *const s =
3053 (u_short *) sc->hpp_mem_start;
3054 u_short *const fence = d + (amount >> 1);
3055
3056 /* Copy out NIC data. */
3057
3058 while (d < fence)
3059 *d++ = *s;
3060
3061 dst += (amount & ~1);
3062 amount &= 1;
3063 }
3064
3065 /*
3066 * read in a byte; however we need to always read 16 bits
3067 * at a time or the hardware gets into a funny state
3068 */
3069
3070 if (amount == 1) {
3071 /* need to read in a short and copy LSB */
3072 volatile u_short *const s =
3073 (volatile u_short *) sc->hpp_mem_start;
3074
3075 *dst = (*s) & 0xFF;
3076 }
3077
3078 /* Restore Boot ROM access. */
3079
3080 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3081
3082
3083 } else {
3084 /* Read in data using the I/O port */
3085 if (use_32bit_access && (amount > 3)) {
3086 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3087 dst += (amount & ~3);
3088 amount &= 3;
3089 }
3090 if (amount > 1) {
3091 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3092 dst += (amount & ~1);
3093 amount &= 1;
3094 }
3095 if (amount == 1) { /* read in a short and keep the LSB */
3096 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3097 }
3098 }
3099}
3100
3101/*
3102 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3103 * IO.
3104 * Only used in the probe routine to test the memory. 'len' must
3105 * be even.
3106 */
1f18ea8c 3107static void
27b16ba9 3108ed_hpp_writemem(struct ed_softc *sc, u_char *src, u_short dst, u_short len)
984263bc
MD
3109{
3110 /* reset remote DMA complete flag */
3111 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3112
3113 /* program the write address in RAM */
3114 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3115
3116 if (sc->hpp_mem_start) {
3117 u_short *s = (u_short *) src;
3118 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3119 u_short *const fence = s + (len >> 1);
3120
3121 /*
3122 * Enable memory mapped access.
3123 */
3124
3125 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3126 ~(ED_HPP_OPTION_MEM_DISABLE |
3127 ED_HPP_OPTION_BOOT_ROM_ENB));
3128
3129 /*
3130 * Copy to NIC memory.
3131 */
3132
3133 while (s < fence)
3134 *d = *s++;
3135
3136 /*
3137 * Restore Boot ROM access.
3138 */
3139
3140 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3141
3142 } else {
3143 /* write data using I/O writes */
3144 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3145 }
3146}
3147
3148/*
3149 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3150 * outsw() or via the memory mapped interface to the same register.
3151 * Writes have to be in word units; byte accesses won't work and may cause
3e4db402 3152 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
984263bc
MD
3153 * allows it.
3154 */
3155
3156static u_short
3157ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3158{
3159 int len, wantbyte;
27b16ba9
SZ
3160 u_short total_len;
3161 u_char savebyte[2];
984263bc
MD
3162 volatile u_short * const d =
3163 (volatile u_short *) sc->hpp_mem_start;
3164 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3165
3166 /* select page 0 registers */
3167 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3168
3169 /* reset remote DMA complete flag */
3170 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3171
3172 /* program the write address in RAM */
3173 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3174
3175 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3176 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3177 ~(ED_HPP_OPTION_MEM_DISABLE |
3178 ED_HPP_OPTION_BOOT_ROM_ENB));
3179
3180 wantbyte = 0;
3181 total_len = 0;
3182
3183 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3184 while (m) {
3185 total_len += (len = m->m_len);
3186 if (len) {
3187 caddr_t data = mtod(m, caddr_t);
3188 /* finish the last word of the previous mbuf */
3189 if (wantbyte) {
3190 savebyte[1] = *data;
1f18ea8c 3191 *d = *((u_short *) savebyte);
984263bc
MD
3192 data++; len--; wantbyte = 0;
3193 }
3194 /* output contiguous words */
3195 if ((len > 3) && (use_32bit_accesses)) {
3196 volatile u_int32_t *const dl =
3197 (volatile u_int32_t *) d;
3198 u_int32_t *sl = (u_int32_t *) data;
3199 u_int32_t *fence = sl + (len >> 2);
3200
3201 while (sl < fence)
3202 *dl = *sl++;
3203
3204 data += (len & ~3);
3205 len &= 3;
3206 }
3207 /* finish off remain 16 bit writes */
3208 if (len > 1) {
3209 u_short *s = (u_short *) data;
3210 u_short *fence = s + (len >> 1);
3211
3212 while (s < fence)
3213 *d = *s++;
3214
3215 data += (len & ~1);
3216 len &= 1;
3217 }
3218 /* save last byte if needed */
3219 if ((wantbyte = (len == 1)) != 0)
3220 savebyte[0] = *data;
3221 }
3222 m = m->m_next; /* to next mbuf */
3223 }
3224 if (wantbyte) /* write last byte */
3225 *d = *((u_short *) savebyte);
3226 } else {
3227 /* use programmed I/O */
3228 while (m) {
3229 total_len += (len = m->m_len);
3230 if (len) {
3231 caddr_t data = mtod(m, caddr_t);
3232 /* finish the last word of the previous mbuf */
3233 if (wantbyte) {
3234 savebyte[1] = *data;
3235 ed_asic_outw(sc, ED_HPP_PAGE_4,
3236 *((u_short *)savebyte));
3237 data++;
3238 len--;
3239 wantbyte = 0;
3240 }
3241 /* output contiguous words */
3242 if ((len > 3) && use_32bit_accesses) {
3243 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3244 data, len >> 2);
3245 data += (len & ~3);
3246 len &= 3;
3247 }
3248 /* finish off remaining 16 bit accesses */
3249 if (len > 1) {
3250 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3251 data, len >> 1);
3252 data += (len & ~1);
3253 len &= 1;
3254 }
3255 if ((wantbyte = (len == 1)) != 0)
3256 savebyte[0] = *data;
3257
3258 } /* if len != 0 */
3259 m = m->m_next;
3260 }
3261 if (wantbyte) /* spit last byte */
3262 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3263
3264 }
3265
3266 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3267 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3268
3269 return (total_len);
3270}
3271
1f18ea8c 3272#ifndef ED_NO_MIIBUS
984263bc
MD
3273/*
3274 * MII bus support routines.
3275 */
3276int
27b16ba9 3277ed_miibus_readreg(device_t dev, int phy, int reg)
984263bc 3278{
888ab9b7
JS
3279 struct ed_softc *sc = device_get_softc(dev);
3280 int failed, val;
3281
3282 crit_enter();
984263bc 3283
984263bc 3284 if (sc->gone) {
888ab9b7 3285 crit_exit();
984263bc
MD
3286 return (0);
3287 }
1f18ea8c 3288
984263bc
MD
3289 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3290 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3291 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3292 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3293 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3294
3295 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3296 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3297 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3298
888ab9b7
JS
3299 crit_exit();
3300
984263bc
MD
3301 return (failed ? 0 : val);
3302}
3303
3304void
27b16ba9 3305ed_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 3306{
888ab9b7
JS
3307 struct ed_softc *sc = device_get_softc(dev);
3308
3309 crit_enter();
984263bc 3310
984263bc 3311 if (sc->gone) {
888ab9b7 3312 crit_exit();
984263bc
MD
3313 return;
3314 }
3315
3316 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3317 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3318 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3319 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3320 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3321 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3322 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3323 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3324
888ab9b7 3325 crit_exit();
984263bc
MD
3326}
3327
3328int
27b16ba9 3329ed_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
3330{
3331 struct ed_softc *sc;
3332 struct mii_data *mii;
3333
3334 sc = ifp->if_softc;
3335 if (sc->gone || sc->miibus == NULL)
3336 return (ENXIO);
3337
3338 mii = device_get_softc(sc->miibus);
3339 return mii_mediachg(mii);
3340}
3341
3342void
27b16ba9 3343ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
3344{
3345 struct ed_softc *sc;
3346 struct mii_data *mii;
3347
3348 sc = ifp->if_softc;
3349 if (sc->gone || sc->miibus == NULL)
3350 return;
3351
3352 mii = device_get_softc(sc->miibus);
3353 mii_pollstat(mii);
3354 ifmr->ifm_active = mii->mii_media_active;
3355 ifmr->ifm_status = mii->mii_media_status;
3356}
3357
3358void
27b16ba9 3359ed_child_detached(device_t dev, device_t child)
984263bc
MD
3360{
3361 struct ed_softc *sc;
3362
3363 sc = device_get_softc(dev);
3364 if (child == sc->miibus)
3365 sc->miibus = NULL;
3366}
1f18ea8c 3367#endif
984263bc
MD
3368
3369static void
27b16ba9 3370ed_setrcr(struct ed_softc *sc)
984263bc
MD
3371{
3372 struct ifnet *ifp = (struct ifnet *)sc;
3373 int i;
3374 u_char reg1;
3375
3376 /* Bit 6 in AX88190 RCR register must be set. */
3377 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3378 reg1 = ED_RCR_INTT;
3379 else
3380 reg1 = 0x00;
3381
3382 /* set page 1 registers */
3383 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3384
3385 if (ifp->if_flags & IFF_PROMISC) {
3386
3387 /*
3388 * Reconfigure the multicast filter.
3389 */
3390 for (i = 0; i < 8; i++)
3391 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3392
3393 /*
3394 * And turn on promiscuous mode. Also enable reception of
3395 * runts and packets with CRC & alignment errors.
3396 */
3397 /* Set page 0 registers */
3398 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3399
3400 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3401 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3402 } else {
3403 /* set up multicast addresses and filter modes */
3404 if (ifp->if_flags & IFF_MULTICAST) {
3405 u_int32_t mcaf[2];
3406
3407 if (ifp->if_flags & IFF_ALLMULTI) {
3408 mcaf[0] = 0xffffffff;
3409 mcaf[1] = 0xffffffff;
3410 } else
3411 ds_getmcaf(sc, mcaf);
3412
3413 /*
3414 * Set multicast filter on chip.
3415 */
3416 for (i = 0; i < 8; i++)
3417 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3418
3419 /* Set page 0 registers */
3420 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3421
3422 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3423 } else {
3424
3425 /*
3426 * Initialize multicast address hashing registers to
3427 * not accept multicasts.
3428 */
3429 for (i = 0; i < 8; ++i)
3430 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3431
3432 /* Set page 0 registers */
3433 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3434
3435 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3436 }
3437 }
3438
3439 /*
3440 * Start interface.
3441 */
3442 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3443}
3444
3445/*
3446 * Compute crc for ethernet address
3447 */
1f18ea8c 3448static uint32_t
27b16ba9 3449ds_mchash(const uint8_t *addr)
984263bc 3450{
1f18ea8c 3451#define ED_POLYNOMIAL 0x04c11db6
6de3da81
CP
3452 uint32_t crc = 0xffffffff;
3453 int carry, idx, bit;
3454 uint8_t data;
1f18ea8c
JS
3455
3456 for (idx = 6; --idx >= 0;) {
3457 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3458 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
984263bc 3459 crc <<= 1;
984263bc 3460 if (carry)
1f18ea8c 3461 crc = (crc ^ ED_POLYNOMIAL) | carry;
984263bc
MD
3462 }
3463 }
3464 return crc;
3465#undef POLYNOMIAL
3466}
3467
3468/*
3469 * Compute the multicast address filter from the
3470 * list of multicast addresses we need to listen to.
3471 */
3472static void
27b16ba9 3473ds_getmcaf(struct ed_softc *sc, u_int32_t *mcaf)
984263bc 3474{
f96d6c88
RG
3475 u_int32_t index;
3476 u_char *af = (u_char *) mcaf;
984263bc
MD
3477 struct ifmultiaddr *ifma;
3478
3479 mcaf[0] = 0;
3480 mcaf[1] = 0;
3481
03df8a20 3482 LIST_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
984263bc
MD
3483 if (ifma->ifma_addr->sa_family != AF_LINK)
3484 continue;
1f18ea8c 3485 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
984263bc
MD
3486 >> 26;
3487 af[index >> 3] |= 1 << (index & 7);
3488 }
3489}