Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / lge / if_lge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
78195a76 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.33 2005/11/28 17:13:43 dillon Exp $
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35 */
36
37/*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * Written by Bill Paul <william.paul@windriver.com>
42 * Wind River Systems
43 */
44
45/*
46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
47 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
49 * are three supported methods for data transfer between host and
50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
51 * Propulsion Technology (tm) DMA. The latter mechanism is a form
52 * of double buffer DMA where the packet data is copied to a
53 * pre-allocated DMA buffer who's physical address has been loaded
54 * into a table at device initialization time. The rationale is that
55 * the virtual to physical address translation needed for normal
56 * scatter/gather DMA is more expensive than the data copy needed
57 * for double buffering. This may be true in Windows NT and the like,
58 * but it isn't true for us, at least on the x86 arch. This driver
59 * uses the scatter/gather I/O method for both TX and RX.
60 *
61 * The LXT1001 only supports TCP/IP checksum offload on receive.
62 * Also, the VLAN tagging is done using a 16-entry table which allows
63 * the chip to perform hardware filtering based on VLAN tags. Sadly,
64 * our vlan support doesn't currently play well with this kind of
65 * hardware support.
66 *
67 * Special thanks to:
68 * - Jeff James at Intel, for arranging to have the LXT1001 manual
69 * released (at long last)
70 * - Beny Chen at D-Link, for actually sending it to me
71 * - Brad Short and Keith Alexis at SMC, for sending me sample
72 * SMC9462SX and SMC9462TX adapters for testing
73 * - Paul Saab at Y!, for not killing me (though it remains to be seen
74 * if in fact he did me much of a favor)
75 */
76
77#include <sys/param.h>
78#include <sys/systm.h>
79#include <sys/sockio.h>
80#include <sys/mbuf.h>
81#include <sys/malloc.h>
82#include <sys/kernel.h>
83#include <sys/socket.h>
78195a76 84#include <sys/serialize.h>
2742eee0 85#include <sys/thread2.h>
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86
87#include <net/if.h>
d1f483a6 88#include <net/ifq_var.h>
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89#include <net/if_arp.h>
90#include <net/ethernet.h>
91#include <net/if_dl.h>
92#include <net/if_media.h>
93
94#include <net/bpf.h>
95
96#include <vm/vm.h> /* for vtophys */
97#include <vm/pmap.h> /* for vtophys */
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98#include <machine/bus.h>
99#include <machine/resource.h>
100#include <sys/bus.h>
101#include <sys/rman.h>
102
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103#include <dev/netif/mii_layer/mii.h>
104#include <dev/netif/mii_layer/miivar.h>
984263bc 105
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106#include <bus/pci/pcireg.h>
107#include <bus/pci/pcivar.h>
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108
109#define LGE_USEIOSPACE
110
1f2de5d4 111#include "if_lgereg.h"
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112
113/* "controller miibus0" required. See GENERIC if you get errors here. */
114#include "miibus_if.h"
115
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116/*
117 * Various supported device vendors/types and their names.
118 */
119static struct lge_type lge_devs[] = {
120 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
121 { 0, 0, NULL }
122};
123
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124static int lge_probe(device_t);
125static int lge_attach(device_t);
126static int lge_detach(device_t);
127
128static int lge_alloc_jumbo_mem(struct lge_softc *);
129static void lge_free_jumbo_mem(struct lge_softc *);
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130static struct lge_jslot
131 *lge_jalloc(struct lge_softc *);
132static void lge_jfree(void *);
133static void lge_jref(void *);
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134
135static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *,
136 struct mbuf *);
137static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *);
138static void lge_rxeof(struct lge_softc *, int);
139static void lge_rxeoc(struct lge_softc *);
140static void lge_txeof(struct lge_softc *);
141static void lge_intr(void *);
142static void lge_tick(void *);
78195a76 143static void lge_tick_serialized(void *);
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144static void lge_start(struct ifnet *);
145static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
146static void lge_init(void *);
147static void lge_stop(struct lge_softc *);
148static void lge_watchdog(struct ifnet *);
149static void lge_shutdown(device_t);
150static int lge_ifmedia_upd(struct ifnet *);
151static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
152
153static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *);
154static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int);
155
156static int lge_miibus_readreg(device_t, int, int);
157static int lge_miibus_writereg(device_t, int, int, int);
158static void lge_miibus_statchg(device_t);
159
160static void lge_setmulti(struct lge_softc *);
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161static void lge_reset(struct lge_softc *);
162static int lge_list_rx_init(struct lge_softc *);
163static int lge_list_tx_init(struct lge_softc *);
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164
165#ifdef LGE_USEIOSPACE
166#define LGE_RES SYS_RES_IOPORT
167#define LGE_RID LGE_PCI_LOIO
168#else
169#define LGE_RES SYS_RES_MEMORY
170#define LGE_RID LGE_PCI_LOMEM
171#endif
172
173static device_method_t lge_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, lge_probe),
176 DEVMETHOD(device_attach, lge_attach),
177 DEVMETHOD(device_detach, lge_detach),
178 DEVMETHOD(device_shutdown, lge_shutdown),
179
180 /* bus interface */
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
183
184 /* MII interface */
185 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
186 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
187 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
188
189 { 0, 0 }
190};
191
63c0e4aa 192static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc));
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193static devclass_t lge_devclass;
194
32832096 195DECLARE_DUMMY_MODULE(if_lge);
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196DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
197DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
198
199#define LGE_SETBIT(sc, reg, x) \
63c0e4aa 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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201
202#define LGE_CLRBIT(sc, reg, x) \
63c0e4aa 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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204
205#define SIO_SET(x) \
63c0e4aa 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
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207
208#define SIO_CLR(x) \
63c0e4aa 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
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210
211/*
212 * Read a word of data stored in the EEPROM at address 'addr.'
213 */
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214static void
215lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest)
984263bc 216{
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217 int i;
218 uint32_t val;
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219
220 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
63c0e4aa 221 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8));
984263bc 222
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223 for (i = 0; i < LGE_TIMEOUT; i++) {
224 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)
984263bc 225 break;
63c0e4aa 226 }
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227
228 if (i == LGE_TIMEOUT) {
229 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
230 return;
231 }
232
233 val = CSR_READ_4(sc, LGE_EEDATA);
234
235 if (addr & 1)
236 *dest = (val >> 16) & 0xFFFF;
237 else
238 *dest = val & 0xFFFF;
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239}
240
241/*
242 * Read a sequence of words from the EEPROM.
243 */
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244static void
245lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt)
984263bc 246{
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247 int i;
248 uint16_t word = 0, *ptr;
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249
250 for (i = 0; i < cnt; i++) {
251 lge_eeprom_getword(sc, off + i, &word);
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252 ptr = (uint16_t *)(dest + (i * 2));
253 *ptr = ntohs(word);
984263bc 254 }
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255}
256
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257static int
258lge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 259{
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260 struct lge_softc *sc = device_get_softc(dev);
261 int i;
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262
263 /*
264 * If we have a non-PCS PHY, pretend that the internal
265 * autoneg stuff at PHY address 0 isn't there so that
266 * the miibus code will find only the GMII PHY.
267 */
268 if (sc->lge_pcs == 0 && phy == 0)
269 return(0);
270
271 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
272
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273 for (i = 0; i < LGE_TIMEOUT; i++) {
274 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
984263bc 275 break;
63c0e4aa 276 }
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277
278 if (i == LGE_TIMEOUT) {
279 printf("lge%d: PHY read timed out\n", sc->lge_unit);
280 return(0);
281 }
282
283 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
284}
285
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286static int
287lge_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 288{
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289 struct lge_softc *sc = device_get_softc(dev);
290 int i;
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291
292 CSR_WRITE_4(sc, LGE_GMIICTL,
293 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
294
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295 for (i = 0; i < LGE_TIMEOUT; i++) {
296 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
984263bc 297 break;
63c0e4aa 298 }
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299
300 if (i == LGE_TIMEOUT) {
301 printf("lge%d: PHY write timed out\n", sc->lge_unit);
302 return(0);
303 }
304
305 return(0);
306}
307
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308static void
309lge_miibus_statchg(device_t dev)
984263bc 310{
030ffb8e 311 struct lge_softc *sc = device_get_softc(dev);
63c0e4aa 312 struct mii_data *mii = device_get_softc(sc->lge_miibus);
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313
314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
315 switch (IFM_SUBTYPE(mii->mii_media_active)) {
7f259627 316 case IFM_1000_T:
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317 case IFM_1000_SX:
318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
319 break;
320 case IFM_100_TX:
321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
322 break;
323 case IFM_10_T:
324 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
325 break;
326 default:
327 /*
328 * Choose something, even if it's wrong. Clearing
329 * all the bits will hose autoneg on the internal
330 * PHY.
331 */
332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
333 break;
334 }
335
63c0e4aa 336 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
984263bc 337 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
63c0e4aa 338 else
984263bc 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
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340}
341
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342static void
343lge_setmulti(struct lge_softc *sc)
984263bc 344{
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345 struct ifnet *ifp = &sc->arpcom.ac_if;
346 struct ifmultiaddr *ifma;
347 uint32_t h = 0, hashes[2] = { 0, 0 };
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348
349 /* Make sure multicast hash table is enabled. */
63c0e4aa 350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST);
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351
352 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
353 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
354 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
355 return;
356 }
357
358 /* first, zot all the existing hash bits */
359 CSR_WRITE_4(sc, LGE_MAR0, 0);
360 CSR_WRITE_4(sc, LGE_MAR1, 0);
361
362 /* now program new ones */
63c0e4aa 363 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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364 if (ifma->ifma_addr->sa_family != AF_LINK)
365 continue;
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366 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
367 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
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368 if (h < 32)
369 hashes[0] |= (1 << h);
370 else
371 hashes[1] |= (1 << (h - 32));
372 }
373
374 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
375 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
376
377 return;
378}
379
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380static void
381lge_reset(struct lge_softc *sc)
984263bc 382{
63c0e4aa 383 int i;
984263bc 384
63c0e4aa 385 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST);
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386
387 for (i = 0; i < LGE_TIMEOUT; i++) {
63c0e4aa 388 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)
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389 break;
390 }
391
392 if (i == LGE_TIMEOUT)
393 printf("lge%d: reset never completed\n", sc->lge_unit);
394
395 /* Wait a little while for the chip to get its brains in order. */
396 DELAY(1000);
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397}
398
399/*
400 * Probe for a Level 1 chip. Check the PCI vendor and device
401 * IDs against our list and return a device name if we find a match.
402 */
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403static int
404lge_probe(device_t dev)
984263bc 405{
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406 struct lge_type *t;
407 uint16_t vendor, product;
984263bc 408
63c0e4aa
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409 vendor = pci_get_vendor(dev);
410 product = pci_get_device(dev);
984263bc 411
63c0e4aa
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412 for (t = lge_devs; t->lge_name != NULL; t++) {
413 if (vendor == t->lge_vid && product == t->lge_did) {
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414 device_set_desc(dev, t->lge_name);
415 return(0);
416 }
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417 }
418
419 return(ENXIO);
420}
421
422/*
423 * Attach the interface. Allocate softc structures, do ifmedia
424 * setup and ethernet/BPF attach.
425 */
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426static int
427lge_attach(device_t dev)
984263bc 428{
63c0e4aa 429 uint8_t eaddr[ETHER_ADDR_LEN];
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430 struct lge_softc *sc;
431 struct ifnet *ifp;
2742eee0 432 int unit, error = 0, rid;
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433
434 sc = device_get_softc(dev);
435 unit = device_get_unit(dev);
29744ced 436 callout_init(&sc->lge_stat_timer);
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437
438 /*
439 * Handle power management nonsense.
440 */
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441 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
442 uint32_t iobase, membase, irq;
984263bc 443
e4f0bbb9
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444 /* Save important PCI config data. */
445 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
446 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
447 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
984263bc 448
e4f0bbb9
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449 /* Reset the power state. */
450 device_printf(dev, "chip is in D%d power mode "
451 "-- setting to D0\n", pci_get_powerstate(dev));
452
453 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
454
455 /* Restore PCI config data. */
456 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
457 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
458 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
984263bc 459 }
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460
461 pci_enable_busmaster(dev);
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462
463 rid = LGE_RID;
4e6d744d 464 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
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465
466 if (sc->lge_res == NULL) {
467 printf("lge%d: couldn't map ports/memory\n", unit);
468 error = ENXIO;
469 goto fail;
470 }
471
472 sc->lge_btag = rman_get_bustag(sc->lge_res);
473 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
474
475 /* Allocate interrupt */
476 rid = 0;
4e6d744d 477 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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478 RF_SHAREABLE | RF_ACTIVE);
479
480 if (sc->lge_irq == NULL) {
481 printf("lge%d: couldn't map interrupt\n", unit);
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482 error = ENXIO;
483 goto fail;
484 }
485
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486 /* Reset the adapter. */
487 lge_reset(sc);
488
489 /*
490 * Get station address from the EEPROM.
491 */
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492 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1);
493 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1);
494 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1);
984263bc 495
984263bc 496 sc->lge_unit = unit;
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497
498 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
2742eee0 499 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
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500
501 if (sc->lge_ldata == NULL) {
502 printf("lge%d: no memory for list buffers!\n", unit);
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503 error = ENXIO;
504 goto fail;
505 }
506 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
507
508 /* Try to allocate memory for jumbo buffers. */
509 if (lge_alloc_jumbo_mem(sc)) {
510 printf("lge%d: jumbo buffer allocation failed\n",
511 sc->lge_unit);
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512 error = ENXIO;
513 goto fail;
514 }
515
516 ifp = &sc->arpcom.ac_if;
517 ifp->if_softc = sc;
cdb7d804 518 if_initname(ifp, "lge", unit);
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519 ifp->if_mtu = ETHERMTU;
520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
521 ifp->if_ioctl = lge_ioctl;
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522 ifp->if_start = lge_start;
523 ifp->if_watchdog = lge_watchdog;
524 ifp->if_init = lge_init;
525 ifp->if_baudrate = 1000000000;
d1f483a6
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526 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
527 ifq_set_ready(&ifp->if_snd);
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528 ifp->if_capabilities = IFCAP_RXCSUM;
529 ifp->if_capenable = ifp->if_capabilities;
530
531 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
532 sc->lge_pcs = 1;
533 else
534 sc->lge_pcs = 0;
535
536 /*
537 * Do MII setup.
538 */
539 if (mii_phy_probe(dev, &sc->lge_miibus,
540 lge_ifmedia_upd, lge_ifmedia_sts)) {
541 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
984263bc
MD
542 error = ENXIO;
543 goto fail;
544 }
545
546 /*
547 * Call MI attach routine.
548 */
78195a76 549 ether_ifattach(ifp, eaddr, NULL);
984263bc 550
78195a76
MD
551 error = bus_setup_intr(dev, sc->lge_irq, INTR_NETSAFE,
552 lge_intr, sc, &sc->lge_intrhand,
553 ifp->if_serializer);
2742eee0
JS
554 if (error) {
555 ether_ifdetach(ifp);
556 printf("lge%d: couldn't set up irq\n", unit);
557 goto fail;
558 }
559
560 return(0);
561
984263bc 562fail:
2742eee0 563 lge_detach(dev);
984263bc
MD
564 return(error);
565}
566
63c0e4aa
JS
567static int
568lge_detach(device_t dev)
984263bc 569{
63c0e4aa
JS
570 struct lge_softc *sc= device_get_softc(dev);
571 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 572
78195a76 573 lwkt_serialize_enter(ifp->if_serializer);
2742eee0
JS
574 if (device_is_attached(dev)) {
575 lge_reset(sc);
576 lge_stop(sc);
577 ether_ifdetach(ifp);
578 }
984263bc 579
2742eee0
JS
580 if (sc->lge_miibus)
581 device_delete_child(dev, sc->lge_miibus);
984263bc 582 bus_generic_detach(dev);
984263bc 583
2742eee0
JS
584 if (sc->lge_intrhand)
585 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
586
2742eee0
JS
587 if (sc->lge_irq)
588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
589 if (sc->lge_res)
590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
984263bc 591
2742eee0
JS
592 if (sc->lge_ldata)
593 contigfree(sc->lge_ldata, sizeof(struct lge_list_data),
594 M_DEVBUF);
595 lge_free_jumbo_mem(sc);
984263bc 596
78195a76 597 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
598 return(0);
599}
600
601/*
602 * Initialize the transmit descriptors.
603 */
63c0e4aa
JS
604static int
605lge_list_tx_init(struct lge_softc *sc)
984263bc 606{
63c0e4aa
JS
607 struct lge_list_data *ld;
608 struct lge_ring_data *cd;
609 int i;
984263bc
MD
610
611 cd = &sc->lge_cdata;
612 ld = sc->lge_ldata;
613 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
614 ld->lge_tx_list[i].lge_mbuf = NULL;
615 ld->lge_tx_list[i].lge_ctl = 0;
616 }
617
618 cd->lge_tx_prod = cd->lge_tx_cons = 0;
619
620 return(0);
621}
622
623
624/*
625 * Initialize the RX descriptors and allocate mbufs for them. Note that
626 * we arralge the descriptors in a closed ring, so that the last descriptor
627 * points back to the first.
628 */
63c0e4aa
JS
629static int
630lge_list_rx_init(struct lge_softc *sc)
984263bc 631{
63c0e4aa
JS
632 struct lge_list_data *ld;
633 struct lge_ring_data *cd;
634 int i;
984263bc
MD
635
636 ld = sc->lge_ldata;
637 cd = &sc->lge_cdata;
638
639 cd->lge_rx_prod = cd->lge_rx_cons = 0;
640
641 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
642
643 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
644 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
645 break;
646 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
647 return(ENOBUFS);
648 }
649
650 /* Clear possible 'rx command queue empty' interrupt. */
651 CSR_READ_4(sc, LGE_ISR);
652
653 return(0);
654}
655
656/*
657 * Initialize an RX descriptor and attach an MBUF cluster.
658 */
63c0e4aa
JS
659static int
660lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
984263bc 661{
63c0e4aa 662 struct mbuf *m_new = NULL;
0050ab7d 663 struct lge_jslot *buf;
984263bc
MD
664
665 if (m == NULL) {
74f1caca 666 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
667 if (m_new == NULL) {
668 printf("lge%d: no memory for rx list "
669 "-- packet dropped!\n", sc->lge_unit);
670 return(ENOBUFS);
671 }
672
673 /* Allocate the jumbo buffer */
674 buf = lge_jalloc(sc);
675 if (buf == NULL) {
676#ifdef LGE_VERBOSE
677 printf("lge%d: jumbo allocation failed "
678 "-- packet dropped!\n", sc->lge_unit);
679#endif
680 m_freem(m_new);
681 return(ENOBUFS);
682 }
683 /* Attach the buffer to the mbuf */
0050ab7d
JS
684 m_new->m_ext.ext_arg = buf;
685 m_new->m_ext.ext_buf = buf->lge_buf;
b542cd49
JS
686 m_new->m_ext.ext_free = lge_jfree;
687 m_new->m_ext.ext_ref = lge_jref;
0050ab7d
JS
688 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN;
689
690 m_new->m_data = m_new->m_ext.ext_buf;
691 m_new->m_flags |= M_EXT;
692 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc
MD
693 } else {
694 m_new = m;
0050ab7d 695 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN;
984263bc
MD
696 m_new->m_data = m_new->m_ext.ext_buf;
697 }
698
699 /*
700 * Adjust alignment so packet payload begins on a
701 * longword boundary. Mandatory for Alpha, useful on
702 * x86 too.
703 */
704 m_adj(m_new, ETHER_ALIGN);
705
706 c->lge_mbuf = m_new;
707 c->lge_fragptr_hi = 0;
708 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
709 c->lge_fraglen = m_new->m_len;
710 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
711 c->lge_sts = 0;
712
713 /*
714 * Put this buffer in the RX command FIFO. To do this,
715 * we just write the physical address of the descriptor
716 * into the RX descriptor address registers. Note that
717 * there are two registers, one high DWORD and one low
718 * DWORD, which lets us specify a 64-bit address if
719 * desired. We only use a 32-bit address for now.
720 * Writing to the low DWORD register is what actually
721 * causes the command to be issued, so we do that
722 * last.
723 */
724 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
725 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
726
727 return(0);
728}
729
63c0e4aa
JS
730static int
731lge_alloc_jumbo_mem(struct lge_softc *sc)
984263bc 732{
0050ab7d 733 struct lge_jslot *entry;
63c0e4aa
JS
734 caddr_t ptr;
735 int i;
984263bc
MD
736
737 /* Grab a big chunk o' storage. */
738 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
2742eee0 739 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
740
741 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
742 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
743 return(ENOBUFS);
744 }
745
746 SLIST_INIT(&sc->lge_jfree_listhead);
984263bc
MD
747
748 /*
749 * Now divide it up into 9K pieces and save the addresses
750 * in an array.
751 */
752 ptr = sc->lge_cdata.lge_jumbo_buf;
753 for (i = 0; i < LGE_JSLOTS; i++) {
0050ab7d
JS
754 entry = &sc->lge_cdata.lge_jslots[i];
755 entry->lge_sc = sc;
756 entry->lge_buf = ptr;
757 entry->lge_inuse = 0;
758 entry->lge_slot = i;
759 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link);
760 ptr += LGE_JLEN;
984263bc
MD
761 }
762
763 return(0);
764}
765
63c0e4aa
JS
766static void
767lge_free_jumbo_mem(struct lge_softc *sc)
984263bc 768{
2742eee0
JS
769 if (sc->lge_cdata.lge_jumbo_buf)
770 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
984263bc
MD
771}
772
773/*
774 * Allocate a jumbo buffer.
775 */
0050ab7d 776static struct lge_jslot *
63c0e4aa 777lge_jalloc(struct lge_softc *sc)
984263bc 778{
0050ab7d 779 struct lge_jslot *entry;
63c0e4aa 780
984263bc 781 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
63c0e4aa 782
984263bc
MD
783 if (entry == NULL) {
784#ifdef LGE_VERBOSE
785 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
786#endif
787 return(NULL);
788 }
789
0050ab7d
JS
790 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link);
791 entry->lge_inuse = 1;
63c0e4aa 792
0050ab7d 793 return(entry);
984263bc
MD
794}
795
796/*
797 * Adjust usage count on a jumbo buffer. In general this doesn't
798 * get used much because our jumbo buffers don't get passed around
799 * a lot, but it's implemented for correctness.
800 */
63c0e4aa 801static void
0050ab7d 802lge_jref(void *arg)
984263bc 803{
0050ab7d
JS
804 struct lge_jslot *entry = (struct lge_jslot *)arg;
805 struct lge_softc *sc = entry->lge_sc;
984263bc 806
0050ab7d 807 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry)
984263bc
MD
808 panic("lge_jref: asked to reference buffer "
809 "that we don't manage!");
0050ab7d 810 else if (entry->lge_inuse == 0)
984263bc
MD
811 panic("lge_jref: buffer already free!");
812 else
0050ab7d 813 entry->lge_inuse++;
984263bc
MD
814}
815
816/*
817 * Release a jumbo buffer.
818 */
63c0e4aa 819static void
0050ab7d 820lge_jfree(void *arg)
984263bc 821{
0050ab7d
JS
822 struct lge_jslot *entry = (struct lge_jslot *)arg;
823 struct lge_softc *sc = entry->lge_sc;
984263bc
MD
824
825 if (sc == NULL)
826 panic("lge_jfree: can't find softc pointer!");
827
0050ab7d 828 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry)
984263bc 829 panic("lge_jfree: asked to free buffer that we don't manage!");
0050ab7d 830 else if (entry->lge_inuse == 0)
984263bc 831 panic("lge_jfree: buffer already free!");
0050ab7d
JS
832 else if (--entry->lge_inuse == 0)
833 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link);
984263bc
MD
834}
835
836/*
837 * A frame has been uploaded: pass the resulting mbuf chain up to
838 * the higher level protocols.
839 */
63c0e4aa
JS
840static void
841lge_rxeof(struct lge_softc *sc, int cnt)
984263bc 842{
63c0e4aa
JS
843 struct ifnet *ifp = &sc->arpcom.ac_if;
844 struct mbuf *m;
845 struct lge_rx_desc *cur_rx;
846 int c, i, total_len = 0;
847 uint32_t rxsts, rxctl;
984263bc 848
984263bc
MD
849
850 /* Find out how many frames were processed. */
851 c = cnt;
852 i = sc->lge_cdata.lge_rx_cons;
853
854 /* Suck them in. */
855 while(c) {
63c0e4aa 856 struct mbuf *m0 = NULL;
984263bc
MD
857
858 cur_rx = &sc->lge_ldata->lge_rx_list[i];
859 rxctl = cur_rx->lge_ctl;
860 rxsts = cur_rx->lge_sts;
861 m = cur_rx->lge_mbuf;
862 cur_rx->lge_mbuf = NULL;
863 total_len = LGE_RXBYTES(cur_rx);
864 LGE_INC(i, LGE_RX_LIST_CNT);
865 c--;
866
867 /*
868 * If an error occurs, update stats, clear the
869 * status word and leave the mbuf cluster in place:
870 * it should simply get re-used next time this descriptor
871 * comes up in the ring.
872 */
873 if (rxctl & LGE_RXCTL_ERRMASK) {
874 ifp->if_ierrors++;
875 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
876 continue;
877 }
878
879 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
880 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
881 total_len + ETHER_ALIGN, 0, ifp, NULL);
882 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
883 if (m0 == NULL) {
884 printf("lge%d: no receive buffers "
885 "available -- packet dropped!\n",
886 sc->lge_unit);
887 ifp->if_ierrors++;
888 continue;
889 }
890 m_adj(m0, ETHER_ALIGN);
891 m = m0;
892 } else {
893 m->m_pkthdr.rcvif = ifp;
894 m->m_pkthdr.len = m->m_len = total_len;
895 }
896
897 ifp->if_ipackets++;
984263bc
MD
898
899 /* Do IP checksum checking. */
900 if (rxsts & LGE_RXSTS_ISIP)
901 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
902 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
903 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
904 if ((rxsts & LGE_RXSTS_ISTCP &&
905 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
906 (rxsts & LGE_RXSTS_ISUDP &&
907 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
908 m->m_pkthdr.csum_flags |=
909 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
910 m->m_pkthdr.csum_data = 0xffff;
911 }
912
78195a76 913 ifp->if_input(ifp, m);
984263bc
MD
914 }
915
916 sc->lge_cdata.lge_rx_cons = i;
984263bc
MD
917}
918
63c0e4aa
JS
919static void
920lge_rxeoc(struct lge_softc *sc)
984263bc 921{
63c0e4aa 922 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 923
984263bc
MD
924 ifp->if_flags &= ~IFF_RUNNING;
925 lge_init(sc);
984263bc
MD
926}
927
928/*
929 * A frame was downloaded to the chip. It's safe for us to clean up
930 * the list buffers.
931 */
63c0e4aa
JS
932static void
933lge_txeof(struct lge_softc *sc)
984263bc 934{
63c0e4aa
JS
935 struct ifnet *ifp = &sc->arpcom.ac_if;
936 struct lge_tx_desc *cur_tx = NULL;
937 uint32_t idx, txdone;
984263bc
MD
938
939 /* Clear the timeout timer. */
940 ifp->if_timer = 0;
941
942 /*
943 * Go through our tx list and free mbufs for those
944 * frames that have been transmitted.
945 */
946 idx = sc->lge_cdata.lge_tx_cons;
947 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
948
949 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
950 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
951
952 ifp->if_opackets++;
953 if (cur_tx->lge_mbuf != NULL) {
954 m_freem(cur_tx->lge_mbuf);
955 cur_tx->lge_mbuf = NULL;
956 }
957 cur_tx->lge_ctl = 0;
958
959 txdone--;
960 LGE_INC(idx, LGE_TX_LIST_CNT);
961 ifp->if_timer = 0;
962 }
963
964 sc->lge_cdata.lge_tx_cons = idx;
965
966 if (cur_tx != NULL)
967 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
968}
969
63c0e4aa
JS
970static void
971lge_tick(void *xsc)
984263bc 972{
63c0e4aa 973 struct lge_softc *sc = xsc;
63c0e4aa 974 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 975
78195a76
MD
976 lwkt_serialize_enter(ifp->if_serializer);
977 lge_tick_serialized(xsc);
978 lwkt_serialize_exit(ifp->if_serializer);
979}
980
981static void
982lge_tick_serialized(void *xsc)
983{
984 struct lge_softc *sc = xsc;
985 struct mii_data *mii;
986 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 987
984263bc
MD
988 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
989 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
990 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
991 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
992
993 if (!sc->lge_link) {
994 mii = device_get_softc(sc->lge_miibus);
995 mii_tick(mii);
996 mii_pollstat(mii);
997 if (mii->mii_media_status & IFM_ACTIVE &&
998 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
999 sc->lge_link++;
1000 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
7f259627 1001 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
984263bc
MD
1002 printf("lge%d: gigabit link up\n",
1003 sc->lge_unit);
d1f483a6 1004 if (!ifq_is_empty(&ifp->if_snd))
63c0e4aa 1005 (*ifp->if_start)(ifp);
984263bc
MD
1006 }
1007 }
1008
29744ced 1009 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
984263bc
MD
1010}
1011
63c0e4aa
JS
1012static void
1013lge_intr(void *arg)
984263bc 1014{
63c0e4aa
JS
1015 struct lge_softc *sc = arg;
1016 struct ifnet *ifp = &sc->arpcom.ac_if;
1017 uint32_t status;
984263bc
MD
1018
1019 /* Supress unwanted interrupts */
63c0e4aa 1020 if ((ifp->if_flags & IFF_UP) == 0) {
984263bc
MD
1021 lge_stop(sc);
1022 return;
1023 }
1024
1025 for (;;) {
1026 /*
1027 * Reading the ISR register clears all interrupts, and
1028 * clears the 'interrupts enabled' bit in the IMR
1029 * register.
1030 */
1031 status = CSR_READ_4(sc, LGE_ISR);
1032
1033 if ((status & LGE_INTRS) == 0)
1034 break;
1035
1036 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1037 lge_txeof(sc);
1038
1039 if (status & LGE_ISR_RXDMA_DONE)
1040 lge_rxeof(sc, LGE_RX_DMACNT(status));
1041
1042 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1043 lge_rxeoc(sc);
1044
1045 if (status & LGE_ISR_PHY_INTR) {
1046 sc->lge_link = 0;
29744ced 1047 callout_stop(&sc->lge_stat_timer);
78195a76 1048 lge_tick_serialized(sc);
984263bc
MD
1049 }
1050 }
1051
1052 /* Re-enable interrupts. */
1053 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1054
d1f483a6 1055 if (!ifq_is_empty(&ifp->if_snd))
63c0e4aa 1056 (*ifp->if_start)(ifp);
984263bc
MD
1057}
1058
1059/*
1060 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1061 * pointers to the fragment pointers.
1062 */
63c0e4aa
JS
1063static int
1064lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1065{
63c0e4aa
JS
1066 struct lge_frag *f = NULL;
1067 struct lge_tx_desc *cur_tx;
1068 struct mbuf *m;
1069 int frag = 0, tot_len = 0;
984263bc
MD
1070
1071 /*
1072 * Start packing the mbufs in this chain into
1073 * the fragment pointers. Stop when we run out
1074 * of fragments or hit the end of the mbuf chain.
1075 */
1076 m = m_head;
1077 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1078 frag = 0;
1079
1080 for (m = m_head; m != NULL; m = m->m_next) {
1081 if (m->m_len != 0) {
1082 tot_len += m->m_len;
1083 f = &cur_tx->lge_frags[frag];
1084 f->lge_fraglen = m->m_len;
1085 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1086 f->lge_fragptr_hi = 0;
1087 frag++;
1088 }
1089 }
1090
1091 if (m != NULL)
1092 return(ENOBUFS);
1093
1094 cur_tx->lge_mbuf = m_head;
1095 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1096 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1097
1098 /* Queue for transmit */
1099 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1100
1101 return(0);
1102}
1103
1104/*
1105 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1106 * to the mbuf data regions directly in the transmit lists. We also save a
1107 * copy of the pointers since the transmit list fragment pointers are
1108 * physical addresses.
1109 */
1110
63c0e4aa
JS
1111static void
1112lge_start(struct ifnet *ifp)
984263bc 1113{
63c0e4aa
JS
1114 struct lge_softc *sc = ifp->if_softc;
1115 struct mbuf *m_head = NULL;
1116 uint32_t idx;
2f54d1d2 1117 int need_timer;
984263bc
MD
1118
1119 if (!sc->lge_link)
1120 return;
1121
1122 idx = sc->lge_cdata.lge_tx_prod;
1123
1124 if (ifp->if_flags & IFF_OACTIVE)
1125 return;
1126
2f54d1d2 1127 need_timer = 0;
984263bc
MD
1128 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1129 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1130 break;
1131
d1f483a6 1132 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
1133 if (m_head == NULL)
1134 break;
1135
1136 if (lge_encap(sc, m_head, &idx)) {
984263bc
MD
1137 ifp->if_flags |= IFF_OACTIVE;
1138 break;
1139 }
d2c71fa0 1140 ifq_dequeue(&ifp->if_snd, m_head);
2f54d1d2 1141 need_timer = 1;
984263bc 1142
7600679e 1143 BPF_MTAP(ifp, m_head);
984263bc
MD
1144 }
1145
2f54d1d2
SZ
1146 if (!need_timer)
1147 return;
1148
984263bc
MD
1149 sc->lge_cdata.lge_tx_prod = idx;
1150
1151 /*
1152 * Set a timeout in case the chip goes out to lunch.
1153 */
1154 ifp->if_timer = 5;
984263bc
MD
1155}
1156
63c0e4aa
JS
1157static void
1158lge_init(void *xsc)
984263bc 1159{
63c0e4aa
JS
1160 struct lge_softc *sc = xsc;
1161 struct ifnet *ifp = &sc->arpcom.ac_if;
1162 struct mii_data *mii;
984263bc 1163
78195a76 1164 if (ifp->if_flags & IFF_RUNNING)
2742eee0 1165 return;
984263bc
MD
1166
1167 /*
1168 * Cancel pending I/O and free all RX/TX buffers.
1169 */
1170 lge_stop(sc);
1171 lge_reset(sc);
1172
1173 mii = device_get_softc(sc->lge_miibus);
1174
1175 /* Set MAC address */
63c0e4aa
JS
1176 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1177 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
984263bc
MD
1178
1179 /* Init circular RX list. */
1180 if (lge_list_rx_init(sc) == ENOBUFS) {
1181 printf("lge%d: initialization failed: no "
1182 "memory for rx buffers\n", sc->lge_unit);
1183 lge_stop(sc);
984263bc
MD
1184 return;
1185 }
1186
1187 /*
1188 * Init tx descriptors.
1189 */
1190 lge_list_tx_init(sc);
1191
1192 /* Set initial value for MODE1 register. */
63c0e4aa
JS
1193 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST |
1194 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD |
1195 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 |
1196 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2);
984263bc
MD
1197
1198 /* If we want promiscuous mode, set the allframes bit. */
1199 if (ifp->if_flags & IFF_PROMISC) {
1200 CSR_WRITE_4(sc, LGE_MODE1,
63c0e4aa 1201 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC);
984263bc
MD
1202 } else {
1203 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1204 }
1205
1206 /*
1207 * Set the capture broadcast bit to capture broadcast frames.
1208 */
1209 if (ifp->if_flags & IFF_BROADCAST) {
1210 CSR_WRITE_4(sc, LGE_MODE1,
63c0e4aa 1211 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST);
984263bc
MD
1212 } else {
1213 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1214 }
1215
1216 /* Packet padding workaround? */
1217 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1218
1219 /* No error frames */
1220 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1221
1222 /* Receive large frames */
63c0e4aa 1223 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS);
984263bc
MD
1224
1225 /* Workaround: disable RX/TX flow control */
1226 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1227 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1228
1229 /* Make sure to strip CRC from received frames */
1230 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1231
1232 /* Turn off magic packet mode */
1233 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1234
1235 /* Turn off all VLAN stuff */
63c0e4aa
JS
1236 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX |
1237 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT);
984263bc
MD
1238
1239 /* Workarond: FIFO overflow */
1240 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1241 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1242
1243 /*
1244 * Load the multicast filter.
1245 */
1246 lge_setmulti(sc);
1247
1248 /*
1249 * Enable hardware checksum validation for all received IPv4
1250 * packets, do not reject packets with bad checksums.
1251 */
63c0e4aa
JS
1252 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM |
1253 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM |
984263bc
MD
1254 LGE_MODE2_RX_ERRCSUM);
1255
1256 /*
1257 * Enable the delivery of PHY interrupts based on
1258 * link/speed/duplex status chalges.
1259 */
63c0e4aa 1260 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL);
984263bc
MD
1261
1262 /* Enable receiver and transmitter. */
1263 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
63c0e4aa 1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB);
984263bc
MD
1265
1266 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
63c0e4aa 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB);
984263bc
MD
1268
1269 /*
1270 * Enable interrupts.
1271 */
63c0e4aa
JS
1272 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 |
1273 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS);
984263bc
MD
1274
1275 lge_ifmedia_upd(ifp);
1276
1277 ifp->if_flags |= IFF_RUNNING;
1278 ifp->if_flags &= ~IFF_OACTIVE;
1279
29744ced 1280 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
984263bc
MD
1281}
1282
1283/*
1284 * Set media options.
1285 */
63c0e4aa
JS
1286static int
1287lge_ifmedia_upd(struct ifnet *ifp)
984263bc 1288{
63c0e4aa
JS
1289 struct lge_softc *sc = ifp->if_softc;
1290 struct mii_data *mii = device_get_softc(sc->lge_miibus);
984263bc 1291
984263bc
MD
1292 sc->lge_link = 0;
1293 if (mii->mii_instance) {
63c0e4aa
JS
1294 struct mii_softc *miisc;
1295 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
984263bc
MD
1296 mii_phy_reset(miisc);
1297 }
1298 mii_mediachg(mii);
1299
1300 return(0);
1301}
1302
1303/*
1304 * Report current media status.
1305 */
63c0e4aa
JS
1306static void
1307lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1308{
030ffb8e 1309 struct lge_softc *sc = ifp->if_softc;
63c0e4aa 1310 struct mii_data *mii;
984263bc
MD
1311
1312 mii = device_get_softc(sc->lge_miibus);
1313 mii_pollstat(mii);
1314 ifmr->ifm_active = mii->mii_media_active;
1315 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1316}
1317
63c0e4aa
JS
1318static int
1319lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1320{
63c0e4aa
JS
1321 struct lge_softc *sc = ifp->if_softc;
1322 struct ifreq *ifr = (struct ifreq *) data;
1323 struct mii_data *mii;
2742eee0 1324 int error = 0;
984263bc 1325
984263bc 1326 switch(command) {
984263bc
MD
1327 case SIOCSIFMTU:
1328 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1329 error = EINVAL;
1330 else
1331 ifp->if_mtu = ifr->ifr_mtu;
1332 break;
1333 case SIOCSIFFLAGS:
1334 if (ifp->if_flags & IFF_UP) {
1335 if (ifp->if_flags & IFF_RUNNING &&
1336 ifp->if_flags & IFF_PROMISC &&
1337 !(sc->lge_if_flags & IFF_PROMISC)) {
1338 CSR_WRITE_4(sc, LGE_MODE1,
1339 LGE_MODE1_SETRST_CTL1|
1340 LGE_MODE1_RX_PROMISC);
1341 } else if (ifp->if_flags & IFF_RUNNING &&
1342 !(ifp->if_flags & IFF_PROMISC) &&
1343 sc->lge_if_flags & IFF_PROMISC) {
1344 CSR_WRITE_4(sc, LGE_MODE1,
1345 LGE_MODE1_RX_PROMISC);
1346 } else {
1347 ifp->if_flags &= ~IFF_RUNNING;
1348 lge_init(sc);
1349 }
1350 } else {
1351 if (ifp->if_flags & IFF_RUNNING)
1352 lge_stop(sc);
1353 }
1354 sc->lge_if_flags = ifp->if_flags;
1355 error = 0;
1356 break;
1357 case SIOCADDMULTI:
1358 case SIOCDELMULTI:
1359 lge_setmulti(sc);
1360 error = 0;
1361 break;
1362 case SIOCGIFMEDIA:
1363 case SIOCSIFMEDIA:
1364 mii = device_get_softc(sc->lge_miibus);
1365 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1366 break;
1367 default:
4cde4dd5 1368 error = ether_ioctl(ifp, command, data);
984263bc
MD
1369 break;
1370 }
1371
984263bc
MD
1372 return(error);
1373}
1374
63c0e4aa
JS
1375static void
1376lge_watchdog(struct ifnet *ifp)
984263bc 1377{
63c0e4aa 1378 struct lge_softc *sc = ifp->if_softc;
984263bc
MD
1379
1380 ifp->if_oerrors++;
1381 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1382
1383 lge_stop(sc);
1384 lge_reset(sc);
1385 ifp->if_flags &= ~IFF_RUNNING;
1386 lge_init(sc);
1387
d1f483a6 1388 if (!ifq_is_empty(&ifp->if_snd))
63c0e4aa 1389 (*ifp->if_start)(ifp);
984263bc
MD
1390}
1391
1392/*
1393 * Stop the adapter and free any mbufs allocated to the
1394 * RX and TX lists.
1395 */
63c0e4aa
JS
1396static void
1397lge_stop(struct lge_softc *sc)
984263bc 1398{
63c0e4aa
JS
1399 struct ifnet *ifp = &sc->arpcom.ac_if;
1400 int i;
984263bc 1401
984263bc 1402 ifp->if_timer = 0;
29744ced 1403 callout_stop(&sc->lge_stat_timer);
984263bc
MD
1404 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1405
1406 /* Disable receiver and transmitter. */
1407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1408 sc->lge_link = 0;
1409
1410 /*
1411 * Free data in the RX lists.
1412 */
1413 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1414 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1415 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1416 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1417 }
1418 }
63c0e4aa 1419 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list));
984263bc
MD
1420
1421 /*
1422 * Free the TX list buffers.
1423 */
1424 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1425 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1426 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1427 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1428 }
1429 }
1430
63c0e4aa 1431 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list));
984263bc
MD
1432
1433 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1434}
1435
1436/*
1437 * Stop all chip I/O so that the kernel's probe routines don't
1438 * get confused by errant DMAs when rebooting.
1439 */
63c0e4aa
JS
1440static void
1441lge_shutdown(device_t dev)
984263bc 1442{
63c0e4aa 1443 struct lge_softc *sc = device_get_softc(dev);
984263bc
MD
1444
1445 lge_reset(sc);
1446 lge_stop(sc);
984263bc 1447}