Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / my / if_my.c
CommitLineData
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1/*
2 * Copyright (c) 2002 Myson Technology Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
27 *
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
78195a76 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.23 2005/11/28 17:13:43 dillon Exp $
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30 *
31 * Myson fast ethernet PCI NIC driver
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32 *
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
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34 */
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/sockio.h>
38#include <sys/mbuf.h>
39#include <sys/malloc.h>
40#include <sys/kernel.h>
41#include <sys/socket.h>
42#include <sys/queue.h>
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43#include <sys/bus.h>
44#include <sys/module.h>
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45#include <sys/serialize.h>
46
47#include <sys/thread2.h>
984263bc 48
984263bc 49#include <net/if.h>
d64721c9 50#include <net/ifq_var.h>
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51#include <net/if_arp.h>
52#include <net/ethernet.h>
53#include <net/if_media.h>
54#include <net/if_dl.h>
55#include <net/bpf.h>
56
57#include <vm/vm.h> /* for vtophys */
58#include <vm/pmap.h> /* for vtophys */
59#include <machine/clock.h> /* for DELAY */
60#include <machine/bus_memio.h>
61#include <machine/bus_pio.h>
62#include <machine/bus.h>
63#include <machine/resource.h>
64#include <sys/bus.h>
65#include <sys/rman.h>
66
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67#include <bus/pci/pcireg.h>
68#include <bus/pci/pcivar.h>
984263bc 69
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70#include "../mii_layer/mii.h"
71#include "../mii_layer/miivar.h"
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72
73#include "miibus_if.h"
74
75/*
76 * #define MY_USEIOSPACE
77 */
78
79static int MY_USEIOSPACE = 1;
80
81#if (MY_USEIOSPACE)
82#define MY_RES SYS_RES_IOPORT
83#define MY_RID MY_PCI_LOIO
84#else
85#define MY_RES SYS_RES_MEMORY
86#define MY_RID MY_PCI_LOMEM
87#endif
88
89
1f2de5d4 90#include "if_myreg.h"
984263bc 91
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92/*
93 * Various supported device vendors/types and their names.
94 */
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95static struct my_type my_devs[] = {
96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
99 {0, 0, NULL}
100};
101
102/*
103 * Various supported PHY vendors/types and their names. Note that this driver
104 * will work with pretty much any MII-compliant PHY, so failure to positively
105 * identify the chip is not a fatal error.
106 */
107static struct my_type my_phys[] = {
108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
113 {0, 0, "<MII-compliant physical interface>"}
114};
115
116static int my_probe(device_t);
117static int my_attach(device_t);
118static int my_detach(device_t);
119static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
120static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
121static void my_rxeof(struct my_softc *);
122static void my_txeof(struct my_softc *);
123static void my_txeoc(struct my_softc *);
124static void my_intr(void *);
125static void my_start(struct ifnet *);
bd4539cc 126static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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127static void my_init(void *);
128static void my_stop(struct my_softc *);
129static void my_watchdog(struct ifnet *);
130static void my_shutdown(device_t);
131static int my_ifmedia_upd(struct ifnet *);
132static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133static u_int16_t my_phy_readreg(struct my_softc *, int);
134static void my_phy_writereg(struct my_softc *, int, int);
135static void my_autoneg_xmit(struct my_softc *);
136static void my_autoneg_mii(struct my_softc *, int, int);
137static void my_setmode_mii(struct my_softc *, int);
138static void my_getmode_mii(struct my_softc *);
139static void my_setcfg(struct my_softc *, int);
140static u_int8_t my_calchash(caddr_t);
141static void my_setmulti(struct my_softc *);
142static void my_reset(struct my_softc *);
143static int my_list_rx_init(struct my_softc *);
144static int my_list_tx_init(struct my_softc *);
145static long my_send_cmd_to_phy(struct my_softc *, int, int);
146
147#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
148#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
149
150static device_method_t my_methods[] = {
151 /* Device interface */
152 DEVMETHOD(device_probe, my_probe),
153 DEVMETHOD(device_attach, my_attach),
154 DEVMETHOD(device_detach, my_detach),
155 DEVMETHOD(device_shutdown, my_shutdown),
156
157 {0, 0}
158};
159
160static driver_t my_driver = {
161 "my",
162 my_methods,
163 sizeof(struct my_softc)
164};
165
166static devclass_t my_devclass;
167
32832096 168DECLARE_DUMMY_MODULE(if_my);
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169DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
170
171static long
172my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
173{
174 long miir;
175 int i;
176 int mask, data;
177
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178 /* enable MII output */
179 miir = CSR_READ_4(sc, MY_MANAGEMENT);
180 miir &= 0xfffffff0;
181
182 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
183
184 /* send 32 1's preamble */
185 for (i = 0; i < 32; i++) {
186 /* low MDC; MDO is already high (miir) */
187 miir &= ~MY_MASK_MIIR_MII_MDC;
188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
189
190 /* high MDC */
191 miir |= MY_MASK_MIIR_MII_MDC;
192 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
193 }
194
195 /* calculate ST+OP+PHYAD+REGAD+TA */
196 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
197
198 /* sent out */
199 mask = 0x8000;
200 while (mask) {
201 /* low MDC, prepare MDO */
202 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
203 if (mask & data)
204 miir |= MY_MASK_MIIR_MII_MDO;
205
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
207 /* high MDC */
208 miir |= MY_MASK_MIIR_MII_MDC;
209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
210 DELAY(30);
211
212 /* next */
213 mask >>= 1;
214 if (mask == 0x2 && opcode == MY_OP_READ)
215 miir &= ~MY_MASK_MIIR_MII_WRITE;
216 }
217
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218 return miir;
219}
220
221
222static u_int16_t
223my_phy_readreg(struct my_softc * sc, int reg)
224{
225 long miir;
226 int mask, data;
227
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228 if (sc->my_info->my_did == MTD803ID)
229 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
230 else {
231 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
232
233 /* read data */
234 mask = 0x8000;
235 data = 0;
236 while (mask) {
237 /* low MDC */
238 miir &= ~MY_MASK_MIIR_MII_MDC;
239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
240
241 /* read MDI */
242 miir = CSR_READ_4(sc, MY_MANAGEMENT);
243 if (miir & MY_MASK_MIIR_MII_MDI)
244 data |= mask;
245
246 /* high MDC, and wait */
247 miir |= MY_MASK_MIIR_MII_MDC;
248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
249 DELAY(30);
250
251 /* next */
252 mask >>= 1;
253 }
254
255 /* low MDC */
256 miir &= ~MY_MASK_MIIR_MII_MDC;
257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
258 }
259
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260 return (u_int16_t) data;
261}
262
263
264static void
265my_phy_writereg(struct my_softc * sc, int reg, int data)
266{
267 long miir;
268 int mask;
269
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270 if (sc->my_info->my_did == MTD803ID)
271 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
272 else {
273 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
274
275 /* write data */
276 mask = 0x8000;
277 while (mask) {
278 /* low MDC, prepare MDO */
279 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
280 if (mask & data)
281 miir |= MY_MASK_MIIR_MII_MDO;
282 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
283 DELAY(1);
284
285 /* high MDC */
286 miir |= MY_MASK_MIIR_MII_MDC;
287 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
288 DELAY(1);
289
290 /* next */
291 mask >>= 1;
292 }
293
294 /* low MDC */
295 miir &= ~MY_MASK_MIIR_MII_MDC;
296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
297 }
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298}
299
300static u_int8_t
301my_calchash(caddr_t addr)
302{
303 u_int32_t crc, carry;
304 int i, j;
305 u_int8_t c;
306
307 /* Compute CRC for the address value. */
308 crc = 0xFFFFFFFF; /* initial value */
309
310 for (i = 0; i < 6; i++) {
311 c = *(addr + i);
312 for (j = 0; j < 8; j++) {
313 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
314 crc <<= 1;
315 c >>= 1;
316 if (carry)
317 crc = (crc ^ 0x04c11db6) | carry;
318 }
319 }
320
321 /*
322 * return the filter bit position Note: I arrived at the following
323 * nonsense through experimentation. It's not the usual way to
324 * generate the bit position but it's the only thing I could come up
325 * with that works.
326 */
327 return (~(crc >> 26) & 0x0000003F);
328}
329
330
331/*
332 * Program the 64-bit multicast hash filter.
333 */
334static void
335my_setmulti(struct my_softc * sc)
336{
c0f0a6cb 337 struct ifnet *ifp = &sc->arpcom.ac_if;
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338 int h = 0;
339 u_int32_t hashes[2] = {0, 0};
340 struct ifmultiaddr *ifma;
341 u_int32_t rxfilt;
342 int mcnt = 0;
343
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344 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
345
346 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
347 rxfilt |= MY_AM;
348 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
349 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
350 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
351
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352 return;
353 }
354 /* first, zot all the existing hash bits */
355 CSR_WRITE_4(sc, MY_MAR0, 0);
356 CSR_WRITE_4(sc, MY_MAR1, 0);
357
358 /* now program new ones */
359 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
360 if (ifma->ifma_addr->sa_family != AF_LINK)
361 continue;
362 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
363 if (h < 32)
364 hashes[0] |= (1 << h);
365 else
366 hashes[1] |= (1 << (h - 32));
367 mcnt++;
368 }
369
370 if (mcnt)
371 rxfilt |= MY_AM;
372 else
373 rxfilt &= ~MY_AM;
374 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
375 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
376 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
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377}
378
379/*
380 * Initiate an autonegotiation session.
381 */
382static void
383my_autoneg_xmit(struct my_softc * sc)
384{
385 u_int16_t phy_sts = 0;
386
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387 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
388 DELAY(500);
389 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
390
391 phy_sts = my_phy_readreg(sc, PHY_BMCR);
392 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
393 my_phy_writereg(sc, PHY_BMCR, phy_sts);
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394}
395
396
397/*
398 * Invoke autonegotiation on a PHY.
399 */
400static void
401my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
402{
403 u_int16_t phy_sts = 0, media, advert, ability;
404 u_int16_t ability2 = 0;
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405 struct ifnet *ifp = &sc->arpcom.ac_if;
406 struct ifmedia *ifm = &sc->ifmedia;
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407
408 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
409
410#ifndef FORCE_AUTONEG_TFOUR
411 /*
412 * First, see if autoneg is supported. If not, there's no point in
413 * continuing.
414 */
415 phy_sts = my_phy_readreg(sc, PHY_BMSR);
416 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
417 if (verbose)
418 printf("my%d: autonegotiation not supported\n",
419 sc->my_unit);
420 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
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421 return;
422 }
423#endif
424 switch (flag) {
425 case MY_FLAG_FORCEDELAY:
426 /*
427 * XXX Never use this option anywhere but in the probe
428 * routine: making the kernel stop dead in its tracks for
429 * three whole seconds after we've gone multi-user is really
430 * bad manners.
431 */
432 my_autoneg_xmit(sc);
433 DELAY(5000000);
434 break;
435 case MY_FLAG_SCHEDDELAY:
436 /*
437 * Wait for the transmitter to go idle before starting an
438 * autoneg session, otherwise my_start() may clobber our
439 * timeout, and we don't want to allow transmission during an
440 * autoneg session since that can screw it up.
441 */
442 if (sc->my_cdata.my_tx_head != NULL) {
443 sc->my_want_auto = 1;
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444 return;
445 }
446 my_autoneg_xmit(sc);
447 ifp->if_timer = 5;
448 sc->my_autoneg = 1;
449 sc->my_want_auto = 0;
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450 return;
451 case MY_FLAG_DELAYTIMEO:
452 ifp->if_timer = 0;
453 sc->my_autoneg = 0;
454 break;
455 default:
456 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
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457 return;
458 }
459
460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
461 if (verbose)
462 printf("my%d: autoneg complete, ", sc->my_unit);
463 phy_sts = my_phy_readreg(sc, PHY_BMSR);
464 } else {
465 if (verbose)
466 printf("my%d: autoneg not complete, ", sc->my_unit);
467 }
468
469 media = my_phy_readreg(sc, PHY_BMCR);
470
471 /* Link is good. Report modes and set duplex mode. */
472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
473 if (verbose)
474 printf("my%d: link status good. ", sc->my_unit);
475 advert = my_phy_readreg(sc, PHY_ANAR);
476 ability = my_phy_readreg(sc, PHY_LPAR);
477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 ability2 = my_phy_readreg(sc, PHY_1000SR);
480 if (ability2 & PHY_1000SR_1000BTXFULL) {
481 advert = 0;
482 ability = 0;
483 /*
484 * this version did not support 1000M,
485 * ifm->ifm_media =
7f259627 486 * IFM_ETHER | IFM_1000_T | IFM_FDX;
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487 */
488 ifm->ifm_media =
489 IFM_ETHER | IFM_100_TX | IFM_FDX;
490 media &= ~PHY_BMCR_SPEEDSEL;
491 media |= PHY_BMCR_1000;
492 media |= PHY_BMCR_DUPLEX;
493 printf("(full-duplex, 1000Mbps)\n");
494 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
495 advert = 0;
496 ability = 0;
497 /*
498 * this version did not support 1000M,
7f259627 499 * ifm->ifm_media = IFM_ETHER | IFM_1000_T;
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500 */
501 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 media &= ~PHY_BMCR_SPEEDSEL;
503 media &= ~PHY_BMCR_DUPLEX;
504 media |= PHY_BMCR_1000;
505 printf("(half-duplex, 1000Mbps)\n");
506 }
507 }
508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 media |= PHY_BMCR_SPEEDSEL;
511 media &= ~PHY_BMCR_DUPLEX;
512 printf("(100baseT4)\n");
513 } else if (advert & PHY_ANAR_100BTXFULL &&
514 ability & PHY_ANAR_100BTXFULL) {
515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 media |= PHY_BMCR_SPEEDSEL;
517 media |= PHY_BMCR_DUPLEX;
518 printf("(full-duplex, 100Mbps)\n");
519 } else if (advert & PHY_ANAR_100BTXHALF &&
520 ability & PHY_ANAR_100BTXHALF) {
521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 media |= PHY_BMCR_SPEEDSEL;
523 media &= ~PHY_BMCR_DUPLEX;
524 printf("(half-duplex, 100Mbps)\n");
525 } else if (advert & PHY_ANAR_10BTFULL &&
526 ability & PHY_ANAR_10BTFULL) {
527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 media &= ~PHY_BMCR_SPEEDSEL;
529 media |= PHY_BMCR_DUPLEX;
530 printf("(full-duplex, 10Mbps)\n");
531 } else if (advert) {
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 printf("(half-duplex, 10Mbps)\n");
536 }
537 media &= ~PHY_BMCR_AUTONEGENBL;
538
539 /* Set ASIC's duplex mode to match the PHY. */
540 my_phy_writereg(sc, PHY_BMCR, media);
541 my_setcfg(sc, media);
542 } else {
543 if (verbose)
544 printf("my%d: no carrier\n", sc->my_unit);
545 }
546
547 my_init(sc);
548 if (sc->my_tx_pend) {
549 sc->my_autoneg = 0;
550 sc->my_tx_pend = 0;
551 my_start(ifp);
552 }
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553}
554
555/*
556 * To get PHY ability.
557 */
558static void
559my_getmode_mii(struct my_softc * sc)
560{
c0f0a6cb 561 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 562 u_int16_t bmsr;
984263bc 563
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564 bmsr = my_phy_readreg(sc, PHY_BMSR);
565 if (bootverbose)
566 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
567
568 /* fallback */
569 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
570
571 if (bmsr & PHY_BMSR_10BTHALF) {
572 if (bootverbose)
573 printf("my%d: 10Mbps half-duplex mode supported\n",
574 sc->my_unit);
575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
576 0, NULL);
577 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
578 }
579 if (bmsr & PHY_BMSR_10BTFULL) {
580 if (bootverbose)
581 printf("my%d: 10Mbps full-duplex mode supported\n",
582 sc->my_unit);
583
584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
585 0, NULL);
586 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
587 }
588 if (bmsr & PHY_BMSR_100BTXHALF) {
589 if (bootverbose)
590 printf("my%d: 100Mbps half-duplex mode supported\n",
591 sc->my_unit);
592 ifp->if_baudrate = 100000000;
593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
595 0, NULL);
596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
597 }
598 if (bmsr & PHY_BMSR_100BTXFULL) {
599 if (bootverbose)
600 printf("my%d: 100Mbps full-duplex mode supported\n",
601 sc->my_unit);
602 ifp->if_baudrate = 100000000;
603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
604 0, NULL);
605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
606 }
607 /* Some also support 100BaseT4. */
608 if (bmsr & PHY_BMSR_100BT4) {
609 if (bootverbose)
610 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
611 ifp->if_baudrate = 100000000;
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
614#ifdef FORCE_AUTONEG_TFOUR
615 if (bootverbose)
616 printf("my%d: forcing on autoneg support for BT4\n",
617 sc->my_unit);
618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
619 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
620#endif
621 }
622#if 0 /* this version did not support 1000M, */
623 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
624 if (bootverbose)
625 printf("my%d: 1000Mbps half-duplex mode supported\n",
626 sc->my_unit);
627
628 ifp->if_baudrate = 1000000000;
7f259627
JS
629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
984263bc
MD
631 0, NULL);
632 if (bootverbose)
633 printf("my%d: 1000Mbps full-duplex mode supported\n",
634 sc->my_unit);
635 ifp->if_baudrate = 1000000000;
7f259627 636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
984263bc 637 0, NULL);
7f259627 638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
984263bc
MD
639 }
640#endif
641 if (bmsr & PHY_BMSR_CANAUTONEG) {
642 if (bootverbose)
643 printf("my%d: autoneg supported\n", sc->my_unit);
644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
645 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
646 }
984263bc
MD
647}
648
649/*
650 * Set speed and duplex mode.
651 */
652static void
653my_setmode_mii(struct my_softc * sc, int media)
654{
c0f0a6cb 655 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 656 u_int16_t bmcr;
984263bc 657
984263bc
MD
658 /*
659 * If an autoneg session is in progress, stop it.
660 */
661 if (sc->my_autoneg) {
662 printf("my%d: canceling autoneg session\n", sc->my_unit);
663 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
664 bmcr = my_phy_readreg(sc, PHY_BMCR);
665 bmcr &= ~PHY_BMCR_AUTONEGENBL;
666 my_phy_writereg(sc, PHY_BMCR, bmcr);
667 }
668 printf("my%d: selecting MII, ", sc->my_unit);
669 bmcr = my_phy_readreg(sc, PHY_BMCR);
670 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
671 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
672
673#if 0 /* this version did not support 1000M, */
7f259627 674 if (IFM_SUBTYPE(media) == IFM_1000_T) {
984263bc
MD
675 printf("1000Mbps/T4, half-duplex\n");
676 bmcr &= ~PHY_BMCR_SPEEDSEL;
677 bmcr &= ~PHY_BMCR_DUPLEX;
678 bmcr |= PHY_BMCR_1000;
679 }
680#endif
681 if (IFM_SUBTYPE(media) == IFM_100_T4) {
682 printf("100Mbps/T4, half-duplex\n");
683 bmcr |= PHY_BMCR_SPEEDSEL;
684 bmcr &= ~PHY_BMCR_DUPLEX;
685 }
686 if (IFM_SUBTYPE(media) == IFM_100_TX) {
687 printf("100Mbps, ");
688 bmcr |= PHY_BMCR_SPEEDSEL;
689 }
690 if (IFM_SUBTYPE(media) == IFM_10_T) {
691 printf("10Mbps, ");
692 bmcr &= ~PHY_BMCR_SPEEDSEL;
693 }
694 if ((media & IFM_GMASK) == IFM_FDX) {
695 printf("full duplex\n");
696 bmcr |= PHY_BMCR_DUPLEX;
697 } else {
698 printf("half duplex\n");
699 bmcr &= ~PHY_BMCR_DUPLEX;
700 }
701 my_phy_writereg(sc, PHY_BMCR, bmcr);
702 my_setcfg(sc, bmcr);
984263bc
MD
703}
704
705/*
706 * The Myson manual states that in order to fiddle with the 'full-duplex' and
707 * '100Mbps' bits in the netconfig register, we first have to put the
708 * transmit and/or receive logic in the idle state.
709 */
710static void
711my_setcfg(struct my_softc * sc, int bmcr)
712{
713 int i, restart = 0;
714
984263bc
MD
715 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
716 restart = 1;
717 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
718 for (i = 0; i < MY_TIMEOUT; i++) {
719 DELAY(10);
720 if (!(CSR_READ_4(sc, MY_TCRRCR) &
721 (MY_TXRUN | MY_RXRUN)))
722 break;
723 }
724 if (i == MY_TIMEOUT)
725 printf("my%d: failed to force tx and rx to idle \n",
726 sc->my_unit);
727 }
728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
730 if (bmcr & PHY_BMCR_1000)
731 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
732 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
733 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
734 if (bmcr & PHY_BMCR_DUPLEX)
735 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
736 else
737 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
738 if (restart)
739 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
984263bc
MD
740}
741
742static void
743my_reset(struct my_softc * sc)
744{
f96d6c88 745 int i;
984263bc 746
984263bc
MD
747 MY_SETBIT(sc, MY_BCR, MY_SWR);
748 for (i = 0; i < MY_TIMEOUT; i++) {
749 DELAY(10);
750 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
751 break;
752 }
753 if (i == MY_TIMEOUT)
754 printf("m0x%d: reset never completed!\n", sc->my_unit);
755
756 /* Wait a little while for the chip to get its brains in order. */
757 DELAY(1000);
984263bc
MD
758}
759
760/*
761 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
762 * list and return a device name if we find a match.
763 */
764static int
765my_probe(device_t dev)
766{
767 struct my_type *t;
c0f0a6cb
JS
768 uint16_t vendor, product;
769
770 vendor = pci_get_vendor(dev);
771 product = pci_get_device(dev);
984263bc 772
c0f0a6cb
JS
773 for (t = my_devs; t->my_name != NULL; t++) {
774 if (vendor == t->my_vid && product == t->my_did) {
984263bc 775 device_set_desc(dev, t->my_name);
984263bc
MD
776 return (0);
777 }
984263bc 778 }
c0f0a6cb 779
984263bc
MD
780 return (ENXIO);
781}
782
783/*
784 * Attach the interface. Allocate softc structures, do ifmedia setup and
785 * ethernet/BPF attach.
786 */
787static int
788my_attach(device_t dev)
789{
c0f0a6cb 790 int i;
984263bc
MD
791 u_char eaddr[ETHER_ADDR_LEN];
792 u_int32_t command, iobase;
793 struct my_softc *sc;
794 struct ifnet *ifp;
795 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
796 unsigned int round;
797 caddr_t roundptr;
798 struct my_type *p;
799 u_int16_t phy_vid, phy_did, phy_sts = 0;
800 int rid, unit, error = 0;
c0f0a6cb
JS
801 struct my_type *t;
802 uint16_t vendor, product;
984263bc 803
c0f0a6cb
JS
804 vendor = pci_get_vendor(dev);
805 product = pci_get_device(dev);
984263bc 806
c0f0a6cb
JS
807 for (t = my_devs; t->my_name != NULL; t++) {
808 if (vendor == t->my_vid && product == t->my_did)
809 break;
984263bc 810 }
c0f0a6cb
JS
811
812 if (t->my_name == NULL)
813 return(ENXIO);
814
815 sc = device_get_softc(dev);
816 unit = device_get_unit(dev);
984263bc
MD
817
818 /*
819 * Map control/status registers.
820 */
984263bc
MD
821 command = pci_read_config(dev, PCIR_COMMAND, 4);
822 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
823 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
824 command = pci_read_config(dev, PCIR_COMMAND, 4);
825
c0f0a6cb 826 if (t->my_did == MTD800ID) {
984263bc
MD
827 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
828 if (iobase & 0x300)
829 MY_USEIOSPACE = 0;
830 }
831 if (MY_USEIOSPACE) {
832 if (!(command & PCIM_CMD_PORTEN)) {
833 printf("my%d: failed to enable I/O ports!\n", unit);
984263bc 834 error = ENXIO;
c0f0a6cb 835 return(error);
984263bc 836 }
984263bc
MD
837 } else {
838 if (!(command & PCIM_CMD_MEMEN)) {
839 printf("my%d: failed to enable memory mapping!\n",
840 unit);
841 error = ENXIO;
c0f0a6cb 842 return(error);
984263bc 843 }
984263bc
MD
844 }
845
846 rid = MY_RID;
4e6d744d 847 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
984263bc
MD
848
849 if (sc->my_res == NULL) {
850 printf("my%d: couldn't map ports/memory\n", unit);
851 error = ENXIO;
852 goto fail;
853 }
854 sc->my_btag = rman_get_bustag(sc->my_res);
855 sc->my_bhandle = rman_get_bushandle(sc->my_res);
856
857 rid = 0;
4e6d744d
JS
858 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
859 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
860
861 if (sc->my_irq == NULL) {
862 printf("my%d: couldn't map interrupt\n", unit);
984263bc
MD
863 error = ENXIO;
864 goto fail;
865 }
984263bc 866
c0f0a6cb 867 sc->my_info = t;
984263bc
MD
868
869 /* Reset the adapter. */
870 my_reset(sc);
871
872 /*
873 * Get station address
874 */
875 for (i = 0; i < ETHER_ADDR_LEN; ++i)
876 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
877
984263bc 878 sc->my_unit = unit;
984263bc
MD
879
880 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
c5541aee 881 M_DEVBUF, M_WAITOK);
984263bc 882 if (sc->my_ldata_ptr == NULL) {
984263bc
MD
883 printf("my%d: no memory for list buffers!\n", unit);
884 error = ENXIO;
885 goto fail;
886 }
887 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
888 round = (unsigned int)sc->my_ldata_ptr & 0xF;
889 roundptr = sc->my_ldata_ptr;
890 for (i = 0; i < 8; i++) {
891 if (round % 8) {
892 round++;
893 roundptr++;
894 } else
895 break;
896 }
897 sc->my_ldata = (struct my_list_data *) roundptr;
898 bzero(sc->my_ldata, sizeof(struct my_list_data));
899
900 ifp = &sc->arpcom.ac_if;
901 ifp->if_softc = sc;
cdb7d804 902 if_initname(ifp, "my", unit);
984263bc
MD
903 ifp->if_mtu = ETHERMTU;
904 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
905 ifp->if_ioctl = my_ioctl;
984263bc
MD
906 ifp->if_start = my_start;
907 ifp->if_watchdog = my_watchdog;
908 ifp->if_init = my_init;
909 ifp->if_baudrate = 10000000;
d64721c9
JS
910 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
911 ifq_set_ready(&ifp->if_snd);
984263bc
MD
912
913 if (sc->my_info->my_did == MTD803ID)
914 sc->my_pinfo = my_phys;
915 else {
916 if (bootverbose)
917 printf("my%d: probing for a PHY\n", sc->my_unit);
918 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
919 if (bootverbose)
920 printf("my%d: checking address: %d\n",
921 sc->my_unit, i);
922 sc->my_phy_addr = i;
923 phy_sts = my_phy_readreg(sc, PHY_BMSR);
924 if ((phy_sts != 0) && (phy_sts != 0xffff))
925 break;
926 else
927 phy_sts = 0;
928 }
929 if (phy_sts) {
930 phy_vid = my_phy_readreg(sc, PHY_VENID);
931 phy_did = my_phy_readreg(sc, PHY_DEVID);
932 if (bootverbose) {
933 printf("my%d: found PHY at address %d, ",
934 sc->my_unit, sc->my_phy_addr);
935 printf("vendor id: %x device id: %x\n",
936 phy_vid, phy_did);
937 }
938 p = my_phys;
939 while (p->my_vid) {
940 if (phy_vid == p->my_vid) {
941 sc->my_pinfo = p;
942 break;
943 }
944 p++;
945 }
946 if (sc->my_pinfo == NULL)
947 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
948 if (bootverbose)
949 printf("my%d: PHY type: %s\n",
950 sc->my_unit, sc->my_pinfo->my_name);
951 } else {
952 printf("my%d: MII without any phy!\n", sc->my_unit);
953 error = ENXIO;
954 goto fail;
955 }
956 }
957
958 /* Do ifmedia setup. */
959 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
960 my_getmode_mii(sc);
961 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
962 media = sc->ifmedia.ifm_media;
963 my_stop(sc);
964 ifmedia_set(&sc->ifmedia, media);
965
78195a76 966 ether_ifattach(ifp, eaddr, NULL);
984263bc 967
78195a76
MD
968 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE,
969 my_intr, sc, &sc->my_intrhand,
970 ifp->if_serializer);
c0f0a6cb
JS
971 if (error) {
972 ether_ifdetach(ifp);
973 printf("my%d: couldn't set up irq\n", unit);
974 goto fail;
975 }
976
984263bc
MD
977 return (0);
978
979fail:
c0f0a6cb 980 my_detach(dev);
984263bc
MD
981 return (error);
982}
983
984static int
985my_detach(device_t dev)
986{
c0f0a6cb
JS
987 struct my_softc *sc = device_get_softc(dev);
988 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 989
78195a76 990 lwkt_serialize_enter(ifp->if_serializer);
c0f0a6cb
JS
991 if (device_is_attached(dev)) {
992 ether_ifdetach(ifp);
993 my_stop(sc);
994 }
984263bc 995
c0f0a6cb
JS
996 if (sc->my_intrhand)
997 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
998
78195a76 999 lwkt_serialize_exit(ifp->if_serializer);
c0f0a6cb
JS
1000
1001 if (sc->my_irq)
1002 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1003 if (sc->my_res)
1004 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
984263bc 1005
984263bc
MD
1006 return (0);
1007}
1008
1009
1010/*
1011 * Initialize the transmit descriptors.
1012 */
1013static int
1014my_list_tx_init(struct my_softc * sc)
1015{
1016 struct my_chain_data *cd;
1017 struct my_list_data *ld;
1018 int i;
1019
984263bc
MD
1020 cd = &sc->my_cdata;
1021 ld = sc->my_ldata;
1022 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1023 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1024 if (i == (MY_TX_LIST_CNT - 1))
1025 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1026 else
1027 cd->my_tx_chain[i].my_nextdesc =
1028 &cd->my_tx_chain[i + 1];
1029 }
1030 cd->my_tx_free = &cd->my_tx_chain[0];
1031 cd->my_tx_tail = cd->my_tx_head = NULL;
984263bc
MD
1032 return (0);
1033}
1034
1035/*
1036 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1037 * arrange the descriptors in a closed ring, so that the last descriptor
1038 * points back to the first.
1039 */
1040static int
1041my_list_rx_init(struct my_softc * sc)
1042{
1043 struct my_chain_data *cd;
1044 struct my_list_data *ld;
1045 int i;
1046
984263bc
MD
1047 cd = &sc->my_cdata;
1048 ld = sc->my_ldata;
1049 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1050 cd->my_rx_chain[i].my_ptr =
1051 (struct my_desc *) & ld->my_rx_list[i];
1052 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1053 return (ENOBUFS);
1054 if (i == (MY_RX_LIST_CNT - 1)) {
1055 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1056 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1057 } else {
1058 cd->my_rx_chain[i].my_nextdesc =
1059 &cd->my_rx_chain[i + 1];
1060 ld->my_rx_list[i].my_next =
1061 vtophys(&ld->my_rx_list[i + 1]);
1062 }
1063 }
1064 cd->my_rx_head = &cd->my_rx_chain[0];
984263bc
MD
1065 return (0);
1066}
1067
1068/*
1069 * Initialize an RX descriptor and attach an MBUF cluster.
1070 */
1071static int
1072my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1073{
1074 struct mbuf *m_new = NULL;
1075
74f1caca 1076 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1077 if (m_new == NULL) {
1078 printf("my%d: no memory for rx list -- packet dropped!\n",
1079 sc->my_unit);
1080 return (ENOBUFS);
1081 }
74f1caca 1082 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
1083 if (!(m_new->m_flags & M_EXT)) {
1084 printf("my%d: no memory for rx list -- packet dropped!\n",
1085 sc->my_unit);
1086 m_freem(m_new);
1087 return (ENOBUFS);
1088 }
1089 c->my_mbuf = m_new;
1090 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1091 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1092 c->my_ptr->my_status = MY_OWNByNIC;
984263bc
MD
1093 return (0);
1094}
1095
1096/*
1097 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1098 * level protocols.
1099 */
1100static void
1101my_rxeof(struct my_softc * sc)
1102{
c0f0a6cb
JS
1103 struct mbuf *m;
1104 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1105 struct my_chain_onefrag *cur_rx;
c0f0a6cb
JS
1106 int total_len = 0;
1107 u_int32_t rxstat;
984263bc 1108
984263bc
MD
1109 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1110 & MY_OWNByNIC)) {
1111 cur_rx = sc->my_cdata.my_rx_head;
1112 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1113
1114 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1115 ifp->if_ierrors++;
1116 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1117 continue;
1118 }
1119 /* No errors; receive the packet. */
1120 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1121 total_len -= ETHER_CRC_LEN;
1122
1123 if (total_len < MINCLSIZE) {
1124 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1125 total_len, 0, ifp, NULL);
1126 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1127 if (m == NULL) {
1128 ifp->if_ierrors++;
1129 continue;
1130 }
1131 } else {
1132 m = cur_rx->my_mbuf;
1133 /*
1134 * Try to conjure up a new mbuf cluster. If that
1135 * fails, it means we have an out of memory condition
1136 * and should leave the buffer in place and continue.
1137 * This will result in a lost packet, but there's
1138 * little else we can do in this situation.
1139 */
1140 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1141 ifp->if_ierrors++;
1142 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1143 continue;
1144 }
1145 m->m_pkthdr.rcvif = ifp;
1146 m->m_pkthdr.len = m->m_len = total_len;
1147 }
1148 ifp->if_ipackets++;
78195a76 1149 ifp->if_input(ifp, m);
984263bc 1150 }
984263bc
MD
1151}
1152
1153
1154/*
1155 * A frame was downloaded to the chip. It's safe for us to clean up the list
1156 * buffers.
1157 */
1158static void
1159my_txeof(struct my_softc * sc)
1160{
c0f0a6cb 1161 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1162 struct my_chain *cur_tx;
984263bc 1163
984263bc
MD
1164 /* Clear the timeout timer. */
1165 ifp->if_timer = 0;
1166 if (sc->my_cdata.my_tx_head == NULL)
1167 return;
1168 /*
1169 * Go through our tx list and free mbufs for those frames that have
1170 * been transmitted.
1171 */
1172 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1173 u_int32_t txstat;
1174
1175 cur_tx = sc->my_cdata.my_tx_head;
1176 txstat = MY_TXSTATUS(cur_tx);
1177 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1178 break;
1179 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1180 if (txstat & MY_TXERR) {
1181 ifp->if_oerrors++;
1182 if (txstat & MY_EC) /* excessive collision */
1183 ifp->if_collisions++;
1184 if (txstat & MY_LC) /* late collision */
1185 ifp->if_collisions++;
1186 }
1187 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1188 MY_NCRShift;
1189 }
1190 ifp->if_opackets++;
1191 m_freem(cur_tx->my_mbuf);
1192 cur_tx->my_mbuf = NULL;
1193 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1194 sc->my_cdata.my_tx_head = NULL;
1195 sc->my_cdata.my_tx_tail = NULL;
1196 break;
1197 }
1198 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1199 }
1200 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1201 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1202 }
984263bc
MD
1203}
1204
1205/*
1206 * TX 'end of channel' interrupt handler.
1207 */
1208static void
1209my_txeoc(struct my_softc * sc)
1210{
c0f0a6cb 1211 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1212
984263bc
MD
1213 ifp->if_timer = 0;
1214 if (sc->my_cdata.my_tx_head == NULL) {
1215 ifp->if_flags &= ~IFF_OACTIVE;
1216 sc->my_cdata.my_tx_tail = NULL;
1217 if (sc->my_want_auto)
1218 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1219 } else {
1220 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1221 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1222 ifp->if_timer = 5;
1223 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1224 }
1225 }
984263bc
MD
1226}
1227
1228static void
1229my_intr(void *arg)
1230{
c0f0a6cb
JS
1231 struct my_softc *sc = arg;
1232 struct ifnet *ifp = &sc->arpcom.ac_if;
1233 u_int32_t status;
984263bc 1234
c0f0a6cb 1235 if (!(ifp->if_flags & IFF_UP))
984263bc 1236 return;
c0f0a6cb 1237
984263bc
MD
1238 /* Disable interrupts. */
1239 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1240
1241 for (;;) {
1242 status = CSR_READ_4(sc, MY_ISR);
1243 status &= MY_INTRS;
1244 if (status)
1245 CSR_WRITE_4(sc, MY_ISR, status);
1246 else
1247 break;
1248
1249 if (status & MY_RI) /* receive interrupt */
1250 my_rxeof(sc);
1251
1252 if ((status & MY_RBU) || (status & MY_RxErr)) {
1253 /* rx buffer unavailable or rx error */
1254 ifp->if_ierrors++;
1255#ifdef foo
1256 my_stop(sc);
1257 my_reset(sc);
1258 my_init(sc);
1259#endif
1260 }
1261 if (status & MY_TI) /* tx interrupt */
1262 my_txeof(sc);
1263 if (status & MY_ETI) /* tx early interrupt */
1264 my_txeof(sc);
1265 if (status & MY_TBU) /* tx buffer unavailable */
1266 my_txeoc(sc);
1267
1268#if 0 /* 90/1/18 delete */
1269 if (status & MY_FBE) {
1270 my_reset(sc);
1271 my_init(sc);
1272 }
1273#endif
1274
1275 }
1276
1277 /* Re-enable interrupts. */
1278 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
d64721c9 1279 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1280 my_start(ifp);
984263bc
MD
1281}
1282
1283/*
1284 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1285 * pointers to the fragment pointers.
1286 */
1287static int
1288my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1289{
1290 struct my_desc *f = NULL;
1291 int total_len;
1292 struct mbuf *m, *m_new = NULL;
1293
984263bc
MD
1294 /* calculate the total tx pkt length */
1295 total_len = 0;
1296 for (m = m_head; m != NULL; m = m->m_next)
1297 total_len += m->m_len;
1298 /*
1299 * Start packing the mbufs in this chain into the fragment pointers.
1300 * Stop when we run out of fragments or hit the end of the mbuf
1301 * chain.
1302 */
1303 m = m_head;
74f1caca 1304 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1305 if (m_new == NULL) {
1306 printf("my%d: no memory for tx list", sc->my_unit);
1307 return (1);
1308 }
1309 if (m_head->m_pkthdr.len > MHLEN) {
74f1caca 1310 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
1311 if (!(m_new->m_flags & M_EXT)) {
1312 m_freem(m_new);
1313 printf("my%d: no memory for tx list", sc->my_unit);
1314 return (1);
1315 }
1316 }
1317 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1318 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1319 m_freem(m_head);
1320 m_head = m_new;
1321 f = &c->my_ptr->my_frag[0];
1322 f->my_status = 0;
1323 f->my_data = vtophys(mtod(m_new, caddr_t));
1324 total_len = m_new->m_len;
1325 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1326 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1327 f->my_ctl |= total_len; /* buffer size */
1328 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1329 if (sc->my_info->my_did == MTD891ID)
1330 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1331 c->my_mbuf = m_head;
1332 c->my_lastdesc = 0;
1333 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
984263bc
MD
1334 return (0);
1335}
1336
1337/*
1338 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1339 * to the mbuf data regions directly in the transmit lists. We also save a
1340 * copy of the pointers since the transmit list fragment pointers are
1341 * physical addresses.
1342 */
1343static void
1344my_start(struct ifnet * ifp)
1345{
c0f0a6cb 1346 struct my_softc *sc = ifp->if_softc;
984263bc
MD
1347 struct mbuf *m_head = NULL;
1348 struct my_chain *cur_tx = NULL, *start_tx;
1349
c0f0a6cb
JS
1350 crit_enter();
1351
984263bc
MD
1352 if (sc->my_autoneg) {
1353 sc->my_tx_pend = 1;
c0f0a6cb 1354 crit_exit();
984263bc
MD
1355 return;
1356 }
1357 /*
1358 * Check for an available queue slot. If there are none, punt.
1359 */
1360 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1361 ifp->if_flags |= IFF_OACTIVE;
c0f0a6cb 1362 crit_exit();
984263bc
MD
1363 return;
1364 }
c0f0a6cb 1365
984263bc
MD
1366 start_tx = sc->my_cdata.my_tx_free;
1367 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
d2c71fa0 1368 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1369 if (m_head == NULL)
1370 break;
1371
1372 /* Pick a descriptor off the free list. */
1373 cur_tx = sc->my_cdata.my_tx_free;
1374 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1375
1376 /* Pack the data into the descriptor. */
1377 my_encap(sc, cur_tx, m_head);
1378
1379 if (cur_tx != start_tx)
1380 MY_TXOWN(cur_tx) = MY_OWNByNIC;
ffaacc81 1381 BPF_MTAP(ifp, cur_tx->my_mbuf);
984263bc
MD
1382 }
1383 /*
1384 * If there are no packets queued, bail.
1385 */
1386 if (cur_tx == NULL) {
c0f0a6cb 1387 crit_exit();
984263bc
MD
1388 return;
1389 }
1390 /*
1391 * Place the request for the upload interrupt in the last descriptor
1392 * in the chain. This way, if we're chaining several packets at once,
1393 * we'll only get an interupt once for the whole chain rather than
1394 * once for each packet.
1395 */
1396 MY_TXCTL(cur_tx) |= MY_TXIC;
1397 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1398 sc->my_cdata.my_tx_tail = cur_tx;
1399 if (sc->my_cdata.my_tx_head == NULL)
1400 sc->my_cdata.my_tx_head = start_tx;
1401 MY_TXOWN(start_tx) = MY_OWNByNIC;
1402 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1403
1404 /*
1405 * Set a timeout in case the chip goes out to lunch.
1406 */
1407 ifp->if_timer = 5;
c0f0a6cb
JS
1408
1409 crit_exit();
984263bc
MD
1410}
1411
1412static void
1413my_init(void *xsc)
1414{
1415 struct my_softc *sc = xsc;
1416 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1417 u_int16_t phy_bmcr = 0;
1418
c0f0a6cb 1419 crit_enter();
984263bc 1420 if (sc->my_autoneg) {
c0f0a6cb 1421 crit_exit();
984263bc
MD
1422 return;
1423 }
984263bc
MD
1424 if (sc->my_pinfo != NULL)
1425 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1426 /*
1427 * Cancel pending I/O and free all RX/TX buffers.
1428 */
1429 my_stop(sc);
1430 my_reset(sc);
1431
1432 /*
1433 * Set cache alignment and burst length.
1434 */
1435#if 0 /* 89/9/1 modify, */
1436 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1437 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1438#endif
1439 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1440 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1441 /*
1442 * 89/12/29 add, for mtd891,
1443 */
1444 if (sc->my_info->my_did == MTD891ID) {
1445 MY_SETBIT(sc, MY_BCR, MY_PROG);
1446 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1447 }
1448 my_setcfg(sc, phy_bmcr);
1449 /* Init circular RX list. */
1450 if (my_list_rx_init(sc) == ENOBUFS) {
1451 printf("my%d: init failed: no memory for rx buffers\n",
1452 sc->my_unit);
1453 my_stop(sc);
c0f0a6cb 1454 crit_exit();
984263bc
MD
1455 return;
1456 }
1457 /* Init TX descriptors. */
1458 my_list_tx_init(sc);
1459
1460 /* If we want promiscuous mode, set the allframes bit. */
1461 if (ifp->if_flags & IFF_PROMISC)
1462 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1463 else
1464 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1465
1466 /*
1467 * Set capture broadcast bit to capture broadcast frames.
1468 */
1469 if (ifp->if_flags & IFF_BROADCAST)
1470 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1471 else
1472 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1473
1474 /*
1475 * Program the multicast filter, if necessary.
1476 */
1477 my_setmulti(sc);
1478
1479 /*
1480 * Load the address of the RX list.
1481 */
1482 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1483 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1484
1485 /*
1486 * Enable interrupts.
1487 */
1488 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1489 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1490
1491 /* Enable receiver and transmitter. */
1492 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1493 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1494 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1495 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1496
1497 /* Restore state of BMCR */
1498 if (sc->my_pinfo != NULL)
1499 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1500 ifp->if_flags |= IFF_RUNNING;
1501 ifp->if_flags &= ~IFF_OACTIVE;
c0f0a6cb 1502 crit_exit();
984263bc
MD
1503}
1504
1505/*
1506 * Set media options.
1507 */
1508
1509static int
1510my_ifmedia_upd(struct ifnet * ifp)
1511{
c0f0a6cb
JS
1512 struct my_softc *sc = ifp->if_softc;
1513 struct ifmedia *ifm = &sc->ifmedia;
984263bc 1514
c0f0a6cb 1515 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
984263bc 1516 return (EINVAL);
c0f0a6cb
JS
1517
1518 crit_enter();
1519
984263bc
MD
1520 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1521 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1522 else
1523 my_setmode_mii(sc, ifm->ifm_media);
c0f0a6cb
JS
1524
1525 crit_exit();
1526
984263bc
MD
1527 return (0);
1528}
1529
1530/*
1531 * Report current media status.
1532 */
1533
1534static void
1535my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1536{
c0f0a6cb 1537 struct my_softc *sc = ifp->if_softc;
984263bc
MD
1538 u_int16_t advert = 0, ability = 0;
1539
c0f0a6cb
JS
1540 crit_enter();
1541
984263bc
MD
1542 ifmr->ifm_active = IFM_ETHER;
1543 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1544#if 0 /* this version did not support 1000M, */
1545 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1546 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1547#endif
1548 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1549 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1550 else
1551 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1552 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1553 ifmr->ifm_active |= IFM_FDX;
1554 else
1555 ifmr->ifm_active |= IFM_HDX;
1556
c0f0a6cb
JS
1557 crit_exit();
1558
984263bc
MD
1559 return;
1560 }
1561 ability = my_phy_readreg(sc, PHY_LPAR);
1562 advert = my_phy_readreg(sc, PHY_ANAR);
1563
1564#if 0 /* this version did not support 1000M, */
1565 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1566 ability2 = my_phy_readreg(sc, PHY_1000SR);
1567 if (ability2 & PHY_1000SR_1000BTXFULL) {
1568 advert = 0;
1569 ability = 0;
7f259627 1570 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX;
984263bc
MD
1571 } else if (ability & PHY_1000SR_1000BTXHALF) {
1572 advert = 0;
1573 ability = 0;
7f259627 1574 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX;
984263bc
MD
1575 }
1576 }
1577#endif
1578 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1579 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1580 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1581 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1582 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1583 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1584 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1585 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1586 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1587 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
c0f0a6cb
JS
1588
1589 crit_exit();
984263bc
MD
1590}
1591
1592static int
bd4539cc 1593my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
1594{
1595 struct my_softc *sc = ifp->if_softc;
1596 struct ifreq *ifr = (struct ifreq *) data;
c0f0a6cb 1597 int error = 0;
984263bc 1598
c0f0a6cb 1599 crit_enter();
984263bc 1600 switch (command) {
984263bc
MD
1601 case SIOCSIFFLAGS:
1602 if (ifp->if_flags & IFF_UP)
1603 my_init(sc);
1604 else if (ifp->if_flags & IFF_RUNNING)
1605 my_stop(sc);
1606 error = 0;
1607 break;
1608 case SIOCADDMULTI:
1609 case SIOCDELMULTI:
1610 my_setmulti(sc);
1611 error = 0;
1612 break;
1613 case SIOCGIFMEDIA:
1614 case SIOCSIFMEDIA:
1615 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1616 break;
1617 default:
4cde4dd5 1618 error = ether_ioctl(ifp, command, data);
984263bc
MD
1619 break;
1620 }
c0f0a6cb
JS
1621
1622 crit_exit();
984263bc
MD
1623 return (error);
1624}
1625
1626static void
1627my_watchdog(struct ifnet * ifp)
1628{
c0f0a6cb
JS
1629 struct my_softc *sc = ifp->if_softc;
1630
1631 crit_enter();
984263bc 1632
984263bc
MD
1633 if (sc->my_autoneg) {
1634 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
c0f0a6cb 1635 crit_exit();
984263bc
MD
1636 return;
1637 }
1638 ifp->if_oerrors++;
1639 printf("my%d: watchdog timeout\n", sc->my_unit);
1640 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1641 printf("my%d: no carrier - transceiver cable problem?\n",
1642 sc->my_unit);
1643 my_stop(sc);
1644 my_reset(sc);
1645 my_init(sc);
d64721c9 1646 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1647 my_start(ifp);
c0f0a6cb 1648 crit_exit();
984263bc
MD
1649}
1650
1651
1652/*
1653 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1654 */
1655static void
1656my_stop(struct my_softc * sc)
1657{
c0f0a6cb 1658 struct ifnet *ifp = &sc->arpcom.ac_if;
f96d6c88 1659 int i;
984263bc 1660
984263bc
MD
1661 ifp->if_timer = 0;
1662
1663 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1664 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1665 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1666 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1667
1668 /*
1669 * Free data in the RX lists.
1670 */
1671 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1672 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1673 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1674 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1675 }
1676 }
1677 bzero((char *)&sc->my_ldata->my_rx_list,
1678 sizeof(sc->my_ldata->my_rx_list));
1679 /*
1680 * Free the TX list buffers.
1681 */
1682 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1683 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1684 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1685 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1686 }
1687 }
1688 bzero((char *)&sc->my_ldata->my_tx_list,
1689 sizeof(sc->my_ldata->my_tx_list));
1690 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1691}
1692
1693/*
1694 * Stop all chip I/O so that the kernel's probe routines don't get confused
1695 * by errant DMAs when rebooting.
1696 */
1697static void
1698my_shutdown(device_t dev)
1699{
1700 struct my_softc *sc;
1701
1702 sc = device_get_softc(dev);
1703 my_stop(sc);
1704 return;
1705}