Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / nge / if_nge.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
78195a76 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.34 2005/11/28 17:13:43 dillon Exp $
984263bc
MD
35 */
36
37/*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60/*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
2b71c8f1
SZ
91#include "opt_polling.h"
92
984263bc
MD
93#include <sys/param.h>
94#include <sys/systm.h>
95#include <sys/sockio.h>
96#include <sys/mbuf.h>
97#include <sys/malloc.h>
98#include <sys/kernel.h>
99#include <sys/socket.h>
78195a76
MD
100#include <sys/serialize.h>
101
88e7510c 102#include <sys/thread2.h>
984263bc
MD
103
104#include <net/if.h>
0b193118 105#include <net/ifq_var.h>
984263bc
MD
106#include <net/if_arp.h>
107#include <net/ethernet.h>
108#include <net/if_dl.h>
109#include <net/if_media.h>
110#include <net/if_types.h>
1f2de5d4 111#include <net/vlan/if_vlan_var.h>
984263bc
MD
112
113#include <net/bpf.h>
114
115#include <vm/vm.h> /* for vtophys */
116#include <vm/pmap.h> /* for vtophys */
984263bc
MD
117#include <machine/bus.h>
118#include <machine/resource.h>
119#include <sys/bus.h>
120#include <sys/rman.h>
121
22bf5b21
JS
122#include <dev/netif/mii_layer/mii.h>
123#include <dev/netif/mii_layer/miivar.h>
984263bc 124
1f2de5d4
MD
125#include <bus/pci/pcireg.h>
126#include <bus/pci/pcivar.h>
984263bc
MD
127
128#define NGE_USEIOSPACE
129
1f2de5d4 130#include "if_ngereg.h"
984263bc 131
984263bc
MD
132
133/* "controller miibus0" required. See GENERIC if you get errors here. */
134#include "miibus_if.h"
135
984263bc
MD
136#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138/*
139 * Various supported device vendors/types and their names.
140 */
141static struct nge_type nge_devs[] = {
142 { NGE_VENDORID, NGE_DEVICEID,
143 "National Semiconductor Gigabit Ethernet" },
144 { 0, 0, NULL }
145};
146
22bf5b21
JS
147static int nge_probe(device_t);
148static int nge_attach(device_t);
149static int nge_detach(device_t);
984263bc 150
22bf5b21 151static int nge_alloc_jumbo_mem(struct nge_softc *);
368e791d
JS
152static struct nge_jslot
153 *nge_jalloc(struct nge_softc *);
154static void nge_jfree(void *);
155static void nge_jref(void *);
156
157static int nge_newbuf(struct nge_softc *, struct nge_desc *,
158 struct mbuf *);
159static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
22bf5b21
JS
160static void nge_rxeof(struct nge_softc *);
161static void nge_txeof(struct nge_softc *);
162static void nge_intr(void *);
163static void nge_tick(void *);
164static void nge_start(struct ifnet *);
368e791d 165static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
22bf5b21
JS
166static void nge_init(void *);
167static void nge_stop(struct nge_softc *);
168static void nge_watchdog(struct ifnet *);
169static void nge_shutdown(device_t);
170static int nge_ifmedia_upd(struct ifnet *);
171static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
172
173static void nge_delay(struct nge_softc *);
174static void nge_eeprom_idle(struct nge_softc *);
175static void nge_eeprom_putbyte(struct nge_softc *, int);
176static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
177static void nge_read_eeprom(struct nge_softc *, void *, int, int);
178
179static void nge_mii_sync(struct nge_softc *);
180static void nge_mii_send(struct nge_softc *, uint32_t, int);
181static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
182static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
183
184static int nge_miibus_readreg(device_t, int, int);
185static int nge_miibus_writereg(device_t, int, int, int);
186static void nge_miibus_statchg(device_t);
187
188static void nge_setmulti(struct nge_softc *);
22bf5b21
JS
189static void nge_reset(struct nge_softc *);
190static int nge_list_rx_init(struct nge_softc *);
191static int nge_list_tx_init(struct nge_softc *);
9c095379
MD
192#ifdef DEVICE_POLLING
193static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
194#endif
984263bc
MD
195
196#ifdef NGE_USEIOSPACE
197#define NGE_RES SYS_RES_IOPORT
198#define NGE_RID NGE_PCI_LOIO
199#else
200#define NGE_RES SYS_RES_MEMORY
201#define NGE_RID NGE_PCI_LOMEM
202#endif
203
204static device_method_t nge_methods[] = {
205 /* Device interface */
206 DEVMETHOD(device_probe, nge_probe),
207 DEVMETHOD(device_attach, nge_attach),
208 DEVMETHOD(device_detach, nge_detach),
209 DEVMETHOD(device_shutdown, nge_shutdown),
210
211 /* bus interface */
212 DEVMETHOD(bus_print_child, bus_generic_print_child),
213 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
214
215 /* MII interface */
216 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
217 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
218 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
219
220 { 0, 0 }
221};
222
22bf5b21 223static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
984263bc
MD
224static devclass_t nge_devclass;
225
32832096
MD
226DECLARE_DUMMY_MODULE(if_nge);
227MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
984263bc
MD
228DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
229DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
230
231#define NGE_SETBIT(sc, reg, x) \
22bf5b21 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
984263bc
MD
233
234#define NGE_CLRBIT(sc, reg, x) \
22bf5b21 235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
984263bc
MD
236
237#define SIO_SET(x) \
22bf5b21 238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
984263bc
MD
239
240#define SIO_CLR(x) \
22bf5b21 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
984263bc 242
22bf5b21
JS
243static void
244nge_delay(struct nge_softc *sc)
984263bc 245{
22bf5b21 246 int idx;
984263bc
MD
247
248 for (idx = (300 / 33) + 1; idx > 0; idx--)
249 CSR_READ_4(sc, NGE_CSR);
984263bc
MD
250}
251
22bf5b21
JS
252static void
253nge_eeprom_idle(struct nge_softc *sc)
984263bc 254{
22bf5b21 255 int i;
984263bc
MD
256
257 SIO_SET(NGE_MEAR_EE_CSEL);
258 nge_delay(sc);
259 SIO_SET(NGE_MEAR_EE_CLK);
260 nge_delay(sc);
261
262 for (i = 0; i < 25; i++) {
263 SIO_CLR(NGE_MEAR_EE_CLK);
264 nge_delay(sc);
265 SIO_SET(NGE_MEAR_EE_CLK);
266 nge_delay(sc);
267 }
268
269 SIO_CLR(NGE_MEAR_EE_CLK);
270 nge_delay(sc);
271 SIO_CLR(NGE_MEAR_EE_CSEL);
272 nge_delay(sc);
273 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
984263bc
MD
274}
275
276/*
277 * Send a read command and address to the EEPROM, check for ACK.
278 */
22bf5b21
JS
279static void
280nge_eeprom_putbyte(struct nge_softc *sc, int addr)
984263bc 281{
22bf5b21 282 int d, i;
984263bc
MD
283
284 d = addr | NGE_EECMD_READ;
285
286 /*
287 * Feed in each bit and stobe the clock.
288 */
289 for (i = 0x400; i; i >>= 1) {
22bf5b21 290 if (d & i)
984263bc 291 SIO_SET(NGE_MEAR_EE_DIN);
22bf5b21 292 else
984263bc 293 SIO_CLR(NGE_MEAR_EE_DIN);
984263bc
MD
294 nge_delay(sc);
295 SIO_SET(NGE_MEAR_EE_CLK);
296 nge_delay(sc);
297 SIO_CLR(NGE_MEAR_EE_CLK);
298 nge_delay(sc);
299 }
984263bc
MD
300}
301
302/*
303 * Read a word of data stored in the EEPROM at address 'addr.'
304 */
22bf5b21
JS
305static void
306nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
984263bc 307{
22bf5b21
JS
308 int i;
309 uint16_t word = 0;
984263bc
MD
310
311 /* Force EEPROM to idle state. */
312 nge_eeprom_idle(sc);
313
314 /* Enter EEPROM access mode. */
315 nge_delay(sc);
316 SIO_CLR(NGE_MEAR_EE_CLK);
317 nge_delay(sc);
318 SIO_SET(NGE_MEAR_EE_CSEL);
319 nge_delay(sc);
320
321 /*
322 * Send address of word we want to read.
323 */
324 nge_eeprom_putbyte(sc, addr);
325
326 /*
327 * Start reading bits from EEPROM.
328 */
329 for (i = 0x8000; i; i >>= 1) {
330 SIO_SET(NGE_MEAR_EE_CLK);
331 nge_delay(sc);
332 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
333 word |= i;
334 nge_delay(sc);
335 SIO_CLR(NGE_MEAR_EE_CLK);
336 nge_delay(sc);
337 }
338
339 /* Turn off EEPROM access mode. */
340 nge_eeprom_idle(sc);
341
342 *dest = word;
984263bc
MD
343}
344
345/*
346 * Read a sequence of words from the EEPROM.
347 */
22bf5b21
JS
348static void
349nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
984263bc 350{
22bf5b21
JS
351 int i;
352 uint16_t word = 0, *ptr;
984263bc
MD
353
354 for (i = 0; i < cnt; i++) {
355 nge_eeprom_getword(sc, off + i, &word);
22bf5b21
JS
356 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
357 *ptr = word;
984263bc 358 }
984263bc
MD
359}
360
361/*
362 * Sync the PHYs by setting data bit and strobing the clock 32 times.
363 */
22bf5b21
JS
364static void
365nge_mii_sync(struct nge_softc *sc)
984263bc 366{
22bf5b21 367 int i;
984263bc 368
22bf5b21 369 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
984263bc
MD
370
371 for (i = 0; i < 32; i++) {
372 SIO_SET(NGE_MEAR_MII_CLK);
373 DELAY(1);
374 SIO_CLR(NGE_MEAR_MII_CLK);
375 DELAY(1);
376 }
984263bc
MD
377}
378
379/*
380 * Clock a series of bits through the MII.
381 */
22bf5b21
JS
382static void
383nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
984263bc 384{
22bf5b21 385 int i;
984263bc
MD
386
387 SIO_CLR(NGE_MEAR_MII_CLK);
388
389 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
22bf5b21 390 if (bits & i)
984263bc 391 SIO_SET(NGE_MEAR_MII_DATA);
22bf5b21 392 else
984263bc 393 SIO_CLR(NGE_MEAR_MII_DATA);
984263bc
MD
394 DELAY(1);
395 SIO_CLR(NGE_MEAR_MII_CLK);
396 DELAY(1);
397 SIO_SET(NGE_MEAR_MII_CLK);
398 }
399}
400
401/*
402 * Read an PHY register through the MII.
403 */
22bf5b21
JS
404static int
405nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 406{
88e7510c 407 int ack, i;
984263bc 408
984263bc
MD
409 /*
410 * Set up frame for RX.
411 */
412 frame->mii_stdelim = NGE_MII_STARTDELIM;
413 frame->mii_opcode = NGE_MII_READOP;
414 frame->mii_turnaround = 0;
415 frame->mii_data = 0;
22bf5b21 416
984263bc
MD
417 CSR_WRITE_4(sc, NGE_MEAR, 0);
418
419 /*
420 * Turn on data xmit.
421 */
422 SIO_SET(NGE_MEAR_MII_DIR);
423
424 nge_mii_sync(sc);
425
426 /*
427 * Send command/address info.
428 */
429 nge_mii_send(sc, frame->mii_stdelim, 2);
430 nge_mii_send(sc, frame->mii_opcode, 2);
431 nge_mii_send(sc, frame->mii_phyaddr, 5);
432 nge_mii_send(sc, frame->mii_regaddr, 5);
433
434 /* Idle bit */
22bf5b21 435 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
984263bc
MD
436 DELAY(1);
437 SIO_SET(NGE_MEAR_MII_CLK);
438 DELAY(1);
439
440 /* Turn off xmit. */
441 SIO_CLR(NGE_MEAR_MII_DIR);
442 /* Check for ack */
443 SIO_CLR(NGE_MEAR_MII_CLK);
444 DELAY(1);
445 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
446 SIO_SET(NGE_MEAR_MII_CLK);
447 DELAY(1);
448
449 /*
450 * Now try reading data bits. If the ack failed, we still
451 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 */
453 if (ack) {
454 for(i = 0; i < 16; i++) {
455 SIO_CLR(NGE_MEAR_MII_CLK);
456 DELAY(1);
457 SIO_SET(NGE_MEAR_MII_CLK);
458 DELAY(1);
459 }
460 goto fail;
461 }
462
463 for (i = 0x8000; i; i >>= 1) {
464 SIO_CLR(NGE_MEAR_MII_CLK);
465 DELAY(1);
466 if (!ack) {
467 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
468 frame->mii_data |= i;
469 DELAY(1);
470 }
471 SIO_SET(NGE_MEAR_MII_CLK);
472 DELAY(1);
473 }
474
475fail:
984263bc
MD
476 SIO_CLR(NGE_MEAR_MII_CLK);
477 DELAY(1);
478 SIO_SET(NGE_MEAR_MII_CLK);
479 DELAY(1);
480
984263bc
MD
481 if (ack)
482 return(1);
483 return(0);
484}
485
486/*
487 * Write to a PHY register through the MII.
488 */
22bf5b21
JS
489static int
490nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 491{
984263bc
MD
492 /*
493 * Set up frame for TX.
494 */
495
496 frame->mii_stdelim = NGE_MII_STARTDELIM;
497 frame->mii_opcode = NGE_MII_WRITEOP;
498 frame->mii_turnaround = NGE_MII_TURNAROUND;
499
500 /*
501 * Turn on data output.
502 */
503 SIO_SET(NGE_MEAR_MII_DIR);
504
505 nge_mii_sync(sc);
506
507 nge_mii_send(sc, frame->mii_stdelim, 2);
508 nge_mii_send(sc, frame->mii_opcode, 2);
509 nge_mii_send(sc, frame->mii_phyaddr, 5);
510 nge_mii_send(sc, frame->mii_regaddr, 5);
511 nge_mii_send(sc, frame->mii_turnaround, 2);
512 nge_mii_send(sc, frame->mii_data, 16);
513
514 /* Idle bit. */
515 SIO_SET(NGE_MEAR_MII_CLK);
516 DELAY(1);
517 SIO_CLR(NGE_MEAR_MII_CLK);
518 DELAY(1);
519
520 /*
521 * Turn off xmit.
522 */
523 SIO_CLR(NGE_MEAR_MII_DIR);
524
984263bc
MD
525 return(0);
526}
527
22bf5b21
JS
528static int
529nge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 530{
22bf5b21
JS
531 struct nge_softc *sc = device_get_softc(dev);
532 struct nge_mii_frame frame;
984263bc
MD
533
534 bzero((char *)&frame, sizeof(frame));
535
536 frame.mii_phyaddr = phy;
537 frame.mii_regaddr = reg;
538 nge_mii_readreg(sc, &frame);
539
540 return(frame.mii_data);
541}
542
22bf5b21
JS
543static int
544nge_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 545{
22bf5b21
JS
546 struct nge_softc *sc = device_get_softc(dev);
547 struct nge_mii_frame frame;
984263bc
MD
548
549 bzero((char *)&frame, sizeof(frame));
550
551 frame.mii_phyaddr = phy;
552 frame.mii_regaddr = reg;
553 frame.mii_data = data;
554 nge_mii_writereg(sc, &frame);
555
556 return(0);
557}
558
22bf5b21
JS
559static void
560nge_miibus_statchg(device_t dev)
984263bc 561{
22bf5b21
JS
562 struct nge_softc *sc = device_get_softc(dev);
563 struct mii_data *mii;
564 int status;
984263bc 565
984263bc
MD
566 if (sc->nge_tbi) {
567 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
568 == IFM_AUTO) {
569 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
570 if (status == 0 || status & NGE_TBIANAR_FDX) {
571 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
574 } else {
575 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 576 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
577 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
578 }
984263bc
MD
579 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
580 != IFM_FDX) {
581 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 582 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
583 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 } else {
585 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 586 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
587 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
588 }
589 } else {
590 mii = device_get_softc(sc->nge_miibus);
591
592 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
593 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 594 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
595 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
596 } else {
597 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 598 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
599 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
600 }
601
602 /* If we have a 1000Mbps link, set the mode_1000 bit. */
7f259627 603 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
984263bc
MD
604 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
605 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
606 } else {
607 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
608 }
609 }
984263bc
MD
610}
611
22bf5b21
JS
612static void
613nge_setmulti(struct nge_softc *sc)
984263bc 614{
22bf5b21
JS
615 struct ifnet *ifp = &sc->arpcom.ac_if;
616 struct ifmultiaddr *ifma;
617 uint32_t filtsave, h = 0, i;
618 int bit, index;
984263bc
MD
619
620 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
621 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 622 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
984263bc
MD
623 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
624 return;
625 }
626
627 /*
628 * We have to explicitly enable the multicast hash table
629 * on the NatSemi chip if we want to use it, which we do.
630 * We also have to tell it that we don't want to use the
631 * hash table for matching unicast addresses.
632 */
633 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
634 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 635 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
984263bc
MD
636
637 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
638
639 /* first, zot all the existing hash bits */
640 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
641 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
642 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
643 }
644
645 /*
646 * From the 11 bits returned by the crc routine, the top 7
647 * bits represent the 16-bit word in the mcast hash table
648 * that needs to be updated, and the lower 4 bits represent
649 * which bit within that byte needs to be set.
650 */
651 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
652 if (ifma->ifma_addr->sa_family != AF_LINK)
653 continue;
4c6f5f4c
JS
654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
984263bc
MD
656 index = (h >> 4) & 0x7F;
657 bit = h & 0xF;
658 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
659 NGE_FILTADDR_MCAST_LO + (index * 2));
660 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
661 }
662
663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
984263bc
MD
664}
665
22bf5b21
JS
666static void
667nge_reset(struct nge_softc *sc)
984263bc 668{
22bf5b21 669 int i;
984263bc
MD
670
671 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
672
673 for (i = 0; i < NGE_TIMEOUT; i++) {
22bf5b21 674 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
984263bc
MD
675 break;
676 }
677
678 if (i == NGE_TIMEOUT)
679 printf("nge%d: reset never completed\n", sc->nge_unit);
680
681 /* Wait a little while for the chip to get its brains in order. */
682 DELAY(1000);
683
684 /*
685 * If this is a NetSemi chip, make sure to clear
686 * PME mode.
687 */
688 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
689 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
984263bc
MD
690}
691
692/*
693 * Probe for an NatSemi chip. Check the PCI vendor and device
694 * IDs against our list and return a device name if we find a match.
695 */
22bf5b21
JS
696static int
697nge_probe(device_t dev)
984263bc 698{
22bf5b21
JS
699 struct nge_type *t;
700 uint16_t vendor, product;
984263bc 701
22bf5b21
JS
702 vendor = pci_get_vendor(dev);
703 product = pci_get_device(dev);
984263bc 704
22bf5b21
JS
705 for (t = nge_devs; t->nge_name != NULL; t++) {
706 if (vendor == t->nge_vid && product == t->nge_did) {
984263bc
MD
707 device_set_desc(dev, t->nge_name);
708 return(0);
709 }
984263bc
MD
710 }
711
712 return(ENXIO);
713}
714
715/*
716 * Attach the interface. Allocate softc structures, do ifmedia
717 * setup and ethernet/BPF attach.
718 */
22bf5b21
JS
719static int
720nge_attach(device_t dev)
984263bc 721{
22bf5b21
JS
722 struct nge_softc *sc;
723 struct ifnet *ifp;
724 uint8_t eaddr[ETHER_ADDR_LEN];
725 uint32_t command;
88e7510c 726 int error = 0, rid, unit;
984263bc
MD
727 const char *sep = "";
728
984263bc
MD
729 sc = device_get_softc(dev);
730 unit = device_get_unit(dev);
43c4cb7e 731 callout_init(&sc->nge_stat_timer);
984263bc
MD
732
733 /*
734 * Handle power management nonsense.
735 */
984263bc
MD
736 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
737 if (command == 0x01) {
984263bc
MD
738 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
739 if (command & NGE_PSTATE_MASK) {
22bf5b21 740 uint32_t iobase, membase, irq;
984263bc
MD
741
742 /* Save important PCI config data. */
743 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
744 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
745 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
746
747 /* Reset the power state. */
748 printf("nge%d: chip is in D%d power mode "
749 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
750 command &= 0xFFFFFFFC;
751 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
752
753 /* Restore PCI config data. */
754 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
755 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
756 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
757 }
758 }
759
760 /*
761 * Map control/status registers.
762 */
763 command = pci_read_config(dev, PCIR_COMMAND, 4);
764 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
765 pci_write_config(dev, PCIR_COMMAND, command, 4);
766 command = pci_read_config(dev, PCIR_COMMAND, 4);
767
768#ifdef NGE_USEIOSPACE
769 if (!(command & PCIM_CMD_PORTEN)) {
770 printf("nge%d: failed to enable I/O ports!\n", unit);
88e7510c
JS
771 error = ENXIO;
772 return(error);
984263bc
MD
773 }
774#else
775 if (!(command & PCIM_CMD_MEMEN)) {
776 printf("nge%d: failed to enable memory mapping!\n", unit);
88e7510c
JS
777 error = ENXIO;
778 return(error);
984263bc
MD
779 }
780#endif
781
782 rid = NGE_RID;
4e6d744d 783 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
984263bc
MD
784
785 if (sc->nge_res == NULL) {
786 printf("nge%d: couldn't map ports/memory\n", unit);
787 error = ENXIO;
88e7510c 788 return(error);
984263bc
MD
789 }
790
791 sc->nge_btag = rman_get_bustag(sc->nge_res);
792 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
793
794 /* Allocate interrupt */
795 rid = 0;
4e6d744d 796 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
797 RF_SHAREABLE | RF_ACTIVE);
798
799 if (sc->nge_irq == NULL) {
800 printf("nge%d: couldn't map interrupt\n", unit);
984263bc
MD
801 error = ENXIO;
802 goto fail;
803 }
804
984263bc
MD
805 /* Reset the adapter. */
806 nge_reset(sc);
807
808 /*
809 * Get station address from the EEPROM.
810 */
22bf5b21
JS
811 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
812 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
813 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
984263bc 814
984263bc 815 sc->nge_unit = unit;
984263bc
MD
816
817 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
56ae9d75 818 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
819
820 if (sc->nge_ldata == NULL) {
821 printf("nge%d: no memory for list buffers!\n", unit);
984263bc
MD
822 error = ENXIO;
823 goto fail;
824 }
825 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
826
827 /* Try to allocate memory for jumbo buffers. */
828 if (nge_alloc_jumbo_mem(sc)) {
829 printf("nge%d: jumbo buffer allocation failed\n",
830 sc->nge_unit);
984263bc
MD
831 error = ENXIO;
832 goto fail;
833 }
834
835 ifp = &sc->arpcom.ac_if;
836 ifp->if_softc = sc;
cdb7d804 837 if_initname(ifp, "nge", unit);
984263bc
MD
838 ifp->if_mtu = ETHERMTU;
839 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
840 ifp->if_ioctl = nge_ioctl;
984263bc 841 ifp->if_start = nge_start;
9c095379
MD
842#ifdef DEVICE_POLLING
843 ifp->if_poll = nge_poll;
844#endif
984263bc
MD
845 ifp->if_watchdog = nge_watchdog;
846 ifp->if_init = nge_init;
847 ifp->if_baudrate = 1000000000;
0b193118
JS
848 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
849 ifq_set_ready(&ifp->if_snd);
984263bc
MD
850 ifp->if_hwassist = NGE_CSUM_FEATURES;
851 ifp->if_capabilities = IFCAP_HWCSUM;
852 ifp->if_capenable = ifp->if_capabilities;
853
854 /*
855 * Do MII setup.
856 */
857 if (mii_phy_probe(dev, &sc->nge_miibus,
858 nge_ifmedia_upd, nge_ifmedia_sts)) {
859 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
860 sc->nge_tbi = 1;
861 device_printf(dev, "Using TBI\n");
862
863 sc->nge_miibus = dev;
864
865 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
866 nge_ifmedia_sts);
867#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
868#define PRINT(s) printf("%s%s", sep, s); sep = ", "
869 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
870 device_printf(dev, " ");
871 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
872 PRINT("1000baseSX");
873 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
874 PRINT("1000baseSX-FDX");
875 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
876 PRINT("auto");
877
878 printf("\n");
879#undef ADD
880#undef PRINT
881 ifmedia_set(&sc->nge_ifmedia,
882 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
883
884 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
885 | NGE_GPIO_GP4_OUT
886 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
887 | NGE_GPIO_GP3_OUTENB
888 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
889
890 } else {
891 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
984263bc
MD
892 error = ENXIO;
893 goto fail;
894 }
895 }
896
897 /*
898 * Call MI attach routine.
899 */
78195a76 900 ether_ifattach(ifp, eaddr, NULL);
984263bc 901
78195a76
MD
902 error = bus_setup_intr(dev, sc->nge_irq, INTR_NETSAFE,
903 nge_intr, sc, &sc->nge_intrhand,
904 ifp->if_serializer);
88e7510c
JS
905 if (error) {
906 ether_ifdetach(ifp);
907 device_printf(dev, "couldn't set up irq\n");
908 goto fail;
909 }
984263bc 910
88e7510c
JS
911 return(0);
912fail:
913 nge_detach(dev);
984263bc
MD
914 return(error);
915}
916
22bf5b21
JS
917static int
918nge_detach(device_t dev)
984263bc 919{
88e7510c
JS
920 struct nge_softc *sc = device_get_softc(dev);
921 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 922
78195a76 923 lwkt_serialize_enter(ifp->if_serializer);
984263bc 924
88e7510c
JS
925 if (device_is_attached(dev)) {
926 nge_reset(sc);
927 nge_stop(sc);
928 ether_ifdetach(ifp);
929 }
984263bc 930
88e7510c 931 if (sc->nge_miibus)
984263bc 932 device_delete_child(dev, sc->nge_miibus);
88e7510c 933 bus_generic_detach(dev);
22bf5b21 934
88e7510c
JS
935 if (sc->nge_intrhand)
936 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
984263bc 937
88e7510c
JS
938 if (sc->nge_irq)
939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
940 if (sc->nge_res)
941 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
942 if (sc->nge_ldata) {
943 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
944 M_DEVBUF);
945 }
946 if (sc->nge_cdata.nge_jumbo_buf)
947 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
984263bc 948
78195a76 949 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
950 return(0);
951}
952
953/*
954 * Initialize the transmit descriptors.
955 */
22bf5b21
JS
956static int
957nge_list_tx_init(struct nge_softc *sc)
984263bc 958{
22bf5b21
JS
959 struct nge_list_data *ld;
960 struct nge_ring_data *cd;
961 int i;
984263bc
MD
962
963 cd = &sc->nge_cdata;
964 ld = sc->nge_ldata;
965
966 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
967 if (i == (NGE_TX_LIST_CNT - 1)) {
968 ld->nge_tx_list[i].nge_nextdesc =
969 &ld->nge_tx_list[0];
970 ld->nge_tx_list[i].nge_next =
971 vtophys(&ld->nge_tx_list[0]);
972 } else {
973 ld->nge_tx_list[i].nge_nextdesc =
974 &ld->nge_tx_list[i + 1];
975 ld->nge_tx_list[i].nge_next =
976 vtophys(&ld->nge_tx_list[i + 1]);
977 }
978 ld->nge_tx_list[i].nge_mbuf = NULL;
979 ld->nge_tx_list[i].nge_ptr = 0;
980 ld->nge_tx_list[i].nge_ctl = 0;
981 }
982
983 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
984
985 return(0);
986}
987
988
989/*
990 * Initialize the RX descriptors and allocate mbufs for them. Note that
991 * we arrange the descriptors in a closed ring, so that the last descriptor
992 * points back to the first.
993 */
22bf5b21
JS
994static int
995nge_list_rx_init(struct nge_softc *sc)
984263bc 996{
22bf5b21
JS
997 struct nge_list_data *ld;
998 struct nge_ring_data *cd;
999 int i;
984263bc
MD
1000
1001 ld = sc->nge_ldata;
1002 cd = &sc->nge_cdata;
1003
1004 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1005 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1006 return(ENOBUFS);
1007 if (i == (NGE_RX_LIST_CNT - 1)) {
1008 ld->nge_rx_list[i].nge_nextdesc =
1009 &ld->nge_rx_list[0];
1010 ld->nge_rx_list[i].nge_next =
1011 vtophys(&ld->nge_rx_list[0]);
1012 } else {
1013 ld->nge_rx_list[i].nge_nextdesc =
1014 &ld->nge_rx_list[i + 1];
1015 ld->nge_rx_list[i].nge_next =
1016 vtophys(&ld->nge_rx_list[i + 1]);
1017 }
1018 }
1019
1020 cd->nge_rx_prod = 0;
1021
1022 return(0);
1023}
1024
1025/*
1026 * Initialize an RX descriptor and attach an MBUF cluster.
1027 */
22bf5b21
JS
1028static int
1029nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
984263bc 1030{
22bf5b21 1031 struct mbuf *m_new = NULL;
368e791d 1032 struct nge_jslot *buf;
984263bc
MD
1033
1034 if (m == NULL) {
74f1caca 1035 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1036 if (m_new == NULL) {
1037 printf("nge%d: no memory for rx list "
1038 "-- packet dropped!\n", sc->nge_unit);
1039 return(ENOBUFS);
1040 }
1041
1042 /* Allocate the jumbo buffer */
1043 buf = nge_jalloc(sc);
1044 if (buf == NULL) {
1045#ifdef NGE_VERBOSE
1046 printf("nge%d: jumbo allocation failed "
1047 "-- packet dropped!\n", sc->nge_unit);
1048#endif
1049 m_freem(m_new);
1050 return(ENOBUFS);
1051 }
1052 /* Attach the buffer to the mbuf */
368e791d
JS
1053 m_new->m_ext.ext_arg = buf;
1054 m_new->m_ext.ext_buf = buf->nge_buf;
b542cd49
JS
1055 m_new->m_ext.ext_free = nge_jfree;
1056 m_new->m_ext.ext_ref = nge_jref;
368e791d
JS
1057 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1058
1059 m_new->m_data = m_new->m_ext.ext_buf;
1060 m_new->m_flags |= M_EXT;
1061 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc
MD
1062 } else {
1063 m_new = m;
368e791d 1064 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
984263bc
MD
1065 m_new->m_data = m_new->m_ext.ext_buf;
1066 }
1067
22bf5b21 1068 m_adj(m_new, sizeof(uint64_t));
984263bc
MD
1069
1070 c->nge_mbuf = m_new;
1071 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1072 c->nge_ctl = m_new->m_len;
1073 c->nge_extsts = 0;
1074
1075 return(0);
1076}
1077
22bf5b21
JS
1078static int
1079nge_alloc_jumbo_mem(struct nge_softc *sc)
984263bc 1080{
22bf5b21
JS
1081 caddr_t ptr;
1082 int i;
368e791d 1083 struct nge_jslot *entry;
984263bc
MD
1084
1085 /* Grab a big chunk o' storage. */
1086 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
56ae9d75 1087 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
1088
1089 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1090 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1091 return(ENOBUFS);
1092 }
1093
1094 SLIST_INIT(&sc->nge_jfree_listhead);
984263bc
MD
1095
1096 /*
1097 * Now divide it up into 9K pieces and save the addresses
1098 * in an array.
1099 */
1100 ptr = sc->nge_cdata.nge_jumbo_buf;
1101 for (i = 0; i < NGE_JSLOTS; i++) {
368e791d
JS
1102 entry = &sc->nge_cdata.nge_jslots[i];
1103 entry->nge_sc = sc;
1104 entry->nge_buf = ptr;
1105 entry->nge_inuse = 0;
1106 entry->nge_slot = i;
1107 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1108 ptr += NGE_JLEN;
984263bc
MD
1109 }
1110
1111 return(0);
1112}
1113
984263bc
MD
1114
1115/*
1116 * Allocate a jumbo buffer.
1117 */
368e791d 1118static struct nge_jslot *
22bf5b21 1119nge_jalloc(struct nge_softc *sc)
984263bc 1120{
368e791d 1121 struct nge_jslot *entry;
22bf5b21 1122
984263bc 1123 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
22bf5b21 1124
984263bc
MD
1125 if (entry == NULL) {
1126#ifdef NGE_VERBOSE
1127 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1128#endif
1129 return(NULL);
1130 }
1131
368e791d
JS
1132 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1133 entry->nge_inuse = 1;
1134
1135 return(entry);
984263bc
MD
1136}
1137
1138/*
1139 * Adjust usage count on a jumbo buffer. In general this doesn't
1140 * get used much because our jumbo buffers don't get passed around
1141 * a lot, but it's implemented for correctness.
1142 */
22bf5b21 1143static void
368e791d 1144nge_jref(void *arg)
984263bc 1145{
368e791d
JS
1146 struct nge_jslot *entry = (struct nge_jslot *)arg;
1147 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1148
1149 if (sc == NULL)
1150 panic("nge_jref: can't find softc pointer!");
1151
368e791d 1152 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
984263bc
MD
1153 panic("nge_jref: asked to reference buffer "
1154 "that we don't manage!");
368e791d 1155 else if (entry->nge_inuse == 0)
984263bc
MD
1156 panic("nge_jref: buffer already free!");
1157 else
368e791d 1158 entry->nge_inuse++;
984263bc
MD
1159}
1160
1161/*
1162 * Release a jumbo buffer.
1163 */
22bf5b21 1164static void
368e791d 1165nge_jfree(void *arg)
984263bc 1166{
368e791d
JS
1167 struct nge_jslot *entry = (struct nge_jslot *)arg;
1168 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1169
1170 if (sc == NULL)
368e791d
JS
1171 panic("nge_jref: can't find softc pointer!");
1172
1173 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1174 panic("nge_jref: asked to reference buffer "
1175 "that we don't manage!");
1176 else if (entry->nge_inuse == 0)
1177 panic("nge_jref: buffer already free!");
1178 else if (--entry->nge_inuse == 0)
1179 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
984263bc
MD
1180}
1181/*
1182 * A frame has been uploaded: pass the resulting mbuf chain up to
1183 * the higher level protocols.
1184 */
22bf5b21
JS
1185static void
1186nge_rxeof(struct nge_softc *sc)
984263bc 1187{
22bf5b21
JS
1188 struct mbuf *m;
1189 struct ifnet *ifp = &sc->arpcom.ac_if;
1190 struct nge_desc *cur_rx;
1191 int i, total_len = 0;
1192 uint32_t rxstat;
984263bc 1193
984263bc
MD
1194 i = sc->nge_cdata.nge_rx_prod;
1195
1196 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
22bf5b21
JS
1197 struct mbuf *m0 = NULL;
1198 uint32_t extsts;
984263bc
MD
1199
1200#ifdef DEVICE_POLLING
46f25451 1201 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1202 if (sc->rxcycles <= 0)
1203 break;
1204 sc->rxcycles--;
1205 }
1206#endif /* DEVICE_POLLING */
1207
1208 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1209 rxstat = cur_rx->nge_rxstat;
1210 extsts = cur_rx->nge_extsts;
1211 m = cur_rx->nge_mbuf;
1212 cur_rx->nge_mbuf = NULL;
1213 total_len = NGE_RXBYTES(cur_rx);
1214 NGE_INC(i, NGE_RX_LIST_CNT);
1215 /*
1216 * If an error occurs, update stats, clear the
1217 * status word and leave the mbuf cluster in place:
1218 * it should simply get re-used next time this descriptor
1219 * comes up in the ring.
1220 */
22bf5b21 1221 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
984263bc
MD
1222 ifp->if_ierrors++;
1223 nge_newbuf(sc, cur_rx, m);
1224 continue;
1225 }
1226
1227 /*
1228 * Ok. NatSemi really screwed up here. This is the
1229 * only gigE chip I know of with alignment constraints
1230 * on receive buffers. RX buffers must be 64-bit aligned.
1231 */
1232#ifdef __i386__
1233 /*
1234 * By popular demand, ignore the alignment problems
1235 * on the Intel x86 platform. The performance hit
1236 * incurred due to unaligned accesses is much smaller
1237 * than the hit produced by forcing buffer copies all
1238 * the time, especially with jumbo frames. We still
1239 * need to fix up the alignment everywhere else though.
1240 */
1241 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1242#endif
1243 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1244 total_len + ETHER_ALIGN, 0, ifp, NULL);
1245 nge_newbuf(sc, cur_rx, m);
1246 if (m0 == NULL) {
1247 printf("nge%d: no receive buffers "
1248 "available -- packet dropped!\n",
1249 sc->nge_unit);
1250 ifp->if_ierrors++;
1251 continue;
1252 }
1253 m_adj(m0, ETHER_ALIGN);
1254 m = m0;
1255#ifdef __i386__
1256 } else {
1257 m->m_pkthdr.rcvif = ifp;
1258 m->m_pkthdr.len = m->m_len = total_len;
1259 }
1260#endif
1261
1262 ifp->if_ipackets++;
984263bc
MD
1263
1264 /* Do IP checksum checking. */
1265 if (extsts & NGE_RXEXTSTS_IPPKT)
1266 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1267 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1268 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1269 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
22bf5b21 1270 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
984263bc 1271 (extsts & NGE_RXEXTSTS_UDPPKT &&
22bf5b21 1272 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
984263bc
MD
1273 m->m_pkthdr.csum_flags |=
1274 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1275 m->m_pkthdr.csum_data = 0xffff;
1276 }
1277
1278 /*
1279 * If we received a packet with a vlan tag, pass it
1280 * to vlan_input() instead of ether_input().
1281 */
78195a76 1282 lwkt_serialize_enter(ifp->if_serializer);
3013ac0e
JS
1283 if (extsts & NGE_RXEXTSTS_VLANPKT)
1284 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1285 else
78195a76
MD
1286 ifp->if_input(ifp, m);
1287 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1288 }
1289
1290 sc->nge_cdata.nge_rx_prod = i;
984263bc
MD
1291}
1292
1293/*
1294 * A frame was downloaded to the chip. It's safe for us to clean up
1295 * the list buffers.
1296 */
22bf5b21
JS
1297static void
1298nge_txeof(struct nge_softc *sc)
984263bc 1299{
22bf5b21
JS
1300 struct ifnet *ifp = &sc->arpcom.ac_if;
1301 struct nge_desc *cur_tx = NULL;
1302 uint32_t idx;
984263bc
MD
1303
1304 /* Clear the timeout timer. */
1305 ifp->if_timer = 0;
1306
1307 /*
1308 * Go through our tx list and free mbufs for those
1309 * frames that have been transmitted.
1310 */
1311 idx = sc->nge_cdata.nge_tx_cons;
1312 while (idx != sc->nge_cdata.nge_tx_prod) {
1313 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1314
1315 if (NGE_OWNDESC(cur_tx))
1316 break;
1317
1318 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1319 sc->nge_cdata.nge_tx_cnt--;
1320 NGE_INC(idx, NGE_TX_LIST_CNT);
1321 continue;
1322 }
1323
1324 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1325 ifp->if_oerrors++;
1326 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1327 ifp->if_collisions++;
1328 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1329 ifp->if_collisions++;
1330 }
1331
1332 ifp->if_collisions +=
1333 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1334
1335 ifp->if_opackets++;
1336 if (cur_tx->nge_mbuf != NULL) {
1337 m_freem(cur_tx->nge_mbuf);
1338 cur_tx->nge_mbuf = NULL;
1339 }
1340
1341 sc->nge_cdata.nge_tx_cnt--;
1342 NGE_INC(idx, NGE_TX_LIST_CNT);
1343 ifp->if_timer = 0;
1344 }
1345
1346 sc->nge_cdata.nge_tx_cons = idx;
1347
1348 if (cur_tx != NULL)
1349 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1350}
1351
22bf5b21
JS
1352static void
1353nge_tick(void *xsc)
984263bc 1354{
22bf5b21
JS
1355 struct nge_softc *sc = xsc;
1356 struct ifnet *ifp = &sc->arpcom.ac_if;
1357 struct mii_data *mii;
984263bc 1358
78195a76 1359 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1360
984263bc 1361 if (sc->nge_tbi) {
22bf5b21 1362 if (sc->nge_link == 0) {
984263bc
MD
1363 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1364 & NGE_TBIBMSR_ANEG_DONE) {
1365 printf("nge%d: gigabit link up\n",
1366 sc->nge_unit);
1367 nge_miibus_statchg(sc->nge_miibus);
1368 sc->nge_link++;
0b193118 1369 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1370 nge_start(ifp);
1371 }
1372 }
1373 } else {
1374 mii = device_get_softc(sc->nge_miibus);
1375 mii_tick(mii);
1376
22bf5b21 1377 if (sc->nge_link == 0) {
984263bc
MD
1378 if (mii->mii_media_status & IFM_ACTIVE &&
1379 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1380 sc->nge_link++;
1381 if (IFM_SUBTYPE(mii->mii_media_active)
7f259627 1382 == IFM_1000_T)
984263bc
MD
1383 printf("nge%d: gigabit link up\n",
1384 sc->nge_unit);
0b193118 1385 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1386 nge_start(ifp);
1387 }
1388 }
1389 }
43c4cb7e 1390 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1391
78195a76 1392 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1393}
1394
1395#ifdef DEVICE_POLLING
984263bc
MD
1396
1397static void
1398nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1399{
22bf5b21 1400 struct nge_softc *sc = ifp->if_softc;
984263bc 1401
9c095379
MD
1402 switch(cmd) {
1403 case POLL_REGISTER:
1404 /* disable interrupts */
1405 CSR_WRITE_4(sc, NGE_IER, 0);
1406 break;
1407 case POLL_DEREGISTER:
1408 /* enable interrupts */
984263bc 1409 CSR_WRITE_4(sc, NGE_IER, 1);
9c095379
MD
1410 break;
1411 default:
1412 /*
1413 * On the nge, reading the status register also clears it.
1414 * So before returning to intr mode we must make sure that all
1415 * possible pending sources of interrupts have been served.
1416 * In practice this means run to completion the *eof routines,
1417 * and then call the interrupt routine
1418 */
1419 sc->rxcycles = count;
1420 nge_rxeof(sc);
1421 nge_txeof(sc);
1422 if (!ifq_is_empty(&ifp->if_snd))
1423 nge_start(ifp);
984263bc 1424
9c095379
MD
1425 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1426 uint32_t status;
984263bc 1427
9c095379
MD
1428 /* Reading the ISR register clears all interrupts. */
1429 status = CSR_READ_4(sc, NGE_ISR);
984263bc 1430
9c095379
MD
1431 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1432 nge_rxeof(sc);
984263bc 1433
9c095379
MD
1434 if (status & (NGE_ISR_RX_IDLE))
1435 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
984263bc 1436
9c095379
MD
1437 if (status & NGE_ISR_SYSERR) {
1438 nge_reset(sc);
1439 nge_init(sc);
1440 }
984263bc 1441 }
9c095379 1442 break;
984263bc
MD
1443 }
1444}
9c095379 1445
984263bc
MD
1446#endif /* DEVICE_POLLING */
1447
22bf5b21
JS
1448static void
1449nge_intr(void *arg)
984263bc 1450{
22bf5b21
JS
1451 struct nge_softc *sc = arg;
1452 struct ifnet *ifp = &sc->arpcom.ac_if;
1453 uint32_t status;
984263bc 1454
984263bc
MD
1455 /* Supress unwanted interrupts */
1456 if (!(ifp->if_flags & IFF_UP)) {
1457 nge_stop(sc);
1458 return;
1459 }
1460
1461 /* Disable interrupts. */
1462 CSR_WRITE_4(sc, NGE_IER, 0);
1463
1464 /* Data LED on for TBI mode */
1465 if(sc->nge_tbi)
1466 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1467 | NGE_GPIO_GP3_OUT);
1468
1469 for (;;) {
1470 /* Reading the ISR register clears all interrupts. */
1471 status = CSR_READ_4(sc, NGE_ISR);
1472
1473 if ((status & NGE_INTRS) == 0)
1474 break;
1475
1476 if ((status & NGE_ISR_TX_DESC_OK) ||
1477 (status & NGE_ISR_TX_ERR) ||
1478 (status & NGE_ISR_TX_OK) ||
1479 (status & NGE_ISR_TX_IDLE))
1480 nge_txeof(sc);
1481
1482 if ((status & NGE_ISR_RX_DESC_OK) ||
1483 (status & NGE_ISR_RX_ERR) ||
1484 (status & NGE_ISR_RX_OFLOW) ||
1485 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1486 (status & NGE_ISR_RX_IDLE) ||
1487 (status & NGE_ISR_RX_OK))
1488 nge_rxeof(sc);
1489
1490 if ((status & NGE_ISR_RX_IDLE))
1491 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1492
1493 if (status & NGE_ISR_SYSERR) {
1494 nge_reset(sc);
1495 ifp->if_flags &= ~IFF_RUNNING;
1496 nge_init(sc);
1497 }
1498
1499#ifdef notyet
1500 /* mii_tick should only be called once per second */
1501 if (status & NGE_ISR_PHY_INTR) {
1502 sc->nge_link = 0;
78195a76 1503 nge_tick_serialized(sc);
984263bc
MD
1504 }
1505#endif
1506 }
1507
1508 /* Re-enable interrupts. */
1509 CSR_WRITE_4(sc, NGE_IER, 1);
1510
0b193118 1511 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1512 nge_start(ifp);
1513
1514 /* Data LED off for TBI mode */
1515
1516 if(sc->nge_tbi)
1517 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1518 & ~NGE_GPIO_GP3_OUT);
984263bc
MD
1519}
1520
1521/*
1522 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1523 * pointers to the fragment pointers.
1524 */
22bf5b21
JS
1525static int
1526nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1527{
22bf5b21
JS
1528 struct nge_desc *f = NULL;
1529 struct mbuf *m;
1530 int frag, cur, cnt = 0;
1531 struct ifvlan *ifv = NULL;
984263bc
MD
1532
1533 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1534 m_head->m_pkthdr.rcvif != NULL &&
1535 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1536 ifv = m_head->m_pkthdr.rcvif->if_softc;
1537
1538 /*
1539 * Start packing the mbufs in this chain into
1540 * the fragment pointers. Stop when we run out
1541 * of fragments or hit the end of the mbuf chain.
1542 */
1543 m = m_head;
1544 cur = frag = *txidx;
1545
1546 for (m = m_head; m != NULL; m = m->m_next) {
1547 if (m->m_len != 0) {
1548 if ((NGE_TX_LIST_CNT -
1549 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1550 return(ENOBUFS);
1551 f = &sc->nge_ldata->nge_tx_list[frag];
1552 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1553 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1554 if (cnt != 0)
1555 f->nge_ctl |= NGE_CMDSTS_OWN;
1556 cur = frag;
1557 NGE_INC(frag, NGE_TX_LIST_CNT);
1558 cnt++;
1559 }
1560 }
1561
1562 if (m != NULL)
1563 return(ENOBUFS);
1564
1565 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1566 if (m_head->m_pkthdr.csum_flags) {
1567 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1568 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1569 NGE_TXEXTSTS_IPCSUM;
1570 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1572 NGE_TXEXTSTS_TCPCSUM;
1573 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1575 NGE_TXEXTSTS_UDPCSUM;
1576 }
1577
1578 if (ifv != NULL) {
1579 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1580 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1581 }
1582
1583 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1584 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1585 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1586 sc->nge_cdata.nge_tx_cnt += cnt;
1587 *txidx = frag;
1588
1589 return(0);
1590}
1591
1592/*
1593 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1594 * to the mbuf data regions directly in the transmit lists. We also save a
1595 * copy of the pointers since the transmit list fragment pointers are
1596 * physical addresses.
1597 */
1598
22bf5b21
JS
1599static void
1600nge_start(struct ifnet *ifp)
984263bc 1601{
22bf5b21
JS
1602 struct nge_softc *sc = ifp->if_softc;
1603 struct mbuf *m_head = NULL;
1604 uint32_t idx;
2f54d1d2 1605 int need_trans;
984263bc
MD
1606
1607 if (!sc->nge_link)
1608 return;
1609
1610 idx = sc->nge_cdata.nge_tx_prod;
1611
1612 if (ifp->if_flags & IFF_OACTIVE)
1613 return;
1614
2f54d1d2 1615 need_trans = 0;
984263bc 1616 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
0b193118 1617 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
1618 if (m_head == NULL)
1619 break;
1620
1621 if (nge_encap(sc, m_head, &idx)) {
984263bc
MD
1622 ifp->if_flags |= IFF_OACTIVE;
1623 break;
1624 }
d2c71fa0 1625 ifq_dequeue(&ifp->if_snd, m_head);
2f54d1d2 1626 need_trans = 1;
984263bc 1627
7600679e 1628 BPF_MTAP(ifp, m_head);
984263bc
MD
1629 }
1630
2f54d1d2
SZ
1631 if (!need_trans)
1632 return;
1633
984263bc
MD
1634 /* Transmit */
1635 sc->nge_cdata.nge_tx_prod = idx;
1636 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1637
1638 /*
1639 * Set a timeout in case the chip goes out to lunch.
1640 */
1641 ifp->if_timer = 5;
984263bc
MD
1642}
1643
22bf5b21
JS
1644static void
1645nge_init(void *xsc)
984263bc 1646{
22bf5b21
JS
1647 struct nge_softc *sc = xsc;
1648 struct ifnet *ifp = &sc->arpcom.ac_if;
1649 struct mii_data *mii;
984263bc 1650
88e7510c 1651 if (ifp->if_flags & IFF_RUNNING) {
88e7510c
JS
1652 return;
1653 }
984263bc
MD
1654
1655 /*
1656 * Cancel pending I/O and free all RX/TX buffers.
1657 */
1658 nge_stop(sc);
43c4cb7e 1659 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1660
22bf5b21 1661 if (sc->nge_tbi)
984263bc 1662 mii = NULL;
22bf5b21 1663 else
984263bc 1664 mii = device_get_softc(sc->nge_miibus);
984263bc
MD
1665
1666 /* Set MAC address */
1667 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1668 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1669 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1670 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1671 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1672 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1673 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1674 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1675 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1676
1677 /* Init circular RX list. */
1678 if (nge_list_rx_init(sc) == ENOBUFS) {
1679 printf("nge%d: initialization failed: no "
1680 "memory for rx buffers\n", sc->nge_unit);
1681 nge_stop(sc);
984263bc
MD
1682 return;
1683 }
1684
1685 /*
1686 * Init tx descriptors.
1687 */
1688 nge_list_tx_init(sc);
1689
1690 /*
1691 * For the NatSemi chip, we have to explicitly enable the
1692 * reception of ARP frames, as well as turn on the 'perfect
1693 * match' filter where we store the station address, otherwise
1694 * we won't receive unicasts meant for this host.
1695 */
1696 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1698
1699 /* If we want promiscuous mode, set the allframes bit. */
22bf5b21 1700 if (ifp->if_flags & IFF_PROMISC)
984263bc 1701 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
22bf5b21 1702 else
984263bc 1703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
984263bc
MD
1704
1705 /*
1706 * Set the capture broadcast bit to capture broadcast frames.
1707 */
22bf5b21 1708 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
22bf5b21 1710 else
984263bc 1711 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
984263bc
MD
1712
1713 /*
1714 * Load the multicast filter.
1715 */
1716 nge_setmulti(sc);
1717
1718 /* Turn the receive filter on */
1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1720
1721 /*
1722 * Load the address of the RX and TX lists.
1723 */
1724 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1725 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1726 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1727 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1728
1729 /* Set RX configuration */
1730 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1731 /*
1732 * Enable hardware checksum validation for all IPv4
1733 * packets, do not reject packets with bad checksums.
1734 */
1735 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1736
1737 /*
1738 * Tell the chip to detect and strip VLAN tag info from
1739 * received frames. The tag will be provided in the extsts
1740 * field in the RX descriptors.
1741 */
1742 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1743 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1744
1745 /* Set TX configuration */
1746 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1747
1748 /*
1749 * Enable TX IPv4 checksumming on a per-packet basis.
1750 */
1751 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1752
1753 /*
1754 * Tell the chip to insert VLAN tags on a per-packet basis as
1755 * dictated by the code in the frame encapsulation routine.
1756 */
1757 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1758
1759 /* Set full/half duplex mode. */
1760 if (sc->nge_tbi) {
1761 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1762 == IFM_FDX) {
1763 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1764 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1765 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1766 } else {
1767 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1768 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1769 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1770 }
1771 } else {
1772 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1773 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1774 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1775 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1776 } else {
1777 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1778 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1779 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1780 }
1781 }
1782
1783 /*
1784 * Enable the delivery of PHY interrupts based on
1785 * link/speed/duplex status changes. Also enable the
1786 * extsts field in the DMA descriptors (needed for
1787 * TCP/IP checksum offload on transmit).
1788 */
22bf5b21
JS
1789 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1790 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
984263bc
MD
1791
1792 /*
1793 * Configure interrupt holdoff (moderation). We can
1794 * have the chip delay interrupt delivery for a certain
1795 * period. Units are in 100us, and the max setting
1796 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1797 */
1798 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1799
1800 /*
1801 * Enable interrupts.
1802 */
1803 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1804#ifdef DEVICE_POLLING
1805 /*
1806 * ... only enable interrupts if we are not polling, make sure
1807 * they are off otherwise.
1808 */
46f25451 1809 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1810 CSR_WRITE_4(sc, NGE_IER, 0);
1811 else
1812#endif /* DEVICE_POLLING */
1813 CSR_WRITE_4(sc, NGE_IER, 1);
1814
1815 /* Enable receiver and transmitter. */
22bf5b21 1816 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
984263bc
MD
1817 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1818
1819 nge_ifmedia_upd(ifp);
1820
1821 ifp->if_flags |= IFF_RUNNING;
1822 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1823}
1824
1825/*
1826 * Set media options.
1827 */
22bf5b21
JS
1828static int
1829nge_ifmedia_upd(struct ifnet *ifp)
984263bc 1830{
22bf5b21
JS
1831 struct nge_softc *sc = ifp->if_softc;
1832 struct mii_data *mii;
984263bc
MD
1833
1834 if (sc->nge_tbi) {
1835 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1836 == IFM_AUTO) {
1837 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1838 CSR_READ_4(sc, NGE_TBI_ANAR)
1839 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1840 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1841 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1842 | NGE_TBIBMCR_RESTART_ANEG);
1843 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1844 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1845 & IFM_GMASK) == IFM_FDX) {
1846 NGE_SETBIT(sc, NGE_TX_CFG,
1847 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1848 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1849
1850 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1851 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1852 } else {
1853 NGE_CLRBIT(sc, NGE_TX_CFG,
1854 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1855 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1856
1857 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1858 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1859 }
1860
1861 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1862 & ~NGE_GPIO_GP3_OUT);
1863 } else {
1864 mii = device_get_softc(sc->nge_miibus);
1865 sc->nge_link = 0;
1866 if (mii->mii_instance) {
1867 struct mii_softc *miisc;
1868 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1869 miisc = LIST_NEXT(miisc, mii_list))
1870 mii_phy_reset(miisc);
1871 }
1872 mii_mediachg(mii);
1873 }
1874
1875 return(0);
1876}
1877
1878/*
1879 * Report current media status.
1880 */
22bf5b21
JS
1881static void
1882nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1883{
22bf5b21
JS
1884 struct nge_softc *sc = ifp->if_softc;
1885 struct mii_data *mii;
984263bc
MD
1886
1887 if (sc->nge_tbi) {
1888 ifmr->ifm_status = IFM_AVALID;
1889 ifmr->ifm_active = IFM_ETHER;
1890
22bf5b21 1891 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
984263bc 1892 ifmr->ifm_status |= IFM_ACTIVE;
984263bc
MD
1893 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1894 ifmr->ifm_active |= IFM_LOOP;
1895 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1896 ifmr->ifm_active |= IFM_NONE;
1897 ifmr->ifm_status = 0;
1898 return;
1899 }
1900 ifmr->ifm_active |= IFM_1000_SX;
1901 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1902 == IFM_AUTO) {
1903 ifmr->ifm_active |= IFM_AUTO;
1904 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1905 & NGE_TBIANAR_FDX) {
1906 ifmr->ifm_active |= IFM_FDX;
1907 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1908 & NGE_TBIANAR_HDX) {
1909 ifmr->ifm_active |= IFM_HDX;
1910 }
1911 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1912 == IFM_FDX)
1913 ifmr->ifm_active |= IFM_FDX;
1914 else
1915 ifmr->ifm_active |= IFM_HDX;
1916
1917 } else {
1918 mii = device_get_softc(sc->nge_miibus);
1919 mii_pollstat(mii);
1920 ifmr->ifm_active = mii->mii_media_active;
1921 ifmr->ifm_status = mii->mii_media_status;
1922 }
984263bc
MD
1923}
1924
22bf5b21
JS
1925static int
1926nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1927{
22bf5b21
JS
1928 struct nge_softc *sc = ifp->if_softc;
1929 struct ifreq *ifr = (struct ifreq *) data;
1930 struct mii_data *mii;
88e7510c 1931 int error = 0;
984263bc 1932
984263bc 1933 switch(command) {
984263bc 1934 case SIOCSIFMTU:
22bf5b21 1935 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
984263bc 1936 error = EINVAL;
22bf5b21 1937 } else {
984263bc
MD
1938 ifp->if_mtu = ifr->ifr_mtu;
1939 /*
1940 * Workaround: if the MTU is larger than
1941 * 8152 (TX FIFO size minus 64 minus 18), turn off
1942 * TX checksum offloading.
1943 */
1944 if (ifr->ifr_mtu >= 8152)
1945 ifp->if_hwassist = 0;
1946 else
1947 ifp->if_hwassist = NGE_CSUM_FEATURES;
1948 }
1949 break;
1950 case SIOCSIFFLAGS:
1951 if (ifp->if_flags & IFF_UP) {
1952 if (ifp->if_flags & IFF_RUNNING &&
1953 ifp->if_flags & IFF_PROMISC &&
1954 !(sc->nge_if_flags & IFF_PROMISC)) {
1955 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1956 NGE_RXFILTCTL_ALLPHYS|
1957 NGE_RXFILTCTL_ALLMULTI);
1958 } else if (ifp->if_flags & IFF_RUNNING &&
1959 !(ifp->if_flags & IFF_PROMISC) &&
1960 sc->nge_if_flags & IFF_PROMISC) {
1961 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1962 NGE_RXFILTCTL_ALLPHYS);
1963 if (!(ifp->if_flags & IFF_ALLMULTI))
1964 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1965 NGE_RXFILTCTL_ALLMULTI);
1966 } else {
1967 ifp->if_flags &= ~IFF_RUNNING;
1968 nge_init(sc);
1969 }
1970 } else {
1971 if (ifp->if_flags & IFF_RUNNING)
1972 nge_stop(sc);
1973 }
1974 sc->nge_if_flags = ifp->if_flags;
1975 error = 0;
1976 break;
1977 case SIOCADDMULTI:
1978 case SIOCDELMULTI:
1979 nge_setmulti(sc);
1980 error = 0;
1981 break;
1982 case SIOCGIFMEDIA:
1983 case SIOCSIFMEDIA:
1984 if (sc->nge_tbi) {
1985 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
1986 command);
1987 } else {
1988 mii = device_get_softc(sc->nge_miibus);
1989 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1990 command);
1991 }
1992 break;
1993 default:
c1484ba2 1994 error = ether_ioctl(ifp, command, data);
984263bc
MD
1995 break;
1996 }
984263bc
MD
1997 return(error);
1998}
1999
22bf5b21
JS
2000static void
2001nge_watchdog(struct ifnet *ifp)
984263bc 2002{
22bf5b21 2003 struct nge_softc *sc = ifp->if_softc;
984263bc
MD
2004
2005 ifp->if_oerrors++;
2006 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2007
2008 nge_stop(sc);
2009 nge_reset(sc);
2010 ifp->if_flags &= ~IFF_RUNNING;
2011 nge_init(sc);
2012
0b193118 2013 if (!ifq_is_empty(&ifp->if_snd))
984263bc 2014 nge_start(ifp);
984263bc
MD
2015}
2016
2017/*
2018 * Stop the adapter and free any mbufs allocated to the
2019 * RX and TX lists.
2020 */
22bf5b21
JS
2021static void
2022nge_stop(struct nge_softc *sc)
984263bc 2023{
22bf5b21
JS
2024 struct ifnet *ifp = &sc->arpcom.ac_if;
2025 struct ifmedia_entry *ifm;
2026 struct mii_data *mii;
2027 int i, itmp, mtmp;
984263bc 2028
984263bc 2029 ifp->if_timer = 0;
22bf5b21 2030 if (sc->nge_tbi)
984263bc 2031 mii = NULL;
22bf5b21 2032 else
984263bc 2033 mii = device_get_softc(sc->nge_miibus);
984263bc 2034
43c4cb7e 2035 callout_stop(&sc->nge_stat_timer);
984263bc
MD
2036 CSR_WRITE_4(sc, NGE_IER, 0);
2037 CSR_WRITE_4(sc, NGE_IMR, 0);
2038 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2039 DELAY(1000);
2040 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2041 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2042
2043 /*
2044 * Isolate/power down the PHY, but leave the media selection
2045 * unchanged so that things will be put back to normal when
2046 * we bring the interface back up.
2047 */
2048 itmp = ifp->if_flags;
2049 ifp->if_flags |= IFF_UP;
2050
2051 if (sc->nge_tbi)
2052 ifm = sc->nge_ifmedia.ifm_cur;
2053 else
2054 ifm = mii->mii_media.ifm_cur;
2055
2056 mtmp = ifm->ifm_media;
2057 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2058
2059 if (!sc->nge_tbi)
2060 mii_mediachg(mii);
2061 ifm->ifm_media = mtmp;
2062 ifp->if_flags = itmp;
2063
2064 sc->nge_link = 0;
2065
2066 /*
2067 * Free data in the RX lists.
2068 */
2069 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2070 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2071 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2072 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2073 }
2074 }
22bf5b21 2075 bzero(&sc->nge_ldata->nge_rx_list,
984263bc
MD
2076 sizeof(sc->nge_ldata->nge_rx_list));
2077
2078 /*
2079 * Free the TX list buffers.
2080 */
2081 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2082 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2083 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2084 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2085 }
2086 }
2087
22bf5b21 2088 bzero(&sc->nge_ldata->nge_tx_list,
984263bc
MD
2089 sizeof(sc->nge_ldata->nge_tx_list));
2090
2091 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
2092}
2093
2094/*
2095 * Stop all chip I/O so that the kernel's probe routines don't
2096 * get confused by errant DMAs when rebooting.
2097 */
22bf5b21
JS
2098static void
2099nge_shutdown(device_t dev)
984263bc 2100{
22bf5b21 2101 struct nge_softc *sc = device_get_softc(dev);
78195a76 2102 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 2103
78195a76 2104 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
2105 nge_reset(sc);
2106 nge_stop(sc);
78195a76 2107 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2108}
78195a76 2109