Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / nv / if_nv.c
CommitLineData
a072e131 1/*
e5829d43 2 * Copyright (c) 2003, 2004 by Quinton Dolan <q@onthenet.com.au>.
a072e131
JS
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
15 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
e5829d43 26 * $Id: if_nv.c,v 1.20 2005/03/12 01:11:00 q Exp $
78195a76 27 * $DragonFly: src/sys/dev/netif/nv/Attic/if_nv.c,v 1.23 2005/11/28 17:13:43 dillon Exp $
a072e131
JS
28 */
29
30/*
31 * NVIDIA nForce MCP Networking Adapter driver
32 *
33 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA
34 * through their web site.
35 *
36 * All mainstream nForce and nForce2 motherboards are supported. This module
e5829d43
JS
37 * is as stable, sometimes more stable, than the linux version. (Recent
38 * Linux stability issues seem to be related to some issues with newer
39 * distributions using GCC 3.x, however this don't appear to effect FreeBSD
40 * 5.x).
a072e131 41 *
e5829d43
JS
42 * In accordance with the NVIDIA distribution license it is necessary to
43 * link this module against the nvlibnet.o binary object included in the
44 * Linux driver source distribution. The binary component is not modified in
45 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c
46 * linux kernel module "wrapper".
a072e131
JS
47 *
48 * The Linux driver uses a common code API that is shared between Win32 and
e5829d43
JS
49 * i386 Linux. This abstracts the low level driver functions and uses
50 * callbacks and hooks to access the underlying hardware device. By using
51 * this same API in a FreeBSD kernel module it is possible to support the
52 * hardware without breaching the Linux source distributions licensing
53 * requirements, or obtaining the hardware programming specifications.
a072e131 54 *
e5829d43
JS
55 * Although not conventional, it works, and given the relatively small
56 * amount of hardware centric code, it's hopefully no more buggy than its
57 * linux counterpart.
58 *
59 * NVIDIA now suppport the nForce3 AMD64 platform, however I have been
60 * unable to access such a system to verify support. However, the code is
61 * reported to work with little modification when compiled with the AMD64
62 * version of the NVIDIA Linux library. All that should be necessary to make
63 * the driver work is to link it directly into the kernel, instead of as a
64 * module, and apply the docs/amd64.diff patch in this source distribution to
65 * the NVIDIA Linux driver source.
66 *
67 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well
68 * as recent versions of DragonFly.
a072e131
JS
69 *
70 * Written by Quinton Dolan <q@onthenet.com.au>
71 * Portions based on existing FreeBSD network drivers.
72 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files.
73 *
74 * $Id: if_nv.c,v 1.9 2003/12/13 15:27:40 q Exp $
75 */
76
2b71c8f1
SZ
77#include "opt_polling.h"
78
a072e131
JS
79#include <sys/param.h>
80#include <sys/systm.h>
81#include <sys/sockio.h>
82#include <sys/mbuf.h>
83#include <sys/malloc.h>
84#include <sys/kernel.h>
85#include <sys/socket.h>
86#include <sys/sysctl.h>
87#include <sys/queue.h>
88#include <sys/module.h>
d28f25d7 89#include <sys/thread2.h>
a072e131
JS
90
91#include <net/if.h>
c7f5b673 92#include <net/ifq_var.h>
a072e131
JS
93#include <net/if_arp.h>
94#include <net/ethernet.h>
95#include <net/if_dl.h>
96#include <net/if_media.h>
97
98#include <net/bpf.h>
99
100#include <net/vlan/if_vlan_var.h>
101
102#include <machine/bus_memio.h>
103#include <machine/bus.h>
104#include <machine/resource.h>
105
106#include <vm/vm.h> /* for vtophys */
107#include <vm/pmap.h> /* for vtophys */
108#include <machine/clock.h> /* for DELAY */
109#include <sys/bus.h>
110#include <sys/rman.h>
59a5a75e 111#include <sys/serialize.h>
a072e131
JS
112
113#include <bus/pci/pcireg.h>
114#include <bus/pci/pcivar.h>
115
116#include <dev/netif/mii_layer/mii.h>
117#include <dev/netif/mii_layer/miivar.h>
118
119MODULE_DEPEND(nv, pci, 1, 1, 1);
a072e131
JS
120MODULE_DEPEND(nv, miibus, 1, 1, 1);
121
122#include "if_nvreg.h"
123#include "miibus_if.h"
124
125static int nv_probe(device_t);
126static int nv_attach(device_t);
127static int nv_detach(device_t);
128static void nv_init(void *);
129static void nv_stop(struct nv_softc *);
130static void nv_shutdown(device_t);
131static int nv_init_rings(struct nv_softc *);
132static void nv_free_rings(struct nv_softc *);
133
134static void nv_ifstart(struct ifnet *);
135static int nv_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
136static void nv_intr(void *);
137static void nv_tick(void *);
138static void nv_setmulti(struct nv_softc *);
139static void nv_watchdog(struct ifnet *);
140static void nv_update_stats(struct nv_softc *);
59a5a75e
MD
141#ifdef DEVICE_POLLING
142static void nv_poll(struct ifnet *, enum poll_cmd, int);
143#endif
a072e131
JS
144
145static int nv_ifmedia_upd(struct ifnet *);
146static void nv_ifmedia_sts(struct ifnet *, struct ifmediareq *);
147static int nv_miibus_readreg(device_t, int, int);
148static void nv_miibus_writereg(device_t, int, int, int);
149
150static void nv_dmamap_cb(void *, bus_dma_segment_t *, int, int);
151static void nv_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int);
152
e5829d43
JS
153static NV_SINT32 nv_osalloc(PNV_VOID, PMEMORY_BLOCK);
154static NV_SINT32 nv_osfree(PNV_VOID, PMEMORY_BLOCK);
155static NV_SINT32 nv_osallocex(PNV_VOID, PMEMORY_BLOCKEX);
156static NV_SINT32 nv_osfreeex(PNV_VOID, PMEMORY_BLOCKEX);
157static NV_SINT32 nv_osclear(PNV_VOID, PNV_VOID, NV_SINT32);
158static NV_SINT32 nv_osdelay(PNV_VOID, NV_UINT32);
159static NV_SINT32 nv_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *);
160static NV_SINT32 nv_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID);
161static NV_SINT32 nv_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32);
162static NV_SINT32 nv_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8);
163static NV_SINT32 nv_oslinkchg(PNV_VOID, NV_SINT32);
164static NV_SINT32 nv_osalloctimer(PNV_VOID, PNV_VOID *);
165static NV_SINT32 nv_osfreetimer(PNV_VOID, PNV_VOID);
166static NV_SINT32 nv_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID);
167static NV_SINT32 nv_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32);
168static NV_SINT32 nv_oscanceltimer(PNV_VOID, PNV_VOID);
169
170static NV_SINT32 nv_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8);
171static PNV_VOID nv_ospreprocpktnopq(PNV_VOID, PNV_VOID);
172static NV_SINT32 nv_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32);
173static NV_SINT32 nv_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *);
174static NV_SINT32 nv_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID);
175static NV_SINT32 nv_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID);
176static PNV_VOID nv_osreturnbufvirt(PNV_VOID, PNV_VOID);
a072e131
JS
177
178static device_method_t nv_methods[] = {
179 /* Device interface */
180 DEVMETHOD(device_probe, nv_probe),
181 DEVMETHOD(device_attach, nv_attach),
182 DEVMETHOD(device_detach, nv_detach),
183 DEVMETHOD(device_shutdown, nv_shutdown),
184
185 /* Bus interface */
186 DEVMETHOD(bus_print_child, bus_generic_print_child),
187 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
188
189 /* MII interface */
190 DEVMETHOD(miibus_readreg, nv_miibus_readreg),
191 DEVMETHOD(miibus_writereg, nv_miibus_writereg),
192
193 {0, 0}
194};
195
196static driver_t nv_driver = {
197 "nv",
198 nv_methods,
199 sizeof(struct nv_softc)
200};
201
202static devclass_t nv_devclass;
203
204static int nv_pollinterval = 0;
205SYSCTL_INT(_hw, OID_AUTO, nv_pollinterval, CTLFLAG_RW,
206 &nv_pollinterval, 0, "delay between interface polls");
207
208DRIVER_MODULE(nv, pci, nv_driver, nv_devclass, 0, 0);
209DRIVER_MODULE(miibus, nv, miibus_driver, miibus_devclass, 0, 0);
210
211static struct nv_type nv_devs[] = {
2980fae4
MD
212 {NVIDIA_VENDORID, NFORCE_MCPNET1_DEVICEID,
213 "NVIDIA nForce MCP Networking Adapter"},
214 {NVIDIA_VENDORID, NFORCE_MCPNET2_DEVICEID,
215 "NVIDIA nForce MCP2 Networking Adapter"},
216 {NVIDIA_VENDORID, NFORCE_MCPNET3_DEVICEID,
217 "NVIDIA nForce MCP3 Networking Adapter"},
218 {NVIDIA_VENDORID, NFORCE_MCPNET4_DEVICEID,
219 "NVIDIA nForce MCP4 Networking Adapter"},
220 {NVIDIA_VENDORID, NFORCE_MCPNET5_DEVICEID,
221 "NVIDIA nForce MCP5 Networking Adapter"},
222 {NVIDIA_VENDORID, NFORCE_MCPNET6_DEVICEID,
223 "NVIDIA nForce MCP6 Networking Adapter"},
224 {NVIDIA_VENDORID, NFORCE_MCPNET7_DEVICEID,
225 "NVIDIA nForce MCP7 Networking Adapter"},
9dda2746
MD
226 {NVIDIA_VENDORID, NFORCE_MCPNET8_DEVICEID,
227 "NVIDIA nForce MCP8 Networking Adapter"},
228 {NVIDIA_VENDORID, NFORCE_MCPNET9_DEVICEID,
229 "NVIDIA nForce MCP9 Networking Adapter"},
230 {NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID,
231 "NVIDIA nForce MCP10 Networking Adapter"},
232 {NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID,
233 "NVIDIA nForce MCP11 Networking Adapter"},
2980fae4 234 {0, 0, NULL}
a072e131
JS
235};
236
237/* DMA MEM map callback function to get data segment physical address */
238static void
239nv_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
240{
241 if (error)
242 return;
243
244 KASSERT(nsegs == 1,
245 ("Too many DMA segments returned when mapping DMA memory"));
246 *(bus_addr_t *)arg = segs->ds_addr;
247}
248
249/* DMA RX map callback function to get data segment physical address */
250static void
251nv_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
252{
253 if (error)
254 return;
255 *(bus_addr_t *)arg = segs->ds_addr;
256}
257
258/*
259 * DMA TX buffer callback function to allocate fragment data segment
260 * addresses
261 */
262static void
263nv_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
264{
265 struct nv_tx_desc *info = arg;
266
267 if (error)
268 return;
269 KASSERT(nsegs < NV_MAX_FRAGS,
270 ("Too many DMA segments returned when mapping mbuf"));
271 info->numfrags = nsegs;
272 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t));
273}
274
275/* Probe for supported hardware ID's */
276static int
277nv_probe(device_t dev)
278{
279 struct nv_type *t = nv_devs;
280
281 /* Check for matching PCI DEVICE ID's */
282 while (t->name != NULL) {
283 if ((pci_get_vendor(dev) == t->vid_id) &&
284 (pci_get_device(dev) == t->dev_id)) {
285 device_set_desc(dev, t->name);
286 return (0);
287 }
288 t++;
289 }
290
291 return (ENXIO);
292}
293
294/* Attach driver and initialise hardware for use */
295static int
296nv_attach(device_t dev)
297{
298 u_char eaddr[ETHER_ADDR_LEN];
299 struct nv_softc *sc;
300 struct ifnet *ifp;
301 OS_API *osapi;
302 ADAPTER_OPEN_PARAMS OpenParams;
d0de58a2 303 int error = 0, i, rid;
9dda2746 304 u_int32_t unit;
a072e131
JS
305
306 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_attach - entry\n");
307
308 sc = device_get_softc(dev);
9dda2746 309 unit = device_get_unit(dev);
a072e131
JS
310
311 sc->dev = dev;
9dda2746 312 sc->unit = unit;
204b91ae 313 callout_init(&sc->nv_stat_timer);
a072e131
JS
314
315 /* Preinitialize data structures */
316 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS));
317
318 /* Enable bus mastering */
319 pci_enable_busmaster(dev);
320
321 /* Allocate memory mapped address space */
322 rid = NV_RID;
4e6d744d 323 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
a072e131
JS
324
325 if (sc->res == NULL) {
326 device_printf(dev, "couldn't map memory\n");
327 error = ENXIO;
328 goto fail;
329 }
330 sc->sc_st = rman_get_bustag(sc->res);
331 sc->sc_sh = rman_get_bushandle(sc->res);
332
333 /* Allocate interrupt */
334 rid = 0;
4e6d744d
JS
335 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
336 RF_SHAREABLE | RF_ACTIVE);
a072e131
JS
337
338 if (sc->irq == NULL) {
339 device_printf(dev, "couldn't map interrupt\n");
340 error = ENXIO;
341 goto fail;
342 }
343 /* Allocate DMA tags */
344 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
345 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS,
346 NV_MAX_FRAGS, MCLBYTES, 0,
347 &sc->mtag);
348 if (error) {
349 device_printf(dev, "couldn't allocate dma tag\n");
350 goto fail;
351 }
352 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
353 BUS_SPACE_MAXADDR, NULL, NULL,
354 sizeof(struct nv_rx_desc) * RX_RING_SIZE, 1,
355 sizeof(struct nv_rx_desc) * RX_RING_SIZE, 0,
356 &sc->rtag);
357 if (error) {
358 device_printf(dev, "couldn't allocate dma tag\n");
359 goto fail;
360 }
361 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
362 BUS_SPACE_MAXADDR, NULL, NULL,
363 sizeof(struct nv_tx_desc) * TX_RING_SIZE, 1,
364 sizeof(struct nv_tx_desc) * TX_RING_SIZE, 0,
365 &sc->ttag);
366 if (error) {
367 device_printf(dev, "couldn't allocate dma tag\n");
368 goto fail;
369 }
4902425b
JS
370
371 error = bus_dmamap_create(sc->ttag, 0, &sc->tmap);
372 if (error) {
373 device_printf(dev, "couldn't create dma map\n");
374 goto fail;
375 }
376
a072e131
JS
377 /* Allocate DMA safe memory and get the DMA addresses. */
378 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
4902425b 379 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tmap);
a072e131
JS
380 if (error) {
381 device_printf(dev, "couldn't allocate dma memory\n");
382 goto fail;
383 }
a072e131
JS
384 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
385 sizeof(struct nv_tx_desc) * TX_RING_SIZE, nv_dmamap_cb,
386 &sc->tx_addr, 0);
387 if (error) {
388 device_printf(dev, "couldn't map dma memory\n");
389 goto fail;
390 }
4902425b
JS
391
392 error = bus_dmamap_create(sc->rtag, 0, &sc->rmap);
393 if (error) {
394 device_printf(dev, "couldn't create dma map\n");
395 goto fail;
396 }
397
a072e131 398 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
4902425b 399 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rmap);
a072e131
JS
400 if (error) {
401 device_printf(dev, "couldn't allocate dma memory\n");
402 goto fail;
403 }
a072e131
JS
404 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
405 sizeof(struct nv_rx_desc) * RX_RING_SIZE, nv_dmamap_cb,
406 &sc->rx_addr, 0);
407 if (error) {
408 device_printf(dev, "couldn't map dma memory\n");
409 goto fail;
410 }
411 /* Initialize rings. */
412 if (nv_init_rings(sc)) {
413 device_printf(dev, "failed to init rings\n");
414 error = ENXIO;
415 goto fail;
416 }
417 /* Setup NVIDIA API callback routines */
418 osapi = &sc->osapi;
419 osapi->pOSCX = sc;
420 osapi->pfnAllocMemory = nv_osalloc;
421 osapi->pfnFreeMemory = nv_osfree;
422 osapi->pfnAllocMemoryEx = nv_osallocex;
423 osapi->pfnFreeMemoryEx = nv_osfreeex;
424 osapi->pfnClearMemory = nv_osclear;
425 osapi->pfnStallExecution = nv_osdelay;
426 osapi->pfnAllocReceiveBuffer = nv_osallocrxbuf;
427 osapi->pfnFreeReceiveBuffer = nv_osfreerxbuf;
428 osapi->pfnPacketWasSent = nv_ospackettx;
429 osapi->pfnPacketWasReceived = nv_ospacketrx;
430 osapi->pfnLinkStateHasChanged = nv_oslinkchg;
431 osapi->pfnAllocTimer = nv_osalloctimer;
432 osapi->pfnFreeTimer = nv_osfreetimer;
433 osapi->pfnInitializeTimer = nv_osinittimer;
434 osapi->pfnSetTimer = nv_ossettimer;
435 osapi->pfnCancelTimer = nv_oscanceltimer;
436 osapi->pfnPreprocessPacket = nv_ospreprocpkt;
437 osapi->pfnPreprocessPacketNopq = nv_ospreprocpktnopq;
438 osapi->pfnIndicatePackets = nv_osindicatepkt;
439 osapi->pfnLockAlloc = nv_oslockalloc;
440 osapi->pfnLockAcquire = nv_oslockacquire;
441 osapi->pfnLockRelease = nv_oslockrelease;
442 osapi->pfnReturnBufferVirtual = nv_osreturnbufvirt;
443
e5829d43
JS
444 sc->linkup = FALSE;
445 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN;
446
447 /* TODO - We don't support hardware offload yet */
448 sc->hwmode = 1;
449 sc->media = 0;
450
a072e131
JS
451 /* Set NVIDIA API startup parameters */
452 OpenParams.MaxDpcLoop = 2;
453 OpenParams.MaxRxPkt = RX_RING_SIZE;
454 OpenParams.MaxTxPkt = TX_RING_SIZE;
455 OpenParams.SentPacketStatusSuccess = 1;
456 OpenParams.SentPacketStatusFailure = 0;
457 OpenParams.MaxRxPktToAccumulate = 6;
458 OpenParams.ulPollInterval = nv_pollinterval;
459 OpenParams.SetForcedModeEveryNthRxPacket = 0;
460 OpenParams.SetForcedModeEveryNthTxPacket = 0;
461 OpenParams.RxForcedInterrupt = 0;
462 OpenParams.TxForcedInterrupt = 0;
463 OpenParams.pOSApi = osapi;
464 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res);
e5829d43
JS
465 OpenParams.bASFEnabled = 0;
466 OpenParams.ulDescriptorVersion = sc->hwmode;
467 OpenParams.ulMaxPacketSize = sc->max_frame_size;
468 OpenParams.DeviceId = pci_get_device(dev);
a072e131
JS
469
470 /* Open NVIDIA Hardware API */
471 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr);
472 if (error) {
473 device_printf(dev, "failed to open NVIDIA Hardware API: 0x%x\n", error);
474 goto fail;
475 }
e5829d43
JS
476
477 /* TODO - Add support for MODE2 hardware offload */
478
479 bzero(&sc->adapterdata, sizeof(sc->adapterdata));
480
481 sc->adapterdata.ulMediaIF = sc->media;
482 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
483 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
484
9dda2746
MD
485 sc->hwapi->pfnInit(sc->hwapi->pADCX,
486 0, /* force speed */
487 0, /* force full duplex */
488 0, /* force mode */
489 0, /* force async mode */
490 &sc->linkup);
491
a072e131
JS
492 /* MAC is loaded backwards into h/w reg */
493 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
494 for (i = 0; i < 6; i++) {
495 eaddr[i] = sc->original_mac_addr[5 - i];
496 }
497 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
498 bcopy(eaddr, (char *)&sc->sc_macaddr, ETHER_ADDR_LEN);
499
a072e131
JS
500 DEBUGOUT(NV_DEBUG_INIT, "nv: do mii_phy_probe\n");
501
502 /* Probe device for MII interface to PHY */
59a5a75e 503 if (mii_phy_probe(dev, &sc->miibus, nv_ifmedia_upd, nv_ifmedia_sts)) {
a072e131
JS
504 device_printf(dev, "MII without any phy!\n");
505 error = ENXIO;
506 goto fail;
507 }
508 /* Setup interface parameters */
509 ifp = &sc->sc_if;
510 ifp->if_softc = sc;
d0de58a2 511 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
a072e131
JS
512 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
513 ifp->if_ioctl = nv_ioctl;
514 ifp->if_start = nv_ifstart;
59a5a75e
MD
515#ifdef DEVICE_POLLING
516 ifp->if_poll = nv_poll;
517#endif
a072e131
JS
518 ifp->if_watchdog = nv_watchdog;
519 ifp->if_timer = 0;
520 ifp->if_init = nv_init;
521 ifp->if_mtu = ETHERMTU;
522 ifp->if_baudrate = IF_Mbps(100);
e5829d43
JS
523 ifp->if_capabilities |= IFCAP_VLAN_MTU;
524 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
ed0996d5 525 ifq_set_ready(&ifp->if_snd);
a072e131
JS
526
527 /* Attach to OS's managers. */
78195a76 528 ether_ifattach(ifp, sc->sc_macaddr, NULL);
a072e131
JS
529
530 /* Activate our interrupt handler. - attach last to avoid lock */
78195a76
MD
531 error = bus_setup_intr(sc->dev, sc->irq, INTR_NETSAFE,
532 nv_intr, sc, &sc->sc_ih, ifp->if_serializer);
a072e131 533 if (error) {
0dd4fceb 534 ether_ifdetach(ifp);
a072e131
JS
535 device_printf(sc->dev, "couldn't set up interrupt handler\n");
536 goto fail;
537 }
538 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_attach - exit\n");
539
540fail:
541 if (error)
542 nv_detach(dev);
543
544 return (error);
545}
546
547/* Detach interface for module unload */
548static int
549nv_detach(device_t dev)
550{
551 struct nv_softc *sc = device_get_softc(dev);
552 struct ifnet *ifp;
553
78195a76
MD
554 ifp = &sc->arpcom.ac_if;
555 lwkt_serialize_enter(ifp->if_serializer);
a072e131
JS
556
557 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_detach - entry\n");
558
a072e131 559 if (device_is_attached(dev)) {
78195a76 560 nv_stop(sc);
a072e131
JS
561 ether_ifdetach(ifp);
562 }
563
564 if (sc->miibus)
565 device_delete_child(dev, sc->miibus);
566 bus_generic_detach(dev);
567
568 /* Reload unreversed address back into MAC in original state */
569 if (sc->original_mac_addr)
570 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
571
572 DEBUGOUT(NV_DEBUG_DEINIT, "nv: do pfnClose\n");
573 /* Detach from NVIDIA hardware API */
574 if (sc->hwapi->pfnClose)
e5829d43 575 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE);
a072e131
JS
576 /* Release resources */
577 if (sc->sc_ih)
578 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih);
579 if (sc->irq)
580 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
581 if (sc->res)
582 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res);
583
584 nv_free_rings(sc);
585
586 if (sc->tx_desc) {
587 bus_dmamap_unload(sc->rtag, sc->rmap);
588 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
589 bus_dmamap_destroy(sc->rtag, sc->rmap);
590 }
591 if (sc->mtag)
592 bus_dma_tag_destroy(sc->mtag);
593 if (sc->ttag)
594 bus_dma_tag_destroy(sc->ttag);
595 if (sc->rtag)
596 bus_dma_tag_destroy(sc->rtag);
597
78195a76 598 lwkt_serialize_exit(ifp->if_serializer);
a072e131
JS
599
600 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_detach - exit\n");
a072e131
JS
601 return (0);
602}
603
78195a76 604/* Initialise interface and start it "RUNNING" */
a072e131
JS
605static void
606nv_init(void *xsc)
607{
608 struct nv_softc *sc = xsc;
609 struct ifnet *ifp;
610 int error;
611
a072e131
JS
612 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init - entry (%d)\n", sc->linkup);
613
614 ifp = &sc->sc_if;
615
616 /* Do nothing if already running */
617 if (ifp->if_flags & IFF_RUNNING)
59a5a75e 618 return;
a072e131 619
78195a76 620 nv_stop(sc);
a072e131
JS
621
622 DEBUGOUT(NV_DEBUG_INIT, "nv: do pfnInit\n");
623 /* Setup Hardware interface and allocate memory structures */
e5829d43
JS
624 error = sc->hwapi->pfnInit(sc->hwapi->pADCX,
625 0, /* force speed */
626 0, /* force full duplex */
627 0, /* force mode */
628 0, /* force async mode */
629 &sc->linkup);
630
a072e131
JS
631 if (error) {
632 device_printf(sc->dev, "failed to start NVIDIA Hardware interface\n");
59a5a75e 633 return;
a072e131
JS
634 }
635 /* Set the MAC address */
636 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, sc->sc_macaddr);
59a5a75e 637
a072e131
JS
638 sc->hwapi->pfnStart(sc->hwapi->pADCX);
639
640 /* Setup multicast filter */
641 nv_setmulti(sc);
642 nv_ifmedia_upd(ifp);
643
644 /* Update interface parameters */
645 ifp->if_flags |= IFF_RUNNING;
646 ifp->if_flags &= ~IFF_OACTIVE;
647
59a5a75e
MD
648 /*
649 * Enable the interrupt. Currently the nvidia API does not support
650 * polling, if we do not call pfnEnableInterrupts() we cannot
651 * issue the nvidia callback to process interrupts. Call the
652 * interrupt service routine in case the interrupt got stuck during
653 * a reset, renegotiation, or timeout.
654 */
655#if 1
78195a76 656 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
657 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
658#else
659 if ((ifp->if_flags & IFF_POLLING) == 0) {
78195a76 660 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
661 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
662 }
663#endif
664 nv_intr(sc);
665
9dda2746
MD
666 /*
667 * Reset watchdog and ring queue indexes. XXX if the interface
668 * is reset with pending tx packets queued to the actual device,
669 * the mbufs are currently lost.
670 */
671 ifp->if_timer = 0;
672 sc->pending_txs = 0;
673
204b91ae 674 callout_reset(&sc->nv_stat_timer, hz, nv_tick, sc);
a072e131
JS
675
676 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init - exit\n");
59a5a75e 677}
a072e131 678
59a5a75e
MD
679#ifdef DEVICE_POLLING
680
681static void
682nv_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
683{
684 struct nv_softc *sc = ifp->if_softc;
685
59a5a75e
MD
686 switch(cmd) {
687 case POLL_REGISTER:
688 /*
689 * We must disable the hardware interrupt on the device
690 * as well as ensure that any interrupt queued prior to
691 * this point does not execute the handler function.
692 *
693 * NOTE! The nvidia API does not support polling with
694 * interrupts disabled, so we have to leave them turned on
695 * unfortunately.
696 */
697#if 0
698 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
78195a76 699 lwkt_serialize_handler_disable(ifp->if_serializer);
59a5a75e
MD
700#endif
701 break;
702 case POLL_DEREGISTER:
703#if 0
78195a76 704 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
705 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
706#endif
707 break;
708 case POLL_AND_CHECK_STATUS:
709 /* fall through */
710 case POLL_ONLY:
711 if (ifp->if_flags & IFF_RUNNING) {
712 nv_intr(sc);
713 }
714 if (ifp->if_flags & IFF_RUNNING) {
715 if (!ifq_is_empty(&ifp->if_snd))
78195a76 716 nv_ifstart(ifp);
59a5a75e
MD
717 }
718 break;
719 }
59a5a75e 720}
a072e131 721
59a5a75e
MD
722#endif
723
a072e131
JS
724/* Stop interface activity ie. not "RUNNING" */
725static void
78195a76 726nv_stop(struct nv_softc *sc)
a072e131
JS
727{
728 struct ifnet *ifp;
729
a072e131
JS
730 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_stop - entry\n");
731
732 ifp = &sc->sc_if;
733 ifp->if_timer = 0;
734
735 /* Cancel tick timer */
204b91ae 736 callout_stop(&sc->nv_stat_timer);
a072e131 737
59a5a75e
MD
738 /*
739 * Stop hardware activity. The serializer handler disablement call
740 * prevents any interrupt scheduled prior to this call from calling
741 * the handler.
742 */
a072e131 743 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
78195a76 744 lwkt_serialize_handler_disable(ifp->if_serializer);
59a5a75e 745
a072e131 746 sc->hwapi->pfnStop(sc->hwapi->pADCX, 0);
59a5a75e 747 sc->hwapi->pfnClearTxDesc(sc->hwapi->pADCX);
a072e131
JS
748
749 DEBUGOUT(NV_DEBUG_DEINIT, "nv: do pfnDeinit\n");
750 /* Shutdown interface and deallocate memory buffers */
751 if (sc->hwapi->pfnDeinit)
752 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0);
753
754 sc->linkup = 0;
755 sc->cur_rx = 0;
e5829d43 756 sc->pending_rxs = 0;
a072e131
JS
757
758 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
759
760 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_stop - exit\n");
a072e131
JS
761}
762
763/* Shutdown interface for unload/reboot */
764static void
765nv_shutdown(device_t dev)
766{
767 struct nv_softc *sc;
768
769 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_shutdown\n");
770
771 sc = device_get_softc(dev);
772
773 /* Stop hardware activity */
78195a76 774 lwkt_serialize_enter(sc->sc_if.if_serializer);
a072e131 775 nv_stop(sc);
78195a76 776 lwkt_serialize_exit(sc->sc_if.if_serializer);
a072e131
JS
777}
778
779/* Allocate TX ring buffers */
780static int
781nv_init_rings(struct nv_softc *sc)
782{
783 int error, i;
784
a072e131
JS
785 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init_rings - entry\n");
786
787 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0;
788 /* Initialise RX ring */
789 for (i = 0; i < RX_RING_SIZE; i++) {
790 struct nv_rx_desc *desc = sc->rx_desc + i;
791 struct nv_map_buffer *buf = &desc->buf;
792
793 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
794 if (buf->mbuf == NULL) {
795 device_printf(sc->dev, "couldn't allocate mbuf\n");
796 nv_free_rings(sc);
797 error = ENOBUFS;
798 goto fail;
799 }
800 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
801 m_adj(buf->mbuf, ETHER_ALIGN);
802
803 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
804 if (error) {
805 device_printf(sc->dev, "couldn't create dma map\n");
806 nv_free_rings(sc);
807 goto fail;
808 }
809 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
810 nv_dmamap_rx_cb, &desc->paddr, 0);
811 if (error) {
812 device_printf(sc->dev, "couldn't dma map mbuf\n");
813 nv_free_rings(sc);
814 goto fail;
815 }
816 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
817
818 desc->buflength = buf->mbuf->m_len;
e5829d43 819 desc->vaddr = mtod(buf->mbuf, caddr_t);
a072e131
JS
820 }
821 bus_dmamap_sync(sc->rtag, sc->rmap,
822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
823
824 /* Initialize TX ring */
825 for (i = 0; i < TX_RING_SIZE; i++) {
826 struct nv_tx_desc *desc = sc->tx_desc + i;
827 struct nv_map_buffer *buf = &desc->buf;
828
829 buf->mbuf = NULL;
830
831 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
832 if (error) {
833 device_printf(sc->dev, "couldn't create dma map\n");
834 nv_free_rings(sc);
835 goto fail;
836 }
837 }
838 bus_dmamap_sync(sc->ttag, sc->tmap,
839 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
840
841 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init_rings - exit\n");
842
843fail:
a072e131
JS
844 return (error);
845}
846
847/* Free the TX ring buffers */
848static void
849nv_free_rings(struct nv_softc *sc)
850{
851 int i;
852
a072e131
JS
853 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_free_rings - entry\n");
854
855 for (i = 0; i < RX_RING_SIZE; i++) {
856 struct nv_rx_desc *desc = sc->rx_desc + i;
857 struct nv_map_buffer *buf = &desc->buf;
858
859 if (buf->mbuf) {
860 bus_dmamap_unload(sc->mtag, buf->map);
861 bus_dmamap_destroy(sc->mtag, buf->map);
862 m_freem(buf->mbuf);
863 }
864 buf->mbuf = NULL;
865 }
866
867 for (i = 0; i < TX_RING_SIZE; i++) {
868 struct nv_tx_desc *desc = sc->tx_desc + i;
869 struct nv_map_buffer *buf = &desc->buf;
870
871 if (buf->mbuf) {
872 bus_dmamap_unload(sc->mtag, buf->map);
873 bus_dmamap_destroy(sc->mtag, buf->map);
874 m_freem(buf->mbuf);
875 }
876 buf->mbuf = NULL;
877 }
878
879 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_free_rings - exit\n");
a072e131
JS
880}
881
882/* Main loop for sending packets from OS to interface */
59a5a75e 883
a072e131
JS
884static void
885nv_ifstart(struct ifnet *ifp)
886{
887 struct nv_softc *sc = ifp->if_softc;
888 struct nv_map_buffer *buf;
889 struct mbuf *m0, *m;
890 struct nv_tx_desc *desc;
891 ADAPTER_WRITE_DATA txdata;
892 int error, i;
893
894 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_ifstart - entry\n");
895
896 /* If link is down/busy or queue is empty do nothing */
59a5a75e 897 if ((ifp->if_flags & IFF_OACTIVE) || ifq_is_empty(&ifp->if_snd))
a072e131
JS
898 return;
899
900 /* Transmit queued packets until sent or TX ring is full */
901 while (sc->pending_txs < TX_RING_SIZE) {
902 desc = sc->tx_desc + sc->cur_tx;
903 buf = &desc->buf;
904
905 /* Get next packet to send. */
d2c71fa0 906 m0 = ifq_dequeue(&ifp->if_snd, NULL);
a072e131
JS
907
908 /* If nothing to send, return. */
909 if (m0 == NULL)
910 return;
911
912 /* Map MBUF for DMA access */
913 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
914 nv_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
915
916 if (error && error != EFBIG) {
917 m_freem(m0);
918 sc->tx_errors++;
919 continue;
920 }
921 /*
922 * Packet has too many fragments - defrag into new mbuf
923 * cluster
924 */
925 if (error) {
926 m = m_defrag(m0, MB_DONTWAIT);
927 if (m == NULL) {
928 m_freem(m0);
929 sc->tx_errors++;
930 continue;
931 }
a072e131
JS
932 m0 = m;
933
934 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
935 nv_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
936 if (error) {
937 m_freem(m);
938 sc->tx_errors++;
939 continue;
940 }
941 }
942 /* Do sync on DMA bounce buffer */
943 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
944
945 buf->mbuf = m0;
946 txdata.ulNumberOfElements = desc->numfrags;
947 txdata.pvID = (PVOID)desc;
948
949 /* Put fragments into API element list */
950 txdata.ulTotalLength = buf->mbuf->m_len;
951 for (i = 0; i < desc->numfrags; i++) {
952 txdata.sElement[i].ulLength = (ulong)desc->frags[i].ds_len;
953 txdata.sElement[i].pPhysical = (PVOID)desc->frags[i].ds_addr;
954 }
955
956 /* Send packet to Nvidia API for transmission */
957 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata);
958
959 switch (error) {
960 case ADAPTERERR_NONE:
961 /* Packet was queued in API TX queue successfully */
962 sc->pending_txs++;
963 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE;
964 break;
965
966 case ADAPTERERR_TRANSMIT_QUEUE_FULL:
967 /* The API TX queue is full - requeue the packet */
968 device_printf(sc->dev, "nv_ifstart: transmit queue is full\n");
969 ifp->if_flags |= IFF_OACTIVE;
970 bus_dmamap_unload(sc->mtag, buf->map);
a072e131 971 buf->mbuf = NULL;
9dda2746 972 m_freem(m0); /* XXX requeue */
a072e131
JS
973 return;
974
975 default:
976 /* The API failed to queue/send the packet so dump it */
977 device_printf(sc->dev, "nv_ifstart: transmit error\n");
978 bus_dmamap_unload(sc->mtag, buf->map);
979 m_freem(buf->mbuf);
980 buf->mbuf = NULL;
981 sc->tx_errors++;
982 return;
983 }
984 /* Set watchdog timer. */
985 ifp->if_timer = 8;
986
987 /* Copy packet to BPF tap */
988 BPF_MTAP(ifp, m0);
989 }
990 ifp->if_flags |= IFF_OACTIVE;
991
992 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_ifstart - exit\n");
993}
994
995/* Handle IOCTL events */
996static int
997nv_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
998{
999 struct nv_softc *sc = ifp->if_softc;
1000 struct ifreq *ifr = (struct ifreq *) data;
1001 struct mii_data *mii;
1002 int error = 0;
1003
a072e131
JS
1004 DEBUGOUT(NV_DEBUG_IOCTL, "nv: nv_ioctl - entry\n");
1005
1006 switch (command) {
1007 case SIOCSIFMTU:
1008 /* Set MTU size */
1009 if (ifp->if_mtu == ifr->ifr_mtu)
1010 break;
e5829d43 1011 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) {
a072e131 1012 ifp->if_mtu = ifr->ifr_mtu;
78195a76
MD
1013 nv_stop(sc);
1014 nv_init(sc);
a072e131
JS
1015 } else
1016 error = EINVAL;
1017 break;
1018
1019 case SIOCSIFFLAGS:
1020 /* Setup interface flags */
1021 if (ifp->if_flags & IFF_UP) {
1022 if ((ifp->if_flags & IFF_RUNNING) == 0) {
78195a76 1023 nv_init(sc);
a072e131
JS
1024 break;
1025 }
1026 } else {
1027 if (ifp->if_flags & IFF_RUNNING) {
78195a76 1028 nv_stop(sc);
a072e131
JS
1029 break;
1030 }
1031 }
1032
1033 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
1034 nv_setmulti(sc);
1035 break;
1036
1037 case SIOCADDMULTI:
1038 case SIOCDELMULTI:
1039 /* Setup multicast filter */
1040 if (ifp->if_flags & IFF_RUNNING) {
1041 nv_setmulti(sc);
1042 }
1043 break;
1044 case SIOCGIFMEDIA:
1045 case SIOCSIFMEDIA:
1046 /* Get/Set interface media parameters */
1047 mii = device_get_softc(sc->miibus);
1048 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1049 break;
1050
1051 default:
1052 /* Everything else we forward to generic ether ioctl */
0b4a1d3a 1053 error = ether_ioctl(ifp, command, data);
a072e131
JS
1054 break;
1055 }
1056
1057 DEBUGOUT(NV_DEBUG_IOCTL, "nv: nv_ioctl - exit\n");
1058
a072e131
JS
1059 return (error);
1060}
1061
59a5a75e
MD
1062/*
1063 * Interrupt service routine. The serializer has already been entered
1064 * since we installed it in our bus_setup_intr() call.
1065 */
a072e131
JS
1066static void
1067nv_intr(void *arg)
1068{
1069 struct nv_softc *sc = arg;
1070 struct ifnet *ifp = &sc->sc_if;
1071
1072 DEBUGOUT(NV_DEBUG_INTERRUPT, "nv: nv_intr - entry\n");
1073
59a5a75e
MD
1074 /*
1075 * Handle an interrupt event. Unfortunately the nvidia API
1076 * does not support interrupt disablement when polling, so we
1077 * have to re-enable after the query masks them off.
1078 */
a072e131
JS
1079 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) {
1080 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
59a5a75e 1081#if 1
78195a76 1082 lwkt_serialize_handler_enable(ifp->if_serializer);
a072e131 1083 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
59a5a75e
MD
1084#else
1085 if ((ifp->if_flags & IFF_POLLING) == 0) {
78195a76 1086 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
1087 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1088 }
1089#endif
a072e131 1090 }
c7f5b673 1091 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1092 nv_ifstart(ifp);
a072e131
JS
1093
1094 /* If no pending packets we don't need a timeout */
1095 if (sc->pending_txs == 0)
1096 sc->sc_if.if_timer = 0;
1097
1098 DEBUGOUT(NV_DEBUG_INTERRUPT, "nv: nv_intr - exit\n");
a072e131
JS
1099}
1100
59a5a75e
MD
1101/*
1102 * Setup multicast filters
1103 *
1104 * Serialized on call
1105 */
a072e131
JS
1106static void
1107nv_setmulti(struct nv_softc *sc)
1108{
1109 struct ifnet *ifp;
1110 struct ifmultiaddr *ifma;
1111 PACKET_FILTER hwfilter;
1112 int i;
1113 u_int8_t oraddr[6];
1114 u_int8_t andaddr[6];
1115
a072e131
JS
1116 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_setmulti - entry\n");
1117
1118 ifp = &sc->sc_if;
1119
1120 /* Initialize filter */
1121 hwfilter.ulFilterFlags = 0;
1122 for (i = 0; i < 6; i++) {
1123 hwfilter.acMulticastAddress[i] = 0;
1124 hwfilter.acMulticastMask[i] = 0;
1125 }
1126
1127 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1128 /* Accept all packets */
1129 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS;
1130 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
a072e131
JS
1131 return;
1132 }
1133 /* Setup multicast filter */
1134 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1135 u_char *addrp;
1136
1137 if (ifma->ifma_addr->sa_family != AF_LINK)
1138 continue;
1139
1140 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1141 for (i = 0; i < 6; i++) {
1142 u_int8_t mcaddr = addrp[i];
1143 andaddr[i] &= mcaddr;
1144 oraddr[i] |= mcaddr;
1145 }
1146 }
1147 for (i = 0; i < 6; i++) {
1148 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i];
1149 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]);
1150 }
1151
1152 /* Send filter to NVIDIA API */
1153 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1154
a072e131 1155 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_setmulti - exit\n");
a072e131
JS
1156}
1157
59a5a75e
MD
1158/*
1159 * Change the current media/mediaopts
1160 *
1161 * Serialized on call
1162 */
a072e131
JS
1163static int
1164nv_ifmedia_upd(struct ifnet *ifp)
1165{
1166 struct nv_softc *sc = ifp->if_softc;
1167 struct mii_data *mii;
1168
1169 DEBUGOUT(NV_DEBUG_MII, "nv: nv_ifmedia_upd\n");
1170
1171 mii = device_get_softc(sc->miibus);
1172
1173 if (mii->mii_instance) {
1174 struct mii_softc *miisc;
1175 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1176 miisc = LIST_NEXT(miisc, mii_list)) {
1177 mii_phy_reset(miisc);
1178 }
1179 }
1180 mii_mediachg(mii);
1181
1182 return (0);
1183}
1184
59a5a75e
MD
1185/*
1186 * Update current miibus PHY status of media
1187 *
1188 * Serialized on call
1189 */
a072e131
JS
1190static void
1191nv_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1192{
1193 struct nv_softc *sc;
1194 struct mii_data *mii;
1195
1196 DEBUGOUT(NV_DEBUG_MII, "nv: nv_ifmedia_sts\n");
1197
1198 sc = ifp->if_softc;
1199 mii = device_get_softc(sc->miibus);
1200 mii_pollstat(mii);
1201
1202 ifmr->ifm_active = mii->mii_media_active;
1203 ifmr->ifm_status = mii->mii_media_status;
a072e131
JS
1204}
1205
1206/* miibus tick timer - maintain link status */
1207static void
1208nv_tick(void *xsc)
1209{
1210 struct nv_softc *sc = xsc;
1211 struct mii_data *mii;
1212 struct ifnet *ifp;
1213
a072e131 1214 ifp = &sc->sc_if;
78195a76 1215 lwkt_serialize_enter(ifp->if_serializer);
a072e131
JS
1216 nv_update_stats(sc);
1217
1218 mii = device_get_softc(sc->miibus);
1219 mii_tick(mii);
1220
59a5a75e 1221 if ((mii->mii_media_status & IFM_ACTIVE) &&
a072e131 1222 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
c7f5b673 1223 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1224 nv_ifstart(ifp);
a072e131 1225 }
204b91ae 1226 callout_reset(&sc->nv_stat_timer, hz, nv_tick, sc);
78195a76 1227 lwkt_serialize_exit(ifp->if_serializer);
a072e131
JS
1228}
1229
1230/* Update ifnet data structure with collected interface stats from API */
1231static void
1232nv_update_stats(struct nv_softc *sc)
1233{
1234 struct ifnet *ifp = &sc->sc_if;
1235 ADAPTER_STATS stats;
1236
a072e131
JS
1237 if (sc->hwapi) {
1238 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats);
1239
1240 ifp->if_ipackets = stats.ulSuccessfulReceptions;
1241 ifp->if_ierrors = stats.ulMissedFrames +
1242 stats.ulFailedReceptions +
1243 stats.ulCRCErrors +
1244 stats.ulFramingErrors +
1245 stats.ulOverFlowErrors;
1246
1247 ifp->if_opackets = stats.ulSuccessfulTransmissions;
1248 ifp->if_oerrors = sc->tx_errors +
1249 stats.ulFailedTransmissions +
1250 stats.ulRetryErrors +
1251 stats.ulUnderflowErrors +
1252 stats.ulLossOfCarrierErrors +
1253 stats.ulLateCollisionErrors;
1254
1255 ifp->if_collisions = stats.ulLateCollisionErrors;
1256 }
a072e131
JS
1257}
1258
1259/* miibus Read PHY register wrapper - calls Nvidia API entry point */
1260static int
1261nv_miibus_readreg(device_t dev, int phy, int reg)
1262{
1263 struct nv_softc *sc = device_get_softc(dev);
e5829d43 1264 ULONG data;
a072e131
JS
1265
1266 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_readreg - entry\n");
1267
1268 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data);
1269
1270 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_readreg - exit\n");
1271
1272 return (data);
1273}
1274
1275/* miibus Write PHY register wrapper - calls Nvidia API entry point */
1276static void
1277nv_miibus_writereg(device_t dev, int phy, int reg, int data)
1278{
1279 struct nv_softc *sc = device_get_softc(dev);
1280
1281 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_writereg - entry\n");
1282
1283 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data);
1284
1285 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_writereg - exit\n");
a072e131
JS
1286}
1287
1288/* Watchdog timer to prevent PHY lockups */
1289static void
1290nv_watchdog(struct ifnet *ifp)
1291{
1292 struct nv_softc *sc = ifp->if_softc;
1293
9dda2746
MD
1294 device_printf(sc->dev, "device timeout (%d) flags %d\n",
1295 sc->pending_txs, ifp->if_flags & IFF_OACTIVE);
a072e131
JS
1296
1297 sc->tx_errors++;
1298
78195a76 1299 nv_stop(sc);
a072e131 1300 ifp->if_flags &= ~IFF_RUNNING;
78195a76 1301 nv_init(sc);
a072e131 1302
c7f5b673 1303 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1304 nv_ifstart(ifp);
a072e131
JS
1305}
1306
1307/* --- Start of NVOSAPI interface --- */
1308
1309/* Allocate DMA enabled general use memory for API */
e5829d43
JS
1310static NV_SINT32
1311nv_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem)
a072e131
JS
1312{
1313 struct nv_softc *sc;
1314 bus_addr_t mem_physical;
1315
1316 DEBUGOUT(NV_DEBUG_API, "nv: nv_osalloc - %d\n", mem->uiLength);
1317
1318 sc = (struct nv_softc *)ctx;
1319
1320 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF,
1321 M_NOWAIT | M_ZERO, 0, ~0, PAGE_SIZE, 0);
1322
1323 if (!mem->pLogical) {
1324 device_printf(sc->dev, "memory allocation failed\n");
1325 return (0);
1326 }
1327 memset(mem->pLogical, 0, (ulong)mem->uiLength);
1328 mem_physical = vtophys(mem->pLogical);
1329 mem->pPhysical = (PVOID)mem_physical;
1330
e5829d43
JS
1331 DEBUGOUT(NV_DEBUG_API, "nv: nv_osalloc %p/%p - %d\n",
1332 mem->pLogical, mem->pPhysical, mem->uiLength);
a072e131
JS
1333
1334 return (1);
1335}
1336
1337/* Free allocated memory */
e5829d43
JS
1338static NV_SINT32
1339nv_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem)
a072e131 1340{
e5829d43
JS
1341 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfree - %p - %d\n",
1342 mem->pLogical, mem->uiLength);
a072e131
JS
1343
1344 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF);
1345 return (1);
1346}
1347
1348/* Copied directly from nvnet.c */
e5829d43
JS
1349static NV_SINT32
1350nv_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
a072e131
JS
1351{
1352 MEMORY_BLOCK mem_block;
1353
1354 DEBUGOUT(NV_DEBUG_API, "nv: nv_osallocex\n");
1355
1356 mem_block_ex->pLogical = NULL;
1357 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength;
1358
1359 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) &&
1360 (mem_block_ex->AlignmentSize > 1)) {
1361 DEBUGOUT(NV_DEBUG_API, " aligning on %d\n",
1362 mem_block_ex->AlignmentSize);
1363 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize;
1364 }
1365 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1366
1367 if (nv_osalloc(ctx, &mem_block) == 0) {
1368 return (0);
1369 }
1370 mem_block_ex->pLogicalOrig = mem_block.pLogical;
e5829d43 1371 mem_block_ex->pPhysicalOrigLow = (uintptr_t)mem_block.pPhysical;
a072e131
JS
1372 mem_block_ex->pPhysicalOrigHigh = 0;
1373
1374 mem_block_ex->pPhysical = mem_block.pPhysical;
1375 mem_block_ex->pLogical = mem_block.pLogical;
1376
1377 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) {
1378 unsigned int offset;
1379 offset = mem_block_ex->pPhysicalOrigLow & (mem_block_ex->AlignmentSize - 1);
1380
1381 if (offset) {
e5829d43 1382 mem_block_ex->pPhysical = (PVOID)((uintptr_t)mem_block_ex->pPhysical +
a072e131 1383 mem_block_ex->AlignmentSize - offset);
e5829d43 1384 mem_block_ex->pLogical = (PVOID)((uintptr_t)mem_block_ex->pLogical +
a072e131
JS
1385 mem_block_ex->AlignmentSize - offset);
1386 } /* if (offset) */
1387 } /* if (mem_block_ex->uiLength !=
1388 * mem_block_ex->uiLengthOrig) */
1389 return (1);
1390}
1391
1392/* Copied directly from nvnet.c */
e5829d43
JS
1393static NV_SINT32
1394nv_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
a072e131
JS
1395{
1396 MEMORY_BLOCK mem_block;
1397
1398 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfreeex\n");
1399
1400 mem_block.pLogical = mem_block_ex->pLogicalOrig;
e5829d43 1401 mem_block.pPhysical = (PVOID)((uintptr_t)mem_block_ex->pPhysicalOrigLow);
a072e131
JS
1402 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1403
1404 return (nv_osfree(ctx, &mem_block));
1405}
1406
1407/* Clear memory region */
e5829d43
JS
1408static NV_SINT32
1409nv_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length)
a072e131
JS
1410{
1411 DEBUGOUT(NV_DEBUG_API, "nv: nv_osclear\n");
1412 memset(mem, 0, length);
1413 return (1);
1414}
1415
1416/* Sleep for a tick */
e5829d43
JS
1417static NV_SINT32
1418nv_osdelay(PNV_VOID ctx, NV_UINT32 usec)
a072e131 1419{
59a5a75e
MD
1420 if (usec >= 1000000 / hz) {
1421 tsleep(nv_osdelay, 0, "nvdelay", (usec * hz / 1000000) + 1);
1422 } else {
1423 DELAY(usec);
1424 }
a072e131
JS
1425 return (1);
1426}
1427
1428/* Allocate memory for rx buffer */
e5829d43
JS
1429static NV_SINT32
1430nv_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id)
a072e131
JS
1431{
1432 struct nv_softc *sc = ctx;
1433 struct nv_rx_desc *desc;
1434 struct nv_map_buffer *buf;
1435 int error;
1436
a072e131
JS
1437 DEBUGOUT(NV_DEBUG_API, "nv: nv_osallocrxbuf\n");
1438
1439 if (sc->pending_rxs == RX_RING_SIZE) {
1440 device_printf(sc->dev, "rx ring buffer is full\n");
1441 goto fail;
1442 }
1443 desc = sc->rx_desc + sc->cur_rx;
1444 buf = &desc->buf;
1445
1446 if (buf->mbuf == NULL) {
1447 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1448 if (buf->mbuf == NULL) {
1449 device_printf(sc->dev, "failed to allocate memory\n");
1450 goto fail;
1451 }
1452 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1453 m_adj(buf->mbuf, ETHER_ALIGN);
1454
1455 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1456 nv_dmamap_rx_cb, &desc->paddr, 0);
1457 if (error) {
1458 device_printf(sc->dev, "failed to dmamap mbuf\n");
1459 m_freem(buf->mbuf);
1460 buf->mbuf = NULL;
1461 goto fail;
1462 }
1463 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1464 desc->buflength = buf->mbuf->m_len;
1465 desc->vaddr = mtod(buf->mbuf, PVOID);
1466 }
1467 sc->pending_rxs++;
1468 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE;
1469
1470 mem->pLogical = (void *)desc->vaddr;
1471 mem->pPhysical = (void *)desc->paddr;
1472 mem->uiLength = desc->buflength;
1473 *id = (void *)desc;
1474
a072e131 1475 return (1);
e5829d43 1476fail:
e5829d43 1477 return (0);
a072e131
JS
1478}
1479
1480
1481/* Free the rx buffer */
e5829d43
JS
1482static NV_SINT32
1483nv_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id)
a072e131
JS
1484{
1485 struct nv_softc *sc = ctx;
1486 struct nv_rx_desc *desc;
1487 struct nv_map_buffer *buf;
1488
a072e131
JS
1489 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfreerxbuf\n");
1490
1491 desc = (struct nv_rx_desc *) id;
1492 buf = &desc->buf;
1493
1494 if (buf->mbuf) {
1495 bus_dmamap_unload(sc->mtag, buf->map);
1496 bus_dmamap_destroy(sc->mtag, buf->map);
1497 m_freem(buf->mbuf);
1498 }
1499 sc->pending_rxs--;
1500 buf->mbuf = NULL;
1501
a072e131
JS
1502 return (1);
1503}
1504
1505/* This gets called by the Nvidia API after our TX packet has been sent */
e5829d43
JS
1506static NV_SINT32
1507nv_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success)
a072e131
JS
1508{
1509 struct nv_softc *sc = ctx;
1510 struct nv_map_buffer *buf;
1511 struct nv_tx_desc *desc = (struct nv_tx_desc *) id;
1512 struct ifnet *ifp;
1513
a072e131
JS
1514 DEBUGOUT(NV_DEBUG_API, "nv: nv_ospackettx\n");
1515
1516 ifp = &sc->sc_if;
a072e131 1517 buf = &desc->buf;
e5829d43 1518 sc->pending_txs--;
a072e131 1519
e5829d43 1520 /* Unload and free mbuf cluster */
a072e131
JS
1521 if (buf->mbuf == NULL)
1522 goto fail;
1523
1524 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
1525 bus_dmamap_unload(sc->mtag, buf->map);
1526 m_freem(buf->mbuf);
1527 buf->mbuf = NULL;
1528
9dda2746
MD
1529 /*
1530 * Make sure we are clear to go if we previously stalled due
1531 * to a full ring.
1532 */
1533 if (sc->pending_txs < TX_RING_SIZE) {
1534 ifp->if_flags &= ~IFF_OACTIVE;
1535 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1536 nv_ifstart(ifp);
9dda2746 1537 }
a072e131 1538fail:
a072e131
JS
1539 return (1);
1540}
1541
1542/* This gets called by the Nvidia API when a new packet has been received */
1543/* XXX What is newbuf used for? XXX */
e5829d43
JS
1544static NV_SINT32
1545nv_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success,
1546 NV_UINT8 *newbuf, NV_UINT8 priority)
a072e131
JS
1547{
1548 struct nv_softc *sc = ctx;
1549 struct ifnet *ifp;
1550 struct nv_rx_desc *desc;
1551 struct nv_map_buffer *buf;
1552 ADAPTER_READ_DATA *readdata;
a072e131
JS
1553
1554 DEBUGOUT(NV_DEBUG_API, "nv: nv_ospacketrx\n");
1555
1556 ifp = &sc->sc_if;
1557
1558 readdata = (ADAPTER_READ_DATA *) data;
1559 desc = readdata->pvID;
1560 buf = &desc->buf;
1561 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1562
1563 if (success) {
1564 /* Sync DMA bounce buffer. */
1565 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1566
1567 /* First mbuf in packet holds the ethernet and packet headers */
1568 buf->mbuf->m_pkthdr.rcvif = ifp;
1569 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len = readdata->ulTotalLength;
1570
1571 bus_dmamap_unload(sc->mtag, buf->map);
1572
1573 /* Give mbuf to OS. */
78195a76 1574 ifp->if_input(ifp, buf->mbuf);
a072e131
JS
1575 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH)
1576 ifp->if_imcasts++;
1577
1578 /* Blat the mbuf pointer, kernel will free the mbuf cluster */
1579 buf->mbuf = NULL;
1580 } else {
1581 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1582 bus_dmamap_unload(sc->mtag, buf->map);
1583 m_freem(buf->mbuf);
1584 buf->mbuf = NULL;
1585 }
1586
1587 sc->cur_rx = desc - sc->rx_desc;
1588 sc->pending_rxs--;
1589
a072e131
JS
1590 return (1);
1591}
1592
1593/* This gets called by NVIDIA API when the PHY link state changes */
e5829d43
JS
1594static NV_SINT32
1595nv_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled)
a072e131
JS
1596{
1597 struct nv_softc *sc = (struct nv_softc *)ctx;
1598 struct ifnet *ifp;
1599
1600 DEBUGOUT(NV_DEBUG_API, "nv: nv_oslinkchg\n");
1601
1602 ifp = &sc->sc_if;
1603
1604 if (enabled)
1605 ifp->if_flags |= IFF_UP;
1606 else
1607 ifp->if_flags &= ~IFF_UP;
1608
1609
1610 return (1);
1611}
1612
1613
1614/* Setup a watchdog timer */
e5829d43
JS
1615static NV_SINT32
1616nv_osalloctimer(PNV_VOID ctx, PNV_VOID *timer)
a072e131
JS
1617{
1618 struct nv_softc *sc = (struct nv_softc *)ctx;
1619
1620 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osalloctimer\n");
1621
01a09a77 1622 callout_init(&sc->ostimer);
a072e131
JS
1623 *timer = &sc->ostimer;
1624
1625 return (1);
1626}
1627
1628/* Free the timer */
e5829d43
JS
1629static NV_SINT32
1630nv_osfreetimer(PNV_VOID ctx, PNV_VOID timer)
a072e131
JS
1631{
1632 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osfreetimer\n");
1633
1634 return (1);
1635}
1636
1637/* Setup timer parameters */
e5829d43
JS
1638static NV_SINT32
1639nv_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters)
a072e131
JS
1640{
1641 struct nv_softc *sc = (struct nv_softc *)ctx;
1642
1643 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osinittimer\n");
1644
1645 sc->ostimer_func = func;
1646 sc->ostimer_params = parameters;
1647
1648 return (1);
1649}
1650
78195a76
MD
1651static void
1652nv_ostimer_callback(void *data)
1653{
1654 struct nv_softc *sc = data;
1655 struct ifnet *ifp = &sc->sc_if;
1656
1657 lwkt_serialize_enter(ifp->if_serializer);
1658 sc->ostimer_func(sc->ostimer_params);
1659 lwkt_serialize_exit(ifp->if_serializer);
1660}
1661
59a5a75e
MD
1662/*
1663 * Set the timer to go off
1664 *
1665 * XXX what the hell are the units for 'delay' ? They sure aren't ticks!
1666 */
e5829d43
JS
1667static NV_SINT32
1668nv_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay)
a072e131
JS
1669{
1670 struct nv_softc *sc = ctx;
1671
1672 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ossettimer\n");
59a5a75e 1673 printf("nv_ossettimer %d\n", (int)delay);
a072e131 1674
78195a76 1675 callout_reset(&sc->ostimer, delay, nv_ostimer_callback, sc);
a072e131
JS
1676
1677 return (1);
1678}
1679
1680/* Cancel the timer */
e5829d43
JS
1681static NV_SINT32
1682nv_oscanceltimer(PNV_VOID ctx, PNV_VOID timer)
a072e131
JS
1683{
1684 struct nv_softc *sc = ctx;
1685
1686 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_oscanceltimer\n");
1687
01a09a77 1688 callout_stop(&sc->ostimer);
a072e131
JS
1689
1690 return (1);
1691}
1692
e5829d43
JS
1693static NV_SINT32
1694nv_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id, NV_UINT8 *newbuffer,
1695 NV_UINT8 priority)
a072e131
JS
1696{
1697 /* Not implemented */
1698 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ospreprocpkt\n");
1699
1700 return (1);
1701}
1702
e5829d43
JS
1703static PNV_VOID
1704nv_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata)
a072e131
JS
1705{
1706 /* Not implemented */
1707 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ospreprocpkt\n");
1708
1709 return (NULL);
1710}
1711
e5829d43
JS
1712static NV_SINT32
1713nv_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno)
a072e131
JS
1714{
1715 /* Not implemented */
1716 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osindicatepkt\n");
1717
1718 return (1);
1719}
1720
1721/* Allocate mutex context (already done in nv_attach) */
e5829d43
JS
1722static NV_SINT32
1723nv_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock)
a072e131
JS
1724{
1725 struct nv_softc *sc = (struct nv_softc *)ctx;
1726
1727 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockalloc\n");
1728
1729 *pLock = (void **)sc;
1730
1731 return (1);
1732}
1733
1734/* Obtain a spin lock */
e5829d43
JS
1735static NV_SINT32
1736nv_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
a072e131
JS
1737{
1738 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockacquire\n");
1739
1740 NV_OSLOCK((struct nv_softc *)lock);
1741
1742 return (1);
1743}
1744
1745/* Release lock */
e5829d43
JS
1746static NV_SINT32
1747nv_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
a072e131
JS
1748{
1749 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockrelease\n");
1750
1751 NV_OSUNLOCK((struct nv_softc *)lock);
1752
1753 return (1);
1754}
1755
1756/* I have no idea what this is for */
e5829d43
JS
1757static PNV_VOID
1758nv_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata)
a072e131
JS
1759{
1760 /* Not implemented */
1761 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_osreturnbufvirt\n");
1762 panic("nv: nv_osreturnbufvirtual not implemented\n");
1763
1764 return (NULL);
1765}
1766
1767
1768/* --- End on NVOSAPI interface --- */