Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / sis / if_sis.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
78195a76 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.30 2005/11/28 17:13:44 dillon Exp $
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34 */
35
36/*
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
39 *
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
42 *
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48/*
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
56 *
57 * The only downside to this chipset is that RX descriptors must be
58 * longword aligned.
59 */
60
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61#include "opt_polling.h"
62
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63#include <sys/param.h>
64#include <sys/systm.h>
65#include <sys/sockio.h>
66#include <sys/mbuf.h>
67#include <sys/malloc.h>
68#include <sys/kernel.h>
69#include <sys/socket.h>
70#include <sys/sysctl.h>
78195a76 71#include <sys/serialize.h>
3b7f6d2b 72#include <sys/thread2.h>
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73
74#include <net/if.h>
e25db1f0 75#include <net/ifq_var.h>
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76#include <net/if_arp.h>
77#include <net/ethernet.h>
78#include <net/if_dl.h>
79#include <net/if_media.h>
80#include <net/if_types.h>
1f2de5d4 81#include <net/vlan/if_vlan_var.h>
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82
83#include <net/bpf.h>
84
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85#include <machine/bus_pio.h>
86#include <machine/bus_memio.h>
87#include <machine/bus.h>
88#include <machine/resource.h>
89#include <sys/bus.h>
90#include <sys/rman.h>
91
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92#include <dev/netif/mii_layer/mii.h>
93#include <dev/netif/mii_layer/miivar.h>
984263bc 94
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95#include <bus/pci/pcireg.h>
96#include <bus/pci/pcivar.h>
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97
98#define SIS_USEIOSPACE
99
1f2de5d4 100#include "if_sisreg.h"
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101
102/* "controller miibus0" required. See GENERIC if you get errors here. */
103#include "miibus_if.h"
104
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105/*
106 * Various supported device vendors/types and their names.
107 */
108static struct sis_type sis_devs[] = {
109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
49eef4c6 111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
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112 { 0, 0, NULL }
113};
114
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115static int sis_probe(device_t);
116static int sis_attach(device_t);
117static int sis_detach(device_t);
118
119static int sis_newbuf(struct sis_softc *, struct sis_desc *,
120 struct mbuf *);
121static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
122static void sis_rxeof(struct sis_softc *);
123static void sis_rxeoc(struct sis_softc *);
124static void sis_txeof(struct sis_softc *);
125static void sis_intr(void *);
126static void sis_tick(void *);
127static void sis_start(struct ifnet *);
bd4539cc 128static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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129static void sis_init(void *);
130static void sis_stop(struct sis_softc *);
131static void sis_watchdog(struct ifnet *);
132static void sis_shutdown(device_t);
133static int sis_ifmedia_upd(struct ifnet *);
134static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135
136static uint16_t sis_reverse(uint16_t);
137static void sis_delay(struct sis_softc *);
138static void sis_eeprom_idle(struct sis_softc *);
139static void sis_eeprom_putbyte(struct sis_softc *, int);
140static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
141static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
984263bc 142#ifdef __i386__
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143static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
144static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
145static device_t sis_find_bridge(device_t);
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146#endif
147
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148static void sis_mii_sync(struct sis_softc *);
149static void sis_mii_send(struct sis_softc *, uint32_t, int);
150static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
151static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
152static int sis_miibus_readreg(device_t, int, int);
153static int sis_miibus_writereg(device_t, int, int, int);
154static void sis_miibus_statchg(device_t);
155
156static void sis_setmulti_sis(struct sis_softc *);
157static void sis_setmulti_ns(struct sis_softc *);
158static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
159static void sis_reset(struct sis_softc *);
160static int sis_list_rx_init(struct sis_softc *);
161static int sis_list_tx_init(struct sis_softc *);
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162
163static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
164static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
165static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
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166#ifdef DEVICE_POLLING
167static poll_handler_t sis_poll;
168#endif
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169#ifdef SIS_USEIOSPACE
170#define SIS_RES SYS_RES_IOPORT
171#define SIS_RID SIS_PCI_LOIO
172#else
173#define SIS_RES SYS_RES_MEMORY
174#define SIS_RID SIS_PCI_LOMEM
175#endif
176
177static device_method_t sis_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, sis_probe),
180 DEVMETHOD(device_attach, sis_attach),
181 DEVMETHOD(device_detach, sis_detach),
182 DEVMETHOD(device_shutdown, sis_shutdown),
183
184 /* bus interface */
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187
188 /* MII interface */
189 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
190 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
191 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
192
193 { 0, 0 }
194};
195
196static driver_t sis_driver = {
197 "sis",
198 sis_methods,
199 sizeof(struct sis_softc)
200};
201
202static devclass_t sis_devclass;
203
32832096 204DECLARE_DUMMY_MODULE(if_sis);
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205DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
206DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
207
208#define SIS_SETBIT(sc, reg, x) \
49eef4c6 209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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210
211#define SIS_CLRBIT(sc, reg, x) \
49eef4c6 212 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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213
214#define SIO_SET(x) \
215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
216
217#define SIO_CLR(x) \
218 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
219
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220static void
221sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
222{
223 struct sis_desc *r;
224
225 r = arg;
226 r->sis_next = segs->ds_addr;
227}
228
229static void
230sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
231{
232 struct sis_desc *r;
233
234 r = arg;
235 r->sis_ptr = segs->ds_addr;
236}
237
238static void
239sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
240{
241 uint32_t *p;
242
243 p = arg;
244 *p = segs->ds_addr;
245}
246
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247/*
248 * Routine to reverse the bits in a word. Stolen almost
249 * verbatim from /usr/games/fortune.
250 */
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251static uint16_t
252sis_reverse(uint16_t n)
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253{
254 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
255 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
256 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
257 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
258
259 return(n);
260}
261
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262static void
263sis_delay(struct sis_softc *sc)
984263bc 264{
49eef4c6 265 int idx;
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266
267 for (idx = (300 / 33) + 1; idx > 0; idx--)
268 CSR_READ_4(sc, SIS_CSR);
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269}
270
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271static void
272sis_eeprom_idle(struct sis_softc *sc)
984263bc 273{
49eef4c6 274 int i;
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275
276 SIO_SET(SIS_EECTL_CSEL);
277 sis_delay(sc);
278 SIO_SET(SIS_EECTL_CLK);
279 sis_delay(sc);
280
281 for (i = 0; i < 25; i++) {
282 SIO_CLR(SIS_EECTL_CLK);
283 sis_delay(sc);
284 SIO_SET(SIS_EECTL_CLK);
285 sis_delay(sc);
286 }
287
288 SIO_CLR(SIS_EECTL_CLK);
289 sis_delay(sc);
290 SIO_CLR(SIS_EECTL_CSEL);
291 sis_delay(sc);
292 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
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293}
294
295/*
296 * Send a read command and address to the EEPROM, check for ACK.
297 */
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298static void
299sis_eeprom_putbyte(struct sis_softc *sc, int addr)
984263bc 300{
49eef4c6 301 int d, i;
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302
303 d = addr | SIS_EECMD_READ;
304
305 /*
306 * Feed in each bit and stobe the clock.
307 */
308 for (i = 0x400; i; i >>= 1) {
49eef4c6 309 if (d & i)
984263bc 310 SIO_SET(SIS_EECTL_DIN);
49eef4c6 311 else
984263bc 312 SIO_CLR(SIS_EECTL_DIN);
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313 sis_delay(sc);
314 SIO_SET(SIS_EECTL_CLK);
315 sis_delay(sc);
316 SIO_CLR(SIS_EECTL_CLK);
317 sis_delay(sc);
318 }
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319}
320
321/*
322 * Read a word of data stored in the EEPROM at address 'addr.'
323 */
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324static void
325sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
984263bc 326{
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327 int i;
328 uint16_t word = 0;
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329
330 /* Force EEPROM to idle state. */
331 sis_eeprom_idle(sc);
332
333 /* Enter EEPROM access mode. */
334 sis_delay(sc);
335 SIO_CLR(SIS_EECTL_CLK);
336 sis_delay(sc);
337 SIO_SET(SIS_EECTL_CSEL);
338 sis_delay(sc);
339
340 /*
341 * Send address of word we want to read.
342 */
343 sis_eeprom_putbyte(sc, addr);
344
345 /*
346 * Start reading bits from EEPROM.
347 */
348 for (i = 0x8000; i; i >>= 1) {
349 SIO_SET(SIS_EECTL_CLK);
350 sis_delay(sc);
351 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
352 word |= i;
353 sis_delay(sc);
354 SIO_CLR(SIS_EECTL_CLK);
355 sis_delay(sc);
356 }
357
358 /* Turn off EEPROM access mode. */
359 sis_eeprom_idle(sc);
360
361 *dest = word;
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362}
363
364/*
365 * Read a sequence of words from the EEPROM.
366 */
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367static void
368sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 369{
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370 int i;
371 uint16_t word = 0, *ptr;
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372
373 for (i = 0; i < cnt; i++) {
374 sis_eeprom_getword(sc, off + i, &word);
49eef4c6 375 ptr = (uint16_t *)(dest + (i * 2));
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376 if (swap)
377 *ptr = ntohs(word);
378 else
379 *ptr = word;
380 }
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381}
382
383#ifdef __i386__
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384static device_t
385sis_find_bridge(device_t dev)
984263bc 386{
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387 devclass_t pci_devclass;
388 device_t *pci_devices;
389 int pci_count = 0;
390 device_t *pci_children;
391 int pci_childcount = 0;
392 device_t *busp, *childp;
393 device_t child = NULL;
394 int i, j;
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395
396 if ((pci_devclass = devclass_find("pci")) == NULL)
397 return(NULL);
398
399 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
400
401 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
402 pci_childcount = 0;
403 device_get_children(*busp, &pci_children, &pci_childcount);
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404 for (j = 0, childp = pci_children; j < pci_childcount;
405 j++, childp++) {
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406 if (pci_get_vendor(*childp) == SIS_VENDORID &&
407 pci_get_device(*childp) == 0x0008) {
408 child = *childp;
409 goto done;
410 }
411 }
412 }
413
414done:
415 free(pci_devices, M_TEMP);
416 free(pci_children, M_TEMP);
417 return(child);
418}
419
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420static void
421sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
422 int cnt)
984263bc 423{
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424 device_t bridge;
425 uint8_t reg;
426 int i;
427 bus_space_tag_t btag;
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428
429 bridge = sis_find_bridge(dev);
430 if (bridge == NULL)
431 return;
432 reg = pci_read_config(bridge, 0x48, 1);
433 pci_write_config(bridge, 0x48, reg|0x40, 1);
434
435 /* XXX */
436 btag = I386_BUS_SPACE_IO;
437
438 for (i = 0; i < cnt; i++) {
439 bus_space_write_1(btag, 0x0, 0x70, i + off);
440 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
441 }
442
443 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
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444}
445
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446static void
447sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
984263bc 448{
49eef4c6 449 uint32_t filtsave, csrsave;
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450
451 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
452 csrsave = CSR_READ_4(sc, SIS_CSR);
453
454 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
455 CSR_WRITE_4(sc, SIS_CSR, 0);
456
457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
458
459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
49eef4c6 460 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 461 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
49eef4c6 462 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
49eef4c6 464 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
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465
466 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
467 CSR_WRITE_4(sc, SIS_CSR, csrsave);
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468}
469#endif
470
471/*
472 * Sync the PHYs by setting data bit and strobing the clock 32 times.
473 */
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474static void
475sis_mii_sync(struct sis_softc *sc)
984263bc 476{
49eef4c6 477 int i;
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478
479 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
480
481 for (i = 0; i < 32; i++) {
482 SIO_SET(SIS_MII_CLK);
483 DELAY(1);
484 SIO_CLR(SIS_MII_CLK);
485 DELAY(1);
486 }
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487}
488
489/*
490 * Clock a series of bits through the MII.
491 */
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492static void
493sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
984263bc 494{
49eef4c6 495 int i;
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496
497 SIO_CLR(SIS_MII_CLK);
498
499 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
49eef4c6 500 if (bits & i)
984263bc 501 SIO_SET(SIS_MII_DATA);
49eef4c6 502 else
984263bc 503 SIO_CLR(SIS_MII_DATA);
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504 DELAY(1);
505 SIO_CLR(SIS_MII_CLK);
506 DELAY(1);
507 SIO_SET(SIS_MII_CLK);
508 }
509}
510
511/*
512 * Read an PHY register through the MII.
513 */
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514static int
515sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 516{
3b7f6d2b 517 int i, ack;
984263bc 518
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519 /*
520 * Set up frame for RX.
521 */
522 frame->mii_stdelim = SIS_MII_STARTDELIM;
523 frame->mii_opcode = SIS_MII_READOP;
524 frame->mii_turnaround = 0;
525 frame->mii_data = 0;
526
527 /*
528 * Turn on data xmit.
529 */
530 SIO_SET(SIS_MII_DIR);
531
532 sis_mii_sync(sc);
533
534 /*
535 * Send command/address info.
536 */
537 sis_mii_send(sc, frame->mii_stdelim, 2);
538 sis_mii_send(sc, frame->mii_opcode, 2);
539 sis_mii_send(sc, frame->mii_phyaddr, 5);
540 sis_mii_send(sc, frame->mii_regaddr, 5);
541
542 /* Idle bit */
543 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
544 DELAY(1);
545 SIO_SET(SIS_MII_CLK);
546 DELAY(1);
547
548 /* Turn off xmit. */
549 SIO_CLR(SIS_MII_DIR);
550
551 /* Check for ack */
552 SIO_CLR(SIS_MII_CLK);
553 DELAY(1);
554 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
555 SIO_SET(SIS_MII_CLK);
556 DELAY(1);
557
558 /*
559 * Now try reading data bits. If the ack failed, we still
560 * need to clock through 16 cycles to keep the PHY(s) in sync.
561 */
562 if (ack) {
563 for(i = 0; i < 16; i++) {
564 SIO_CLR(SIS_MII_CLK);
565 DELAY(1);
566 SIO_SET(SIS_MII_CLK);
567 DELAY(1);
568 }
569 goto fail;
570 }
571
572 for (i = 0x8000; i; i >>= 1) {
573 SIO_CLR(SIS_MII_CLK);
574 DELAY(1);
575 if (!ack) {
576 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
577 frame->mii_data |= i;
578 DELAY(1);
579 }
580 SIO_SET(SIS_MII_CLK);
581 DELAY(1);
582 }
583
584fail:
585
586 SIO_CLR(SIS_MII_CLK);
587 DELAY(1);
588 SIO_SET(SIS_MII_CLK);
589 DELAY(1);
590
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591 if (ack)
592 return(1);
593 return(0);
594}
595
596/*
597 * Write to a PHY register through the MII.
598 */
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599static int
600sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 601{
984263bc
MD
602 /*
603 * Set up frame for TX.
604 */
605
606 frame->mii_stdelim = SIS_MII_STARTDELIM;
607 frame->mii_opcode = SIS_MII_WRITEOP;
608 frame->mii_turnaround = SIS_MII_TURNAROUND;
49eef4c6 609
984263bc 610 /*
49eef4c6 611 * Turn on data output.
984263bc
MD
612 */
613 SIO_SET(SIS_MII_DIR);
614
615 sis_mii_sync(sc);
616
617 sis_mii_send(sc, frame->mii_stdelim, 2);
618 sis_mii_send(sc, frame->mii_opcode, 2);
619 sis_mii_send(sc, frame->mii_phyaddr, 5);
620 sis_mii_send(sc, frame->mii_regaddr, 5);
621 sis_mii_send(sc, frame->mii_turnaround, 2);
622 sis_mii_send(sc, frame->mii_data, 16);
623
624 /* Idle bit. */
625 SIO_SET(SIS_MII_CLK);
626 DELAY(1);
627 SIO_CLR(SIS_MII_CLK);
628 DELAY(1);
629
630 /*
631 * Turn off xmit.
632 */
633 SIO_CLR(SIS_MII_DIR);
634
984263bc
MD
635 return(0);
636}
637
49eef4c6
JS
638static int
639sis_miibus_readreg(device_t dev, int phy, int reg)
984263bc 640{
49eef4c6
JS
641 struct sis_softc *sc;
642 struct sis_mii_frame frame;
984263bc
MD
643
644 sc = device_get_softc(dev);
645
646 if (sc->sis_type == SIS_TYPE_83815) {
647 if (phy != 0)
648 return(0);
649 /*
650 * The NatSemi chip can take a while after
651 * a reset to come ready, during which the BMSR
652 * returns a value of 0. This is *never* supposed
653 * to happen: some of the BMSR bits are meant to
654 * be hardwired in the on position, and this can
655 * confuse the miibus code a bit during the probe
656 * and attach phase. So we make an effort to check
657 * for this condition and wait for it to clear.
658 */
659 if (!CSR_READ_4(sc, NS_BMSR))
660 DELAY(1000);
661 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
662 }
663 /*
49eef4c6
JS
664 * Chipsets < SIS_635 seem not to be able to read/write
665 * through mdio. Use the enhanced PHY access register
666 * again for them.
667 */
984263bc
MD
668 if (sc->sis_type == SIS_TYPE_900 &&
669 sc->sis_rev < SIS_REV_635) {
49eef4c6 670 int i, val = 0;
984263bc
MD
671
672 if (phy != 0)
673 return(0);
674
675 CSR_WRITE_4(sc, SIS_PHYCTL,
676 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
677 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
678
679 for (i = 0; i < SIS_TIMEOUT; i++) {
680 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
681 break;
682 }
683
684 if (i == SIS_TIMEOUT) {
10c5bfa0 685 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
686 return(0);
687 }
688
689 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
690
691 if (val == 0xFFFF)
692 return(0);
693
694 return(val);
695 } else {
696 bzero((char *)&frame, sizeof(frame));
49eef4c6 697
984263bc
MD
698 frame.mii_phyaddr = phy;
699 frame.mii_regaddr = reg;
700 sis_mii_readreg(sc, &frame);
49eef4c6 701
984263bc
MD
702 return(frame.mii_data);
703 }
704}
705
49eef4c6
JS
706static int
707sis_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 708{
49eef4c6
JS
709 struct sis_softc *sc;
710 struct sis_mii_frame frame;
984263bc
MD
711
712 sc = device_get_softc(dev);
713
714 if (sc->sis_type == SIS_TYPE_83815) {
715 if (phy != 0)
716 return(0);
717 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
718 return(0);
719 }
720
721 if (sc->sis_type == SIS_TYPE_900 &&
722 sc->sis_rev < SIS_REV_635) {
49eef4c6 723 int i;
984263bc
MD
724
725 if (phy != 0)
726 return(0);
49eef4c6 727
984263bc
MD
728 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
729 (reg << 6) | SIS_PHYOP_WRITE);
730 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
731
732 for (i = 0; i < SIS_TIMEOUT; i++) {
733 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
734 break;
735 }
49eef4c6 736
984263bc 737 if (i == SIS_TIMEOUT)
10c5bfa0 738 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
739 } else {
740 bzero((char *)&frame, sizeof(frame));
49eef4c6 741
984263bc
MD
742 frame.mii_phyaddr = phy;
743 frame.mii_regaddr = reg;
744 frame.mii_data = data;
745 sis_mii_writereg(sc, &frame);
746 }
747 return(0);
748}
749
49eef4c6 750static void sis_miibus_statchg(device_t dev)
984263bc 751{
49eef4c6 752 struct sis_softc *sc;
984263bc
MD
753
754 sc = device_get_softc(dev);
755 sis_init(sc);
984263bc
MD
756}
757
49eef4c6
JS
758static uint32_t
759sis_mchash(struct sis_softc *sc, const uint8_t *addr)
984263bc 760{
49eef4c6
JS
761 uint32_t crc, carry;
762 int i, j;
763 uint8_t c;
984263bc
MD
764
765 /* Compute CRC for the address value. */
766 crc = 0xFFFFFFFF; /* initial value */
767
768 for (i = 0; i < 6; i++) {
769 c = *(addr + i);
770 for (j = 0; j < 8; j++) {
771 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
772 crc <<= 1;
773 c >>= 1;
774 if (carry)
775 crc = (crc ^ 0x04c11db6) | carry;
776 }
777 }
778
779 /*
780 * return the filter bit position
781 *
782 * The NatSemi chip has a 512-bit filter, which is
783 * different than the SiS, so we special-case it.
784 */
785 if (sc->sis_type == SIS_TYPE_83815)
786 return (crc >> 23);
49eef4c6 787 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
788 return (crc >> 24);
789 else
790 return (crc >> 25);
791}
792
49eef4c6
JS
793static void
794sis_setmulti_ns(struct sis_softc *sc)
984263bc 795{
49eef4c6
JS
796 struct ifnet *ifp;
797 struct ifmultiaddr *ifma;
798 uint32_t h = 0, i, filtsave;
799 int bit, index;
984263bc
MD
800
801 ifp = &sc->arpcom.ac_if;
802
803 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
804 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
805 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
806 return;
807 }
808
809 /*
810 * We have to explicitly enable the multicast hash table
811 * on the NatSemi chip if we want to use it, which we do.
812 */
813 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
814 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
815
816 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
817
818 /* first, zot all the existing hash bits */
819 for (i = 0; i < 32; i++) {
820 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
821 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
822 }
823
49eef4c6 824 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
825 if (ifma->ifma_addr->sa_family != AF_LINK)
826 continue;
49eef4c6
JS
827 h = sis_mchash(sc,
828 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
984263bc
MD
829 index = h >> 3;
830 bit = h & 0x1F;
831 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
832 if (bit > 0xF)
833 bit -= 0x10;
834 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
835 }
836
837 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
984263bc
MD
838}
839
49eef4c6
JS
840static void
841sis_setmulti_sis(struct sis_softc *sc)
984263bc 842{
49eef4c6
JS
843 struct ifnet *ifp;
844 struct ifmultiaddr *ifma;
845 uint32_t h, i, n, ctl;
846 uint16_t hashes[16];
984263bc
MD
847
848 ifp = &sc->arpcom.ac_if;
849
850 /* hash table size */
49eef4c6 851 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
852 n = 16;
853 else
854 n = 8;
855
856 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
857
858 if (ifp->if_flags & IFF_BROADCAST)
859 ctl |= SIS_RXFILTCTL_BROAD;
860
861 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
862 ctl |= SIS_RXFILTCTL_ALLMULTI;
863 if (ifp->if_flags & IFF_PROMISC)
864 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
865 for (i = 0; i < n; i++)
866 hashes[i] = ~0;
867 } else {
868 for (i = 0; i < n; i++)
869 hashes[i] = 0;
870 i = 0;
871 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
872 if (ifma->ifma_addr->sa_family != AF_LINK)
873 continue;
49eef4c6 874 h = sis_mchash(sc,
984263bc
MD
875 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
876 hashes[h >> 4] |= 1 << (h & 0xf);
877 i++;
878 }
879 if (i > n) {
880 ctl |= SIS_RXFILTCTL_ALLMULTI;
881 for (i = 0; i < n; i++)
882 hashes[i] = ~0;
883 }
884 }
885
886 for (i = 0; i < n; i++) {
887 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
888 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
889 }
890
891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
892}
893
49eef4c6
JS
894static void
895sis_reset(struct sis_softc *sc)
984263bc 896{
10c5bfa0 897 struct ifnet *ifp = &sc->arpcom.ac_if;
49eef4c6 898 int i;
984263bc
MD
899
900 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
901
902 for (i = 0; i < SIS_TIMEOUT; i++) {
903 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
904 break;
905 }
906
907 if (i == SIS_TIMEOUT)
10c5bfa0 908 if_printf(ifp, "reset never completed\n");
984263bc
MD
909
910 /* Wait a little while for the chip to get its brains in order. */
911 DELAY(1000);
912
913 /*
914 * If this is a NetSemi chip, make sure to clear
915 * PME mode.
916 */
917 if (sc->sis_type == SIS_TYPE_83815) {
918 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
919 CSR_WRITE_4(sc, NS_CLKRUN, 0);
920 }
984263bc
MD
921}
922
923/*
924 * Probe for an SiS chip. Check the PCI vendor and device
925 * IDs against our list and return a device name if we find a match.
926 */
49eef4c6
JS
927static int
928sis_probe(device_t dev)
984263bc 929{
49eef4c6 930 struct sis_type *t;
984263bc
MD
931
932 t = sis_devs;
933
934 while(t->sis_name != NULL) {
935 if ((pci_get_vendor(dev) == t->sis_vid) &&
936 (pci_get_device(dev) == t->sis_did)) {
937 device_set_desc(dev, t->sis_name);
938 return(0);
939 }
940 t++;
941 }
942
943 return(ENXIO);
944}
945
946/*
947 * Attach the interface. Allocate softc structures, do ifmedia
948 * setup and ethernet/BPF attach.
949 */
49eef4c6
JS
950static int
951sis_attach(device_t dev)
984263bc 952{
49eef4c6
JS
953 uint8_t eaddr[ETHER_ADDR_LEN];
954 uint32_t command;
955 struct sis_softc *sc;
956 struct ifnet *ifp;
10c5bfa0 957 int error, rid, waittime;
984263bc 958
984263bc
MD
959 error = waittime = 0;
960 sc = device_get_softc(dev);
984263bc
MD
961
962 if (pci_get_device(dev) == SIS_DEVICEID_900)
963 sc->sis_type = SIS_TYPE_900;
964 if (pci_get_device(dev) == SIS_DEVICEID_7016)
965 sc->sis_type = SIS_TYPE_7016;
966 if (pci_get_vendor(dev) == NS_VENDORID)
967 sc->sis_type = SIS_TYPE_83815;
968
969 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
970
971 /*
972 * Handle power management nonsense.
973 */
974
975 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
976 if (command == 0x01) {
977
978 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
979 if (command & SIS_PSTATE_MASK) {
49eef4c6 980 uint32_t iobase, membase, irq;
984263bc
MD
981
982 /* Save important PCI config data. */
983 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
984 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
985 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
986
987 /* Reset the power state. */
10c5bfa0
JS
988 device_printf(dev, "chip is in D%d power mode "
989 "-- setting to D0\n", command & SIS_PSTATE_MASK);
984263bc
MD
990 command &= 0xFFFFFFFC;
991 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
992
993 /* Restore PCI config data. */
994 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
995 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
996 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
997 }
998 }
999
1000 /*
1001 * Map control/status registers.
1002 */
1003 command = pci_read_config(dev, PCIR_COMMAND, 4);
1004 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1005 pci_write_config(dev, PCIR_COMMAND, command, 4);
1006 command = pci_read_config(dev, PCIR_COMMAND, 4);
1007
1008#ifdef SIS_USEIOSPACE
1009 if (!(command & PCIM_CMD_PORTEN)) {
10c5bfa0 1010 device_printf(dev, "failed to enable I/O ports!\n");
984263bc
MD
1011 error = ENXIO;;
1012 goto fail;
1013 }
1014#else
1015 if (!(command & PCIM_CMD_MEMEN)) {
10c5bfa0 1016 device_printf(dev, "failed to enable memory mapping!\n");
984263bc
MD
1017 error = ENXIO;;
1018 goto fail;
1019 }
1020#endif
1021
1022 rid = SIS_RID;
4e6d744d 1023 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
984263bc
MD
1024
1025 if (sc->sis_res == NULL) {
10c5bfa0 1026 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
1027 error = ENXIO;
1028 goto fail;
1029 }
1030
1031 sc->sis_btag = rman_get_bustag(sc->sis_res);
1032 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1033
1034 /* Allocate interrupt */
1035 rid = 0;
4e6d744d 1036 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
1037 RF_SHAREABLE | RF_ACTIVE);
1038
1039 if (sc->sis_irq == NULL) {
10c5bfa0 1040 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
1041 error = ENXIO;
1042 goto fail;
1043 }
1044
984263bc
MD
1045 /* Reset the adapter. */
1046 sis_reset(sc);
1047
1048 if (sc->sis_type == SIS_TYPE_900 &&
1049 (sc->sis_rev == SIS_REV_635 ||
1050 sc->sis_rev == SIS_REV_900B)) {
1051 SIO_SET(SIS_CFG_RND_CNT);
1052 SIO_SET(SIS_CFG_PERR_DETECT);
1053 }
1054
1055 /*
1056 * Get station address from the EEPROM.
1057 */
1058 switch (pci_get_vendor(dev)) {
1059 case NS_VENDORID:
1060 /*
1061 * Reading the MAC address out of the EEPROM on
1062 * the NatSemi chip takes a bit more work than
1063 * you'd expect. The address spans 4 16-bit words,
1064 * with the first word containing only a single bit.
1065 * You have to shift everything over one bit to
1066 * get it aligned properly. Also, the bits are
1067 * stored backwards (the LSB is really the MSB,
1068 * and so on) so you have to reverse them in order
1069 * to get the MAC address into the form we want.
1070 * Why? Who the hell knows.
1071 */
1072 {
49eef4c6 1073 uint16_t tmp[4];
984263bc
MD
1074
1075 sis_read_eeprom(sc, (caddr_t)&tmp,
1076 NS_EE_NODEADDR, 4, 0);
1077
1078 /* Shift everything over one bit. */
1079 tmp[3] = tmp[3] >> 1;
1080 tmp[3] |= tmp[2] << 15;
1081 tmp[2] = tmp[2] >> 1;
1082 tmp[2] |= tmp[1] << 15;
1083 tmp[1] = tmp[1] >> 1;
1084 tmp[1] |= tmp[0] << 15;
1085
1086 /* Now reverse all the bits. */
1087 tmp[3] = sis_reverse(tmp[3]);
1088 tmp[2] = sis_reverse(tmp[2]);
1089 tmp[1] = sis_reverse(tmp[1]);
1090
1091 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1092 }
1093 break;
1094 case SIS_VENDORID:
1095 default:
1096#ifdef __i386__
1097 /*
1098 * If this is a SiS 630E chipset with an embedded
1099 * SiS 900 controller, we have to read the MAC address
1100 * from the APC CMOS RAM. Our method for doing this
1101 * is very ugly since we have to reach out and grab
1102 * ahold of hardware for which we cannot properly
1103 * allocate resources. This code is only compiled on
1104 * the i386 architecture since the SiS 630E chipset
1105 * is for x86 motherboards only. Note that there are
1106 * a lot of magic numbers in this hack. These are
1107 * taken from SiS's Linux driver. I'd like to replace
1108 * them with proper symbolic definitions, but that
1109 * requires some datasheets that I don't have access
1110 * to at the moment.
1111 */
1112 if (sc->sis_rev == SIS_REV_630S ||
1113 sc->sis_rev == SIS_REV_630E ||
1114 sc->sis_rev == SIS_REV_630EA1)
1115 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1116
1117 else if (sc->sis_rev == SIS_REV_635 ||
1118 sc->sis_rev == SIS_REV_630ET)
1119 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1120 else if (sc->sis_rev == SIS_REV_96x) {
1121 /*
1122 * Allow to read EEPROM from LAN. It is shared
1123 * between a 1394 controller and the NIC and each
1124 * time we access it, we need to set SIS_EECMD_REQ.
1125 */
1126 SIO_SET(SIS_EECMD_REQ);
1127 for (waittime = 0; waittime < SIS_TIMEOUT;
1128 waittime++) {
1129 /* Force EEPROM to idle state. */
1130 sis_eeprom_idle(sc);
1131 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1132 sis_read_eeprom(sc, (caddr_t)&eaddr,
1133 SIS_EE_NODEADDR, 3, 0);
1134 break;
1135 }
1136 DELAY(1);
1137 }
1138 /*
1139 * Set SIS_EECTL_CLK to high, so a other master
1140 * can operate on the i2c bus.
1141 */
1142 SIO_SET(SIS_EECTL_CLK);
1143 /* Refuse EEPROM access by LAN */
1144 SIO_SET(SIS_EECMD_DONE);
1145 } else
1146#endif
1147 sis_read_eeprom(sc, (caddr_t)&eaddr,
1148 SIS_EE_NODEADDR, 3, 0);
1149 break;
1150 }
1151
5047f29c 1152 callout_init(&sc->sis_timer);
984263bc 1153
4ddeda6c
JS
1154 /*
1155 * Allocate the parent bus DMA tag appropriate for PCI.
1156 */
1157#define SIS_NSEG_NEW 32
1158 error = bus_dma_tag_create(NULL, /* parent */
1159 1, 0, /* alignment, boundary */
1160 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1161 BUS_SPACE_MAXADDR, /* highaddr */
1162 NULL, NULL, /* filter, filterarg */
1163 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1164 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1165 BUS_DMA_ALLOCNOW, /* flags */
1166 &sc->sis_parent_tag);
1167 if (error)
1168 goto fail;
984263bc 1169
4ddeda6c
JS
1170 /*
1171 * Now allocate a tag for the DMA descriptor lists and a chunk
1172 * of DMA-able memory based on the tag. Also obtain the physical
1173 * addresses of the RX and TX ring, which we'll need later.
1174 * All of our lists are allocated as a contiguous block of memory.
1175 */
1176 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1177 1, 0, /* alignment, boundary */
1178 BUS_SPACE_MAXADDR, /* lowaddr */
1179 BUS_SPACE_MAXADDR, /* highaddr */
1180 NULL, NULL, /* filter, filterarg */
1181 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1182 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1183 0, /* flags */
1184 &sc->sis_ldata.sis_rx_tag);
1185 if (error)
1186 goto fail;
1187
1188 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1189 (void **)&sc->sis_ldata.sis_rx_list,
1190 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1191 &sc->sis_ldata.sis_rx_dmamap);
1192
1193 if (error) {
1194 device_printf(dev, "no memory for rx list buffers!\n");
1195 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1196 sc->sis_ldata.sis_rx_tag = NULL;
1197 goto fail;
1198 }
1199
1200 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1201 sc->sis_ldata.sis_rx_dmamap,
1202 sc->sis_ldata.sis_rx_list,
1203 sizeof(struct sis_desc), sis_dma_map_ring,
1204 &sc->sis_cdata.sis_rx_paddr, 0);
1205
1206 if (error) {
1207 device_printf(dev, "cannot get address of the rx ring!\n");
1208 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1209 sc->sis_ldata.sis_rx_list,
1210 sc->sis_ldata.sis_rx_dmamap);
1211 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1212 sc->sis_ldata.sis_rx_tag = NULL;
1213 goto fail;
1214 }
1215
1216 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1217 1, 0, /* alignment, boundary */
1218 BUS_SPACE_MAXADDR, /* lowaddr */
1219 BUS_SPACE_MAXADDR, /* highaddr */
1220 NULL, NULL, /* filter, filterarg */
1221 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1222 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1223 0, /* flags */
1224 &sc->sis_ldata.sis_tx_tag);
1225 if (error)
1226 goto fail;
1227
1228 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1229 (void **)&sc->sis_ldata.sis_tx_list,
1230 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1231 &sc->sis_ldata.sis_tx_dmamap);
1232
1233 if (error) {
1234 device_printf(dev, "no memory for tx list buffers!\n");
1235 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1236 sc->sis_ldata.sis_tx_tag = NULL;
1237 goto fail;
1238 }
1239
1240 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1241 sc->sis_ldata.sis_tx_dmamap,
1242 sc->sis_ldata.sis_tx_list,
1243 sizeof(struct sis_desc), sis_dma_map_ring,
1244 &sc->sis_cdata.sis_tx_paddr, 0);
1245
1246 if (error) {
1247 device_printf(dev, "cannot get address of the tx ring!\n");
1248 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1249 sc->sis_ldata.sis_tx_list,
1250 sc->sis_ldata.sis_tx_dmamap);
1251 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1252 sc->sis_ldata.sis_tx_tag = NULL;
984263bc
MD
1253 goto fail;
1254 }
4ddeda6c
JS
1255
1256 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1257 1, 0, /* alignment, boundary */
1258 BUS_SPACE_MAXADDR, /* lowaddr */
1259 BUS_SPACE_MAXADDR, /* highaddr */
1260 NULL, NULL, /* filter, filterarg */
1261 MCLBYTES, 1, /* maxsize, nsegments */
1262 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1263 0, /* flags */
1264 &sc->sis_tag);
1265 if (error)
1266 goto fail;
984263bc
MD
1267
1268 ifp = &sc->arpcom.ac_if;
1269 ifp->if_softc = sc;
10c5bfa0 1270 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
1271 ifp->if_mtu = ETHERMTU;
1272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1273 ifp->if_ioctl = sis_ioctl;
984263bc
MD
1274 ifp->if_start = sis_start;
1275 ifp->if_watchdog = sis_watchdog;
1276 ifp->if_init = sis_init;
1277 ifp->if_baudrate = 10000000;
e25db1f0
JS
1278 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1279 ifq_set_ready(&ifp->if_snd);
d9168eb7 1280#ifdef DEVICE_POLLING
9c095379 1281 ifp->if_poll = sis_poll;
d9168eb7
JS
1282#endif
1283 ifp->if_capenable = ifp->if_capabilities;
984263bc
MD
1284
1285 /*
1286 * Do MII setup.
1287 */
1288 if (mii_phy_probe(dev, &sc->sis_miibus,
1289 sis_ifmedia_upd, sis_ifmedia_sts)) {
4ddeda6c 1290 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
1291 error = ENXIO;
1292 goto fail;
1293 }
1294
1295 /*
1296 * Call MI attach routine.
1297 */
78195a76 1298 ether_ifattach(ifp, eaddr, NULL);
984263bc
MD
1299
1300 /*
1301 * Tell the upper layer(s) we support long frames.
1302 */
1303 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1304
78195a76 1305 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE,
e9cb6d99 1306 sis_intr, sc,
78195a76
MD
1307 &sc->sis_intrhand,
1308 ifp->if_serializer);
4ddeda6c
JS
1309
1310 if (error) {
1311 device_printf(dev, "couldn't set up irq\n");
1312 ether_ifdetach(ifp);
1313 goto fail;
1314 }
1315
984263bc 1316fail:
4ddeda6c
JS
1317 if (error)
1318 sis_detach(dev);
1319
984263bc
MD
1320 return(error);
1321}
1322
4ddeda6c
JS
1323/*
1324 * Shutdown hardware and free up resources. It is called in both the error case
1325 * and the normal detach case so it needs to be careful about only freeing
1326 * resources that have actually been allocated.
1327 */
49eef4c6
JS
1328static int
1329sis_detach(device_t dev)
984263bc 1330{
3b7f6d2b
JS
1331 struct sis_softc *sc = device_get_softc(dev);
1332 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1333
78195a76 1334 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1335
4ddeda6c
JS
1336 if (device_is_attached(dev)) {
1337 sis_reset(sc);
1338 sis_stop(sc);
1339 ether_ifdetach(ifp);
1340 }
1341 if (sc->sis_miibus)
1342 device_delete_child(dev, sc->sis_miibus);
984263bc 1343 bus_generic_detach(dev);
984263bc 1344
4ddeda6c
JS
1345 if (sc->sis_intrhand)
1346 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
3b7f6d2b 1347
4ddeda6c
JS
1348 if (sc->sis_irq)
1349 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1350 if (sc->sis_res)
1351 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
984263bc 1352
4ddeda6c
JS
1353 if (sc->sis_ldata.sis_rx_tag) {
1354 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1355 sc->sis_ldata.sis_rx_dmamap);
1356 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1357 sc->sis_ldata.sis_rx_list,
1358 sc->sis_ldata.sis_rx_dmamap);
1359 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1360 }
1361
1362 if (sc->sis_ldata.sis_tx_tag) {
1363 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1364 sc->sis_ldata.sis_tx_dmamap);
1365 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1366 sc->sis_ldata.sis_tx_list,
1367 sc->sis_ldata.sis_tx_dmamap);
1368 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1369 }
1370 if (sc->sis_tag)
1371 bus_dma_tag_destroy(sc->sis_tag);
1372 if (sc->sis_parent_tag)
1373 bus_dma_tag_destroy(sc->sis_parent_tag);
984263bc 1374
78195a76 1375 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1376 return(0);
1377}
1378
1379/*
1380 * Initialize the transmit descriptors.
1381 */
49eef4c6
JS
1382static int
1383sis_list_tx_init(struct sis_softc *sc)
984263bc 1384{
49eef4c6
JS
1385 struct sis_list_data *ld;
1386 struct sis_ring_data *cd;
1387 int i, nexti;
984263bc
MD
1388
1389 cd = &sc->sis_cdata;
4ddeda6c 1390 ld = &sc->sis_ldata;
984263bc
MD
1391
1392 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1393 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1394 ld->sis_tx_list[i].sis_nextdesc =
1395 &ld->sis_tx_list[nexti];
4ddeda6c
JS
1396 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1397 sc->sis_ldata.sis_tx_dmamap,
1398 &ld->sis_tx_list[nexti],
1399 sizeof(struct sis_desc), sis_dma_map_desc_next,
1400 &ld->sis_tx_list[i], 0);
984263bc
MD
1401 ld->sis_tx_list[i].sis_mbuf = NULL;
1402 ld->sis_tx_list[i].sis_ptr = 0;
1403 ld->sis_tx_list[i].sis_ctl = 0;
1404 }
1405
1406 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1407
4ddeda6c
JS
1408 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1409 BUS_DMASYNC_PREWRITE);
1410
984263bc
MD
1411 return(0);
1412}
1413
984263bc
MD
1414/*
1415 * Initialize the RX descriptors and allocate mbufs for them. Note that
1416 * we arrange the descriptors in a closed ring, so that the last descriptor
1417 * points back to the first.
1418 */
49eef4c6
JS
1419static int
1420sis_list_rx_init(struct sis_softc *sc)
984263bc 1421{
49eef4c6
JS
1422 struct sis_list_data *ld;
1423 struct sis_ring_data *cd;
1424 int i, nexti;
984263bc 1425
4ddeda6c 1426 ld = &sc->sis_ldata;
984263bc
MD
1427 cd = &sc->sis_cdata;
1428
1429 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1430 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1431 return(ENOBUFS);
1432 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1433 ld->sis_rx_list[i].sis_nextdesc =
1434 &ld->sis_rx_list[nexti];
4ddeda6c
JS
1435 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1436 sc->sis_ldata.sis_rx_dmamap,
1437 &ld->sis_rx_list[nexti],
1438 sizeof(struct sis_desc), sis_dma_map_desc_next,
1439 &ld->sis_rx_list[i], 0);
984263bc
MD
1440 }
1441
4ddeda6c
JS
1442 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1443 BUS_DMASYNC_PREWRITE);
1444
984263bc
MD
1445 cd->sis_rx_prod = 0;
1446
1447 return(0);
1448}
1449
1450/*
1451 * Initialize an RX descriptor and attach an MBUF cluster.
1452 */
49eef4c6
JS
1453static int
1454sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
984263bc 1455{
984263bc 1456 if (m == NULL) {
74f1caca 1457 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
1458 if (m == NULL)
1459 return(ENOBUFS);
1460 } else {
1461 m->m_data = m->m_ext.ext_buf;
1462 }
1463
1464 c->sis_mbuf = m;
984263bc
MD
1465 c->sis_ctl = SIS_RXLEN;
1466
4ddeda6c
JS
1467 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1468 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1469 sis_dma_map_desc_ptr, c, 0);
1470 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1471
984263bc
MD
1472 return(0);
1473}
1474
1475/*
1476 * A frame has been uploaded: pass the resulting mbuf chain up to
1477 * the higher level protocols.
1478 */
49eef4c6
JS
1479static void
1480sis_rxeof(struct sis_softc *sc)
984263bc 1481{
49eef4c6
JS
1482 struct mbuf *m;
1483 struct ifnet *ifp;
1484 struct sis_desc *cur_rx;
1485 int i, total_len = 0;
1486 uint32_t rxstat;
984263bc
MD
1487
1488 ifp = &sc->arpcom.ac_if;
1489 i = sc->sis_cdata.sis_rx_prod;
1490
4ddeda6c 1491 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
984263bc
MD
1492
1493#ifdef DEVICE_POLLING
46f25451 1494 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1495 if (sc->rxcycles <= 0)
1496 break;
1497 sc->rxcycles--;
1498 }
1499#endif /* DEVICE_POLLING */
4ddeda6c 1500 cur_rx = &sc->sis_ldata.sis_rx_list[i];
984263bc 1501 rxstat = cur_rx->sis_rxstat;
4ddeda6c
JS
1502 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1503 BUS_DMASYNC_POSTWRITE);
1504 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1505 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
984263bc
MD
1506 m = cur_rx->sis_mbuf;
1507 cur_rx->sis_mbuf = NULL;
1508 total_len = SIS_RXBYTES(cur_rx);
1509 SIS_INC(i, SIS_RX_LIST_CNT);
1510
1511 /*
1512 * If an error occurs, update stats, clear the
1513 * status word and leave the mbuf cluster in place:
1514 * it should simply get re-used next time this descriptor
1515 * comes up in the ring.
1516 */
1517 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1518 ifp->if_ierrors++;
1519 if (rxstat & SIS_RXSTAT_COLL)
1520 ifp->if_collisions++;
1521 sis_newbuf(sc, cur_rx, m);
1522 continue;
1523 }
1524
1525 /* No errors; receive the packet. */
1526#ifdef __i386__
1527 /*
1528 * On the x86 we do not have alignment problems, so try to
1529 * allocate a new buffer for the receive ring, and pass up
1530 * the one where the packet is already, saving the expensive
1531 * copy done in m_devget().
1532 * If we are on an architecture with alignment problems, or
1533 * if the allocation fails, then use m_devget and leave the
1534 * existing buffer in the receive ring.
1535 */
1536 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1537 m->m_pkthdr.len = m->m_len = total_len;
1538 else
1539#endif
1540 {
1541 struct mbuf *m0;
1542 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1543 total_len + ETHER_ALIGN, 0, ifp, NULL);
1544 sis_newbuf(sc, cur_rx, m);
1545 if (m0 == NULL) {
1546 ifp->if_ierrors++;
1547 continue;
1548 }
1549 m_adj(m0, ETHER_ALIGN);
1550 m = m0;
1551 }
1552
1553 ifp->if_ipackets++;
78195a76 1554 ifp->if_input(ifp, m);
984263bc
MD
1555 }
1556
1557 sc->sis_cdata.sis_rx_prod = i;
984263bc
MD
1558}
1559
49eef4c6
JS
1560static void
1561sis_rxeoc(struct sis_softc *sc)
984263bc
MD
1562{
1563 sis_rxeof(sc);
4ddeda6c 1564 sis_init(sc);
984263bc
MD
1565}
1566
1567/*
1568 * A frame was downloaded to the chip. It's safe for us to clean up
1569 * the list buffers.
1570 */
1571
49eef4c6
JS
1572static void
1573sis_txeof(struct sis_softc *sc)
984263bc 1574{
4ddeda6c 1575 struct sis_desc *cur_tx;
49eef4c6
JS
1576 struct ifnet *ifp;
1577 uint32_t idx;
984263bc
MD
1578
1579 ifp = &sc->arpcom.ac_if;
1580
1581 /*
1582 * Go through our tx list and free mbufs for those
1583 * frames that have been transmitted.
1584 */
4ddeda6c
JS
1585 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1586 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1587 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
984263bc
MD
1588
1589 if (SIS_OWNDESC(cur_tx))
1590 break;
1591
4ddeda6c 1592 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
984263bc 1593 continue;
984263bc
MD
1594
1595 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1596 ifp->if_oerrors++;
1597 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1598 ifp->if_collisions++;
1599 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1600 ifp->if_collisions++;
1601 }
1602
1603 ifp->if_collisions +=
1604 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1605
1606 ifp->if_opackets++;
1607 if (cur_tx->sis_mbuf != NULL) {
1608 m_freem(cur_tx->sis_mbuf);
1609 cur_tx->sis_mbuf = NULL;
4ddeda6c
JS
1610 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1611 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
984263bc 1612 }
984263bc
MD
1613 }
1614
1615 if (idx != sc->sis_cdata.sis_tx_cons) {
4ddeda6c 1616 /* we freed up some buffers */
984263bc
MD
1617 sc->sis_cdata.sis_tx_cons = idx;
1618 ifp->if_flags &= ~IFF_OACTIVE;
1619 }
49eef4c6 1620
984263bc 1621 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
984263bc
MD
1622}
1623
49eef4c6
JS
1624static void
1625sis_tick(void *xsc)
984263bc 1626{
3b7f6d2b 1627 struct sis_softc *sc = xsc;
49eef4c6 1628 struct mii_data *mii;
3b7f6d2b 1629 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1630
78195a76 1631 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
1632
1633 mii = device_get_softc(sc->sis_miibus);
1634 mii_tick(mii);
1635
1636 if (!sc->sis_link) {
1637 mii_pollstat(mii);
1638 if (mii->mii_media_status & IFM_ACTIVE &&
1639 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1640 sc->sis_link++;
e25db1f0
JS
1641 if (!ifq_is_empty(&ifp->if_snd))
1642 sis_start(ifp);
984263bc
MD
1643 }
1644
5047f29c 1645 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
78195a76 1646 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1647}
1648
1649#ifdef DEVICE_POLLING
984263bc
MD
1650
1651static void
1652sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1653{
1654 struct sis_softc *sc = ifp->if_softc;
1655
9c095379
MD
1656 switch(cmd) {
1657 case POLL_REGISTER:
1658 /* disable interrupts */
1659 CSR_WRITE_4(sc, SIS_IER, 0);
1660 break;
1661 case POLL_DEREGISTER:
1662 /* enable interrupts */
984263bc 1663 CSR_WRITE_4(sc, SIS_IER, 1);
9c095379
MD
1664 break;
1665 default:
1666 /*
1667 * On the sis, reading the status register also clears it.
1668 * So before returning to intr mode we must make sure that all
1669 * possible pending sources of interrupts have been served.
1670 * In practice this means run to completion the *eof routines,
1671 * and then call the interrupt routine
1672 */
1673 sc->rxcycles = count;
1674 sis_rxeof(sc);
1675 sis_txeof(sc);
1676 if (!ifq_is_empty(&ifp->if_snd))
1677 sis_start(ifp);
984263bc 1678
9c095379
MD
1679 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1680 uint32_t status;
984263bc 1681
9c095379
MD
1682 /* Reading the ISR register clears all interrupts. */
1683 status = CSR_READ_4(sc, SIS_ISR);
984263bc 1684
9c095379
MD
1685 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1686 sis_rxeoc(sc);
984263bc 1687
9c095379
MD
1688 if (status & (SIS_ISR_RX_IDLE))
1689 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
984263bc 1690
9c095379
MD
1691 if (status & SIS_ISR_SYSERR) {
1692 sis_reset(sc);
1693 sis_init(sc);
1694 }
984263bc 1695 }
9c095379 1696 break;
984263bc
MD
1697 }
1698}
1699#endif /* DEVICE_POLLING */
1700
49eef4c6
JS
1701static void
1702sis_intr(void *arg)
984263bc 1703{
49eef4c6
JS
1704 struct sis_softc *sc;
1705 struct ifnet *ifp;
1706 uint32_t status;
984263bc
MD
1707
1708 sc = arg;
1709 ifp = &sc->arpcom.ac_if;
1710
984263bc
MD
1711 /* Supress unwanted interrupts */
1712 if (!(ifp->if_flags & IFF_UP)) {
1713 sis_stop(sc);
1714 return;
1715 }
1716
1717 /* Disable interrupts. */
1718 CSR_WRITE_4(sc, SIS_IER, 0);
1719
1720 for (;;) {
1721 /* Reading the ISR register clears all interrupts. */
1722 status = CSR_READ_4(sc, SIS_ISR);
1723
1724 if ((status & SIS_INTRS) == 0)
1725 break;
1726
1727 if (status &
49eef4c6
JS
1728 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1729 SIS_ISR_TX_IDLE) )
984263bc
MD
1730 sis_txeof(sc);
1731
49eef4c6
JS
1732 if (status &
1733 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
984263bc
MD
1734 sis_rxeof(sc);
1735
49eef4c6 1736 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
984263bc
MD
1737 sis_rxeoc(sc);
1738
1739 if (status & (SIS_ISR_RX_IDLE))
1740 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1741
1742 if (status & SIS_ISR_SYSERR) {
1743 sis_reset(sc);
1744 sis_init(sc);
1745 }
1746 }
1747
1748 /* Re-enable interrupts. */
1749 CSR_WRITE_4(sc, SIS_IER, 1);
1750
e25db1f0 1751 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1752 sis_start(ifp);
984263bc
MD
1753}
1754
1755/*
1756 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1757 * pointers to the fragment pointers.
1758 */
49eef4c6
JS
1759static int
1760sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1761{
49eef4c6
JS
1762 struct sis_desc *f = NULL;
1763 struct mbuf *m;
1764 int frag, cur, cnt = 0;
984263bc 1765
4ddeda6c
JS
1766 /*
1767 * If there's no way we can send any packets, return now.
1768 */
1769 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1770 return (ENOBUFS);
1771
984263bc
MD
1772 /*
1773 * Start packing the mbufs in this chain into
1774 * the fragment pointers. Stop when we run out
1775 * of fragments or hit the end of the mbuf chain.
1776 */
1777 m = m_head;
1778 cur = frag = *txidx;
1779
1780 for (m = m_head; m != NULL; m = m->m_next) {
1781 if (m->m_len != 0) {
1782 if ((SIS_TX_LIST_CNT -
1783 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1784 return(ENOBUFS);
4ddeda6c 1785 f = &sc->sis_ldata.sis_tx_list[frag];
984263bc 1786 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
4ddeda6c
JS
1787 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1788 bus_dmamap_load(sc->sis_tag, f->sis_map,
1789 mtod(m, void *), m->m_len,
1790 sis_dma_map_desc_ptr, f, 0);
1791 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1792 BUS_DMASYNC_PREREAD);
984263bc
MD
1793 if (cnt != 0)
1794 f->sis_ctl |= SIS_CMDSTS_OWN;
1795 cur = frag;
1796 SIS_INC(frag, SIS_TX_LIST_CNT);
1797 cnt++;
1798 }
1799 }
1800
1801 if (m != NULL)
1802 return(ENOBUFS);
1803
4ddeda6c
JS
1804 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1805 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1806 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
984263bc
MD
1807 sc->sis_cdata.sis_tx_cnt += cnt;
1808 *txidx = frag;
1809
1810 return(0);
1811}
1812
1813/*
1814 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1815 * to the mbuf data regions directly in the transmit lists. We also save a
1816 * copy of the pointers since the transmit list fragment pointers are
1817 * physical addresses.
1818 */
1819
49eef4c6
JS
1820static void
1821sis_start(struct ifnet *ifp)
984263bc 1822{
49eef4c6
JS
1823 struct sis_softc *sc;
1824 struct mbuf *m_head = NULL;
1825 uint32_t idx;
2f54d1d2 1826 int need_trans;
984263bc
MD
1827
1828 sc = ifp->if_softc;
1829
1830 if (!sc->sis_link)
1831 return;
1832
1833 idx = sc->sis_cdata.sis_tx_prod;
1834
1835 if (ifp->if_flags & IFF_OACTIVE)
1836 return;
1837
2f54d1d2 1838 need_trans = 0;
4ddeda6c 1839 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
e25db1f0 1840 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
1841 if (m_head == NULL)
1842 break;
1843
1844 if (sis_encap(sc, m_head, &idx)) {
984263bc
MD
1845 ifp->if_flags |= IFF_OACTIVE;
1846 break;
1847 }
d2c71fa0 1848 ifq_dequeue(&ifp->if_snd, m_head);
2f54d1d2 1849 need_trans = 1;
984263bc
MD
1850
1851 /*
1852 * If there's a BPF listener, bounce a copy of this frame
1853 * to him.
1854 */
49eef4c6 1855 BPF_MTAP(ifp, m_head);
984263bc
MD
1856 }
1857
2f54d1d2
SZ
1858 if (!need_trans)
1859 return;
1860
984263bc
MD
1861 /* Transmit */
1862 sc->sis_cdata.sis_tx_prod = idx;
1863 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1864
1865 /*
1866 * Set a timeout in case the chip goes out to lunch.
1867 */
1868 ifp->if_timer = 5;
984263bc
MD
1869}
1870
49eef4c6
JS
1871static void
1872sis_init(void *xsc)
984263bc 1873{
49eef4c6
JS
1874 struct sis_softc *sc = xsc;
1875 struct ifnet *ifp = &sc->arpcom.ac_if;
1876 struct mii_data *mii;
984263bc 1877
984263bc
MD
1878 /*
1879 * Cancel pending I/O and free all RX/TX buffers.
1880 */
1881 sis_stop(sc);
1882
1883 mii = device_get_softc(sc->sis_miibus);
1884
1885 /* Set MAC address */
1886 if (sc->sis_type == SIS_TYPE_83815) {
1887 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1888 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1889 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1891 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1892 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1894 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1895 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1896 } else {
1897 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1898 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1899 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1900 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1901 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1902 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1903 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1904 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1905 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1906 }
1907
1908 /* Init circular RX list. */
1909 if (sis_list_rx_init(sc) == ENOBUFS) {
10c5bfa0
JS
1910 if_printf(ifp, "initialization failed: "
1911 "no memory for rx buffers\n");
984263bc 1912 sis_stop(sc);
984263bc
MD
1913 return;
1914 }
1915
1916 /*
1917 * Init tx descriptors.
1918 */
1919 sis_list_tx_init(sc);
1920
1921 /*
1922 * For the NatSemi chip, we have to explicitly enable the
1923 * reception of ARP frames, as well as turn on the 'perfect
1924 * match' filter where we store the station address, otherwise
1925 * we won't receive unicasts meant for this host.
1926 */
1927 if (sc->sis_type == SIS_TYPE_83815) {
1928 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1929 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1930 }
1931
1932 /* If we want promiscuous mode, set the allframes bit. */
49eef4c6 1933 if (ifp->if_flags & IFF_PROMISC)
984263bc 1934 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
49eef4c6 1935 else
984263bc 1936 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
984263bc
MD
1937
1938 /*
1939 * Set the capture broadcast bit to capture broadcast frames.
1940 */
49eef4c6 1941 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1942 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
49eef4c6 1943 else
984263bc 1944 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
984263bc
MD
1945
1946 /*
1947 * Load the multicast filter.
1948 */
1949 if (sc->sis_type == SIS_TYPE_83815)
1950 sis_setmulti_ns(sc);
1951 else
1952 sis_setmulti_sis(sc);
1953
1954 /* Turn the receive filter on */
1955 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1956
1957 /*
1958 * Load the address of the RX and TX lists.
1959 */
4ddeda6c
JS
1960 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1961 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
984263bc
MD
1962
1963 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1964 * the PCI bus. When this bit is set, the Max DMA Burst Size
1965 * for TX/RX DMA should be no larger than 16 double words.
1966 */
49eef4c6 1967 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
984263bc 1968 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
49eef4c6 1969 else
984263bc 1970 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
984263bc
MD
1971
1972 /* Accept Long Packets for VLAN support */
1973 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1974
1975 /* Set TX configuration */
49eef4c6 1976 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
984263bc 1977 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
49eef4c6 1978 else
984263bc 1979 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
984263bc
MD
1980
1981 /* Set full/half duplex mode. */
1982 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1983 SIS_SETBIT(sc, SIS_TX_CFG,
1984 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1985 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1986 } else {
1987 SIS_CLRBIT(sc, SIS_TX_CFG,
1988 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1989 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1990 }
1991
1992 /*
1993 * Enable interrupts.
1994 */
1995 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1996#ifdef DEVICE_POLLING
1997 /*
1998 * ... only enable interrupts if we are not polling, make sure
1999 * they are off otherwise.
2000 */
46f25451 2001 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
2002 CSR_WRITE_4(sc, SIS_IER, 0);
2003 else
2004#endif /* DEVICE_POLLING */
2005 CSR_WRITE_4(sc, SIS_IER, 1);
2006
2007 /* Enable receiver and transmitter. */
2008 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2010
2011#ifdef notdef
2012 mii_mediachg(mii);
2013#endif
2014
2015 /*
2016 * Page 75 of the DP83815 manual recommends the
2017 * following register settings "for optimum
2018 * performance." Note however that at least three
2019 * of the registers are listed as "reserved" in
2020 * the register map, so who knows what they do.
2021 */
2022 if (sc->sis_type == SIS_TYPE_83815) {
2023 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2024 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2025 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2026 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2027 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2028 }
2029
2030 ifp->if_flags |= IFF_RUNNING;
2031 ifp->if_flags &= ~IFF_OACTIVE;
2032
5047f29c 2033 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
984263bc
MD
2034}
2035
2036/*
2037 * Set media options.
2038 */
49eef4c6
JS
2039static int
2040sis_ifmedia_upd(struct ifnet *ifp)
984263bc 2041{
49eef4c6
JS
2042 struct sis_softc *sc;
2043 struct mii_data *mii;
984263bc
MD
2044
2045 sc = ifp->if_softc;
2046
2047 mii = device_get_softc(sc->sis_miibus);
2048 sc->sis_link = 0;
2049 if (mii->mii_instance) {
2050 struct mii_softc *miisc;
49eef4c6 2051 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
984263bc
MD
2052 mii_phy_reset(miisc);
2053 }
2054 mii_mediachg(mii);
2055
2056 return(0);
2057}
2058
2059/*
2060 * Report current media status.
2061 */
49eef4c6
JS
2062static void
2063sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 2064{
49eef4c6
JS
2065 struct sis_softc *sc;
2066 struct mii_data *mii;
984263bc
MD
2067
2068 sc = ifp->if_softc;
2069
2070 mii = device_get_softc(sc->sis_miibus);
2071 mii_pollstat(mii);
2072 ifmr->ifm_active = mii->mii_media_active;
2073 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
2074}
2075
49eef4c6 2076static int
bd4539cc 2077sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 2078{
49eef4c6
JS
2079 struct sis_softc *sc = ifp->if_softc;
2080 struct ifreq *ifr = (struct ifreq *) data;
2081 struct mii_data *mii;
3b7f6d2b
JS
2082 int error = 0;
2083
984263bc 2084 switch(command) {
984263bc
MD
2085 case SIOCSIFFLAGS:
2086 if (ifp->if_flags & IFF_UP) {
2087 sis_init(sc);
2088 } else {
2089 if (ifp->if_flags & IFF_RUNNING)
2090 sis_stop(sc);
2091 }
2092 error = 0;
2093 break;
2094 case SIOCADDMULTI:
2095 case SIOCDELMULTI:
2096 if (sc->sis_type == SIS_TYPE_83815)
2097 sis_setmulti_ns(sc);
2098 else
2099 sis_setmulti_sis(sc);
2100 error = 0;
2101 break;
2102 case SIOCGIFMEDIA:
2103 case SIOCSIFMEDIA:
2104 mii = device_get_softc(sc->sis_miibus);
2105 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2106 break;
2107 default:
4ddeda6c 2108 error = ether_ioctl(ifp, command, data);
984263bc
MD
2109 break;
2110 }
984263bc
MD
2111 return(error);
2112}
2113
49eef4c6
JS
2114static void
2115sis_watchdog(struct ifnet *ifp)
984263bc 2116{
49eef4c6 2117 struct sis_softc *sc;
984263bc
MD
2118
2119 sc = ifp->if_softc;
2120
2121 ifp->if_oerrors++;
10c5bfa0 2122 if_printf(ifp, "watchdog timeout\n");
984263bc
MD
2123
2124 sis_stop(sc);
2125 sis_reset(sc);
2126 sis_init(sc);
2127
e25db1f0 2128 if (!ifq_is_empty(&ifp->if_snd))
984263bc 2129 sis_start(ifp);
984263bc
MD
2130}
2131
2132/*
2133 * Stop the adapter and free any mbufs allocated to the
2134 * RX and TX lists.
2135 */
49eef4c6
JS
2136static void
2137sis_stop(struct sis_softc *sc)
984263bc 2138{
49eef4c6
JS
2139 int i;
2140 struct ifnet *ifp;
984263bc
MD
2141
2142 ifp = &sc->arpcom.ac_if;
2143 ifp->if_timer = 0;
2144
5047f29c 2145 callout_stop(&sc->sis_timer);
984263bc
MD
2146
2147 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
2148 CSR_WRITE_4(sc, SIS_IER, 0);
2149 CSR_WRITE_4(sc, SIS_IMR, 0);
2150 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2151 DELAY(1000);
2152 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2153 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2154
2155 sc->sis_link = 0;
2156
2157 /*
2158 * Free data in the RX lists.
2159 */
2160 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
4ddeda6c
JS
2161 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2162 bus_dmamap_unload(sc->sis_tag,
2163 sc->sis_ldata.sis_rx_list[i].sis_map);
2164 bus_dmamap_destroy(sc->sis_tag,
2165 sc->sis_ldata.sis_rx_list[i].sis_map);
2166 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2167 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
984263bc
MD
2168 }
2169 }
4ddeda6c 2170 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
984263bc
MD
2171
2172 /*
2173 * Free the TX list buffers.
2174 */
2175 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
4ddeda6c
JS
2176 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2177 bus_dmamap_unload(sc->sis_tag,
2178 sc->sis_ldata.sis_tx_list[i].sis_map);
2179 bus_dmamap_destroy(sc->sis_tag,
2180 sc->sis_ldata.sis_tx_list[i].sis_map);
2181 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2182 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
984263bc
MD
2183 }
2184 }
2185
4ddeda6c 2186 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
984263bc
MD
2187}
2188
2189/*
2190 * Stop all chip I/O so that the kernel's probe routines don't
2191 * get confused by errant DMAs when rebooting.
2192 */
49eef4c6
JS
2193static void
2194sis_shutdown(device_t dev)
984263bc
MD
2195{
2196 struct sis_softc *sc;
78195a76 2197 struct ifnet *ifp;
984263bc
MD
2198
2199 sc = device_get_softc(dev);
78195a76
MD
2200 ifp = &sc->arpcom.ac_if;
2201 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
2202 sis_reset(sc);
2203 sis_stop(sc);
78195a76 2204 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2205}
78195a76 2206