Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / ti / if_ti.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
78195a76 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.38 2005/11/28 17:13:44 dillon Exp $
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34 */
35
36/*
37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
38 * Manuals, sample driver and firmware source kits are available
39 * from http://www.alteon.com/support/openkits.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
44 */
45
46/*
47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
51 * filtering and jumbo (9014 byte) frames. The hardware is largely
52 * controlled by firmware, which must be loaded into the NIC during
53 * initialization.
54 *
55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
56 * revision, which supports new features such as extended commands,
57 * extended jumbo receive ring desciptors and a mini receive ring.
58 *
59 * Alteon Networks is to be commended for releasing such a vast amount
60 * of development material for the Tigon NIC without requiring an NDA
61 * (although they really should have done it a long time ago). With
62 * any luck, the other vendors will finally wise up and follow Alteon's
63 * stellar example.
64 *
65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
66 * this driver by #including it as a C header file. This bloats the
67 * driver somewhat, but it's the easiest method considering that the
68 * driver code and firmware code need to be kept in sync. The source
69 * for the firmware is not provided with the FreeBSD distribution since
70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
71 *
72 * The following people deserve special thanks:
73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
74 * for testing
75 * - Raymond Lee of Netgear, for providing a pair of Netgear
76 * GA620 Tigon 2 boards for testing
77 * - Ulf Zimmermann, for bringing the GA260 to my attention and
78 * convincing me to write this driver.
79 * - Andrew Gallatin for providing FreeBSD/Alpha support.
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/sockio.h>
85#include <sys/mbuf.h>
86#include <sys/malloc.h>
87#include <sys/kernel.h>
88#include <sys/socket.h>
89#include <sys/queue.h>
78195a76 90#include <sys/serialize.h>
9228feed 91#include <sys/thread2.h>
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92
93#include <net/if.h>
c49a85fd 94#include <net/ifq_var.h>
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95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99#include <net/if_types.h>
1f2de5d4 100#include <net/vlan/if_vlan_var.h>
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101
102#include <net/bpf.h>
103
104#include <netinet/in_systm.h>
105#include <netinet/in.h>
106#include <netinet/ip.h>
107
108#include <vm/vm.h> /* for vtophys */
109#include <vm/pmap.h> /* for vtophys */
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110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
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115#include <bus/pci/pcireg.h>
116#include <bus/pci/pcivar.h>
984263bc 117
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118#include "if_tireg.h"
119#include "ti_fw.h"
120#include "ti_fw2.h"
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121
122/*
123 * Temporarily disable the checksum offload support for now.
124 * Tests with ftp.freesoftware.com show that after about 12 hours,
125 * the firmware will begin calculating completely bogus TX checksums
126 * and refuse to stop until the interface is reset. Unfortunately,
127 * there isn't enough time to fully debug this before the 4.1
128 * release, so this will need to stay off for now.
129 */
130#ifdef notdef
131#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
132#else
133#define TI_CSUM_FEATURES 0
134#endif
135
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136/*
137 * Various supported device vendors/types and their names.
138 */
139
140static struct ti_type ti_devs[] = {
141 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
142 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
143 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
144 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
145 { TC_VENDORID, TC_DEVICEID_3C985,
146 "3Com 3c985-SX Gigabit Ethernet" },
147 { NG_VENDORID, NG_DEVICEID_GA620,
148 "Netgear GA620 1000baseSX Gigabit Ethernet" },
149 { NG_VENDORID, NG_DEVICEID_GA620T,
150 "Netgear GA620 1000baseT Gigabit Ethernet" },
151 { SGI_VENDORID, SGI_DEVICEID_TIGON,
152 "Silicon Graphics Gigabit Ethernet" },
153 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
154 "Farallon PN9000SX Gigabit Ethernet" },
155 { 0, 0, NULL }
156};
157
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158static int ti_probe(device_t);
159static int ti_attach(device_t);
160static int ti_detach(device_t);
161static void ti_txeof(struct ti_softc *);
162static void ti_rxeof(struct ti_softc *);
163
164static void ti_stats_update(struct ti_softc *);
165static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *);
166
167static void ti_intr(void *);
168static void ti_start(struct ifnet *);
169static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
170static void ti_init(void *);
171static void ti_init2(struct ti_softc *);
172static void ti_stop(struct ti_softc *);
173static void ti_watchdog(struct ifnet *);
174static void ti_shutdown(device_t);
175static int ti_ifmedia_upd(struct ifnet *);
176static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
177
178static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
179static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
180static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
181
182static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
183static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
184static void ti_setmulti(struct ti_softc *);
185
186static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t);
187static void ti_loadfw(struct ti_softc *);
188static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
189static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *,
190 caddr_t, int);
191static void ti_handle_events(struct ti_softc *);
192static int ti_alloc_jumbo_mem(struct ti_softc *);
946bb09b
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193static struct ti_jslot *
194 ti_jalloc(struct ti_softc *);
195static void ti_jfree(void *);
196static void ti_jref(void *);
461f6da9
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197static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
198static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
199static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
200static int ti_init_rx_ring_std(struct ti_softc *);
201static void ti_free_rx_ring_std(struct ti_softc *);
202static int ti_init_rx_ring_jumbo(struct ti_softc *);
203static void ti_free_rx_ring_jumbo(struct ti_softc *);
204static int ti_init_rx_ring_mini(struct ti_softc *);
205static void ti_free_rx_ring_mini(struct ti_softc *);
206static void ti_free_tx_ring(struct ti_softc *);
207static int ti_init_tx_ring(struct ti_softc *);
208
209static int ti_64bitslot_war(struct ti_softc *);
210static int ti_chipinit(struct ti_softc *);
211static int ti_gibinit(struct ti_softc *);
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212
213static device_method_t ti_methods[] = {
214 /* Device interface */
215 DEVMETHOD(device_probe, ti_probe),
216 DEVMETHOD(device_attach, ti_attach),
217 DEVMETHOD(device_detach, ti_detach),
218 DEVMETHOD(device_shutdown, ti_shutdown),
219 { 0, 0 }
220};
221
984263bc 222
461f6da9 223static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc));
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224static devclass_t ti_devclass;
225
32832096 226DECLARE_DUMMY_MODULE(if_ti);
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227DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
228
229/*
230 * Send an instruction or address to the EEPROM, check for ACK.
231 */
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232static uint32_t
233ti_eeprom_putbyte(struct ti_softc *sc, int byte)
984263bc 234{
461f6da9 235 int ack = 0, i;
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236
237 /*
238 * Make sure we're in TX mode.
239 */
240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
241
242 /*
243 * Feed in each bit and stobe the clock.
244 */
245 for (i = 0x80; i; i >>= 1) {
461f6da9 246 if (byte & i)
984263bc 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
461f6da9 248 else
984263bc 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
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250 DELAY(1);
251 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
252 DELAY(1);
253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
254 }
255
256 /*
257 * Turn off TX mode.
258 */
259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
260
261 /*
262 * Check for ack.
263 */
264 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
265 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
266 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
267
268 return(ack);
269}
270
271/*
272 * Read a byte of data stored in the EEPROM at address 'addr.'
273 * We have to send two address bytes since the EEPROM can hold
274 * more than 256 bytes of data.
275 */
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276static uint8_t
277ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
984263bc 278{
db3e3aa0 279 struct ifnet *ifp = &sc->arpcom.ac_if;
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280 int i;
281 uint8_t byte = 0;
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282
283 EEPROM_START;
284
285 /*
286 * Send write control code to EEPROM.
287 */
288 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
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289 if_printf(ifp, "failed to send write command, status: %x\n",
290 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
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291 return(1);
292 }
293
294 /*
295 * Send first byte of address of byte we want to read.
296 */
297 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
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298 if_printf(ifp, "failed to send address, status: %x\n",
299 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
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300 return(1);
301 }
302 /*
303 * Send second byte address of byte we want to read.
304 */
305 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
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306 if_printf(ifp, "failed to send address, status: %x\n",
307 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
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308 return(1);
309 }
310
311 EEPROM_STOP;
312 EEPROM_START;
313 /*
314 * Send read control code to EEPROM.
315 */
316 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
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317 if_printf(ifp, "failed to send read command, status: %x\n",
318 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
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319 return(1);
320 }
321
322 /*
323 * Start reading bits from EEPROM.
324 */
325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
326 for (i = 0x80; i; i >>= 1) {
327 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
328 DELAY(1);
329 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
330 byte |= i;
331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
332 DELAY(1);
333 }
334
335 EEPROM_STOP;
336
337 /*
338 * No ACK generated for read, so just return byte.
339 */
340
341 *dest = byte;
342
343 return(0);
344}
345
346/*
347 * Read a sequence of bytes from the EEPROM.
348 */
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349static int
350ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
984263bc 351{
461f6da9
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352 int err = 0, i;
353 uint8_t byte = 0;
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354
355 for (i = 0; i < cnt; i++) {
356 err = ti_eeprom_getbyte(sc, off + i, &byte);
357 if (err)
358 break;
359 *(dest + i) = byte;
360 }
361
362 return(err ? 1 : 0);
363}
364
365/*
366 * NIC memory access function. Can be used to either clear a section
367 * of NIC local memory or (if buf is non-NULL) copy data into it.
368 */
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369static void
370ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf)
984263bc 371{
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372 int cnt, segptr, segsize;
373 caddr_t ti_winbase, ptr;
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374
375 segptr = addr;
376 cnt = len;
377 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
378 ptr = buf;
379
380 while(cnt) {
381 if (cnt < TI_WINLEN)
382 segsize = cnt;
383 else
384 segsize = TI_WINLEN - (segptr % TI_WINLEN);
385 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
386 if (buf == NULL)
387 bzero((char *)ti_winbase + (segptr &
388 (TI_WINLEN - 1)), segsize);
389 else {
390 bcopy((char *)ptr, (char *)ti_winbase +
391 (segptr & (TI_WINLEN - 1)), segsize);
392 ptr += segsize;
393 }
394 segptr += segsize;
395 cnt -= segsize;
396 }
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397}
398
399/*
400 * Load firmware image into the NIC. Check that the firmware revision
401 * is acceptable and see if we want the firmware for the Tigon 1 or
402 * Tigon 2.
403 */
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404static void
405ti_loadfw(struct ti_softc *sc)
984263bc 406{
48b0bfa0 407 struct ifnet *ifp = &sc->arpcom.ac_if;
db3e3aa0 408
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409 switch(sc->ti_hwrev) {
410 case TI_HWREV_TIGON:
411 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
412 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
413 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
db3e3aa0
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414 if_printf(ifp, "firmware revision mismatch; want "
415 "%d.%d.%d, got %d.%d.%d\n",
416 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
417 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
418 tigonFwReleaseMinor, tigonFwReleaseFix);
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419 return;
420 }
421 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
422 (caddr_t)tigonFwText);
423 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
424 (caddr_t)tigonFwData);
425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
426 (caddr_t)tigonFwRodata);
427 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
428 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
429 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
430 break;
431 case TI_HWREV_TIGON_II:
432 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
433 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
434 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
db3e3aa0
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435 if_printf(ifp, "firmware revision mismatch; want "
436 "%d.%d.%d, got %d.%d.%d\n",
437 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
438 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
439 tigon2FwReleaseMinor, tigon2FwReleaseFix);
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440 return;
441 }
442 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
443 (caddr_t)tigon2FwText);
444 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
445 (caddr_t)tigon2FwData);
446 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
447 (caddr_t)tigon2FwRodata);
448 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
449 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
450 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
451 break;
452 default:
db3e3aa0 453 if_printf(ifp, "can't load firmware: unknown hardware rev\n");
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454 break;
455 }
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456}
457
458/*
459 * Send the NIC a command via the command ring.
460 */
461f6da9
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461static void
462ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
984263bc 463{
461f6da9 464 uint32_t index;
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465
466 if (sc->ti_rdata->ti_cmd_ring == NULL)
467 return;
468
469 index = sc->ti_cmd_saved_prodidx;
461f6da9 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
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471 TI_INC(index, TI_CMD_RING_CNT);
472 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
473 sc->ti_cmd_saved_prodidx = index;
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474}
475
476/*
477 * Send the NIC an extended command. The 'len' parameter specifies the
478 * number of command slots to include after the initial command.
479 */
461f6da9
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480static void
481ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
984263bc 482{
461f6da9
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483 uint32_t index;
484 int i;
984263bc
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485
486 if (sc->ti_rdata->ti_cmd_ring == NULL)
487 return;
488
489 index = sc->ti_cmd_saved_prodidx;
461f6da9 490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
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491 TI_INC(index, TI_CMD_RING_CNT);
492 for (i = 0; i < len; i++) {
493 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
461f6da9 494 *(uint32_t *)(&arg[i * 4]));
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495 TI_INC(index, TI_CMD_RING_CNT);
496 }
497 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
498 sc->ti_cmd_saved_prodidx = index;
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499}
500
501/*
502 * Handle events that have triggered interrupts.
503 */
461f6da9
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504static void
505ti_handle_events(struct ti_softc *sc)
984263bc 506{
db3e3aa0 507 struct ifnet *ifp = &sc->arpcom.ac_if;
461f6da9 508 struct ti_event_desc *e;
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509
510 if (sc->ti_rdata->ti_event_ring == NULL)
511 return;
512
513 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
514 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
515 switch(e->ti_event) {
516 case TI_EV_LINKSTAT_CHANGED:
517 sc->ti_linkstat = e->ti_code;
db3e3aa0
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518 if (e->ti_code == TI_EV_CODE_LINK_UP) {
519 if_printf(ifp, "10/100 link up\n");
520 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) {
521 if_printf(ifp, "gigabit link up\n");
522 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) {
523 if_printf(ifp, "link down\n");
524 }
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525 break;
526 case TI_EV_ERROR:
db3e3aa0
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527 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) {
528 if_printf(ifp, "invalid command\n");
529 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) {
530 if_printf(ifp, "unknown command\n");
531 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) {
532 if_printf(ifp, "bad config data\n");
533 }
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534 break;
535 case TI_EV_FIRMWARE_UP:
536 ti_init2(sc);
537 break;
538 case TI_EV_STATS_UPDATED:
539 ti_stats_update(sc);
540 break;
541 case TI_EV_RESET_JUMBO_RING:
542 case TI_EV_MCAST_UPDATED:
543 /* Who cares. */
544 break;
545 default:
db3e3aa0 546 if_printf(ifp, "unknown event: %d\n", e->ti_event);
984263bc
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547 break;
548 }
549 /* Advance the consumer index. */
550 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
551 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
552 }
984263bc
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553}
554
555/*
556 * Memory management for the jumbo receive ring is a pain in the
557 * butt. We need to allocate at least 9018 bytes of space per frame,
558 * _and_ it has to be contiguous (unless you use the extended
559 * jumbo descriptor format). Using malloc() all the time won't
560 * work: malloc() allocates memory in powers of two, which means we
561 * would end up wasting a considerable amount of space by allocating
562 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
563 * to do our own memory management.
564 *
565 * The driver needs to allocate a contiguous chunk of memory at boot
566 * time. We then chop this up ourselves into 9K pieces and use them
567 * as external mbuf storage.
568 *
569 * One issue here is how much memory to allocate. The jumbo ring has
570 * 256 slots in it, but at 9K per slot than can consume over 2MB of
571 * RAM. This is a bit much, especially considering we also need
572 * RAM for the standard ring and mini ring (on the Tigon 2). To
573 * save space, we only actually allocate enough memory for 64 slots
574 * by default, which works out to between 500 and 600K. This can
575 * be tuned by changing a #define in if_tireg.h.
576 */
577
461f6da9
JS
578static int
579ti_alloc_jumbo_mem(struct ti_softc *sc)
984263bc 580{
946bb09b 581 struct ti_jslot *entry;
461f6da9
JS
582 caddr_t ptr;
583 int i;
984263bc
MD
584
585 /* Grab a big chunk o' storage. */
586 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
91cefeab 587 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
588
589 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
db3e3aa0 590 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
984263bc
MD
591 return(ENOBUFS);
592 }
593
594 SLIST_INIT(&sc->ti_jfree_listhead);
984263bc
MD
595
596 /*
597 * Now divide it up into 9K pieces and save the addresses
598 * in an array. Note that we play an evil trick here by using
599 * the first few bytes in the buffer to hold the the address
600 * of the softc structure for this interface. This is because
601 * ti_jfree() needs it, but it is called by the mbuf management
602 * code which will not pass it to us explicitly.
603 */
604 ptr = sc->ti_cdata.ti_jumbo_buf;
605 for (i = 0; i < TI_JSLOTS; i++) {
946bb09b
JS
606 entry = &sc->ti_cdata.ti_jslots[i];
607 entry->ti_sc = sc;
608 entry->ti_buf = ptr;
609 entry->ti_inuse = 0;
610 entry->ti_slot = i;
611 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
612 ptr += TI_JLEN;
984263bc
MD
613 }
614
615 return(0);
616}
617
618/*
619 * Allocate a jumbo buffer.
620 */
946bb09b 621static struct ti_jslot *
461f6da9 622ti_jalloc(struct ti_softc *sc)
984263bc 623{
946bb09b 624 struct ti_jslot *entry;
461f6da9 625
984263bc 626 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
461f6da9 627
984263bc 628 if (entry == NULL) {
db3e3aa0 629 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
984263bc
MD
630 return(NULL);
631 }
632
946bb09b
JS
633 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link);
634 entry->ti_inuse = 1;
635 return(entry);
984263bc
MD
636}
637
638/*
639 * Adjust usage count on a jumbo buffer. In general this doesn't
640 * get used much because our jumbo buffers don't get passed around
641 * too much, but it's implemented for correctness.
642 */
461f6da9 643static void
946bb09b 644ti_jref(void *arg)
984263bc 645{
946bb09b
JS
646 struct ti_jslot *entry = (struct ti_jslot *)arg;
647 struct ti_softc *sc = entry->ti_sc;
984263bc
MD
648
649 if (sc == NULL)
650 panic("ti_jref: can't find softc pointer!");
651
946bb09b 652 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
984263bc
MD
653 panic("ti_jref: asked to reference buffer "
654 "that we don't manage!");
946bb09b 655 if (entry->ti_inuse == 0)
984263bc 656 panic("ti_jref: buffer already free!");
946bb09b 657 entry->ti_inuse++;
984263bc
MD
658}
659
660/*
661 * Release a jumbo buffer.
662 */
461f6da9 663static void
946bb09b 664ti_jfree(void *arg)
984263bc 665{
946bb09b
JS
666 struct ti_jslot *entry = (struct ti_jslot *)arg;
667 struct ti_softc *sc = entry->ti_sc;
984263bc
MD
668
669 if (sc == NULL)
946bb09b 670 panic("ti_jref: can't find softc pointer!");
984263bc 671
946bb09b
JS
672 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
673 panic("ti_jref: asked to reference buffer "
674 "that we don't manage!");
675 if (entry->ti_inuse == 0)
676 panic("ti_jref: buffer already free!");
677 if (--entry->ti_inuse == 0)
678 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
984263bc
MD
679}
680
681
682/*
683 * Intialize a standard receive ring descriptor.
684 */
461f6da9
JS
685static int
686ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
984263bc 687{
461f6da9
JS
688 struct mbuf *m_new;
689 struct ti_rx_desc *r;
984263bc
MD
690
691 if (m == NULL) {
17b71a59 692 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc 693 if (m_new == NULL)
17b71a59 694 return (ENOBUFS);
984263bc
MD
695 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
696 } else {
697 m_new = m;
698 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
699 m_new->m_data = m_new->m_ext.ext_buf;
700 }
701
17b71a59 702
984263bc
MD
703 m_adj(m_new, ETHER_ALIGN);
704 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
705 r = &sc->ti_rdata->ti_rx_std_ring[i];
706 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
707 r->ti_type = TI_BDTYPE_RECV_BD;
708 r->ti_flags = 0;
709 if (sc->arpcom.ac_if.if_hwassist)
710 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
711 r->ti_len = m_new->m_len;
712 r->ti_idx = i;
713
714 return(0);
715}
716
717/*
718 * Intialize a mini receive ring descriptor. This only applies to
719 * the Tigon 2.
720 */
461f6da9
JS
721static int
722ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
984263bc 723{
461f6da9
JS
724 struct mbuf *m_new;
725 struct ti_rx_desc *r;
984263bc
MD
726
727 if (m == NULL) {
74f1caca 728 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
729 if (m_new == NULL) {
730 return(ENOBUFS);
731 }
732 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
733 } else {
734 m_new = m;
735 m_new->m_data = m_new->m_pktdat;
736 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
737 }
738
739 m_adj(m_new, ETHER_ALIGN);
740 r = &sc->ti_rdata->ti_rx_mini_ring[i];
741 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
742 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
743 r->ti_type = TI_BDTYPE_RECV_BD;
744 r->ti_flags = TI_BDFLAG_MINI_RING;
745 if (sc->arpcom.ac_if.if_hwassist)
746 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
747 r->ti_len = m_new->m_len;
748 r->ti_idx = i;
749
750 return(0);
751}
752
753/*
754 * Initialize a jumbo receive ring descriptor. This allocates
755 * a jumbo buffer from the pool managed internally by the driver.
756 */
461f6da9
JS
757static int
758ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
984263bc 759{
461f6da9
JS
760 struct mbuf *m_new;
761 struct ti_rx_desc *r;
946bb09b 762 struct ti_jslot *buf;
984263bc
MD
763
764 if (m == NULL) {
984263bc 765 /* Allocate the mbuf. */
74f1caca 766 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
767 if (m_new == NULL) {
768 return(ENOBUFS);
769 }
770
771 /* Allocate the jumbo buffer */
772 buf = ti_jalloc(sc);
773 if (buf == NULL) {
774 m_freem(m_new);
db3e3aa0
JS
775 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
776 "-- packet dropped!\n");
984263bc
MD
777 return(ENOBUFS);
778 }
779
780 /* Attach the buffer to the mbuf. */
946bb09b 781 m_new->m_ext.ext_arg = buf;
b542cd49
JS
782 m_new->m_ext.ext_free = ti_jfree;
783 m_new->m_ext.ext_ref = ti_jref;
946bb09b
JS
784 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
785
786 m_new->m_data = m_new->m_ext.ext_buf;
787 m_new->m_flags |= M_EXT;
788 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc
MD
789 } else {
790 m_new = m;
791 m_new->m_data = m_new->m_ext.ext_buf;
792 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
793 }
794
795 m_adj(m_new, ETHER_ALIGN);
796 /* Set up the descriptor. */
797 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
798 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
799 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
800 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
801 r->ti_flags = TI_BDFLAG_JUMBO_RING;
802 if (sc->arpcom.ac_if.if_hwassist)
803 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
804 r->ti_len = m_new->m_len;
805 r->ti_idx = i;
806
807 return(0);
808}
809
810/*
811 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
812 * that's 1MB or memory, which is a lot. For now, we fill only the first
813 * 256 ring entries and hope that our CPU is fast enough to keep up with
814 * the NIC.
815 */
461f6da9
JS
816static int
817ti_init_rx_ring_std(struct ti_softc *sc)
984263bc 818{
461f6da9
JS
819 int i;
820 struct ti_cmd_desc cmd;
984263bc
MD
821
822 for (i = 0; i < TI_SSLOTS; i++) {
823 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
824 return(ENOBUFS);
825 };
826
827 TI_UPDATE_STDPROD(sc, i - 1);
828 sc->ti_std = i - 1;
829
830 return(0);
831}
832
461f6da9
JS
833static void
834ti_free_rx_ring_std(struct ti_softc *sc)
984263bc 835{
461f6da9 836 int i;
984263bc
MD
837
838 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
839 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
840 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
841 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
842 }
461f6da9 843 bzero(&sc->ti_rdata->ti_rx_std_ring[i],
984263bc
MD
844 sizeof(struct ti_rx_desc));
845 }
984263bc
MD
846}
847
461f6da9
JS
848static int
849ti_init_rx_ring_jumbo(struct ti_softc *sc)
984263bc 850{
461f6da9
JS
851 int i;
852 struct ti_cmd_desc cmd;
984263bc
MD
853
854 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
855 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
856 return(ENOBUFS);
461f6da9 857 }
984263bc
MD
858
859 TI_UPDATE_JUMBOPROD(sc, i - 1);
860 sc->ti_jumbo = i - 1;
861
862 return(0);
863}
864
461f6da9
JS
865static void
866ti_free_rx_ring_jumbo(struct ti_softc *sc)
984263bc 867{
461f6da9 868 int i;
984263bc
MD
869
870 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
871 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
872 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
873 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
874 }
461f6da9 875 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i],
984263bc
MD
876 sizeof(struct ti_rx_desc));
877 }
984263bc
MD
878}
879
461f6da9
JS
880static int
881ti_init_rx_ring_mini(struct ti_softc *sc)
984263bc 882{
461f6da9 883 int i;
984263bc
MD
884
885 for (i = 0; i < TI_MSLOTS; i++) {
886 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
887 return(ENOBUFS);
461f6da9 888 }
984263bc
MD
889
890 TI_UPDATE_MINIPROD(sc, i - 1);
891 sc->ti_mini = i - 1;
892
893 return(0);
894}
895
461f6da9
JS
896static void
897ti_free_rx_ring_mini(struct ti_softc *sc)
984263bc 898{
461f6da9 899 int i;
984263bc
MD
900
901 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
902 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
903 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
904 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
905 }
461f6da9 906 bzero(&sc->ti_rdata->ti_rx_mini_ring[i],
984263bc
MD
907 sizeof(struct ti_rx_desc));
908 }
984263bc
MD
909}
910
461f6da9
JS
911static void
912ti_free_tx_ring(struct ti_softc *sc)
984263bc 913{
461f6da9 914 int i;
984263bc
MD
915
916 if (sc->ti_rdata->ti_tx_ring == NULL)
917 return;
918
919 for (i = 0; i < TI_TX_RING_CNT; i++) {
920 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
921 m_freem(sc->ti_cdata.ti_tx_chain[i]);
922 sc->ti_cdata.ti_tx_chain[i] = NULL;
923 }
461f6da9 924 bzero(&sc->ti_rdata->ti_tx_ring[i],
984263bc
MD
925 sizeof(struct ti_tx_desc));
926 }
984263bc
MD
927}
928
461f6da9
JS
929static int
930ti_init_tx_ring(struct ti_softc *sc)
984263bc
MD
931{
932 sc->ti_txcnt = 0;
933 sc->ti_tx_saved_considx = 0;
934 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
935 return(0);
936}
937
938/*
939 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
940 * but we have to support the old way too so that Tigon 1 cards will
941 * work.
942 */
461f6da9
JS
943static void
944ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
984263bc 945{
461f6da9
JS
946 struct ti_cmd_desc cmd;
947 uint16_t *m;
948 uint32_t ext[2] = {0, 0};
984263bc 949
461f6da9 950 m = (uint16_t *)&addr->octet[0];
984263bc
MD
951
952 switch(sc->ti_hwrev) {
953 case TI_HWREV_TIGON:
954 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
955 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
956 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
957 break;
958 case TI_HWREV_TIGON_II:
959 ext[0] = htons(m[0]);
960 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
961 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
962 break;
963 default:
db3e3aa0 964 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n");
984263bc
MD
965 break;
966 }
984263bc
MD
967}
968
461f6da9
JS
969static void
970ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
984263bc 971{
461f6da9
JS
972 struct ti_cmd_desc cmd;
973 uint16_t *m;
974 uint32_t ext[2] = {0, 0};
984263bc 975
461f6da9 976 m = (uint16_t *)&addr->octet[0];
984263bc
MD
977
978 switch(sc->ti_hwrev) {
979 case TI_HWREV_TIGON:
980 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
981 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
982 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
983 break;
984 case TI_HWREV_TIGON_II:
985 ext[0] = htons(m[0]);
986 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
987 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
988 break;
989 default:
db3e3aa0 990 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n");
984263bc
MD
991 break;
992 }
984263bc
MD
993}
994
995/*
996 * Configure the Tigon's multicast address filter.
997 *
998 * The actual multicast table management is a bit of a pain, thanks to
999 * slight brain damage on the part of both Alteon and us. With our
1000 * multicast code, we are only alerted when the multicast address table
1001 * changes and at that point we only have the current list of addresses:
1002 * we only know the current state, not the previous state, so we don't
1003 * actually know what addresses were removed or added. The firmware has
1004 * state, but we can't get our grubby mits on it, and there is no 'delete
1005 * all multicast addresses' command. Hence, we have to maintain our own
1006 * state so we know what addresses have been programmed into the NIC at
1007 * any given time.
1008 */
461f6da9
JS
1009static void
1010ti_setmulti(struct ti_softc *sc)
984263bc 1011{
461f6da9
JS
1012 struct ifnet *ifp = &sc->arpcom.ac_if;
1013 struct ifmultiaddr *ifma;
1014 struct ti_cmd_desc cmd;
1015 struct ti_mc_entry *mc;
1016 uint32_t intrs;
984263bc
MD
1017
1018 if (ifp->if_flags & IFF_ALLMULTI) {
1019 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1020 return;
984263bc
MD
1021 }
1022
461f6da9
JS
1023 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1024
984263bc
MD
1025 /* Disable interrupts. */
1026 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1027 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1028
1029 /* First, zot all the existing filters. */
1030 while (sc->ti_mc_listhead.slh_first != NULL) {
1031 mc = sc->ti_mc_listhead.slh_first;
1032 ti_del_mcast(sc, &mc->mc_addr);
1033 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1034 free(mc, M_DEVBUF);
1035 }
1036
1037 /* Now program new ones. */
461f6da9 1038 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1039 if (ifma->ifma_addr->sa_family != AF_LINK)
1040 continue;
c5541aee 1041 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
984263bc 1042 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
461f6da9 1043 &mc->mc_addr, ETHER_ADDR_LEN);
984263bc
MD
1044 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1045 ti_add_mcast(sc, &mc->mc_addr);
1046 }
1047
1048 /* Re-enable interrupts. */
1049 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
984263bc
MD
1050}
1051
1052/*
1053 * Check to see if the BIOS has configured us for a 64 bit slot when
1054 * we aren't actually in one. If we detect this condition, we can work
1055 * around it on the Tigon 2 by setting a bit in the PCI state register,
1056 * but for the Tigon 1 we must give up and abort the interface attach.
1057 */
461f6da9
JS
1058static int
1059ti_64bitslot_war(struct ti_softc *sc)
984263bc 1060{
461f6da9 1061 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) {
984263bc
MD
1062 CSR_WRITE_4(sc, 0x600, 0);
1063 CSR_WRITE_4(sc, 0x604, 0);
1064 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1065 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1066 if (sc->ti_hwrev == TI_HWREV_TIGON)
1067 return(EINVAL);
461f6da9
JS
1068 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS);
1069 return(0);
984263bc
MD
1070 }
1071 }
1072
1073 return(0);
1074}
1075
1076/*
1077 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1078 * self-test results.
1079 */
461f6da9
JS
1080static int
1081ti_chipinit(struct ti_softc *sc)
984263bc 1082{
461f6da9
JS
1083 struct ifnet *ifp = &sc->arpcom.ac_if;
1084 uint32_t cacheline;
1085 uint32_t pci_writemax = 0;
984263bc
MD
1086
1087 /* Initialize link to down state. */
1088 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1089
461f6da9
JS
1090 if (ifp->if_capenable & IFCAP_HWCSUM)
1091 ifp->if_hwassist = TI_CSUM_FEATURES;
984263bc 1092 else
461f6da9 1093 ifp->if_hwassist = 0;
984263bc
MD
1094
1095 /* Set endianness before we access any non-PCI registers. */
1096#if BYTE_ORDER == BIG_ENDIAN
1097 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1098 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1099#else
1100 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1101 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1102#endif
1103
1104 /* Check the ROM failed bit to see if self-tests passed. */
1105 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
db3e3aa0 1106 if_printf(ifp, "board self-diagnostics failed!\n");
984263bc
MD
1107 return(ENODEV);
1108 }
1109
1110 /* Halt the CPU. */
1111 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1112
1113 /* Figure out the hardware revision. */
1114 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1115 case TI_REV_TIGON_I:
1116 sc->ti_hwrev = TI_HWREV_TIGON;
1117 break;
1118 case TI_REV_TIGON_II:
1119 sc->ti_hwrev = TI_HWREV_TIGON_II;
1120 break;
1121 default:
db3e3aa0 1122 if_printf(ifp, "unsupported chip revision\n");
984263bc
MD
1123 return(ENODEV);
1124 }
1125
1126 /* Do special setup for Tigon 2. */
1127 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1128 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1129 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1130 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1131 }
1132
1133 /* Set up the PCI state register. */
1134 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1135 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1136 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1137 }
1138
1139 /* Clear the read/write max DMA parameters. */
1140 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1141 TI_PCISTATE_READ_MAXDMA));
1142
1143 /* Get cache line size. */
1144 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1145
1146 /*
1147 * If the system has set enabled the PCI memory write
1148 * and invalidate command in the command register, set
1149 * the write max parameter accordingly. This is necessary
1150 * to use MWI with the Tigon 2.
1151 */
1152 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1153 switch(cacheline) {
1154 case 1:
1155 case 4:
1156 case 8:
1157 case 16:
1158 case 32:
1159 case 64:
1160 break;
1161 default:
1162 /* Disable PCI memory write and invalidate. */
db3e3aa0
JS
1163 if (bootverbose) {
1164 if_printf(ifp, "cache line size %d not "
1165 "supported; disabling PCI MWI\n",
1166 cacheline);
1167 }
984263bc
MD
1168 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1169 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1170 break;
1171 }
1172 }
1173
984263bc 1174 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
984263bc
MD
1175
1176 /* This sets the min dma param all the way up (0xff). */
1177 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1178
1179 /* Configure DMA variables. */
1180#if BYTE_ORDER == BIG_ENDIAN
1181 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1182 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1183 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1184 TI_OPMODE_DONT_FRAG_JUMBO);
1185#else
1186 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1187 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1188 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1189#endif
1190
1191 /*
1192 * Only allow 1 DMA channel to be active at a time.
1193 * I don't think this is a good idea, but without it
1194 * the firmware racks up lots of nicDmaReadRingFull
1195 * errors. This is not compatible with hardware checksums.
1196 */
db3e3aa0 1197 if (ifp->if_hwassist == 0)
984263bc
MD
1198 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1199
1200 /* Recommended settings from Tigon manual. */
1201 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1202 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1203
1204 if (ti_64bitslot_war(sc)) {
db3e3aa0
JS
1205 if_printf(ifp, "bios thinks we're in a 64 bit slot, "
1206 "but we aren't");
984263bc
MD
1207 return(EINVAL);
1208 }
1209
1210 return(0);
1211}
1212
1213/*
1214 * Initialize the general information block and firmware, and
1215 * start the CPU(s) running.
1216 */
461f6da9
JS
1217static int
1218ti_gibinit(struct ti_softc *sc)
984263bc 1219{
461f6da9
JS
1220 struct ifnet *ifp = &sc->arpcom.ac_if;
1221 struct ti_rcb *rcb;
1222 int i;
984263bc
MD
1223
1224 /* Disable interrupts for now. */
1225 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1226
1227 /* Tell the chip where to find the general information block. */
1228 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1229 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1230
1231 /* Load the firmware into SRAM. */
1232 ti_loadfw(sc);
1233
1234 /* Set up the contents of the general info and ring control blocks. */
1235
1236 /* Set up the event ring and producer pointer. */
1237 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1238
1239 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1240 rcb->ti_flags = 0;
1241 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1242 vtophys(&sc->ti_ev_prodidx);
1243 sc->ti_ev_prodidx.ti_idx = 0;
1244 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1245 sc->ti_ev_saved_considx = 0;
1246
1247 /* Set up the command ring and producer mailbox. */
1248 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1249
1250 sc->ti_rdata->ti_cmd_ring =
1251 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1252 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1253 rcb->ti_flags = 0;
1254 rcb->ti_max_len = 0;
461f6da9 1255 for (i = 0; i < TI_CMD_RING_CNT; i++)
984263bc 1256 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
984263bc
MD
1257 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1258 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1259 sc->ti_cmd_saved_prodidx = 0;
1260
1261 /*
1262 * Assign the address of the stats refresh buffer.
1263 * We re-use the current stats buffer for this to
1264 * conserve memory.
1265 */
1266 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1267 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1268
1269 /* Set up the standard receive ring. */
1270 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1271 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1272 rcb->ti_max_len = TI_FRAMELEN;
1273 rcb->ti_flags = 0;
461f6da9 1274 if (ifp->if_hwassist)
984263bc
MD
1275 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1276 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1277 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1278
1279 /* Set up the jumbo receive ring. */
1280 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1281 TI_HOSTADDR(rcb->ti_hostaddr) =
1282 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1283 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1284 rcb->ti_flags = 0;
461f6da9 1285 if (ifp->if_hwassist)
984263bc
MD
1286 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1287 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1288 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1289
1290 /*
1291 * Set up the mini ring. Only activated on the
1292 * Tigon 2 but the slot in the config block is
1293 * still there on the Tigon 1.
1294 */
1295 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1296 TI_HOSTADDR(rcb->ti_hostaddr) =
1297 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1298 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1299 if (sc->ti_hwrev == TI_HWREV_TIGON)
1300 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1301 else
1302 rcb->ti_flags = 0;
461f6da9 1303 if (ifp->if_hwassist)
984263bc
MD
1304 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1305 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1306 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1307
1308 /*
1309 * Set up the receive return ring.
1310 */
1311 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1312 TI_HOSTADDR(rcb->ti_hostaddr) =
1313 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1314 rcb->ti_flags = 0;
1315 rcb->ti_max_len = TI_RETURN_RING_CNT;
1316 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1317 vtophys(&sc->ti_return_prodidx);
1318
1319 /*
1320 * Set up the tx ring. Note: for the Tigon 2, we have the option
1321 * of putting the transmit ring in the host's address space and
1322 * letting the chip DMA it instead of leaving the ring in the NIC's
1323 * memory and accessing it through the shared memory region. We
1324 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1325 * so we have to revert to the shared memory scheme if we detect
1326 * a Tigon 1 chip.
1327 */
1328 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1329 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1330 sc->ti_rdata->ti_tx_ring_nic =
1331 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1332 }
461f6da9 1333 bzero(sc->ti_rdata->ti_tx_ring,
984263bc
MD
1334 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1335 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1336 if (sc->ti_hwrev == TI_HWREV_TIGON)
1337 rcb->ti_flags = 0;
1338 else
1339 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1340 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
461f6da9 1341 if (ifp->if_hwassist)
984263bc
MD
1342 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1343 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1344 rcb->ti_max_len = TI_TX_RING_CNT;
1345 if (sc->ti_hwrev == TI_HWREV_TIGON)
1346 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1347 else
1348 TI_HOSTADDR(rcb->ti_hostaddr) =
1349 vtophys(&sc->ti_rdata->ti_tx_ring);
1350 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1351 vtophys(&sc->ti_tx_considx);
1352
1353 /* Set up tuneables */
1354 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1355 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1356 (sc->ti_rx_coal_ticks / 10));
1357 else
1358 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1359 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1360 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1361 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1362 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1363 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1364
1365 /* Turn interrupts on. */
1366 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1367 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1368
1369 /* Start CPU. */
1370 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1371
1372 return(0);
1373}
1374
1375/*
1376 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1377 * against our list and return its name if we find a match.
1378 */
461f6da9
JS
1379static int
1380ti_probe(device_t dev)
984263bc 1381{
461f6da9
JS
1382 struct ti_type *t;
1383 uint16_t vendor, product;
984263bc 1384
461f6da9
JS
1385 vendor = pci_get_vendor(dev);
1386 product = pci_get_device(dev);
984263bc 1387
461f6da9
JS
1388 for (t = ti_devs; t->ti_name != NULL; t++) {
1389 if (vendor == t->ti_vid && product == t->ti_did) {
984263bc
MD
1390 device_set_desc(dev, t->ti_name);
1391 return(0);
1392 }
984263bc
MD
1393 }
1394
1395 return(ENXIO);
1396}
1397
461f6da9
JS
1398static int
1399ti_attach(device_t dev)
984263bc 1400{
461f6da9
JS
1401 struct ti_softc *sc;
1402 struct ifnet *ifp;
db3e3aa0 1403 int error = 0, rid;
d1be6acb 1404 uint8_t eaddr[ETHER_ADDR_LEN];
984263bc 1405
984263bc 1406 sc = device_get_softc(dev);
461f6da9 1407 ifp = &sc->arpcom.ac_if;
db3e3aa0 1408 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
461f6da9 1409 ifp->if_capabilities = IFCAP_HWCSUM;
db3e3aa0 1410 ifp->if_capenable = ifp->if_capabilities;
984263bc 1411
d2c18477 1412 pci_enable_busmaster(dev);
984263bc 1413
ae2f9d60
JS
1414 /*
1415 * Initialize media before any possible error may occur,
1416 * so we can destroy it unconditionally, if an error occurs later on.
1417 */
1418 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1419
984263bc 1420 rid = TI_PCI_LOMEM;
4e6d744d
JS
1421 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1422 RF_ACTIVE);
984263bc
MD
1423
1424 if (sc->ti_res == NULL) {
db3e3aa0 1425 device_printf(dev, "couldn't map memory\n");
984263bc
MD
1426 error = ENXIO;
1427 goto fail;
1428 }
1429
1430 sc->ti_btag = rman_get_bustag(sc->ti_res);
1431 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1432 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1433
984263bc
MD
1434 /* Allocate interrupt */
1435 rid = 0;
4e6d744d 1436 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc 1437 RF_SHAREABLE | RF_ACTIVE);
984263bc 1438 if (sc->ti_irq == NULL) {
db3e3aa0 1439 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
1440 error = ENXIO;
1441 goto fail;
1442 }
1443
984263bc 1444 if (ti_chipinit(sc)) {
db3e3aa0 1445 device_printf(dev, "chip initialization failed\n");
984263bc
MD
1446 error = ENXIO;
1447 goto fail;
1448 }
1449
1450 /* Zero out the NIC's on-board SRAM. */
1451 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1452
1453 /* Init again -- zeroing memory may have clobbered some registers. */
1454 if (ti_chipinit(sc)) {
db3e3aa0 1455 device_printf(dev, "chip initialization failed\n");
984263bc
MD
1456 error = ENXIO;
1457 goto fail;
1458 }
1459
1460 /*
1461 * Get station address from the EEPROM. Note: the manual states
1462 * that the MAC address is at offset 0x8c, however the data is
1463 * stored as two longwords (since that's how it's loaded into
1464 * the NIC). This means the MAC address is actually preceeded
1465 * by two zero bytes. We need to skip over those.
1466 */
d1be6acb 1467 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
db3e3aa0 1468 device_printf(dev, "failed to read station address\n");
984263bc
MD
1469 error = ENXIO;
1470 goto fail;
1471 }
1472
984263bc
MD
1473 /* Allocate the general information block and ring buffers. */
1474 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
91cefeab 1475 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
1476
1477 if (sc->ti_rdata == NULL) {
db3e3aa0 1478 device_printf(dev, "no memory for list buffers!\n");
ae2f9d60 1479 error = ENXIO;
984263bc
MD
1480 goto fail;
1481 }
1482
1483 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1484
1485 /* Try to allocate memory for jumbo buffers. */
1486 if (ti_alloc_jumbo_mem(sc)) {
db3e3aa0 1487 device_printf(dev, "jumbo buffer allocation failed\n");
984263bc
MD
1488 error = ENXIO;
1489 goto fail;
1490 }
1491
1492 /*
1493 * We really need a better way to tell a 1000baseTX card
1494 * from a 1000baseSX one, since in theory there could be
1495 * OEMed 1000baseTX cards from lame vendors who aren't
1496 * clever enough to change the PCI ID. For the moment
1497 * though, the AceNIC is the only copper card available.
1498 */
1499 if (pci_get_vendor(dev) == ALT_VENDORID &&
1500 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1501 sc->ti_copper = 1;
1502 /* Ok, it's not the only copper card available. */
1503 if (pci_get_vendor(dev) == NG_VENDORID &&
1504 pci_get_device(dev) == NG_DEVICEID_GA620T)
1505 sc->ti_copper = 1;
1506
1507 /* Set default tuneable values. */
1508 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1509 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1510 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1511 sc->ti_rx_max_coal_bds = 64;
1512 sc->ti_tx_max_coal_bds = 128;
1513 sc->ti_tx_buf_ratio = 21;
1514
1515 /* Set up ifnet structure */
984263bc 1516 ifp->if_softc = sc;
984263bc
MD
1517 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1518 ifp->if_ioctl = ti_ioctl;
984263bc
MD
1519 ifp->if_start = ti_start;
1520 ifp->if_watchdog = ti_watchdog;
1521 ifp->if_init = ti_init;
1522 ifp->if_mtu = ETHERMTU;
c49a85fd
JS
1523 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1);
1524 ifq_set_ready(&ifp->if_snd);
984263bc
MD
1525
1526 /* Set up ifmedia support. */
984263bc
MD
1527 if (sc->ti_copper) {
1528 /*
1529 * Copper cards allow manual 10/100 mode selection,
1530 * but not manual 1000baseTX mode selection. Why?
1531 * Becuase currently there's no way to specify the
1532 * master/slave setting through the firmware interface,
1533 * so Alteon decided to just bag it and handle it
1534 * via autonegotiation.
1535 */
1536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1537 ifmedia_add(&sc->ifmedia,
1538 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1539 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1540 ifmedia_add(&sc->ifmedia,
1541 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
7f259627 1542 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
984263bc 1543 ifmedia_add(&sc->ifmedia,
7f259627 1544 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL);
984263bc
MD
1545 } else {
1546 /* Fiber cards don't support 10/100 modes. */
1547 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1548 ifmedia_add(&sc->ifmedia,
1549 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1550 }
1551 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1552 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1553
1554 /*
1555 * Call MI attach routine.
1556 */
78195a76 1557 ether_ifattach(ifp, eaddr, NULL);
984263bc 1558
78195a76
MD
1559 error = bus_setup_intr(dev, sc->ti_irq, INTR_NETSAFE,
1560 ti_intr, sc, &sc->ti_intrhand,
1561 ifp->if_serializer);
ae2f9d60
JS
1562 if (error) {
1563 device_printf(dev, "couldn't set up irq\n");
1564 ether_ifdetach(ifp);
1565 goto fail;
1566 }
1567 return 0;
984263bc 1568
ae2f9d60
JS
1569fail:
1570 ti_detach(dev);
984263bc
MD
1571 return(error);
1572}
1573
461f6da9
JS
1574static int
1575ti_detach(device_t dev)
984263bc 1576{
461f6da9
JS
1577 struct ti_softc *sc = device_get_softc(dev);
1578 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1579
78195a76 1580 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1581
ae2f9d60
JS
1582 if (device_is_attached(dev)) {
1583 if (bus_child_present(dev))
1584 ti_stop(sc);
1585 ether_ifdetach(ifp);
1586 }
984263bc 1587
ae2f9d60
JS
1588 if (sc->ti_intrhand != NULL)
1589 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
984263bc 1590
ae2f9d60
JS
1591 if (sc->ti_irq != NULL)
1592 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1593 if (sc->ti_res != NULL) {
1594 bus_release_resource(dev, SYS_RES_MEMORY,
1595 TI_PCI_LOMEM, sc->ti_res);
1596 }
1597 if (sc->ti_cdata.ti_jumbo_buf != NULL)
1598 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1599 if (sc->ti_rdata != NULL)
1600 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1601 ifmedia_removeall(&sc->ifmedia);
1602
78195a76
MD
1603 lwkt_serialize_exit(ifp->if_serializer);
1604
984263bc
MD
1605 return(0);
1606}
1607
1608/*
1609 * Frame reception handling. This is called if there's a frame
1610 * on the receive return list.
1611 *
1612 * Note: we have to be able to handle three possibilities here:
1613 * 1) the frame is from the mini receive ring (can only happen)
1614 * on Tigon 2 boards)
1615 * 2) the frame is from the jumbo recieve ring
1616 * 3) the frame is from the standard receive ring
1617 */
461f6da9
JS
1618static void
1619ti_rxeof(struct ti_softc *sc)
984263bc 1620{
461f6da9
JS
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
1622 struct ti_cmd_desc cmd;
984263bc
MD
1623
1624 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
461f6da9
JS
1625 struct ti_rx_desc *cur_rx;
1626 uint32_t rxidx;
1627 struct mbuf *m;
1628 uint16_t vlan_tag = 0;
1629 int have_tag = 0;
984263bc
MD
1630
1631 cur_rx =
1632 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1633 rxidx = cur_rx->ti_idx;
1634 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1635
1636 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1637 have_tag = 1;
1638 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1639 }
1640
1641 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1642 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1643 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1644 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1645 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1646 ifp->if_ierrors++;
1647 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1648 continue;
1649 }
1650 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1651 ifp->if_ierrors++;
1652 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1653 continue;
1654 }
1655 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1656 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1657 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1658 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1659 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1660 ifp->if_ierrors++;
1661 ti_newbuf_mini(sc, sc->ti_mini, m);
1662 continue;
1663 }
1664 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1665 ifp->if_ierrors++;
1666 ti_newbuf_mini(sc, sc->ti_mini, m);
1667 continue;
1668 }
1669 } else {
1670 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1671 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1672 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1673 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1674 ifp->if_ierrors++;
1675 ti_newbuf_std(sc, sc->ti_std, m);
1676 continue;
1677 }
1678 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1679 ifp->if_ierrors++;
1680 ti_newbuf_std(sc, sc->ti_std, m);
1681 continue;
1682 }
1683 }
1684
1685 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1686 ifp->if_ipackets++;
984263bc
MD
1687 m->m_pkthdr.rcvif = ifp;
1688
984263bc
MD
1689 if (ifp->if_hwassist) {
1690 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1691 CSUM_DATA_VALID;
1692 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1693 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1694 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1695 }
1696
1697 /*
1698 * If we received a packet with a vlan tag, pass it
1699 * to vlan_input() instead of ether_input().
1700 */
78195a76 1701 lwkt_serialize_enter(ifp->if_serializer);
461f6da9 1702 if (have_tag)
3013ac0e 1703 VLAN_INPUT_TAG(m, vlan_tag);
461f6da9 1704 else
78195a76
MD
1705 ifp->if_input(ifp, m);
1706 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1707 }
1708
1709 /* Only necessary on the Tigon 1. */
1710 if (sc->ti_hwrev == TI_HWREV_TIGON)
1711 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1712 sc->ti_rx_saved_considx);
1713
1714 TI_UPDATE_STDPROD(sc, sc->ti_std);
1715 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1716 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
984263bc
MD
1717}
1718
461f6da9
JS
1719static void
1720ti_txeof(struct ti_softc *sc)
984263bc 1721{
461f6da9
JS
1722 struct ifnet *ifp = &sc->arpcom.ac_if;
1723 struct ti_tx_desc *cur_tx = NULL;
984263bc
MD
1724
1725 /*
1726 * Go through our tx ring and free mbufs for those
1727 * frames that have been sent.
1728 */
1729 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
461f6da9 1730 uint32_t idx = 0;
984263bc
MD
1731
1732 idx = sc->ti_tx_saved_considx;
461f6da9 1733 if (sc->ti_hwrev != TI_HWREV_TIGON) {
984263bc
MD
1734 if (idx > 383)
1735 CSR_WRITE_4(sc, TI_WINBASE,
1736 TI_TX_RING_BASE + 6144);
1737 else if (idx > 255)
1738 CSR_WRITE_4(sc, TI_WINBASE,
1739 TI_TX_RING_BASE + 4096);
1740 else if (idx > 127)
1741 CSR_WRITE_4(sc, TI_WINBASE,
1742 TI_TX_RING_BASE + 2048);
1743 else
1744 CSR_WRITE_4(sc, TI_WINBASE,
1745 TI_TX_RING_BASE);
1746 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1747 } else
1748 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1749 if (cur_tx->ti_flags & TI_BDFLAG_END)
1750 ifp->if_opackets++;
1751 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1752 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1753 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1754 }
1755 sc->ti_txcnt--;
1756 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1757 ifp->if_timer = 0;
1758 }
1759
1760 if (cur_tx != NULL)
1761 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1762}
1763
461f6da9
JS
1764static void
1765ti_intr(void *xsc)
984263bc 1766{
461f6da9
JS
1767 struct ti_softc *sc = xsc;
1768 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1769
1770#ifdef notdef
1771 /* Avoid this for now -- checking this register is expensive. */
1772 /* Make sure this is really our interrupt. */
461f6da9 1773 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0)
984263bc
MD
1774 return;
1775#endif
1776
1777 /* Ack interrupt and stop others from occuring. */
1778 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1779
1780 if (ifp->if_flags & IFF_RUNNING) {
1781 /* Check RX return ring producer/consumer */
1782 ti_rxeof(sc);
1783
1784 /* Check TX ring producer/consumer */
1785 ti_txeof(sc);
1786 }
1787
1788 ti_handle_events(sc);
1789
1790 /* Re-enable interrupts. */
1791 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1792
c49a85fd 1793 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
984263bc 1794 ti_start(ifp);
984263bc
MD
1795}
1796
461f6da9
JS
1797static void
1798ti_stats_update(struct ti_softc *sc)
984263bc 1799{
461f6da9 1800 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1801
1802 ifp->if_collisions +=
1803 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1804 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1805 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1806 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1807 ifp->if_collisions;
984263bc
MD
1808}
1809
1810/*
1811 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1812 * pointers to descriptors.
1813 */
461f6da9
JS
1814static int
1815ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1816{
461f6da9
JS
1817 struct ti_tx_desc *f = NULL;
1818 struct mbuf *m;
1819 struct ifvlan *ifv = NULL;
1820 uint32_t cnt = 0, cur, frag;
1821 uint16_t csum_flags = 0;
984263bc
MD
1822
1823 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1824 m_head->m_pkthdr.rcvif != NULL &&
1825 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1826 ifv = m_head->m_pkthdr.rcvif->if_softc;
1827
1828 m = m_head;
1829 cur = frag = *txidx;
1830
1831 if (m_head->m_pkthdr.csum_flags) {
1832 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1833 csum_flags |= TI_BDFLAG_IP_CKSUM;
1834 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1835 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1836 if (m_head->m_flags & M_LASTFRAG)
1837 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1838 else if (m_head->m_flags & M_FRAG)
1839 csum_flags |= TI_BDFLAG_IP_FRAG;
1840 }
1841 /*
1842 * Start packing the mbufs in this chain into
1843 * the fragment pointers. Stop when we run out
1844 * of fragments or hit the end of the mbuf chain.
1845 */
1846 for (m = m_head; m != NULL; m = m->m_next) {
1847 if (m->m_len != 0) {
1848 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1849 if (frag > 383)
1850 CSR_WRITE_4(sc, TI_WINBASE,
1851 TI_TX_RING_BASE + 6144);
1852 else if (frag > 255)
1853 CSR_WRITE_4(sc, TI_WINBASE,
1854 TI_TX_RING_BASE + 4096);
1855 else if (frag > 127)
1856 CSR_WRITE_4(sc, TI_WINBASE,
1857 TI_TX_RING_BASE + 2048);
1858 else
1859 CSR_WRITE_4(sc, TI_WINBASE,
1860 TI_TX_RING_BASE);
1861 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
1862 } else
1863 f = &sc->ti_rdata->ti_tx_ring[frag];
1864 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1865 break;
1866 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
1867 f->ti_len = m->m_len;
1868 f->ti_flags = csum_flags;
1869
1870 if (ifv != NULL) {
1871 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
1872 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
1873 } else {
1874 f->ti_vlan_tag = 0;
1875 }
1876
1877 /*
1878 * Sanity check: avoid coming within 16 descriptors
1879 * of the end of the ring.
1880 */
1881 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
1882 return(ENOBUFS);
1883 cur = frag;
1884 TI_INC(frag, TI_TX_RING_CNT);
1885 cnt++;
1886 }
1887 }
1888
1889 if (m != NULL)
1890 return(ENOBUFS);
1891
1892 if (frag == sc->ti_tx_saved_considx)
1893 return(ENOBUFS);
1894
1895 if (sc->ti_hwrev == TI_HWREV_TIGON)
1896 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
1897 TI_BDFLAG_END;
1898 else
1899 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
1900 sc->ti_cdata.ti_tx_chain[cur] = m_head;
1901 sc->ti_txcnt += cnt;
1902
1903 *txidx = frag;
1904
1905 return(0);
1906}
1907
1908/*
1909 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1910 * to the mbuf data regions directly in the transmit descriptors.
1911 */
461f6da9
JS
1912static void
1913ti_start(struct ifnet *ifp)
984263bc 1914{
461f6da9
JS
1915 struct ti_softc *sc = ifp->if_softc;
1916 struct mbuf *m_head = NULL;
1917 uint32_t prodidx = 0;
2f54d1d2 1918 int need_trans;
984263bc
MD
1919
1920 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
1921
2f54d1d2 1922 need_trans = 0;
984263bc 1923 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
c49a85fd 1924 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
1925 if (m_head == NULL)
1926 break;
1927
1928 /*
1929 * XXX
1930 * safety overkill. If this is a fragmented packet chain
1931 * with delayed TCP/UDP checksums, then only encapsulate
1932 * it if we have enough descriptors to handle the entire
1933 * chain at once.
1934 * (paranoia -- may not actually be needed)
1935 */
1936 if (m_head->m_flags & M_FIRSTFRAG &&
1937 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
1938 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
1939 m_head->m_pkthdr.csum_data + 16) {
984263bc
MD
1940 ifp->if_flags |= IFF_OACTIVE;
1941 break;
1942 }
1943 }
1944
1945 /*
1946 * Pack the data into the transmit ring. If we
1947 * don't have room, set the OACTIVE flag and wait
1948 * for the NIC to drain the ring.
1949 */
1950 if (ti_encap(sc, m_head, &prodidx)) {
984263bc
MD
1951 ifp->if_flags |= IFF_OACTIVE;
1952 break;
1953 }
d2c71fa0 1954 ifq_dequeue(&ifp->if_snd, m_head);
2f54d1d2
SZ
1955 need_trans = 1;
1956
7600679e 1957 BPF_MTAP(ifp, m_head);
984263bc
MD
1958 }
1959
2f54d1d2
SZ
1960 if (!need_trans)
1961 return;
1962
984263bc
MD
1963 /* Transmit */
1964 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
1965
1966 /*
1967 * Set a timeout in case the chip goes out to lunch.
1968 */
1969 ifp->if_timer = 5;
984263bc
MD
1970}
1971
461f6da9
JS
1972static void
1973ti_init(void *xsc)
984263bc 1974{
461f6da9 1975 struct ti_softc *sc = xsc;
984263bc 1976
984263bc
MD
1977 /* Cancel pending I/O and flush buffers. */
1978 ti_stop(sc);
1979
1980 /* Init the gen info block, ring control blocks and firmware. */
1981 if (ti_gibinit(sc)) {
db3e3aa0 1982 if_printf(&sc->arpcom.ac_if, "initialization failure\n");
984263bc
MD
1983 return;
1984 }
984263bc
MD
1985}
1986
461f6da9
JS
1987static void
1988ti_init2(struct ti_softc *sc)
984263bc 1989{
461f6da9
JS
1990 struct ifnet *ifp = &sc->arpcom.ac_if;
1991 struct ti_cmd_desc cmd;
1992 uint16_t *m;
1993 struct ifmedia *ifm;
1994 int tmp;
984263bc
MD
1995
1996 /* Specify MTU and interface index. */
3e4a09e7 1997 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
984263bc
MD
1998 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
1999 ETHER_HDR_LEN + ETHER_CRC_LEN);
2000 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2001
2002 /* Load our MAC address. */
461f6da9 2003 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
984263bc
MD
2004 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2005 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2006 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2007
2008 /* Enable or disable promiscuous mode as needed. */
461f6da9 2009 if (ifp->if_flags & IFF_PROMISC)
984263bc 2010 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
461f6da9 2011 else
984263bc 2012 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
984263bc
MD
2013
2014 /* Program multicast filter. */
2015 ti_setmulti(sc);
2016
2017 /*
2018 * If this is a Tigon 1, we should tell the
2019 * firmware to use software packet filtering.
2020 */
461f6da9 2021 if (sc->ti_hwrev == TI_HWREV_TIGON)
984263bc 2022 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
984263bc
MD
2023
2024 /* Init RX ring. */
2025 ti_init_rx_ring_std(sc);
2026
2027 /* Init jumbo RX ring. */
2028 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2029 ti_init_rx_ring_jumbo(sc);
2030
2031 /*
2032 * If this is a Tigon 2, we can also configure the
2033 * mini ring.
2034 */
2035 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2036 ti_init_rx_ring_mini(sc);
2037
2038 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2039 sc->ti_rx_saved_considx = 0;
2040
2041 /* Init TX ring. */
2042 ti_init_tx_ring(sc);
2043
2044 /* Tell firmware we're alive. */
2045 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2046
2047 /* Enable host interrupts. */
2048 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2049
2050 ifp->if_flags |= IFF_RUNNING;
2051 ifp->if_flags &= ~IFF_OACTIVE;
2052
2053 /*
2054 * Make sure to set media properly. We have to do this
2055 * here since we have to issue commands in order to set
2056 * the link negotiation and we can't issue commands until
2057 * the firmware is running.
2058 */
2059 ifm = &sc->ifmedia;
2060 tmp = ifm->ifm_media;
2061 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2062 ti_ifmedia_upd(ifp);
2063 ifm->ifm_media = tmp;
984263bc
MD
2064}
2065
2066/*
2067 * Set media options.
2068 */
461f6da9
JS
2069static int
2070ti_ifmedia_upd(struct ifnet *ifp)
984263bc 2071{
461f6da9
JS
2072 struct ti_softc *sc = ifp->if_softc;
2073 struct ifmedia *ifm = &sc->ifmedia;
2074 struct ti_cmd_desc cmd;
984263bc
MD
2075
2076 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2077 return(EINVAL);
2078
2079 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2080 case IFM_AUTO:
461f6da9
JS
2081 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB |
2082 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y |
2083 TI_GLNK_AUTONEGENB | TI_GLNK_ENB);
2084 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB |
2085 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX |
2086 TI_LNK_AUTONEGENB | TI_LNK_ENB);
984263bc
MD
2087 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2088 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2089 break;
2090 case IFM_1000_SX:
7f259627 2091 case IFM_1000_T:
461f6da9
JS
2092 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB |
2093 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB);
984263bc 2094 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
461f6da9 2095 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
984263bc 2096 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
984263bc
MD
2097 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2098 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2099 break;
2100 case IFM_100_FX:
2101 case IFM_10_FL:
2102 case IFM_100_TX:
2103 case IFM_10_T:
2104 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
461f6da9 2105 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF);
984263bc 2106 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
461f6da9 2107 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX)
984263bc 2108 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
461f6da9 2109 else
984263bc 2110 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
461f6da9 2111 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
984263bc 2112 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
461f6da9 2113 else
984263bc 2114 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
984263bc
MD
2115 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2116 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2117 break;
2118 }
2119
2120 return(0);
2121}
2122
2123/*
2124 * Report current media status.
2125 */
461f6da9
JS
2126static void
2127ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 2128{
461f6da9
JS
2129 struct ti_softc *sc = ifp->if_softc;
2130 uint32_t media = 0;
984263bc
MD
2131
2132 ifmr->ifm_status = IFM_AVALID;
2133 ifmr->ifm_active = IFM_ETHER;
2134
2135 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2136 return;
2137
2138 ifmr->ifm_status |= IFM_ACTIVE;
2139
2140 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2141 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2142 if (sc->ti_copper)
7f259627 2143 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD
2144 else
2145 ifmr->ifm_active |= IFM_1000_SX;
2146 if (media & TI_GLNK_FULL_DUPLEX)
2147 ifmr->ifm_active |= IFM_FDX;
2148 else
2149 ifmr->ifm_active |= IFM_HDX;
2150 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2151 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2152 if (sc->ti_copper) {
2153 if (media & TI_LNK_100MB)
2154 ifmr->ifm_active |= IFM_100_TX;
2155 if (media & TI_LNK_10MB)
2156 ifmr->ifm_active |= IFM_10_T;
2157 } else {
2158 if (media & TI_LNK_100MB)
2159 ifmr->ifm_active |= IFM_100_FX;
2160 if (media & TI_LNK_10MB)
2161 ifmr->ifm_active |= IFM_10_FL;
2162 }
2163 if (media & TI_LNK_FULL_DUPLEX)
2164 ifmr->ifm_active |= IFM_FDX;
2165 if (media & TI_LNK_HALF_DUPLEX)
2166 ifmr->ifm_active |= IFM_HDX;
2167 }
984263bc
MD
2168}
2169
461f6da9
JS
2170static int
2171ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 2172{
461f6da9
JS
2173 struct ti_softc *sc = ifp->if_softc;
2174 struct ifreq *ifr = (struct ifreq *) data;
2175 struct ti_cmd_desc cmd;
9228feed 2176 int error = 0, mask;
984263bc 2177
984263bc 2178 switch(command) {
984263bc
MD
2179 case SIOCSIFMTU:
2180 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2181 error = EINVAL;
2182 else {
2183 ifp->if_mtu = ifr->ifr_mtu;
2184 ti_init(sc);
2185 }
2186 break;
2187 case SIOCSIFFLAGS:
2188 if (ifp->if_flags & IFF_UP) {
2189 /*
2190 * If only the state of the PROMISC flag changed,
2191 * then just use the 'set promisc mode' command
2192 * instead of reinitializing the entire NIC. Doing
2193 * a full re-init means reloading the firmware and
2194 * waiting for it to start up, which may take a
2195 * second or two.
2196 */
2197 if (ifp->if_flags & IFF_RUNNING &&
2198 ifp->if_flags & IFF_PROMISC &&
2199 !(sc->ti_if_flags & IFF_PROMISC)) {
2200 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2201 TI_CMD_CODE_PROMISC_ENB, 0);
2202 } else if (ifp->if_flags & IFF_RUNNING &&
2203 !(ifp->if_flags & IFF_PROMISC) &&
2204 sc->ti_if_flags & IFF_PROMISC) {
2205 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2206 TI_CMD_CODE_PROMISC_DIS, 0);
2207 } else
2208 ti_init(sc);
461f6da9
JS
2209 } else if (ifp->if_flags & IFF_RUNNING) {
2210 ti_stop(sc);
984263bc
MD
2211 }
2212 sc->ti_if_flags = ifp->if_flags;
2213 error = 0;
2214 break;
2215 case SIOCADDMULTI:
2216 case SIOCDELMULTI:
2217 if (ifp->if_flags & IFF_RUNNING) {
2218 ti_setmulti(sc);
2219 error = 0;
2220 }
2221 break;
2222 case SIOCSIFMEDIA:
2223 case SIOCGIFMEDIA:
2224 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2225 break;
2226 case SIOCSIFCAP:
2227 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2228 if (mask & IFCAP_HWCSUM) {
2229 if (IFCAP_HWCSUM & ifp->if_capenable)
2230 ifp->if_capenable &= ~IFCAP_HWCSUM;
2231 else
2232 ifp->if_capenable |= IFCAP_HWCSUM;
2233 if (ifp->if_flags & IFF_RUNNING)
2234 ti_init(sc);
2235 }
2236 error = 0;
2237 break;
2238 default:
4cde4dd5 2239 error = ether_ioctl(ifp, command, data);
984263bc
MD
2240 break;
2241 }
984263bc
MD
2242 return(error);
2243}
2244
461f6da9
JS
2245static void
2246ti_watchdog(struct ifnet *ifp)
984263bc 2247{
461f6da9 2248 struct ti_softc *sc = ifp->if_softc;
984263bc 2249
db3e3aa0 2250 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc
MD
2251 ti_stop(sc);
2252 ti_init(sc);
2253
2254 ifp->if_oerrors++;
2f54d1d2
SZ
2255
2256 if (!ifq_is_empty(&ifp->if_snd))
2257 ifp->if_start(ifp);
984263bc
MD
2258}
2259
2260/*
2261 * Stop the adapter and free any mbufs allocated to the
2262 * RX and TX lists.
2263 */
461f6da9
JS
2264static void
2265ti_stop(struct ti_softc *sc)
984263bc 2266{
461f6da9
JS
2267 struct ifnet *ifp = &sc->arpcom.ac_if;
2268 struct ti_cmd_desc cmd;
984263bc
MD
2269
2270 /* Disable host interrupts. */
2271 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2272 /*
2273 * Tell firmware we're shutting down.
2274 */
2275 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2276
2277 /* Halt and reinitialize. */
2278 ti_chipinit(sc);
2279 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2280 ti_chipinit(sc);
2281
2282 /* Free the RX lists. */
2283 ti_free_rx_ring_std(sc);
2284
2285 /* Free jumbo RX list. */
2286 ti_free_rx_ring_jumbo(sc);
2287
2288 /* Free mini RX list. */
2289 ti_free_rx_ring_mini(sc);
2290
2291 /* Free TX buffers. */
2292 ti_free_tx_ring(sc);
2293
2294 sc->ti_ev_prodidx.ti_idx = 0;
2295 sc->ti_return_prodidx.ti_idx = 0;
2296 sc->ti_tx_considx.ti_idx = 0;
2297 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2298
2299 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
2300}
2301
2302/*
2303 * Stop all chip I/O so that the kernel's probe routines don't
2304 * get confused by errant DMAs when rebooting.
2305 */
461f6da9
JS
2306static void
2307ti_shutdown(device_t dev)
984263bc 2308{
461f6da9 2309 struct ti_softc *sc = device_get_softc(dev);
984263bc
MD
2310
2311 ti_chipinit(sc);
984263bc 2312}