Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / tx / if_tx.c
CommitLineData
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1/*-
2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
78195a76 27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.33 2005/11/28 17:13:44 dillon Exp $
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28 */
29
30/*
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
32 *
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
38 *
39 * Thanks are going to Steve Bauer and Jason Wright.
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/sockio.h>
45#include <sys/mbuf.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/queue.h>
78195a76 50#include <sys/serialize.h>
9228feed 51#include <sys/thread2.h>
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52
53#include <net/if.h>
882ec277 54#include <net/ifq_var.h>
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55#include <net/if_arp.h>
56#include <net/ethernet.h>
57#include <net/if_dl.h>
58#include <net/if_media.h>
59
60#include <net/bpf.h>
61
1f2de5d4 62#include <net/vlan/if_vlan_var.h>
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63
64#include <vm/vm.h> /* for vtophys */
65#include <vm/pmap.h> /* for vtophys */
66#include <machine/bus_memio.h>
67#include <machine/bus_pio.h>
68#include <machine/bus.h>
69#include <machine/resource.h>
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70#include <sys/bus.h>
71#include <sys/rman.h>
72
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73#include <bus/pci/pcireg.h>
74#include <bus/pci/pcivar.h>
f668be28 75#include <bus/pci/pcidevs.h>
984263bc 76
f668be28
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77#include <dev/netif/mii_layer/mii.h>
78#include <dev/netif/mii_layer/miivar.h>
79#include <dev/netif/mii_layer/miidevs.h>
80#include <dev/netif/mii_layer/lxtphyreg.h>
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81
82#include "miibus_if.h"
83
f668be28
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84#include <dev/netif/tx/if_txreg.h>
85#include <dev/netif/tx/if_txvar.h>
984263bc 86
bd4539cc 87static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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88static void epic_intr(void *);
89static void epic_tx_underrun(epic_softc_t *);
90static int epic_common_attach(epic_softc_t *);
91static void epic_ifstart(struct ifnet *);
92static void epic_ifwatchdog(struct ifnet *);
9e6fd080 93static void epic_stats_update(void *);
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94static int epic_init(epic_softc_t *);
95static void epic_stop(epic_softc_t *);
96static void epic_rx_done(epic_softc_t *);
97static void epic_tx_done(epic_softc_t *);
98static int epic_init_rings(epic_softc_t *);
99static void epic_free_rings(epic_softc_t *);
100static void epic_stop_activity(epic_softc_t *);
101static int epic_queue_last_packet(epic_softc_t *);
102static void epic_start_activity(epic_softc_t *);
103static void epic_set_rx_mode(epic_softc_t *);
104static void epic_set_tx_mode(epic_softc_t *);
105static void epic_set_mc_table(epic_softc_t *);
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106static int epic_read_eeprom(epic_softc_t *,u_int16_t);
107static void epic_output_eepromw(epic_softc_t *, u_int16_t);
108static u_int16_t epic_input_eepromw(epic_softc_t *);
109static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
110static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
111static u_int8_t epic_read_eepromreg(epic_softc_t *);
112
113static int epic_read_phy_reg(epic_softc_t *, int, int);
114static void epic_write_phy_reg(epic_softc_t *, int, int, int);
115
116static int epic_miibus_readreg(device_t, int, int);
117static int epic_miibus_writereg(device_t, int, int, int);
118static void epic_miibus_statchg(device_t);
119static void epic_miibus_mediainit(device_t);
120
121static int epic_ifmedia_upd(struct ifnet *);
122static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
123
124static int epic_probe(device_t);
125static int epic_attach(device_t);
126static void epic_shutdown(device_t);
127static int epic_detach(device_t);
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128
129static device_method_t epic_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, epic_probe),
132 DEVMETHOD(device_attach, epic_attach),
133 DEVMETHOD(device_detach, epic_detach),
134 DEVMETHOD(device_shutdown, epic_shutdown),
135
136 /* MII interface */
137 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
138 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
139 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
140 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
141
142 { 0, 0 }
143};
144
145static driver_t epic_driver = {
146 "tx",
147 epic_methods,
148 sizeof(epic_softc_t)
149};
150
151static devclass_t epic_devclass;
152
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153DECLARE_DUMMY_MODULE(if_tx);
154MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
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155DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
156DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
157
158static struct epic_type epic_devs[] = {
f668be28 159 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
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160 "SMC EtherPower II 10/100" },
161 { 0, 0, NULL }
162};
163
164static int
2b272d21 165epic_probe(device_t dev)
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166{
167 struct epic_type *t;
f668be28
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168 uint16_t vid, did;
169
170 vid = pci_get_vendor(dev);
171 did = pci_get_device(dev);
172 for (t = epic_devs; t->name != NULL; ++t) {
173 if (vid == t->ven_id && did == t->dev_id) {
174 device_set_desc(dev, t->name);
175 return 0;
984263bc 176 }
984263bc 177 }
f668be28 178 return ENXIO;
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179}
180
181#if defined(EPIC_USEIOSPACE)
182#define EPIC_RES SYS_RES_IOPORT
f668be28 183#define EPIC_RID PCIR_BAR(0)
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184#else
185#define EPIC_RES SYS_RES_MEMORY
f668be28 186#define EPIC_RID PCIR_BAR(1)
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187#endif
188
189/*
190 * Attach routine: map registers, allocate softc, rings and descriptors.
191 * Reset to known state.
192 */
193static int
2b272d21 194epic_attach(device_t dev)
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195{
196 struct ifnet *ifp;
197 epic_softc_t *sc;
c8e12de8 198 int error;
9228feed 199 int i, rid, tmp;
984263bc 200
984263bc 201 sc = device_get_softc(dev);
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202
203 /* Preinitialize softc structure */
984263bc 204 sc->dev = dev;
9e6fd080 205 callout_init(&sc->tx_stat_timer);
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206
207 /* Fill ifnet structure */
208 ifp = &sc->sc_if;
c8e12de8 209 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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210 ifp->if_softc = sc;
211 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
212 ifp->if_ioctl = epic_ifioctl;
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213 ifp->if_start = epic_ifstart;
214 ifp->if_watchdog = epic_ifwatchdog;
215 ifp->if_init = (if_init_f_t*)epic_init;
216 ifp->if_timer = 0;
217 ifp->if_baudrate = 10000000;
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218 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
219 ifq_set_ready(&ifp->if_snd);
984263bc 220
38e96c87 221 pci_enable_busmaster(dev);
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222
223 rid = EPIC_RID;
4e6d744d 224 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
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225
226 if (sc->res == NULL) {
227 device_printf(dev, "couldn't map ports/memory\n");
228 error = ENXIO;
229 goto fail;
230 }
231
232 sc->sc_st = rman_get_bustag(sc->res);
233 sc->sc_sh = rman_get_bushandle(sc->res);
234
235 /* Allocate interrupt */
236 rid = 0;
4e6d744d 237 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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238 RF_SHAREABLE | RF_ACTIVE);
239
240 if (sc->irq == NULL) {
241 device_printf(dev, "couldn't map interrupt\n");
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242 error = ENXIO;
243 goto fail;
244 }
245
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246 /* Do OS independent part, including chip wakeup and reset */
247 error = epic_common_attach(sc);
248 if (error) {
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249 error = ENXIO;
250 goto fail;
251 }
252
253 /* Do ifmedia setup */
254 if (mii_phy_probe(dev, &sc->miibus,
255 epic_ifmedia_upd, epic_ifmedia_sts)) {
256 device_printf(dev, "ERROR! MII without any PHY!?\n");
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257 error = ENXIO;
258 goto fail;
259 }
260
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261 /* board type and ... */
262 printf(" type ");
263 for(i=0x2c;i<0x32;i++) {
264 tmp = epic_read_eeprom(sc, i);
265 if (' ' == (u_int8_t)tmp) break;
266 printf("%c", (u_int8_t)tmp);
267 tmp >>= 8;
268 if (' ' == (u_int8_t)tmp) break;
269 printf("%c", (u_int8_t)tmp);
270 }
271 printf("\n");
272
273 /* Attach to OS's managers */
78195a76 274 ether_ifattach(ifp, sc->sc_macaddr, NULL);
984263bc 275 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
984263bc 276
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277 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE,
278 epic_intr, sc, &sc->sc_ih,
279 ifp->if_serializer);
984263bc 280
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281 if (error) {
282 device_printf(dev, "couldn't set up irq\n");
283 ether_ifdetach(ifp);
284 goto fail;
285 }
286
287 return(0);
288
289fail:
290 epic_detach(dev);
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291 return(error);
292}
293
294/*
295 * Detach driver and free resources
296 */
297static int
2b272d21 298epic_detach(device_t dev)
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299{
300 struct ifnet *ifp;
301 epic_softc_t *sc;
984263bc 302
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303 sc = device_get_softc(dev);
304 ifp = &sc->arpcom.ac_if;
305
78195a76 306 lwkt_serialize_enter(ifp->if_serializer);
984263bc 307
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308 if (device_is_attached(dev)) {
309 ether_ifdetach(ifp);
310 epic_stop(sc);
311 }
984263bc 312
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313 if (sc->miibus)
314 device_delete_child(dev, sc->miibus);
984263bc 315 bus_generic_detach(dev);
984263bc 316
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317 if (sc->sc_ih)
318 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
984263bc 319
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320 if (sc->irq)
321 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
322 if (sc->res)
323 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
324
325 if (sc->tx_flist)
326 free(sc->tx_flist, M_DEVBUF);
327 if (sc->tx_desc)
328 free(sc->tx_desc, M_DEVBUF);
329 if (sc->rx_desc)
330 free(sc->rx_desc, M_DEVBUF);
331
78195a76 332 lwkt_serialize_exit(ifp->if_serializer);
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333 return(0);
334}
335
336#undef EPIC_RES
337#undef EPIC_RID
338
339/*
340 * Stop all chip I/O so that the kernel's probe routines don't
341 * get confused by errant DMAs when rebooting.
342 */
343static void
2b272d21 344epic_shutdown(device_t dev)
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345{
346 epic_softc_t *sc;
78195a76 347 struct ifnet *ifp;
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348
349 sc = device_get_softc(dev);
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350 ifp = &sc->arpcom.ac_if;
351 lwkt_serialize_enter(ifp->if_serializer);
984263bc 352 epic_stop(sc);
78195a76 353 lwkt_serialize_exit(ifp->if_serializer);
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354}
355
356/*
357 * This is if_ioctl handler.
358 */
359static int
2b272d21 360epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
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361{
362 epic_softc_t *sc = ifp->if_softc;
363 struct mii_data *mii;
364 struct ifreq *ifr = (struct ifreq *) data;
9228feed 365 int error = 0;
984263bc 366
984263bc 367 switch (command) {
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368 case SIOCSIFMTU:
369 if (ifp->if_mtu == ifr->ifr_mtu)
370 break;
371
372 /* XXX Though the datasheet doesn't imply any
373 * limitations on RX and TX sizes beside max 64Kb
374 * DMA transfer, seems we can't send more then 1600
375 * data bytes per ethernet packet. (Transmitter hangs
376 * up if more data is sent)
377 */
378 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
379 ifp->if_mtu = ifr->ifr_mtu;
380 epic_stop(sc);
381 epic_init(sc);
382 } else
383 error = EINVAL;
384 break;
385
386 case SIOCSIFFLAGS:
387 /*
388 * If the interface is marked up and stopped, then start it.
389 * If it is marked down and running, then stop it.
390 */
391 if (ifp->if_flags & IFF_UP) {
392 if ((ifp->if_flags & IFF_RUNNING) == 0) {
393 epic_init(sc);
394 break;
395 }
396 } else {
397 if (ifp->if_flags & IFF_RUNNING) {
398 epic_stop(sc);
399 break;
400 }
401 }
402
403 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
404 epic_stop_activity(sc);
405 epic_set_mc_table(sc);
406 epic_set_rx_mode(sc);
407 epic_start_activity(sc);
408 break;
409
410 case SIOCADDMULTI:
411 case SIOCDELMULTI:
412 epic_set_mc_table(sc);
413 error = 0;
414 break;
415
416 case SIOCSIFMEDIA:
417 case SIOCGIFMEDIA:
418 mii = device_get_softc(sc->miibus);
419 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
420 break;
421
422 default:
4cde4dd5
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423 error = ether_ioctl(ifp, command, data);
424 break;
984263bc 425 }
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426 return error;
427}
428
429/*
430 * OS-independed part of attach process. allocate memory for descriptors
431 * and frag lists, wake up chip, read MAC address and PHY identyfier.
432 * Return -1 on failure.
433 */
434static int
2b272d21 435epic_common_attach(epic_softc_t *sc)
984263bc 436{
f668be28 437 uint16_t sub_vid;
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438 int i;
439
440 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
c5541aee 441 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 442 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
c5541aee 443 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 444 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
c5541aee 445 M_DEVBUF, M_WAITOK | M_ZERO);
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446
447 /* Bring the chip out of low-power mode. */
448 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
449 DELAY(500);
450
451 /* Workaround for Application Note 7-15 */
452 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
453
454 /* Read mac address from EEPROM */
455 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
456 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
457
458 /* Set Non-Volatile Control Register from EEPROM */
459 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
460
461 /* Set defaults */
462 sc->tx_threshold = TRANSMIT_THRESHOLD;
463 sc->txcon = TXCON_DEFAULT;
464 sc->miicfg = MIICFG_SMI_ENABLE;
465 sc->phyid = EPIC_UNKN_PHY;
466 sc->serinst = -1;
467
468 /* Fetch card id */
f668be28 469 sub_vid = pci_get_subvendor(sc->dev);
38e96c87 470 sc->cardid = pci_get_subdevice(sc->dev);
984263bc 471
f668be28
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472 if (sub_vid != PCI_VENDOR_SMC)
473 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
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474
475 return 0;
476}
477
478/*
479 * This is if_start handler. It takes mbufs from if_snd queue
480 * and queue them for transmit, one by one, until TX ring become full
481 * or queue become empty.
482 */
483static void
2b272d21 484epic_ifstart(struct ifnet *ifp)
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485{
486 epic_softc_t *sc = ifp->if_softc;
487 struct epic_tx_buffer *buf;
488 struct epic_tx_desc *desc;
489 struct epic_frag_list *flist;
490 struct mbuf *m0;
f96d6c88
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491 struct mbuf *m;
492 int i;
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493
494 while (sc->pending_txs < TX_RING_SIZE) {
495 buf = sc->tx_buffer + sc->cur_tx;
496 desc = sc->tx_desc + sc->cur_tx;
497 flist = sc->tx_flist + sc->cur_tx;
498
499 /* Get next packet to send */
d2c71fa0 500 m0 = ifq_dequeue(&ifp->if_snd, NULL);
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501
502 /* If nothing to send, return */
882ec277
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503 if (m0 == NULL)
504 return;
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505
506 /* Fill fragments list */
507 for (m = m0, i = 0;
508 (NULL != m) && (i < EPIC_MAX_FRAGS);
509 m = m->m_next, i++) {
510 flist->frag[i].fraglen = m->m_len;
511 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
512 }
513 flist->numfrags = i;
514
515 /* If packet was more than EPIC_MAX_FRAGS parts, */
516 /* recopy packet to new allocated mbuf cluster */
517 if (NULL != m) {
290d24ac 518 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
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519 if (NULL == m) {
520 m_freem(m0);
521 ifp->if_oerrors++;
522 continue;
523 }
524
525 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
526 flist->frag[0].fraglen =
527 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
528 m->m_pkthdr.rcvif = ifp;
529
530 flist->numfrags = 1;
531 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
532 m_freem(m0);
533 m0 = m;
534 }
535
536 buf->mbuf = m0;
537 sc->pending_txs++;
538 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
539 desc->control = 0x01;
540 desc->txlength =
541 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
542 desc->status = 0x8000;
543 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
544
545 /* Set watchdog timer */
546 ifp->if_timer = 8;
547
7600679e 548 BPF_MTAP(ifp, m0);
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549 }
550
551 ifp->if_flags |= IFF_OACTIVE;
552
553 return;
554
555}
556
557/*
558 * Synopsis: Finish all received frames.
559 */
560static void
2b272d21 561epic_rx_done(epic_softc_t *sc)
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562{
563 u_int16_t len;
3013ac0e 564 struct ifnet *ifp = &sc->sc_if;
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565 struct epic_rx_buffer *buf;
566 struct epic_rx_desc *desc;
567 struct mbuf *m;
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568
569 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
570 buf = sc->rx_buffer + sc->cur_rx;
571 desc = sc->rx_desc + sc->cur_rx;
572
573 /* Switch to next descriptor */
574 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
575
576 /*
577 * Check for RX errors. This should only happen if
578 * SAVE_ERRORED_PACKETS is set. RX errors generate
579 * RXE interrupt usually.
580 */
581 if ((desc->status & 1) == 0) {
582 sc->sc_if.if_ierrors++;
583 desc->status = 0x8000;
584 continue;
585 }
586
587 /* Save packet length and mbuf contained packet */
588 len = desc->rxlength - ETHER_CRC_LEN;
589 m = buf->mbuf;
590
591 /* Try to get mbuf cluster */
290d24ac 592 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
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593 if (NULL == buf->mbuf) {
594 buf->mbuf = m;
595 desc->status = 0x8000;
3013ac0e 596 ifp->if_ierrors++;
984263bc
MD
597 continue;
598 }
599
600 /* Point to new mbuf, and give descriptor to chip */
601 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
602 desc->status = 0x8000;
603
604 /* First mbuf in packet holds the ethernet and packet headers */
3013ac0e 605 m->m_pkthdr.rcvif = ifp;
984263bc
MD
606 m->m_pkthdr.len = m->m_len = len;
607
984263bc 608 /* Give mbuf to OS */
78195a76 609 ifp->if_input(ifp, m);
984263bc
MD
610
611 /* Successfuly received frame */
3013ac0e 612 ifp->if_ipackets++;
984263bc
MD
613 }
614
615 return;
616}
617
618/*
619 * Synopsis: Do last phase of transmission. I.e. if desc is
620 * transmitted, decrease pending_txs counter, free mbuf contained
621 * packet, switch to next descriptor and repeat until no packets
622 * are pending or descriptor is not transmitted yet.
623 */
624static void
2b272d21 625epic_tx_done(epic_softc_t *sc)
984263bc
MD
626{
627 struct epic_tx_buffer *buf;
628 struct epic_tx_desc *desc;
629 u_int16_t status;
630
631 while (sc->pending_txs > 0) {
632 buf = sc->tx_buffer + sc->dirty_tx;
633 desc = sc->tx_desc + sc->dirty_tx;
634 status = desc->status;
635
636 /* If packet is not transmitted, thou followed */
637 /* packets are not transmitted too */
638 if (status & 0x8000) break;
639
640 /* Packet is transmitted. Switch to next and */
641 /* free mbuf */
642 sc->pending_txs--;
643 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
644 m_freem(buf->mbuf);
645 buf->mbuf = NULL;
646
647 /* Check for errors and collisions */
648 if (status & 0x0001) sc->sc_if.if_opackets++;
649 else sc->sc_if.if_oerrors++;
650 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
651#if defined(EPIC_DIAG)
c8e12de8
JS
652 if ((status & 0x1001) == 0x1001) {
653 if_printf(&sc->sc_if,
654 "Tx ERROR: excessive coll. number\n");
655 }
984263bc
MD
656#endif
657 }
658
659 if (sc->pending_txs < TX_RING_SIZE)
660 sc->sc_if.if_flags &= ~IFF_OACTIVE;
661}
662
663/*
664 * Interrupt function
665 */
666static void
2b272d21 667epic_intr(void *arg)
984263bc
MD
668{
669 epic_softc_t * sc = (epic_softc_t *) arg;
670 int status, i = 4;
671
672 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
673 CSR_WRITE_4(sc, INTSTAT, status);
674
675 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
676 epic_rx_done(sc);
677 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
678#if defined(EPIC_DIAG)
679 if (status & INTSTAT_OVW)
c8e12de8 680 if_printf(&sc->sc_if, "RX buffer overflow\n");
984263bc 681 if (status & INTSTAT_RQE)
c8e12de8 682 if_printf(&sc->sc_if, "RX FIFO overflow\n");
984263bc
MD
683#endif
684 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
685 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
686 sc->sc_if.if_ierrors++;
687 }
688 }
689
690 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
691 epic_tx_done(sc);
882ec277 692 if (!ifq_is_empty(&sc->sc_if.if_snd))
984263bc
MD
693 epic_ifstart(&sc->sc_if);
694 }
695
696 /* Check for rare errors */
697 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
698 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
699 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
700 INTSTAT_APE|INTSTAT_DPE)) {
c8e12de8 701 if_printf(&sc->sc_if, "PCI fatal errors occured: %s%s%s%s\n",
984263bc
MD
702 (status&INTSTAT_PMA)?"PMA ":"",
703 (status&INTSTAT_PTA)?"PTA ":"",
704 (status&INTSTAT_APE)?"APE ":"",
705 (status&INTSTAT_DPE)?"DPE":""
706 );
707
708 epic_stop(sc);
709 epic_init(sc);
710
711 break;
712 }
713
714 if (status & INTSTAT_RXE) {
715#if defined(EPIC_DIAG)
c8e12de8 716 if_printf(sc->sc_if, "CRC/Alignment error\n");
984263bc
MD
717#endif
718 sc->sc_if.if_ierrors++;
719 }
720
721 if (status & INTSTAT_TXU) {
722 epic_tx_underrun(sc);
723 sc->sc_if.if_oerrors++;
724 }
725 }
726 }
727
728 /* If no packets are pending, then no timeouts */
729 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
730
731 return;
732}
733
734/*
735 * Handle the TX underrun error: increase the TX threshold
736 * and restart the transmitter.
737 */
738static void
2b272d21 739epic_tx_underrun(epic_softc_t *sc)
984263bc
MD
740{
741 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
742 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
743#if defined(EPIC_DIAG)
c8e12de8 744 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
984263bc
MD
745#endif
746 } else {
747 sc->tx_threshold += 0x40;
748#if defined(EPIC_DIAG)
c8e12de8
JS
749 if_printf(&sc->sc_if, "Tx UNDERRUN: "
750 "TX threshold increased to %d\n", sc->tx_threshold);
984263bc
MD
751#endif
752 }
753
754 /* We must set TXUGO to reset the stuck transmitter */
755 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
756
757 /* Update the TX threshold */
758 epic_stop_activity(sc);
759 epic_set_tx_mode(sc);
760 epic_start_activity(sc);
761
762 return;
763}
764
765/*
766 * Synopsis: This one is called if packets wasn't transmitted
767 * during timeout. Try to deallocate transmitted packets, and
768 * if success continue to work.
769 */
770static void
2b272d21 771epic_ifwatchdog(struct ifnet *ifp)
984263bc
MD
772{
773 epic_softc_t *sc = ifp->if_softc;
984263bc 774
c8e12de8 775 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
984263bc
MD
776
777 /* Try to finish queued packets */
778 epic_tx_done(sc);
779
780 /* If not successful */
781 if (sc->pending_txs > 0) {
782
783 ifp->if_oerrors+=sc->pending_txs;
784
785 /* Reinitialize board */
c8e12de8 786 if_printf(ifp, "reinitialization\n");
984263bc
MD
787 epic_stop(sc);
788 epic_init(sc);
789
790 } else
c8e12de8 791 if_printf(ifp, "seems we can continue normaly\n");
984263bc
MD
792
793 /* Start output */
882ec277
JS
794 if (!ifq_is_empty(&ifp->if_snd))
795 epic_ifstart(ifp);
984263bc
MD
796}
797
798/*
799 * Despite the name of this function, it doesn't update statistics, it only
800 * helps in autonegotiation process.
801 */
802static void
9e6fd080 803epic_stats_update(void *xsc)
984263bc 804{
9e6fd080 805 epic_softc_t *sc = xsc;
78195a76 806 struct ifnet *ifp = &sc->sc_if;
984263bc 807 struct mii_data * mii;
984263bc 808
78195a76 809 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
810
811 mii = device_get_softc(sc->miibus);
812 mii_tick(mii);
813
9e6fd080 814 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
984263bc 815
78195a76 816 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
817}
818
819/*
820 * Set media options.
821 */
822static int
2b272d21 823epic_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
824{
825 epic_softc_t *sc;
826 struct mii_data *mii;
827 struct ifmedia *ifm;
828 struct mii_softc *miisc;
829 int cfg, media;
830
831 sc = ifp->if_softc;
832 mii = device_get_softc(sc->miibus);
833 ifm = &mii->mii_media;
834 media = ifm->ifm_cur->ifm_media;
835
836 /* Do not do anything if interface is not up */
837 if ((ifp->if_flags & IFF_UP) == 0)
838 return (0);
839
840 /*
841 * Lookup current selected PHY
842 */
843 if (IFM_INST(media) == sc->serinst) {
844 sc->phyid = EPIC_SERIAL;
845 sc->physc = NULL;
846 } else {
847 /* If we're not selecting serial interface, select MII mode */
848 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
849 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
850
851 /* Default to unknown PHY */
852 sc->phyid = EPIC_UNKN_PHY;
853
854 /* Lookup selected PHY */
855 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
856 miisc = LIST_NEXT(miisc, mii_list)) {
857 if (IFM_INST(media) == miisc->mii_inst) {
858 sc->physc = miisc;
859 break;
860 }
861 }
862
863 /* Identify selected PHY */
864 if (sc->physc) {
865 int id1, id2, model, oui;
866
867 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
868 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
869
870 oui = MII_OUI(id1, id2);
871 model = MII_MODEL(id2);
872 switch (oui) {
873 case MII_OUI_QUALSEMI:
874 if (model == MII_MODEL_QUALSEMI_QS6612)
875 sc->phyid = EPIC_QS6612_PHY;
876 break;
877 case MII_OUI_xxALTIMA:
878 if (model == MII_MODEL_xxALTIMA_AC101)
879 sc->phyid = EPIC_AC101_PHY;
880 break;
881 case MII_OUI_xxLEVEL1:
882 if (model == MII_MODEL_xxLEVEL1_LXT970)
883 sc->phyid = EPIC_LXT970_PHY;
884 break;
885 }
886 }
887 }
888
889 /*
890 * Do PHY specific card setup
891 */
892
893 /* Call this, to isolate all not selected PHYs and
894 * set up selected
895 */
896 mii_mediachg(mii);
897
898 /* Do our own setup */
899 switch (sc->phyid) {
900 case EPIC_QS6612_PHY:
901 break;
902 case EPIC_AC101_PHY:
903 /* We have to powerup fiber tranceivers */
904 if (IFM_SUBTYPE(media) == IFM_100_FX)
905 sc->miicfg |= MIICFG_694_ENABLE;
906 else
907 sc->miicfg &= ~MIICFG_694_ENABLE;
908 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
909
910 break;
911 case EPIC_LXT970_PHY:
912 /* We have to powerup fiber tranceivers */
913 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
914 if (IFM_SUBTYPE(media) == IFM_100_FX)
915 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
916 else
917 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
918 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
919
920 break;
921 case EPIC_SERIAL:
922 /* Select serial PHY, (10base2/BNC usually) */
923 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
924 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
925
926 /* There is no driver to fill this */
927 mii->mii_media_active = media;
928 mii->mii_media_status = 0;
929
930 /* We need to call this manualy as i wasn't called
931 * in mii_mediachg()
932 */
933 epic_miibus_statchg(sc->dev);
934
935 break;
936 default:
c8e12de8 937 if_printf(ifp, "ERROR! Unknown PHY selected\n");
984263bc
MD
938 return (EINVAL);
939 }
940
941 return(0);
942}
943
944/*
945 * Report current media status.
946 */
947static void
2b272d21 948epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
949{
950 epic_softc_t *sc;
951 struct mii_data *mii;
952 struct ifmedia *ifm;
953
954 sc = ifp->if_softc;
955 mii = device_get_softc(sc->miibus);
956 ifm = &mii->mii_media;
957
958 /* Nothing should be selected if interface is down */
959 if ((ifp->if_flags & IFF_UP) == 0) {
960 ifmr->ifm_active = IFM_NONE;
961 ifmr->ifm_status = 0;
962
963 return;
964 }
965
966 /* Call underlying pollstat, if not serial PHY */
967 if (sc->phyid != EPIC_SERIAL)
968 mii_pollstat(mii);
969
970 /* Simply copy media info */
971 ifmr->ifm_active = mii->mii_media_active;
972 ifmr->ifm_status = mii->mii_media_status;
973
974 return;
975}
976
977/*
978 * Callback routine, called on media change.
979 */
980static void
2b272d21 981epic_miibus_statchg(device_t dev)
984263bc
MD
982{
983 epic_softc_t *sc;
984 struct mii_data *mii;
985 int media;
986
987 sc = device_get_softc(dev);
988 mii = device_get_softc(sc->miibus);
989 media = mii->mii_media_active;
990
991 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
992
993 /* If we are in full-duplex mode or loopback operation,
994 * we need to decouple receiver and transmitter.
995 */
996 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
997 sc->txcon |= TXCON_FULL_DUPLEX;
998
999 /* On some cards we need manualy set fullduplex led */
1000 if (sc->cardid == SMC9432FTX ||
1001 sc->cardid == SMC9432FTX_SC) {
1002 if (IFM_OPTIONS(media) & IFM_FDX)
1003 sc->miicfg |= MIICFG_694_ENABLE;
1004 else
1005 sc->miicfg &= ~MIICFG_694_ENABLE;
1006
1007 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1008 }
1009
1010 /* Update baudrate */
1011 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1012 IFM_SUBTYPE(media) == IFM_100_FX)
1013 sc->sc_if.if_baudrate = 100000000;
1014 else
1015 sc->sc_if.if_baudrate = 10000000;
1016
1017 epic_stop_activity(sc);
1018 epic_set_tx_mode(sc);
1019 epic_start_activity(sc);
1020
1021 return;
1022}
1023
1024static void
2b272d21 1025epic_miibus_mediainit(device_t dev)
984263bc
MD
1026{
1027 epic_softc_t *sc;
1028 struct mii_data *mii;
1029 struct ifmedia *ifm;
1030 int media;
1031
1032 sc = device_get_softc(dev);
1033 mii = device_get_softc(sc->miibus);
1034 ifm = &mii->mii_media;
1035
1036 /* Add Serial Media Interface if present, this applies to
1037 * SMC9432BTX serie
1038 */
1039 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1040 /* Store its instance */
1041 sc->serinst = mii->mii_instance++;
1042
1043 /* Add as 10base2/BNC media */
1044 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1045 ifmedia_add(ifm, media, 0, NULL);
1046
1047 /* Report to user */
c8e12de8 1048 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
984263bc
MD
1049 }
1050
1051 return;
1052}
1053
1054/*
1055 * Reset chip, allocate rings, and update media.
1056 */
1057static int
2b272d21 1058epic_init(epic_softc_t *sc)
984263bc
MD
1059{
1060 struct ifnet *ifp = &sc->sc_if;
9228feed 1061 int i;
984263bc 1062
984263bc
MD
1063 /* If interface is already running, then we need not do anything */
1064 if (ifp->if_flags & IFF_RUNNING) {
984263bc
MD
1065 return 0;
1066 }
1067
1068 /* Soft reset the chip (we have to power up card before) */
1069 CSR_WRITE_4(sc, GENCTL, 0);
1070 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1071
1072 /*
1073 * Reset takes 15 pci ticks which depends on PCI bus speed.
1074 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1075 */
1076 DELAY(500);
1077
1078 /* Wake up */
1079 CSR_WRITE_4(sc, GENCTL, 0);
1080
1081 /* Workaround for Application Note 7-15 */
1082 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1083
1084 /* Initialize rings */
1085 if (epic_init_rings(sc)) {
c8e12de8 1086 if_printf(ifp, "failed to init rings\n");
984263bc
MD
1087 return -1;
1088 }
1089
1090 /* Give rings to EPIC */
1091 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1092 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1093
1094 /* Put node address to EPIC */
1095 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1096 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1097 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1098
1099 /* Set tx mode, includeing transmit threshold */
1100 epic_set_tx_mode(sc);
1101
1102 /* Compute and set RXCON. */
1103 epic_set_rx_mode(sc);
1104
1105 /* Set multicast table */
1106 epic_set_mc_table(sc);
1107
1108 /* Enable interrupts by setting the interrupt mask. */
1109 CSR_WRITE_4(sc, INTMASK,
1110 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1111 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1112 INTSTAT_FATAL);
1113
1114 /* Acknowledge all pending interrupts */
1115 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1116
1117 /* Enable interrupts, set for PCI read multiple and etc */
1118 CSR_WRITE_4(sc, GENCTL,
1119 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1120 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1121
1122 /* Mark interface running ... */
1123 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1124 else ifp->if_flags &= ~IFF_RUNNING;
1125
1126 /* ... and free */
1127 ifp->if_flags &= ~IFF_OACTIVE;
1128
1129 /* Start Rx process */
1130 epic_start_activity(sc);
1131
1132 /* Set appropriate media */
1133 epic_ifmedia_upd(ifp);
1134
9e6fd080 1135 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
984263bc 1136
984263bc
MD
1137 return 0;
1138}
1139
1140/*
1141 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1142 * access RXCON.
1143 */
1144static void
2b272d21 1145epic_set_rx_mode(epic_softc_t *sc)
984263bc
MD
1146{
1147 u_int32_t flags = sc->sc_if.if_flags;
1148 u_int32_t rxcon = RXCON_DEFAULT;
1149
1150#if defined(EPIC_EARLY_RX)
1151 rxcon |= RXCON_EARLY_RX;
1152#endif
1153
1154 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1155
1156 CSR_WRITE_4(sc, RXCON, rxcon);
1157
1158 return;
1159}
1160
1161/*
1162 * Synopsis: Set transmit control register. Chip must be in idle state to
1163 * access TXCON.
1164 */
1165static void
2b272d21 1166epic_set_tx_mode(epic_softc_t *sc)
984263bc
MD
1167{
1168 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1169 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1170
1171 CSR_WRITE_4(sc, TXCON, sc->txcon);
1172}
1173
1174/*
1175 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1176 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1177 * individual frames, multicast filter must be manually programmed)
1178 *
1179 * Note: EPIC must be in idle state.
1180 */
1181static void
2b272d21 1182epic_set_mc_table(epic_softc_t *sc)
984263bc
MD
1183{
1184 struct ifnet *ifp = &sc->sc_if;
1185 struct ifmultiaddr *ifma;
1186 u_int16_t filter[4];
1187 u_int8_t h;
1188
1189 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1190 CSR_WRITE_4(sc, MC0, 0xFFFF);
1191 CSR_WRITE_4(sc, MC1, 0xFFFF);
1192 CSR_WRITE_4(sc, MC2, 0xFFFF);
1193 CSR_WRITE_4(sc, MC3, 0xFFFF);
1194
1195 return;
1196 }
1197
1198 filter[0] = 0;
1199 filter[1] = 0;
1200 filter[2] = 0;
1201 filter[3] = 0;
1202
984263bc 1203 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1204 if (ifma->ifma_addr->sa_family != AF_LINK)
1205 continue;
7cf92e2d
JS
1206 h = (ether_crc32_be(
1207 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1208 ETHER_ADDR_LEN) >> 26) & 0x3f;
984263bc
MD
1209 filter[h >> 4] |= 1 << (h & 0xF);
1210 }
1211
1212 CSR_WRITE_4(sc, MC0, filter[0]);
1213 CSR_WRITE_4(sc, MC1, filter[1]);
1214 CSR_WRITE_4(sc, MC2, filter[2]);
1215 CSR_WRITE_4(sc, MC3, filter[3]);
1216
1217 return;
1218}
1219
984263bc
MD
1220/*
1221 * Synopsis: Start receive process and transmit one, if they need.
1222 */
1223static void
2b272d21 1224epic_start_activity(epic_softc_t *sc)
984263bc
MD
1225{
1226 /* Start rx process */
1227 CSR_WRITE_4(sc, COMMAND,
1228 COMMAND_RXQUEUED | COMMAND_START_RX |
1229 (sc->pending_txs?COMMAND_TXQUEUED:0));
1230}
1231
1232/*
1233 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1234 * packet needs to be queued to stop Tx DMA.
1235 */
1236static void
2b272d21 1237epic_stop_activity(epic_softc_t *sc)
984263bc
MD
1238{
1239 int status, i;
1240
1241 /* Stop Tx and Rx DMA */
1242 CSR_WRITE_4(sc, COMMAND,
1243 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1244
1245 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1246 for (i=0; i<0x1000; i++) {
1247 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1248 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1249 break;
1250 DELAY(1);
1251 }
1252
1253 /* Catch all finished packets */
1254 epic_rx_done(sc);
1255 epic_tx_done(sc);
1256
1257 status = CSR_READ_4(sc, INTSTAT);
1258
1259 if ((status & INTSTAT_RXIDLE) == 0)
c8e12de8 1260 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
984263bc
MD
1261
1262 if ((status & INTSTAT_TXIDLE) == 0)
c8e12de8 1263 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
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MD
1264
1265 /*
1266 * May need to queue one more packet if TQE, this is rare
1267 * but existing case.
1268 */
1269 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1270 (void) epic_queue_last_packet(sc);
1271
1272}
1273
1274/*
1275 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1276 * a packet from current descriptor will be copied to internal RAM. We
1277 * compose a dummy packet here and queue it for transmission.
1278 *
1279 * XXX the packet will then be actually sent over network...
1280 */
1281static int
2b272d21 1282epic_queue_last_packet(epic_softc_t *sc)
984263bc
MD
1283{
1284 struct epic_tx_desc *desc;
1285 struct epic_frag_list *flist;
1286 struct epic_tx_buffer *buf;
1287 struct mbuf *m0;
1288 int i;
1289
c8e12de8 1290 if_printf(&sc->sc_if, "queue last packet\n");
984263bc
MD
1291
1292 desc = sc->tx_desc + sc->cur_tx;
1293 flist = sc->tx_flist + sc->cur_tx;
1294 buf = sc->tx_buffer + sc->cur_tx;
1295
1296 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1297 return (EBUSY);
1298
74f1caca 1299 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
984263bc
MD
1300 if (NULL == m0)
1301 return (ENOBUFS);
1302
1303 /* Prepare mbuf */
1304 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1305 flist->frag[0].fraglen = m0->m_len;
1306 m0->m_pkthdr.len = m0->m_len;
1307 m0->m_pkthdr.rcvif = &sc->sc_if;
1308 bzero(mtod(m0,caddr_t), m0->m_len);
1309
1310 /* Fill fragments list */
1311 flist->frag[0].fraglen = m0->m_len;
1312 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1313 flist->numfrags = 1;
1314
1315 /* Fill in descriptor */
1316 buf->mbuf = m0;
1317 sc->pending_txs++;
1318 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1319 desc->control = 0x01;
1320 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1321 desc->status = 0x8000;
1322
1323 /* Launch transmition */
1324 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1325
1326 /* Wait Tx DMA to stop (for how long??? XXX) */
1327 for (i=0; i<1000; i++) {
1328 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1329 break;
1330 DELAY(1);
1331 }
1332
1333 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
c8e12de8 1334 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
984263bc
MD
1335 else
1336 epic_tx_done(sc);
1337
1338 return 0;
1339}
1340
1341/*
1342 * Synopsis: Shut down board and deallocates rings.
1343 */
1344static void
2b272d21 1345epic_stop(epic_softc_t *sc)
984263bc 1346{
984263bc
MD
1347 sc->sc_if.if_timer = 0;
1348
9e6fd080 1349 callout_stop(&sc->tx_stat_timer);
984263bc
MD
1350
1351 /* Disable interrupts */
1352 CSR_WRITE_4(sc, INTMASK, 0);
1353 CSR_WRITE_4(sc, GENCTL, 0);
1354
1355 /* Try to stop Rx and TX processes */
1356 epic_stop_activity(sc);
1357
1358 /* Reset chip */
1359 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1360 DELAY(1000);
1361
1362 /* Make chip go to bed */
1363 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1364
1365 /* Free memory allocated for rings */
1366 epic_free_rings(sc);
1367
1368 /* Mark as stoped */
1369 sc->sc_if.if_flags &= ~IFF_RUNNING;
984263bc
MD
1370}
1371
1372/*
1373 * Synopsis: This function should free all memory allocated for rings.
1374 */
1375static void
2b272d21 1376epic_free_rings(epic_softc_t *sc)
984263bc
MD
1377{
1378 int i;
1379
1380 for (i=0; i<RX_RING_SIZE; i++) {
1381 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1382 struct epic_rx_desc *desc = sc->rx_desc + i;
1383
1384 desc->status = 0;
1385 desc->buflength = 0;
1386 desc->bufaddr = 0;
1387
1388 if (buf->mbuf) m_freem(buf->mbuf);
1389 buf->mbuf = NULL;
1390 }
1391
1392 for (i=0; i<TX_RING_SIZE; i++) {
1393 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1394 struct epic_tx_desc *desc = sc->tx_desc + i;
1395
1396 desc->status = 0;
1397 desc->buflength = 0;
1398 desc->bufaddr = 0;
1399
1400 if (buf->mbuf) m_freem(buf->mbuf);
1401 buf->mbuf = NULL;
1402 }
1403}
1404
1405/*
1406 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1407 * Point Tx descs to fragment lists. Check that all descs and fraglists
1408 * are bounded and aligned properly.
1409 */
1410static int
2b272d21 1411epic_init_rings(epic_softc_t *sc)
984263bc
MD
1412{
1413 int i;
1414
1415 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1416
1417 for (i = 0; i < RX_RING_SIZE; i++) {
1418 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1419 struct epic_rx_desc *desc = sc->rx_desc + i;
1420
1421 desc->status = 0; /* Owned by driver */
1422 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1423
1424 if ((desc->next & 3) ||
1425 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1426 epic_free_rings(sc);
1427 return EFAULT;
1428 }
1429
290d24ac 1430 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
1431 if (NULL == buf->mbuf) {
1432 epic_free_rings(sc);
1433 return ENOBUFS;
1434 }
1435 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1436
1437 desc->buflength = MCLBYTES; /* Max RX buffer length */
1438 desc->status = 0x8000; /* Set owner bit to NIC */
1439 }
1440
1441 for (i = 0; i < TX_RING_SIZE; i++) {
1442 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1443 struct epic_tx_desc *desc = sc->tx_desc + i;
1444
1445 desc->status = 0;
1446 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1447
1448 if ((desc->next & 3) ||
1449 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1450 epic_free_rings(sc);
1451 return EFAULT;
1452 }
1453
1454 buf->mbuf = NULL;
1455 desc->bufaddr = vtophys(sc->tx_flist + i);
1456
1457 if ((desc->bufaddr & 3) ||
1458 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1459 epic_free_rings(sc);
1460 return EFAULT;
1461 }
1462 }
1463
1464 return 0;
1465}
1466
1467/*
1468 * EEPROM operation functions
1469 */
1470static void
2b272d21 1471epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
984263bc
MD
1472{
1473 u_int16_t i;
1474
1475 CSR_WRITE_1(sc, EECTL, val);
1476
1477 for (i=0; i<0xFF; i++)
1478 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1479
1480 return;
1481}
1482
1483static u_int8_t
2b272d21 1484epic_read_eepromreg(epic_softc_t *sc)
984263bc
MD
1485{
1486 return CSR_READ_1(sc, EECTL);
1487}
1488
1489static u_int8_t
2b272d21 1490epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
984263bc
MD
1491{
1492 epic_write_eepromreg(sc, val);
1493 epic_write_eepromreg(sc, (val | 0x4));
1494 epic_write_eepromreg(sc, val);
1495
1496 return epic_read_eepromreg(sc);
1497}
1498
1499static void
2b272d21 1500epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
984263bc
MD
1501{
1502 int i;
1503
1504 for (i = 0xF; i >= 0; i--) {
1505 if (val & (1 << i))
1506 epic_eeprom_clock(sc, 0x0B);
1507 else
1508 epic_eeprom_clock(sc, 0x03);
1509 }
1510}
1511
1512static u_int16_t
2b272d21 1513epic_input_eepromw(epic_softc_t *sc)
984263bc
MD
1514{
1515 u_int16_t retval = 0;
1516 int i;
1517
1518 for (i = 0xF; i >= 0; i--) {
1519 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1520 retval |= (1 << i);
1521 }
1522
1523 return retval;
1524}
1525
1526static int
2b272d21 1527epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
984263bc
MD
1528{
1529 u_int16_t dataval;
1530 u_int16_t read_cmd;
1531
1532 epic_write_eepromreg(sc, 3);
1533
1534 if (epic_read_eepromreg(sc) & 0x40)
1535 read_cmd = (loc & 0x3F) | 0x180;
1536 else
1537 read_cmd = (loc & 0xFF) | 0x600;
1538
1539 epic_output_eepromw(sc, read_cmd);
1540
1541 dataval = epic_input_eepromw(sc);
1542
1543 epic_write_eepromreg(sc, 1);
1544
1545 return dataval;
1546}
1547
1548/*
1549 * Here goes MII read/write routines
1550 */
1551static int
2b272d21 1552epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
984263bc
MD
1553{
1554 int i;
1555
1556 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1557
1558 for (i = 0; i < 0x100; i++) {
1559 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1560 DELAY(1);
1561 }
1562
1563 return (CSR_READ_4(sc, MIIDATA));
1564}
1565
1566static void
2b272d21 1567epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
984263bc
MD
1568{
1569 int i;
1570
1571 CSR_WRITE_4(sc, MIIDATA, val);
1572 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1573
1574 for(i=0;i<0x100;i++) {
1575 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1576 DELAY(1);
1577 }
1578
1579 return;
1580}
1581
1582static int
2b272d21 1583epic_miibus_readreg(device_t dev, int phy, int reg)
984263bc
MD
1584{
1585 epic_softc_t *sc;
1586
1587 sc = device_get_softc(dev);
1588
1589 return (PHY_READ_2(sc, phy, reg));
1590}
1591
1592static int
2b272d21 1593epic_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc
MD
1594{
1595 epic_softc_t *sc;
1596
1597 sc = device_get_softc(dev);
1598
1599 PHY_WRITE_2(sc, phy, reg, data);
1600
1601 return (0);
1602}