Make all network interrupt service routines MPSAFE part 1/3.
[dragonfly.git] / sys / dev / netif / txp / if_txp.c
CommitLineData
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1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2/* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
78195a76 3/* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.33 2005/11/28 17:13:44 dillon Exp $ */
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4
5/*
6 * Copyright (c) 2001
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/*
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/malloc.h>
48#include <sys/kernel.h>
49#include <sys/socket.h>
78195a76 50#include <sys/serialize.h>
9228feed 51#include <sys/thread2.h>
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52
53#include <net/if.h>
871d7209 54#include <net/ifq_var.h>
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55#include <net/if_arp.h>
56#include <net/ethernet.h>
57#include <net/if_dl.h>
58#include <net/if_types.h>
1f2de5d4 59#include <net/vlan/if_vlan_var.h>
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60
61#include <netinet/in.h>
62#include <netinet/in_systm.h>
63#include <netinet/in_var.h>
64#include <netinet/ip.h>
65#include <netinet/if_ether.h>
3f9db7f8 66#include <sys/in_cksum.h>
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67
68#include <net/if_media.h>
69
70#include <net/bpf.h>
71
72#include <vm/vm.h> /* for vtophys */
73#include <vm/pmap.h> /* for vtophys */
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74#include <machine/bus_pio.h>
75#include <machine/bus_memio.h>
76#include <machine/bus.h>
77#include <machine/resource.h>
78#include <sys/bus.h>
79#include <sys/rman.h>
80
1f2de5d4
MD
81#include "../mii_layer/mii.h"
82#include "../mii_layer/miivar.h"
83#include <bus/pci/pcireg.h>
84#include <bus/pci/pcivar.h>
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85
86#define TXP_USEIOSPACE
87#define __STRICT_ALIGNMENT
88
1f2de5d4
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89#include "if_txpreg.h"
90#include "3c990img.h"
984263bc 91
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92/*
93 * Various supported device vendors/types and their names.
94 */
95static struct txp_type txp_devs[] = {
96 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
97 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
99 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
101 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
103 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
105 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
107 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
108 { 0, 0, NULL }
109};
110
b5101a88
RG
111static int txp_probe (device_t);
112static int txp_attach (device_t);
113static int txp_detach (device_t);
114static void txp_intr (void *);
115static void txp_tick (void *);
116static int txp_shutdown (device_t);
bd4539cc 117static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
b5101a88
RG
118static void txp_start (struct ifnet *);
119static void txp_stop (struct txp_softc *);
120static void txp_init (void *);
121static void txp_watchdog (struct ifnet *);
122
fcb8c909 123static void txp_release_resources (device_t);
b5101a88
RG
124static int txp_chip_init (struct txp_softc *);
125static int txp_reset_adapter (struct txp_softc *);
126static int txp_download_fw (struct txp_softc *);
127static int txp_download_fw_wait (struct txp_softc *);
128static int txp_download_fw_section (struct txp_softc *,
129 struct txp_fw_section_header *, int);
130static int txp_alloc_rings (struct txp_softc *);
131static int txp_rxring_fill (struct txp_softc *);
132static void txp_rxring_empty (struct txp_softc *);
133static void txp_set_filter (struct txp_softc *);
134
135static int txp_cmd_desc_numfree (struct txp_softc *);
136static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
137 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
138static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
984263bc 139 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
b5101a88
RG
140 struct txp_rsp_desc **, int);
141static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
142 struct txp_rsp_desc **);
143static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
144 struct txp_rsp_desc *);
145static void txp_capabilities (struct txp_softc *);
146
147static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
148static int txp_ifmedia_upd (struct ifnet *);
984263bc 149#ifdef TXP_DEBUG
b5101a88 150static void txp_show_descriptor (void *);
984263bc 151#endif
b5101a88
RG
152static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
153static void txp_rxbuf_reclaim (struct txp_softc *);
154static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
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155
156#ifdef TXP_USEIOSPACE
157#define TXP_RES SYS_RES_IOPORT
158#define TXP_RID TXP_PCI_LOIO
159#else
160#define TXP_RES SYS_RES_MEMORY
161#define TXP_RID TXP_PCI_LOMEM
162#endif
163
164static device_method_t txp_methods[] = {
165 /* Device interface */
166 DEVMETHOD(device_probe, txp_probe),
167 DEVMETHOD(device_attach, txp_attach),
168 DEVMETHOD(device_detach, txp_detach),
169 DEVMETHOD(device_shutdown, txp_shutdown),
170 { 0, 0 }
171};
172
173static driver_t txp_driver = {
174 "txp",
175 txp_methods,
176 sizeof(struct txp_softc)
177};
178
179static devclass_t txp_devclass;
180
32832096 181DECLARE_DUMMY_MODULE(if_txp);
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182DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
183
184static int
185txp_probe(dev)
186 device_t dev;
187{
188 struct txp_type *t;
6a89baeb 189 uint16_t vid, did;
984263bc 190
6a89baeb
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191 vid = pci_get_vendor(dev);
192 did = pci_get_device(dev);
984263bc 193
6a89baeb
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194 for (t = txp_devs; t->txp_name != NULL; ++t) {
195 if ((vid == t->txp_vid) && (did == t->txp_did)) {
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196 device_set_desc(dev, t->txp_name);
197 return(0);
198 }
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199 }
200
201 return(ENXIO);
202}
203
204static int
205txp_attach(dev)
206 device_t dev;
207{
208 struct txp_softc *sc;
209 struct ifnet *ifp;
52bcf561
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210 uint16_t p1;
211 uint32_t p2;
212 uint8_t enaddr[ETHER_ADDR_LEN];
fcb8c909 213 int error = 0, rid;
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214
215 sc = device_get_softc(dev);
9e6fd080 216 callout_init(&sc->txp_stat_timer);
984263bc 217
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218 ifp = &sc->sc_arpcom.ac_if;
219 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
220
6cc66259 221 pci_enable_busmaster(dev);
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222
223 rid = TXP_RID;
4e6d744d 224 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
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225
226 if (sc->sc_res == NULL) {
227 device_printf(dev, "couldn't map ports/memory\n");
402379ab 228 return(ENXIO);
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229 }
230
231 sc->sc_bt = rman_get_bustag(sc->sc_res);
232 sc->sc_bh = rman_get_bushandle(sc->sc_res);
233
234 /* Allocate interrupt */
235 rid = 0;
4e6d744d 236 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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237 RF_SHAREABLE | RF_ACTIVE);
238
239 if (sc->sc_irq == NULL) {
240 device_printf(dev, "couldn't map interrupt\n");
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241 error = ENXIO;
242 goto fail;
243 }
244
984263bc 245 if (txp_chip_init(sc)) {
402379ab 246 error = ENXIO;
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247 goto fail;
248 }
249
250 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
140e8e99 251 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
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252 error = txp_download_fw(sc);
253 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
254 sc->sc_fwbuf = NULL;
255
402379ab 256 if (error)
984263bc 257 goto fail;
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258
259 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
140e8e99 260 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
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261 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
262
263 if (txp_alloc_rings(sc)) {
402379ab 264 error = ENXIO;
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265 goto fail;
266 }
267
268 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
269 NULL, NULL, NULL, 1)) {
402379ab 270 error = ENXIO;
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271 goto fail;
272 }
273
274 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
275 &p1, &p2, NULL, 1)) {
402379ab 276 error = ENXIO;
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277 goto fail;
278 }
279
280 txp_set_filter(sc);
281
52bcf561
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282 enaddr[0] = ((uint8_t *)&p1)[1];
283 enaddr[1] = ((uint8_t *)&p1)[0];
284 enaddr[2] = ((uint8_t *)&p2)[3];
285 enaddr[3] = ((uint8_t *)&p2)[2];
286 enaddr[4] = ((uint8_t *)&p2)[1];
287 enaddr[5] = ((uint8_t *)&p2)[0];
984263bc 288
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289 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
290 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
291 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
292 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
293 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
294 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
297
298 sc->sc_xcvr = TXP_XCVR_AUTO;
299 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
300 NULL, NULL, NULL, 0);
301 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
302
984263bc 303 ifp->if_softc = sc;
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304 ifp->if_mtu = ETHERMTU;
305 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
306 ifp->if_ioctl = txp_ioctl;
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307 ifp->if_start = txp_start;
308 ifp->if_watchdog = txp_watchdog;
309 ifp->if_init = txp_init;
310 ifp->if_baudrate = 100000000;
871d7209
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311 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
312 ifq_set_ready(&ifp->if_snd);
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313 ifp->if_hwassist = 0;
314 txp_capabilities(sc);
315
78195a76 316 ether_ifattach(ifp, enaddr, NULL);
140e8e99 317
78195a76
MD
318 error = bus_setup_intr(dev, sc->sc_irq, INTR_NETSAFE,
319 txp_intr, sc, &sc->sc_intrhand,
320 ifp->if_serializer);
140e8e99
JS
321 if (error) {
322 device_printf(dev, "couldn't set up irq\n");
323 ether_ifdetach(ifp);
324 goto fail;
325 }
326
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327 return(0);
328
329fail:
fcb8c909 330 txp_release_resources(dev);
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331 return(error);
332}
333
334static int
335txp_detach(dev)
336 device_t dev;
337{
338 struct txp_softc *sc;
339 struct ifnet *ifp;
340 int i;
341
342 sc = device_get_softc(dev);
343 ifp = &sc->sc_arpcom.ac_if;
78195a76 344 lwkt_serialize_enter(ifp->if_serializer);
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345
346 txp_stop(sc);
347 txp_shutdown(dev);
348
349 ifmedia_removeall(&sc->sc_ifmedia);
0a8b5977 350 ether_ifdetach(ifp);
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351
352 for (i = 0; i < RXBUF_ENTRIES; i++)
353 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
354
fcb8c909 355 txp_release_resources(dev);
78195a76 356 lwkt_serialize_exit(ifp->if_serializer);
140e8e99 357
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358 return(0);
359}
360
361static void
fcb8c909 362txp_release_resources(device_t dev)
984263bc 363{
fcb8c909 364 struct txp_softc *sc;
984263bc 365
fcb8c909 366 sc = device_get_softc(dev);
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367
368 if (sc->sc_intrhand != NULL)
369 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
370
371 if (sc->sc_irq != NULL)
372 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
373
374 if (sc->sc_res != NULL)
375 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
376
377 if (sc->sc_ldata != NULL)
378 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
379
380 return;
381}
382
383static int
384txp_chip_init(sc)
385 struct txp_softc *sc;
386{
387 /* disable interrupts */
388 WRITE_REG(sc, TXP_IER, 0);
389 WRITE_REG(sc, TXP_IMR,
390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
392 TXP_INT_LATCH);
393
394 /* ack all interrupts */
395 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
396 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
397 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
398 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
399 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
400
401 if (txp_reset_adapter(sc))
402 return (-1);
403
404 /* disable interrupts */
405 WRITE_REG(sc, TXP_IER, 0);
406 WRITE_REG(sc, TXP_IMR,
407 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
408 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
409 TXP_INT_LATCH);
410
411 /* ack all interrupts */
412 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
413 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
414 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
415 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
416 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
417
418 return (0);
419}
420
421static int
422txp_reset_adapter(sc)
423 struct txp_softc *sc;
424{
425 u_int32_t r;
426 int i;
427
428 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
429 DELAY(1000);
430 WRITE_REG(sc, TXP_SRR, 0);
431
432 /* Should wait max 6 seconds */
433 for (i = 0; i < 6000; i++) {
434 r = READ_REG(sc, TXP_A2H_0);
435 if (r == STAT_WAITING_FOR_HOST_REQUEST)
436 break;
437 DELAY(1000);
438 }
439
440 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909 441 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
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442 return (-1);
443 }
444
445 return (0);
446}
447
448static int
449txp_download_fw(sc)
450 struct txp_softc *sc;
451{
452 struct txp_fw_file_header *fileheader;
453 struct txp_fw_section_header *secthead;
454 int sect;
455 u_int32_t r, i, ier, imr;
456
457 ier = READ_REG(sc, TXP_IER);
458 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
459
460 imr = READ_REG(sc, TXP_IMR);
461 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
462
463 for (i = 0; i < 10000; i++) {
464 r = READ_REG(sc, TXP_A2H_0);
465 if (r == STAT_WAITING_FOR_HOST_REQUEST)
466 break;
467 DELAY(50);
468 }
469 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909
JS
470 if_printf(&sc->sc_arpcom.ac_if,
471 "not waiting for host request\n");
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472 return (-1);
473 }
474
475 /* Ack the status */
476 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
477
478 fileheader = (struct txp_fw_file_header *)tc990image;
479 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
fcb8c909 480 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
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481 return (-1);
482 }
483
484 /* Tell boot firmware to get ready for image */
485 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
486 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
487
488 if (txp_download_fw_wait(sc)) {
fcb8c909 489 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
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490 return (-1);
491 }
492
493 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
494 sizeof(struct txp_fw_file_header));
495
496 for (sect = 0; sect < fileheader->nsections; sect++) {
497 if (txp_download_fw_section(sc, secthead, sect))
498 return (-1);
499 secthead = (struct txp_fw_section_header *)
500 (((u_int8_t *)secthead) + secthead->nbytes +
501 sizeof(*secthead));
502 }
503
504 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
505
506 for (i = 0; i < 10000; i++) {
507 r = READ_REG(sc, TXP_A2H_0);
508 if (r == STAT_WAITING_FOR_BOOT)
509 break;
510 DELAY(50);
511 }
512 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 513 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
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514 return (-1);
515 }
516
517 WRITE_REG(sc, TXP_IER, ier);
518 WRITE_REG(sc, TXP_IMR, imr);
519
520 return (0);
521}
522
523static int
524txp_download_fw_wait(sc)
525 struct txp_softc *sc;
526{
527 u_int32_t i, r;
528
529 for (i = 0; i < 10000; i++) {
530 r = READ_REG(sc, TXP_ISR);
531 if (r & TXP_INT_A2H_0)
532 break;
533 DELAY(50);
534 }
535
536 if (!(r & TXP_INT_A2H_0)) {
fcb8c909 537 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
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538 return (-1);
539 }
540
541 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
542
543 r = READ_REG(sc, TXP_A2H_0);
544 if (r != STAT_WAITING_FOR_SEGMENT) {
fcb8c909 545 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
984263bc
MD
546 return (-1);
547 }
548 return (0);
549}
550
551static int
552txp_download_fw_section(sc, sect, sectnum)
553 struct txp_softc *sc;
554 struct txp_fw_section_header *sect;
555 int sectnum;
556{
557 vm_offset_t dma;
558 int rseg, err = 0;
559 struct mbuf m;
560 u_int16_t csum;
561
562 /* Skip zero length sections */
563 if (sect->nbytes == 0)
564 return (0);
565
566 /* Make sure we aren't past the end of the image */
567 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
568 if (rseg >= sizeof(tc990image)) {
fcb8c909 569 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
984263bc
MD
570 "section %d\n", sectnum);
571 return (-1);
572 }
573
574 /* Make sure this section doesn't go past the end */
575 rseg += sect->nbytes;
576 if (rseg >= sizeof(tc990image)) {
fcb8c909 577 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
984263bc
MD
578 sectnum);
579 return (-1);
580 }
581
582 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
583 dma = vtophys(sc->sc_fwbuf);
584
585 /*
586 * dummy up mbuf and verify section checksum
587 */
588 m.m_type = MT_DATA;
589 m.m_next = m.m_nextpkt = NULL;
590 m.m_len = sect->nbytes;
591 m.m_data = sc->sc_fwbuf;
592 m.m_flags = 0;
593 csum = in_cksum(&m, sect->nbytes);
594 if (csum != sect->cksum) {
fcb8c909 595 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
984263bc
MD
596 "cksum (expected 0x%x got 0x%x)\n",
597 sectnum, sect->cksum, csum);
598 err = -1;
599 goto bail;
600 }
601
602 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
603 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
604 WRITE_REG(sc, TXP_H2A_3, sect->addr);
605 WRITE_REG(sc, TXP_H2A_4, 0);
606 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
607 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
608
609 if (txp_download_fw_wait(sc)) {
fcb8c909 610 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
984263bc
MD
611 "section %d\n", sectnum);
612 err = -1;
613 }
614
615bail:
616 return (err);
617}
618
619static void
620txp_intr(vsc)
621 void *vsc;
622{
623 struct txp_softc *sc = vsc;
624 struct txp_hostvar *hv = sc->sc_hostvar;
625 u_int32_t isr;
626
627 /* mask all interrupts */
628 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
629 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
630 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
631 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
632 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
633
634 isr = READ_REG(sc, TXP_ISR);
635 while (isr) {
636 WRITE_REG(sc, TXP_ISR, isr);
637
638 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
639 txp_rx_reclaim(sc, &sc->sc_rxhir);
640 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
641 txp_rx_reclaim(sc, &sc->sc_rxlor);
642
643 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
644 txp_rxbuf_reclaim(sc);
645
646 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
647 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
648 txp_tx_reclaim(sc, &sc->sc_txhir);
649
650 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
651 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
652 txp_tx_reclaim(sc, &sc->sc_txlor);
653
654 isr = READ_REG(sc, TXP_ISR);
655 }
656
657 /* unmask all interrupts */
658 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
659
660 txp_start(&sc->sc_arpcom.ac_if);
661
662 return;
663}
664
665static void
666txp_rx_reclaim(sc, r)
667 struct txp_softc *sc;
668 struct txp_rx_ring *r;
669{
670 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
671 struct txp_rx_desc *rxd;
672 struct mbuf *m;
673 struct txp_swdesc *sd = NULL;
674 u_int32_t roff, woff;
984263bc
MD
675
676 roff = *r->r_roff;
677 woff = *r->r_woff;
678 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
679
680 while (roff != woff) {
681
682 if (rxd->rx_flags & RX_FLAGS_ERROR) {
fcb8c909 683 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
984263bc
MD
684 ifp->if_ierrors++;
685 goto next;
686 }
687
688 /* retrieve stashed pointer */
689 sd = rxd->rx_sd;
690
691 m = sd->sd_mbuf;
692 sd->sd_mbuf = NULL;
693
694 m->m_pkthdr.len = m->m_len = rxd->rx_len;
695
696#ifdef __STRICT_ALIGNMENT
697 {
698 /*
699 * XXX Nice chip, except it won't accept "off by 2"
700 * buffers, so we're force to copy. Supposedly
701 * this will be fixed in a newer firmware rev
702 * and this will be temporary.
703 */
704 struct mbuf *mnew;
705
74f1caca 706 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
984263bc
MD
707 if (mnew == NULL) {
708 m_freem(m);
709 goto next;
710 }
711 if (m->m_len > (MHLEN - 2)) {
74f1caca 712 MCLGET(mnew, MB_DONTWAIT);
984263bc
MD
713 if (!(mnew->m_flags & M_EXT)) {
714 m_freem(mnew);
715 m_freem(m);
716 goto next;
717 }
718 }
719 mnew->m_pkthdr.rcvif = ifp;
720 m_adj(mnew, 2);
721 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
722 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
723 m_freem(m);
724 m = mnew;
725 }
726#endif
727
728 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
729 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
730 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
731 m->m_pkthdr.csum_flags |=
732 CSUM_IP_CHECKED|CSUM_IP_VALID;
733
734 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
735 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
736 m->m_pkthdr.csum_flags |=
737 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
738 m->m_pkthdr.csum_data = 0xffff;
739 }
740
78195a76 741 lwkt_serialize_enter(ifp->if_serializer);
3013ac0e
JS
742 if (rxd->rx_stat & RX_STAT_VLAN)
743 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
744 else
78195a76
MD
745 ifp->if_input(ifp, m);
746 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
747
748next:
749
750 roff += sizeof(struct txp_rx_desc);
751 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
752 roff = 0;
753 rxd = r->r_desc;
754 } else
755 rxd++;
756 woff = *r->r_woff;
757 }
758
759 *r->r_roff = woff;
760
761 return;
762}
763
764static void
765txp_rxbuf_reclaim(sc)
766 struct txp_softc *sc;
767{
768 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
769 struct txp_hostvar *hv = sc->sc_hostvar;
770 struct txp_rxbuf_desc *rbd;
771 struct txp_swdesc *sd;
772 u_int32_t i;
773
774 if (!(ifp->if_flags & IFF_RUNNING))
775 return;
776
777 i = sc->sc_rxbufprod;
778 rbd = sc->sc_rxbufs + i;
779
780 while (1) {
781 sd = rbd->rb_sd;
782 if (sd->sd_mbuf != NULL)
783 break;
784
74f1caca 785 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
786 if (sd->sd_mbuf == NULL)
787 goto err_sd;
788
74f1caca 789 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
790 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
791 goto err_mbuf;
792 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
793 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
794
795 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
796 & 0xffffffff;
797 rbd->rb_paddrhi = 0;
798
799 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
800
801 if (++i == RXBUF_ENTRIES) {
802 i = 0;
803 rbd = sc->sc_rxbufs;
804 } else
805 rbd++;
806 }
807
808 sc->sc_rxbufprod = i;
809
810 return;
811
812err_mbuf:
813 m_freem(sd->sd_mbuf);
814err_sd:
815 free(sd, M_DEVBUF);
816}
817
818/*
819 * Reclaim mbufs and entries from a transmit ring.
820 */
821static void
822txp_tx_reclaim(sc, r)
823 struct txp_softc *sc;
824 struct txp_tx_ring *r;
825{
826 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
827 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
828 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
829 struct txp_tx_desc *txd = r->r_desc + cons;
830 struct txp_swdesc *sd = sc->sc_txd + cons;
831 struct mbuf *m;
832
833 while (cons != idx) {
834 if (cnt == 0)
835 break;
836
837 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
838 TX_FLAGS_TYPE_DATA) {
839 m = sd->sd_mbuf;
840 if (m != NULL) {
841 m_freem(m);
842 txd->tx_addrlo = 0;
843 txd->tx_addrhi = 0;
844 ifp->if_opackets++;
845 }
846 }
847 ifp->if_flags &= ~IFF_OACTIVE;
848
849 if (++cons == TX_ENTRIES) {
850 txd = r->r_desc;
851 cons = 0;
852 sd = sc->sc_txd;
853 } else {
854 txd++;
855 sd++;
856 }
857
858 cnt--;
859 }
860
861 r->r_cons = cons;
862 r->r_cnt = cnt;
863 if (cnt == 0)
864 ifp->if_timer = 0;
865}
866
867static int
868txp_shutdown(dev)
869 device_t dev;
870{
871 struct txp_softc *sc;
78195a76 872 struct ifnet *ifp;
984263bc
MD
873
874 sc = device_get_softc(dev);
78195a76
MD
875 ifp = &sc->sc_arpcom.ac_if;
876 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
877
878 /* mask all interrupts */
879 WRITE_REG(sc, TXP_IMR,
880 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
881 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
882 TXP_INT_LATCH);
883
884 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
885 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
886 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
887
78195a76 888 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
889 return(0);
890}
891
892static int
893txp_alloc_rings(sc)
894 struct txp_softc *sc;
895{
896 struct txp_boot_record *boot;
897 struct txp_ldata *ld;
898 u_int32_t r;
899 int i;
900
901 ld = sc->sc_ldata;
902 boot = &ld->txp_boot;
903
904 /* boot record */
905 sc->sc_boot = boot;
906
907 /* host variables */
908 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
909 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
910 boot->br_hostvar_hi = 0;
911 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
912
913 /* hi priority tx ring */
914 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
915 boot->br_txhipri_hi = 0;
916 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
917 sc->sc_txhir.r_reg = TXP_H2A_1;
918 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
919 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
920 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
921
922 /* lo priority tx ring */
923 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
924 boot->br_txlopri_hi = 0;
925 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
926 sc->sc_txlor.r_reg = TXP_H2A_3;
927 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
928 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
929 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
930
931 /* high priority rx ring */
932 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
933 boot->br_rxhipri_hi = 0;
934 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
935 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
936 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
937 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
938
939 /* low priority rx ring */
940 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
941 boot->br_rxlopri_hi = 0;
942 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
943 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
944 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
945 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
946
947 /* command ring */
948 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
949 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
950 boot->br_cmd_hi = 0;
951 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
952 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
953 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
954 sc->sc_cmdring.lastwrite = 0;
955
956 /* response ring */
957 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
958 boot->br_resp_lo = vtophys(&ld->txp_rspring);
959 boot->br_resp_hi = 0;
960 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
961 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
962 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
963 sc->sc_rspring.lastwrite = 0;
964
965 /* receive buffer ring */
966 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
967 boot->br_rxbuf_hi = 0;
968 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
969 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
970
971 for (i = 0; i < RXBUF_ENTRIES; i++) {
972 struct txp_swdesc *sd;
973 if (sc->sc_rxbufs[i].rb_sd != NULL)
974 continue;
975 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
c5541aee 976 M_DEVBUF, M_WAITOK);
984263bc
MD
977 if (sc->sc_rxbufs[i].rb_sd == NULL)
978 return(ENOBUFS);
979 sd = sc->sc_rxbufs[i].rb_sd;
980 sd->sd_mbuf = NULL;
981 }
982 sc->sc_rxbufprod = 0;
983
984 /* zero dma */
985 bzero(&ld->txp_zero, sizeof(u_int32_t));
986 boot->br_zero_lo = vtophys(&ld->txp_zero);
987 boot->br_zero_hi = 0;
988
989 /* See if it's waiting for boot, and try to boot it */
990 for (i = 0; i < 10000; i++) {
991 r = READ_REG(sc, TXP_A2H_0);
992 if (r == STAT_WAITING_FOR_BOOT)
993 break;
994 DELAY(50);
995 }
996
997 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 998 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
984263bc
MD
999 return(ENXIO);
1000 }
1001
1002 WRITE_REG(sc, TXP_H2A_2, 0);
1003 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
1004 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
1005
1006 /* See if it booted */
1007 for (i = 0; i < 10000; i++) {
1008 r = READ_REG(sc, TXP_A2H_0);
1009 if (r == STAT_RUNNING)
1010 break;
1011 DELAY(50);
1012 }
1013 if (r != STAT_RUNNING) {
fcb8c909 1014 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
984263bc
MD
1015 return(ENXIO);
1016 }
1017
1018 /* Clear TX and CMD ring write registers */
1019 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1020 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1021 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1022 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1023
1024 return (0);
1025}
1026
1027static int
bd4539cc 1028txp_ioctl(ifp, command, data, cr)
984263bc
MD
1029 struct ifnet *ifp;
1030 u_long command;
1031 caddr_t data;
bd4539cc 1032 struct ucred *cr;
984263bc
MD
1033{
1034 struct txp_softc *sc = ifp->if_softc;
1035 struct ifreq *ifr = (struct ifreq *)data;
9228feed 1036 int error = 0;
984263bc 1037
984263bc 1038 switch(command) {
984263bc
MD
1039 case SIOCSIFFLAGS:
1040 if (ifp->if_flags & IFF_UP) {
1041 txp_init(sc);
1042 } else {
1043 if (ifp->if_flags & IFF_RUNNING)
1044 txp_stop(sc);
1045 }
1046 break;
1047 case SIOCADDMULTI:
1048 case SIOCDELMULTI:
1049 /*
1050 * Multicast list has changed; set the hardware
1051 * filter accordingly.
1052 */
1053 txp_set_filter(sc);
1054 error = 0;
1055 break;
1056 case SIOCGIFMEDIA:
1057 case SIOCSIFMEDIA:
1058 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1059 break;
1060 default:
417b83e4 1061 error = ether_ioctl(ifp, command, data);
984263bc
MD
1062 break;
1063 }
984263bc
MD
1064 return(error);
1065}
1066
1067static int
1068txp_rxring_fill(sc)
1069 struct txp_softc *sc;
1070{
1071 int i;
1072 struct ifnet *ifp;
1073 struct txp_swdesc *sd;
1074
1075 ifp = &sc->sc_arpcom.ac_if;
1076
1077 for (i = 0; i < RXBUF_ENTRIES; i++) {
1078 sd = sc->sc_rxbufs[i].rb_sd;
74f1caca 1079 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
1080 if (sd->sd_mbuf == NULL)
1081 return(ENOBUFS);
1082
74f1caca 1083 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
1084 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1085 m_freem(sd->sd_mbuf);
1086 return(ENOBUFS);
1087 }
1088 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1089 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1090
1091 sc->sc_rxbufs[i].rb_paddrlo =
1092 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1093 sc->sc_rxbufs[i].rb_paddrhi = 0;
1094 }
1095
1096 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1097 sizeof(struct txp_rxbuf_desc);
1098
1099 return(0);
1100}
1101
1102static void
1103txp_rxring_empty(sc)
1104 struct txp_softc *sc;
1105{
1106 int i;
1107 struct txp_swdesc *sd;
1108
1109 if (sc->sc_rxbufs == NULL)
1110 return;
1111
1112 for (i = 0; i < RXBUF_ENTRIES; i++) {
1113 if (&sc->sc_rxbufs[i] == NULL)
1114 continue;
1115 sd = sc->sc_rxbufs[i].rb_sd;
1116 if (sd == NULL)
1117 continue;
1118 if (sd->sd_mbuf != NULL) {
1119 m_freem(sd->sd_mbuf);
1120 sd->sd_mbuf = NULL;
1121 }
1122 }
1123
1124 return;
1125}
1126
1127static void
1128txp_init(xsc)
1129 void *xsc;
1130{
1131 struct txp_softc *sc;
1132 struct ifnet *ifp;
1133 u_int16_t p1;
1134 u_int32_t p2;
984263bc
MD
1135
1136 sc = xsc;
1137 ifp = &sc->sc_arpcom.ac_if;
1138
1139 if (ifp->if_flags & IFF_RUNNING)
1140 return;
1141
1142 txp_stop(sc);
1143
984263bc
MD
1144 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1145 NULL, NULL, NULL, 1);
1146
1147 /* Set station address. */
1148 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1149 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1150 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1151 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1152 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1153 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1154 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1155 NULL, NULL, NULL, 1);
1156
1157 txp_set_filter(sc);
1158
1159 txp_rxring_fill(sc);
1160
1161 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1162 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1163
1164 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1165 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1166 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1167 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1168 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1169 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1170
1171 ifp->if_flags |= IFF_RUNNING;
1172 ifp->if_flags &= ~IFF_OACTIVE;
1173 ifp->if_timer = 0;
1174
9e6fd080 1175 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
984263bc
MD
1176}
1177
1178static void
1179txp_tick(vsc)
1180 void *vsc;
1181{
1182 struct txp_softc *sc = vsc;
1183 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1184 struct txp_rsp_desc *rsp = NULL;
1185 struct txp_ext_desc *ext;
984263bc 1186
78195a76 1187 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
1188 txp_rxbuf_reclaim(sc);
1189
1190 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1191 &rsp, 1))
1192 goto out;
1193 if (rsp->rsp_numdesc != 6)
1194 goto out;
1195 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1196 NULL, NULL, NULL, 1))
1197 goto out;
1198 ext = (struct txp_ext_desc *)(rsp + 1);
1199
1200 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1201 ext[4].ext_1 + ext[4].ext_4;
1202 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1203 ext[2].ext_1;
1204 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1205 ext[1].ext_3;
1206 ifp->if_opackets += rsp->rsp_par2;
1207 ifp->if_ipackets += ext[2].ext_3;
1208
1209out:
1210 if (rsp != NULL)
1211 free(rsp, M_DEVBUF);
1212
9e6fd080 1213 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
78195a76 1214 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1215}
1216
1217static void
1218txp_start(ifp)
1219 struct ifnet *ifp;
1220{
1221 struct txp_softc *sc = ifp->if_softc;
1222 struct txp_tx_ring *r = &sc->sc_txhir;
1223 struct txp_tx_desc *txd;
1224 struct txp_frag_desc *fxd;
1225 struct mbuf *m, *m0;
1226 struct txp_swdesc *sd;
1227 u_int32_t firstprod, firstcnt, prod, cnt;
1228 struct ifvlan *ifv;
1229
1230 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1231 return;
1232
1233 prod = r->r_prod;
1234 cnt = r->r_cnt;
1235
1236 while (1) {
871d7209 1237 m = ifq_poll(&ifp->if_snd);
984263bc
MD
1238 if (m == NULL)
1239 break;
1240
1241 firstprod = prod;
1242 firstcnt = cnt;
1243
1244 sd = sc->sc_txd + prod;
1245 sd->sd_mbuf = m;
1246
1247 if ((TX_ENTRIES - cnt) < 4)
1248 goto oactive;
1249
1250 txd = r->r_desc + prod;
1251
1252 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1253 txd->tx_numdesc = 0;
1254 txd->tx_addrlo = 0;
1255 txd->tx_addrhi = 0;
1256 txd->tx_totlen = 0;
1257 txd->tx_pflags = 0;
1258
1259 if (++prod == TX_ENTRIES)
1260 prod = 0;
1261
1262 if (++cnt >= (TX_ENTRIES - 4))
1263 goto oactive;
1264
1265 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1266 m->m_pkthdr.rcvif != NULL) {
1267 ifv = m->m_pkthdr.rcvif->if_softc;
1268 txd->tx_pflags = TX_PFLAGS_VLAN |
1269 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1270 }
1271
1272 if (m->m_pkthdr.csum_flags & CSUM_IP)
1273 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1274
1275#if 0
1276 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1277 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1278 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1279 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1280#endif
1281
1282 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1283 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1284 if (m0->m_len == 0)
1285 continue;
1286 if (++cnt >= (TX_ENTRIES - 4))
1287 goto oactive;
1288
1289 txd->tx_numdesc++;
1290
1291 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1292 fxd->frag_rsvd1 = 0;
1293 fxd->frag_len = m0->m_len;
1294 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1295 fxd->frag_addrhi = 0;
1296 fxd->frag_rsvd2 = 0;
1297
1298 if (++prod == TX_ENTRIES) {
1299 fxd = (struct txp_frag_desc *)r->r_desc;
1300 prod = 0;
1301 } else
1302 fxd++;
1303
1304 }
1305
1306 ifp->if_timer = 5;
1307
d2c71fa0 1308 ifq_dequeue(&ifp->if_snd, m);
7600679e 1309 BPF_MTAP(ifp, m);
984263bc
MD
1310 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1311 }
1312
1313 r->r_prod = prod;
1314 r->r_cnt = cnt;
1315 return;
1316
1317oactive:
1318 ifp->if_flags |= IFF_OACTIVE;
1319 r->r_prod = firstprod;
1320 r->r_cnt = firstcnt;
984263bc
MD
1321 return;
1322}
1323
1324/*
1325 * Handle simple commands sent to the typhoon
1326 */
1327static int
1328txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1329 struct txp_softc *sc;
1330 u_int16_t id, in1, *out1;
1331 u_int32_t in2, in3, *out2, *out3;
1332 int wait;
1333{
1334 struct txp_rsp_desc *rsp = NULL;
1335
1336 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1337 return (-1);
1338
1339 if (!wait)
1340 return (0);
1341
1342 if (out1 != NULL)
1343 *out1 = rsp->rsp_par1;
1344 if (out2 != NULL)
1345 *out2 = rsp->rsp_par2;
1346 if (out3 != NULL)
1347 *out3 = rsp->rsp_par3;
1348 free(rsp, M_DEVBUF);
1349 return (0);
1350}
1351
1352static int
1353txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1354 struct txp_softc *sc;
1355 u_int16_t id, in1;
1356 u_int32_t in2, in3;
1357 struct txp_ext_desc *in_extp;
1358 u_int8_t in_extn;
1359 struct txp_rsp_desc **rspp;
1360 int wait;
1361{
1362 struct txp_hostvar *hv = sc->sc_hostvar;
1363 struct txp_cmd_desc *cmd;
1364 struct txp_ext_desc *ext;
1365 u_int32_t idx, i;
1366 u_int16_t seq;
1367
1368 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
fcb8c909 1369 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
984263bc
MD
1370 return (-1);
1371 }
1372
1373 idx = sc->sc_cmdring.lastwrite;
1374 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1375 bzero(cmd, sizeof(*cmd));
1376
1377 cmd->cmd_numdesc = in_extn;
1378 cmd->cmd_seq = seq = sc->sc_seq++;
1379 cmd->cmd_id = id;
1380 cmd->cmd_par1 = in1;
1381 cmd->cmd_par2 = in2;
1382 cmd->cmd_par3 = in3;
1383 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1384 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1385
1386 idx += sizeof(struct txp_cmd_desc);
1387 if (idx == sc->sc_cmdring.size)
1388 idx = 0;
1389
1390 for (i = 0; i < in_extn; i++) {
1391 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1392 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1393 in_extp++;
1394 idx += sizeof(struct txp_cmd_desc);
1395 if (idx == sc->sc_cmdring.size)
1396 idx = 0;
1397 }
1398
1399 sc->sc_cmdring.lastwrite = idx;
1400
1401 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1402
1403 if (!wait)
1404 return (0);
1405
1406 for (i = 0; i < 10000; i++) {
1407 idx = hv->hv_resp_read_idx;
1408 if (idx != hv->hv_resp_write_idx) {
1409 *rspp = NULL;
1410 if (txp_response(sc, idx, id, seq, rspp))
1411 return (-1);
1412 if (*rspp != NULL)
1413 break;
1414 }
1415 DELAY(50);
1416 }
1417 if (i == 1000 || (*rspp) == NULL) {
fcb8c909 1418 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
984263bc
MD
1419 return (-1);
1420 }
1421
1422 return (0);
1423}
1424
1425static int
1426txp_response(sc, ridx, id, seq, rspp)
1427 struct txp_softc *sc;
1428 u_int32_t ridx;
1429 u_int16_t id;
1430 u_int16_t seq;
1431 struct txp_rsp_desc **rspp;
1432{
1433 struct txp_hostvar *hv = sc->sc_hostvar;
1434 struct txp_rsp_desc *rsp;
1435
1436 while (ridx != hv->hv_resp_write_idx) {
1437 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1438
1439 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1440 *rspp = (struct txp_rsp_desc *)malloc(
1441 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
c5541aee 1442 M_DEVBUF, M_INTWAIT);
984263bc
MD
1443 if ((*rspp) == NULL)
1444 return (-1);
1445 txp_rsp_fixup(sc, rsp, *rspp);
1446 return (0);
1447 }
1448
1449 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
fcb8c909 1450 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
984263bc
MD
1451 txp_rsp_fixup(sc, rsp, NULL);
1452 ridx = hv->hv_resp_read_idx;
1453 continue;
1454 }
1455
1456 switch (rsp->rsp_id) {
1457 case TXP_CMD_CYCLE_STATISTICS:
1458 case TXP_CMD_MEDIA_STATUS_READ:
1459 break;
1460 case TXP_CMD_HELLO_RESPONSE:
fcb8c909 1461 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
984263bc
MD
1462 break;
1463 default:
fcb8c909 1464 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
984263bc
MD
1465 rsp->rsp_id);
1466 }
1467
1468 txp_rsp_fixup(sc, rsp, NULL);
1469 ridx = hv->hv_resp_read_idx;
1470 hv->hv_resp_read_idx = ridx;
1471 }
1472
1473 return (0);
1474}
1475
1476static void
1477txp_rsp_fixup(sc, rsp, dst)
1478 struct txp_softc *sc;
1479 struct txp_rsp_desc *rsp, *dst;
1480{
1481 struct txp_rsp_desc *src = rsp;
1482 struct txp_hostvar *hv = sc->sc_hostvar;
1483 u_int32_t i, ridx;
1484
1485 ridx = hv->hv_resp_read_idx;
1486
1487 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1488 if (dst != NULL)
1489 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1490 ridx += sizeof(struct txp_rsp_desc);
1491 if (ridx == sc->sc_rspring.size) {
1492 src = sc->sc_rspring.base;
1493 ridx = 0;
1494 } else
1495 src++;
1496 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1497 }
1498
1499 hv->hv_resp_read_idx = ridx;
1500}
1501
1502static int
1503txp_cmd_desc_numfree(sc)
1504 struct txp_softc *sc;
1505{
1506 struct txp_hostvar *hv = sc->sc_hostvar;
1507 struct txp_boot_record *br = sc->sc_boot;
1508 u_int32_t widx, ridx, nfree;
1509
1510 widx = sc->sc_cmdring.lastwrite;
1511 ridx = hv->hv_cmd_read_idx;
1512
1513 if (widx == ridx) {
1514 /* Ring is completely free */
1515 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1516 } else {
1517 if (widx > ridx)
1518 nfree = br->br_cmd_siz -
1519 (widx - ridx + sizeof(struct txp_cmd_desc));
1520 else
1521 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1522 }
1523
1524 return (nfree / sizeof(struct txp_cmd_desc));
1525}
1526
1527static void
1528txp_stop(sc)
1529 struct txp_softc *sc;
1530{
1531 struct ifnet *ifp;
1532
1533 ifp = &sc->sc_arpcom.ac_if;
1534
1535 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1536
9e6fd080 1537 callout_stop(&sc->txp_stat_timer);
984263bc
MD
1538
1539 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1540 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1541
1542 txp_rxring_empty(sc);
1543
1544 return;
1545}
1546
1547static void
1548txp_watchdog(ifp)
1549 struct ifnet *ifp;
1550{
1551 return;
1552}
1553
1554static int
1555txp_ifmedia_upd(ifp)
1556 struct ifnet *ifp;
1557{
1558 struct txp_softc *sc = ifp->if_softc;
1559 struct ifmedia *ifm = &sc->sc_ifmedia;
1560 u_int16_t new_xcvr;
1561
1562 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1563 return (EINVAL);
1564
1565 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1566 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1567 new_xcvr = TXP_XCVR_10_FDX;
1568 else
1569 new_xcvr = TXP_XCVR_10_HDX;
1570 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1571 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1572 new_xcvr = TXP_XCVR_100_FDX;
1573 else
1574 new_xcvr = TXP_XCVR_100_HDX;
1575 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1576 new_xcvr = TXP_XCVR_AUTO;
1577 } else
1578 return (EINVAL);
1579
1580 /* nothing to do */
1581 if (sc->sc_xcvr == new_xcvr)
1582 return (0);
1583
1584 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1585 NULL, NULL, NULL, 0);
1586 sc->sc_xcvr = new_xcvr;
1587
1588 return (0);
1589}
1590
1591static void
1592txp_ifmedia_sts(ifp, ifmr)
1593 struct ifnet *ifp;
1594 struct ifmediareq *ifmr;
1595{
1596 struct txp_softc *sc = ifp->if_softc;
1597 struct ifmedia *ifm = &sc->sc_ifmedia;
1598 u_int16_t bmsr, bmcr, anlpar;
1599
1600 ifmr->ifm_status = IFM_AVALID;
1601 ifmr->ifm_active = IFM_ETHER;
1602
1603 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1604 &bmsr, NULL, NULL, 1))
1605 goto bail;
1606 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1607 &bmsr, NULL, NULL, 1))
1608 goto bail;
1609
1610 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1611 &bmcr, NULL, NULL, 1))
1612 goto bail;
1613
1614 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1615 &anlpar, NULL, NULL, 1))
1616 goto bail;
1617
1618 if (bmsr & BMSR_LINK)
1619 ifmr->ifm_status |= IFM_ACTIVE;
1620
1621 if (bmcr & BMCR_ISO) {
1622 ifmr->ifm_active |= IFM_NONE;
1623 ifmr->ifm_status = 0;
1624 return;
1625 }
1626
1627 if (bmcr & BMCR_LOOP)
1628 ifmr->ifm_active |= IFM_LOOP;
1629
1630 if (bmcr & BMCR_AUTOEN) {
1631 if ((bmsr & BMSR_ACOMP) == 0) {
1632 ifmr->ifm_active |= IFM_NONE;
1633 return;
1634 }
1635
1636 if (anlpar & ANLPAR_T4)
1637 ifmr->ifm_active |= IFM_100_T4;
1638 else if (anlpar & ANLPAR_TX_FD)
1639 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1640 else if (anlpar & ANLPAR_TX)
1641 ifmr->ifm_active |= IFM_100_TX;
1642 else if (anlpar & ANLPAR_10_FD)
1643 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1644 else if (anlpar & ANLPAR_10)
1645 ifmr->ifm_active |= IFM_10_T;
1646 else
1647 ifmr->ifm_active |= IFM_NONE;
1648 } else
1649 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1650 return;
1651
1652bail:
1653 ifmr->ifm_active |= IFM_NONE;
1654 ifmr->ifm_status &= ~IFM_AVALID;
1655}
1656
1657#ifdef TXP_DEBUG
1658static void
1659txp_show_descriptor(d)
1660 void *d;
1661{
1662 struct txp_cmd_desc *cmd = d;
1663 struct txp_rsp_desc *rsp = d;
1664 struct txp_tx_desc *txd = d;
1665 struct txp_frag_desc *frgd = d;
1666
1667 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1668 case CMD_FLAGS_TYPE_CMD:
1669 /* command descriptor */
1670 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1671 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1672 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1673 break;
1674 case CMD_FLAGS_TYPE_RESP:
1675 /* response descriptor */
1676 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1677 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1678 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1679 break;
1680 case CMD_FLAGS_TYPE_DATA:
1681 /* data header (assuming tx for now) */
1682 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1683 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1684 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1685 break;
1686 case CMD_FLAGS_TYPE_FRAG:
1687 /* fragment descriptor */
1688 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1689 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1690 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1691 break;
1692 default:
1693 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1694 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1695 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1696 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1697 break;
1698 }
1699}
1700#endif
1701
1702static void
1703txp_set_filter(sc)
1704 struct txp_softc *sc;
1705{
1706 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1769a3b9 1707 uint16_t filter;
984263bc 1708 struct ifmultiaddr *ifma;
984263bc
MD
1709
1710 if (ifp->if_flags & IFF_PROMISC) {
1711 filter = TXP_RXFILT_PROMISC;
1712 goto setit;
1713 }
1714
1715 filter = TXP_RXFILT_DIRECT;
1716
1717 if (ifp->if_flags & IFF_BROADCAST)
1718 filter |= TXP_RXFILT_BROADCAST;
1719
1769a3b9 1720 if (ifp->if_flags & IFF_ALLMULTI) {
984263bc 1721 filter |= TXP_RXFILT_ALLMULTI;
1769a3b9
JS
1722 } else {
1723 uint32_t hashbit, hash[2];
1724 int mcnt = 0;
1725
984263bc
MD
1726 hash[0] = hash[1] = 0;
1727
03df8a20 1728 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1729 if (ifma->ifma_addr->sa_family != AF_LINK)
1730 continue;
1731
984263bc 1732 mcnt++;
1769a3b9
JS
1733 hashbit = (uint16_t)(ether_crc32_be(
1734 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1735 ETHER_ADDR_LEN) & (64 - 1));
984263bc
MD
1736 hash[hashbit / 32] |= (1 << hashbit % 32);
1737 }
1738
1739 if (mcnt > 0) {
1740 filter |= TXP_RXFILT_HASHMULTI;
1741 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1742 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1743 }
1744 }
1745
1746setit:
984263bc
MD
1747 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1748 NULL, NULL, NULL, 1);
984263bc
MD
1749}
1750
1751static void
1752txp_capabilities(sc)
1753 struct txp_softc *sc;
1754{
1755 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1756 struct txp_rsp_desc *rsp = NULL;
1757 struct txp_ext_desc *ext;
1758
1759 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1760 goto out;
1761
1762 if (rsp->rsp_numdesc != 1)
1763 goto out;
1764 ext = (struct txp_ext_desc *)(rsp + 1);
1765
1766 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1767 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1768 ifp->if_capabilities = 0;
1769
1770 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1771 sc->sc_tx_capability |= OFFLOAD_VLAN;
1772 sc->sc_rx_capability |= OFFLOAD_VLAN;
1773 }
1774
1775#if 0
1776 /* not ready yet */
1777 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1778 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1779 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1780 ifp->if_capabilities |= IFCAP_IPSEC;
1781 }
1782#endif
1783
1784 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1785 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1786 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1787 ifp->if_capabilities |= IFCAP_HWCSUM;
1788 ifp->if_hwassist |= CSUM_IP;
1789 }
1790
1791 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1792#if 0
1793 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1794#endif
1795 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1796 ifp->if_capabilities |= IFCAP_HWCSUM;
1797 }
1798
1799 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1800#if 0
1801 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1802#endif
1803 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1804 ifp->if_capabilities |= IFCAP_HWCSUM;
1805 }
1806 ifp->if_capenable = ifp->if_capabilities;
1807
1808 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1809 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1810 goto out;
1811
1812out:
1813 if (rsp != NULL)
1814 free(rsp, M_DEVBUF);
1815
1816 return;
1817}