lapic timer: Add necessary bits for lapic timer interrupt delivery
[dragonfly.git] / sys / platform / pc32 / apic / mpapic.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
0ca0cd25 26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
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27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
72740893 31#include <machine/globaldata.h>
984263bc 32#include <machine/smp.h>
d595a6c0 33#include <machine/md_var.h>
a9295349 34#include <machine_base/apic/mpapic.h>
984263bc 35#include <machine/segments.h>
96728c05 36#include <sys/thread2.h>
984263bc 37
a9295349 38#include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
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39
40/* EISA Edge/Level trigger control registers */
41#define ELCR0 0x4d0 /* eisa irq 0-7 */
42#define ELCR1 0x4d1 /* eisa irq 8-15 */
43
b52c8db0 44static void lapic_timer_calibrate(void);
086575e9 45static void lapic_timer_set_divisor(int);
78ea5a2a
SZ
46void lapic_timer_process(void);
47void lapic_timer_process_frame(struct intrframe *);
b52c8db0 48
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49/*
50 * pointers to pmapped apic hardware.
51 */
52
984263bc 53volatile ioapic_t **ioapic;
984263bc 54
086575e9
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55static sysclock_t lapic_timer_freq;
56static int lapic_timer_divisor_idx = -1;
57static const uint32_t lapic_timer_divisors[] = {
58 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
59 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
60};
61#define APIC_TIMER_NDIVISORS \
62 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
63
64
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65/*
66 * Enable APIC, configure interrupts.
67 */
68void
b52c8db0 69apic_initialize(boolean_t bsp)
984263bc 70{
78ea5a2a 71 uint32_t timer;
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72 u_int temp;
73
9d6bf2df 74 /*
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75 * setup LVT1 as ExtINT on the BSP. This is theoretically an
76 * aggregate interrupt input from the 8259. The INTA cycle
77 * will be routed to the external controller (the 8259) which
78 * is expected to supply the vector.
79 *
80 * Must be setup edge triggered, active high.
81 *
82 * Disable LVT1 on the APs. It doesn't matter what delivery
83 * mode we use because we leave it masked.
9d6bf2df 84 */
984263bc 85 temp = lapic.lvt_lint0;
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MD
86 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
87 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
72740893 88 if (mycpu->gd_cpuid == 0)
9d6bf2df 89 temp |= APIC_LVT_DM_EXTINT;
984263bc 90 else
97359a5b 91 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
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92 lapic.lvt_lint0 = temp;
93
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94 /*
95 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
96 */
984263bc 97 temp = lapic.lvt_lint1;
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98 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
99 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
100 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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101 lapic.lvt_lint1 = temp;
102
d9eea1a5 103 /*
c6a1aabe 104 * Mask the apic error interrupt, apic performance counter
78ea5a2a 105 * interrupt.
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106 */
107 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
108 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
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109
110 /* Set apic timer vector and mask the apic timer interrupt. */
111 timer = lapic.lvt_timer;
112 timer &= ~APIC_LVTT_VECTOR;
113 timer |= XTIMER_OFFSET;
114 timer |= APIC_LVTT_MASKED;
115 lapic.lvt_timer = timer;
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116
117 /*
d9eea1a5
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118 * Set the Task Priority Register as needed. At the moment allow
119 * interrupts on all cpus (the APs will remain CLId until they are
120 * ready to deal). We could disable all but IPIs by setting
121 * temp |= TPR_IPI_ONLY for cpu != 0.
122 */
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123 temp = lapic.tpr;
124 temp &= ~APIC_TPR_PRIO; /* clear priority field */
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125#ifndef APIC_IO
126 /*
127 * If we are NOT running the IO APICs, the LAPIC will only be used
128 * for IPIs. Set the TPR to prevent any unintentional interrupts.
129 */
130 temp |= TPR_IPI_ONLY;
131#endif
8a8d5d85 132
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133 lapic.tpr = temp;
134
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135 /*
136 * enable the local APIC
137 */
984263bc 138 temp = lapic.svr;
9d6bf2df 139 temp |= APIC_SVR_ENABLE; /* enable the APIC */
97359a5b 140 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 141
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142 /*
143 * Set the spurious interrupt vector. The low 4 bits of the vector
144 * must be 1111.
145 */
146 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 147 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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148 temp &= ~APIC_SVR_VECTOR;
149 temp |= XSPURIOUSINT_OFFSET;
984263bc 150
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151 lapic.svr = temp;
152
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153 /*
154 * Pump out a few EOIs to clean out interrupts that got through
155 * before we were able to set the TPR.
156 */
157 lapic.eoi = 0;
158 lapic.eoi = 0;
159 lapic.eoi = 0;
160
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SZ
161 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
162 /*
163 * Detect the presence of C1E capability mostly on latest
164 * dual-cores (or future) k8 family. This feature renders
165 * the local APIC timer dead, so we disable it by reading
166 * the Interrupt Pending Message register and clearing both
167 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
168 *
169 * Reference:
170 * "BIOS and Kernel Developer's Guide for AMD NPT
171 * Family 0Fh Processors"
172 * #32559 revision 3.00
173 */
174 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
175 (cpu_id & 0x0fff0000) >= 0x00040000) {
176 uint64_t msr;
177
178 msr = rdmsr(0xc0010055);
179 if (msr & 0x18000000)
180 wrmsr(0xc0010055, msr & ~0x18000000ULL);
181 }
182 }
183
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184 if (bsp)
185 lapic_timer_calibrate();
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186 else
187 lapic_timer_set_divisor(lapic_timer_divisor_idx);
b52c8db0 188
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189 if (bootverbose)
190 apic_dump("apic_initialize()");
191}
192
193
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194static void
195lapic_timer_set_divisor(int divisor_idx)
196{
197 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
198 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
199}
200
201static void
202lapic_timer_oneshot(u_int count)
203{
204 uint32_t value;
205
206 value = lapic.lvt_timer;
207 value &= ~APIC_LVTT_PERIODIC;
208 lapic.lvt_timer = value;
209 lapic.icr_timer = count;
210}
211
212static void
213lapic_timer_calibrate(void)
214{
47bdf646 215 sysclock_t value;
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216
217 /* Try to calibrate the local APIC timer. */
218 for (lapic_timer_divisor_idx = 0;
219 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
220 lapic_timer_divisor_idx++) {
221 lapic_timer_set_divisor(lapic_timer_divisor_idx);
222 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
223 DELAY(2000000);
224 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
225 if (value != APIC_TIMER_MAX_COUNT)
226 break;
227 }
228 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
229 panic("lapic: no proper timer divisor?!\n");
47bdf646 230 lapic_timer_freq = value / 2;
b52c8db0 231
47bdf646
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232 kprintf("lapic: divisor index %d, frequency %u Hz\n",
233 lapic_timer_divisor_idx, lapic_timer_freq);
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234}
235
78ea5a2a
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236void
237lapic_timer_process(void)
238{
239}
240
241void
242lapic_timer_process_frame(struct intrframe *frame)
243{
244}
245
b52c8db0 246
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247/*
248 * dump contents of local APIC registers
249 */
250void
251apic_dump(char* str)
252{
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253 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
254 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
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255 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
256}
257
258
259#if defined(APIC_IO)
260
261/*
262 * IO APIC code,
263 */
264
265#define IOAPIC_ISA_INTS 16
266#define REDIRCNT_IOAPIC(A) \
267 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
268
3ae0cd58
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269static int trigger (int apic, int pin, u_int32_t * flags);
270static void polarity (int apic, int pin, u_int32_t * flags, int level);
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271
272#define DEFAULT_FLAGS \
273 ((u_int32_t) \
274 (IOART_INTMSET | \
275 IOART_DESTPHY | \
276 IOART_DELLOPRI))
277
278#define DEFAULT_ISA_FLAGS \
279 ((u_int32_t) \
280 (IOART_INTMSET | \
281 IOART_TRGREDG | \
282 IOART_INTAHI | \
283 IOART_DESTPHY | \
284 IOART_DELLOPRI))
285
286void
287io_apic_set_id(int apic, int id)
288{
289 u_int32_t ux;
290
291 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
292 if (((ux & APIC_ID_MASK) >> 24) != id) {
26be20a0 293 kprintf("Changing APIC ID for IO APIC #%d"
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294 " from %d to %d on chip\n",
295 apic, ((ux & APIC_ID_MASK) >> 24), id);
296 ux &= ~APIC_ID_MASK; /* clear the ID field */
297 ux |= (id << 24);
298 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
299 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
300 if (((ux & APIC_ID_MASK) >> 24) != id)
301 panic("can't control IO APIC #%d ID, reg: 0x%08x",
302 apic, ux);
303 }
304}
305
306
307int
308io_apic_get_id(int apic)
309{
310 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
311}
312
313
314
315/*
316 * Setup the IO APIC.
317 */
318
319extern int apic_pin_trigger; /* 'opaque' */
320
321void
322io_apic_setup_intpin(int apic, int pin)
323{
324 int bus, bustype, irq;
325 u_char select; /* the select register is 8 bits */
326 u_int32_t flags; /* the window register is 32 bits */
327 u_int32_t target; /* the window register is 32 bits */
328 u_int32_t vector; /* the window register is 32 bits */
329 int level;
984263bc 330
984263bc 331 select = pin * 2 + IOAPIC_REDTBL0; /* register */
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332
333 /*
334 * Always clear an IO APIC pin before [re]programming it. This is
335 * particularly important if the pin is set up for a level interrupt
336 * as the IOART_REM_IRR bit might be set. When we reprogram the
337 * vector any EOI from pending ints on this pin could be lost and
338 * IRR might never get reset.
984263bc 339 *
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340 * To fix this problem, clear the vector and make sure it is
341 * programmed as an edge interrupt. This should theoretically
342 * clear IRR so we can later, safely program it as a level
343 * interrupt.
984263bc 344 */
8a8d5d85 345 imen_lock();
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MD
346
347 flags = io_apic_read(apic, select) & IOART_RESV;
348 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
349 flags |= IOART_DESTPHY | IOART_DELFIXED;
350
351 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
352 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
353
354 vector = 0;
355
356 io_apic_write(apic, select, flags | vector);
357 io_apic_write(apic, select + 1, target);
358
8a8d5d85 359 imen_unlock();
65de6d19
MD
360
361 /*
362 * We only deal with vectored interrupts here. ? documentation is
363 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
364 * vs ExTINT, etc.
365 *
366 * This test also catches unconfigured pins.
367 */
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MD
368 if (apic_int_type(apic, pin) != 0)
369 return;
65de6d19
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370
371 /*
372 * Leave the pin unprogrammed if it does not correspond to
373 * an IRQ.
374 */
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MD
375 irq = apic_irq(apic, pin);
376 if (irq < 0)
377 return;
378
379 /* determine the bus type for this pin */
380 bus = apic_src_bus_id(apic, pin);
65de6d19 381 if (bus < 0)
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MD
382 return;
383 bustype = apic_bus_type(bus);
384
385 if ((bustype == ISA) &&
386 (pin < IOAPIC_ISA_INTS) &&
387 (irq == pin) &&
388 (apic_polarity(apic, pin) == 0x1) &&
389 (apic_trigger(apic, pin) == 0x3)) {
390 /*
391 * A broken BIOS might describe some ISA
392 * interrupts as active-high level-triggered.
393 * Use default ISA flags for those interrupts.
394 */
395 flags = DEFAULT_ISA_FLAGS;
396 } else {
397 /*
398 * Program polarity and trigger mode according to
399 * interrupt entry.
400 */
401 flags = DEFAULT_FLAGS;
402 level = trigger(apic, pin, &flags);
403 if (level == 1)
404 apic_pin_trigger |= (1 << irq);
405 polarity(apic, pin, &flags, level);
406 }
407
5737d650 408 if (bootverbose) {
26be20a0 409 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
984263bc 410 apic, pin, irq);
5737d650 411 }
65de6d19
MD
412
413 /*
414 * Program the appropriate registers. This routing may be
415 * overridden when an interrupt handler for a device is
9d522d14 416 * actually added (see register_int(), which calls through
65de6d19
MD
417 * the MACHINTR ABI to set up an interrupt handler/vector).
418 *
419 * The order in which we must program the two registers for
420 * safety is unclear! XXX
421 */
8a8d5d85 422 imen_lock();
65de6d19
MD
423
424 vector = IDT_OFFSET + irq; /* IDT vec */
425 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
426 target |= IOART_HI_DEST_BROADCAST;
427 flags |= io_apic_read(apic, select) & IOART_RESV;
984263bc
MD
428 io_apic_write(apic, select, flags | vector);
429 io_apic_write(apic, select + 1, target);
65de6d19 430
8a8d5d85 431 imen_unlock();
984263bc
MD
432}
433
434int
435io_apic_setup(int apic)
436{
437 int maxpin;
438 int pin;
439
440 if (apic == 0)
441 apic_pin_trigger = 0; /* default to edge-triggered */
442
443 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
26be20a0 444 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
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445
446 for (pin = 0; pin < maxpin; ++pin) {
447 io_apic_setup_intpin(apic, pin);
448 }
1f1464ad
MD
449 while (pin < 32) {
450 if (apic_int_type(apic, pin) >= 0) {
26be20a0 451 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
1f1464ad
MD
452 " cannot program!\n", apic, pin);
453 }
454 ++pin;
455 }
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456
457 /* return GOOD status */
458 return 0;
459}
460#undef DEFAULT_ISA_FLAGS
461#undef DEFAULT_FLAGS
462
463
464#define DEFAULT_EXTINT_FLAGS \
465 ((u_int32_t) \
466 (IOART_INTMSET | \
467 IOART_TRGREDG | \
468 IOART_INTAHI | \
469 IOART_DESTPHY | \
470 IOART_DELLOPRI))
471
472/*
473 * Setup the source of External INTerrupts.
474 */
475int
476ext_int_setup(int apic, int intr)
477{
478 u_char select; /* the select register is 8 bits */
479 u_int32_t flags; /* the window register is 32 bits */
480 u_int32_t target; /* the window register is 32 bits */
481 u_int32_t vector; /* the window register is 32 bits */
482
483 if (apic_int_type(apic, intr) != 3)
484 return -1;
485
35408d22 486 target = IOART_HI_DEST_BROADCAST;
984263bc 487 select = IOAPIC_REDTBL0 + (2 * intr);
97359a5b 488 vector = IDT_OFFSET + intr;
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MD
489 flags = DEFAULT_EXTINT_FLAGS;
490
491 io_apic_write(apic, select, flags | vector);
492 io_apic_write(apic, select + 1, target);
493
494 return 0;
495}
496#undef DEFAULT_EXTINT_FLAGS
497
498
499/*
500 * Set the trigger level for an IO APIC pin.
501 */
502static int
503trigger(int apic, int pin, u_int32_t * flags)
504{
505 int id;
506 int eirq;
507 int level;
508 static int intcontrol = -1;
509
510 switch (apic_trigger(apic, pin)) {
511
512 case 0x00:
513 break;
514
515 case 0x01:
516 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
517 return 0;
518
519 case 0x03:
520 *flags |= IOART_TRGRLVL;
521 return 1;
522
523 case -1:
524 default:
525 goto bad;
526 }
527
528 if ((id = apic_src_bus_id(apic, pin)) == -1)
529 goto bad;
530
531 switch (apic_bus_type(id)) {
532 case ISA:
533 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
534 return 0;
535
536 case EISA:
537 eirq = apic_src_bus_irq(apic, pin);
538
539 if (eirq < 0 || eirq > 15) {
26be20a0 540 kprintf("EISA IRQ %d?!?!\n", eirq);
984263bc
MD
541 goto bad;
542 }
543
544 if (intcontrol == -1) {
545 intcontrol = inb(ELCR1) << 8;
546 intcontrol |= inb(ELCR0);
26be20a0 547 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
984263bc
MD
548 }
549
550 /* Use ELCR settings to determine level or edge mode */
551 level = (intcontrol >> eirq) & 1;
552
553 /*
554 * Note that on older Neptune chipset based systems, any
555 * pci interrupts often show up here and in the ELCR as well
556 * as level sensitive interrupts attributed to the EISA bus.
557 */
558
559 if (level)
560 *flags |= IOART_TRGRLVL;
561 else
562 *flags &= ~IOART_TRGRLVL;
563
564 return level;
565
566 case PCI:
567 *flags |= IOART_TRGRLVL;
568 return 1;
569
570 case -1:
571 default:
572 goto bad;
573 }
574
575bad:
576 panic("bad APIC IO INT flags");
577}
578
579
580/*
581 * Set the polarity value for an IO APIC pin.
582 */
583static void
584polarity(int apic, int pin, u_int32_t * flags, int level)
585{
586 int id;
587
588 switch (apic_polarity(apic, pin)) {
589
590 case 0x00:
591 break;
592
593 case 0x01:
594 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
595 return;
596
597 case 0x03:
598 *flags |= IOART_INTALO;
599 return;
600
601 case -1:
602 default:
603 goto bad;
604 }
605
606 if ((id = apic_src_bus_id(apic, pin)) == -1)
607 goto bad;
608
609 switch (apic_bus_type(id)) {
610 case ISA:
611 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
612 return;
613
614 case EISA:
615 /* polarity converter always gives active high */
616 *flags &= ~IOART_INTALO;
617 return;
618
619 case PCI:
620 *flags |= IOART_INTALO;
621 return;
622
623 case -1:
624 default:
625 goto bad;
626 }
627
628bad:
629 panic("bad APIC IO INT flags");
630}
631
632
633/*
634 * Print contents of apic_imen.
635 */
636extern u_int apic_imen; /* keep apic_imen 'opaque' */
637void
638imen_dump(void)
639{
640 int x;
641
26be20a0 642 kprintf("SMP: enabled INTs: ");
984263bc
MD
643 for (x = 0; x < 24; ++x)
644 if ((apic_imen & (1 << x)) == 0)
26be20a0
SW
645 kprintf("%d, ", x);
646 kprintf("apic_imen: 0x%08x\n", apic_imen);
984263bc
MD
647}
648
649
650/*
651 * Inter Processor Interrupt functions.
652 */
653
97359a5b 654#endif /* APIC_IO */
984263bc
MD
655
656/*
657 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
658 *
659 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
660 * vector is any valid SYSTEM INT vector
661 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
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662 *
663 * A backlog of requests can create a deadlock between cpus. To avoid this
664 * we have to be able to accept IPIs at the same time we are trying to send
665 * them. The critical section prevents us from attempting to send additional
666 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
667 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
668 * to occur but fortunately it does not happen too often.
984263bc 669 */
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670int
671apic_ipi(int dest_type, int vector, int delivery_mode)
672{
673 u_long icr_lo;
674
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675 crit_enter();
676 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
677 unsigned int eflags = read_eflags();
678 cpu_enable_intr();
679 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
680 lwkt_process_ipiq();
681 }
682 write_eflags(eflags);
984263bc 683 }
984263bc 684
9d6bf2df 685 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 686 delivery_mode | vector;
984263bc 687 lapic.icr_lo = icr_lo;
96728c05 688 crit_exit();
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689 return 0;
690}
691
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692void
693single_apic_ipi(int cpu, int vector, int delivery_mode)
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694{
695 u_long icr_lo;
696 u_long icr_hi;
984263bc 697
41a01a4d 698 crit_enter();
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699 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
700 unsigned int eflags = read_eflags();
701 cpu_enable_intr();
702 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
703 lwkt_process_ipiq();
704 }
705 write_eflags(eflags);
984263bc 706 }
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707 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
708 icr_hi |= (CPU_TO_ID(cpu) << 24);
709 lapic.icr_hi = icr_hi;
710
b2f93ae9 711 /* build ICR_LOW */
9d6bf2df 712 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
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713 | APIC_DEST_DESTFLD | delivery_mode | vector;
714
715 /* write APIC ICR */
716 lapic.icr_lo = icr_lo;
41a01a4d 717 crit_exit();
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718}
719
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720#if 0
721
722/*
723 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
724 *
725 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
726 * to the target, and the scheduler does not 'poll' for IPI messages.
727 */
728int
729single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
730{
731 u_long icr_lo;
732 u_long icr_hi;
733
734 crit_enter();
735 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
736 crit_exit();
737 return(0);
738 }
739 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
740 icr_hi |= (CPU_TO_ID(cpu) << 24);
741 lapic.icr_hi = icr_hi;
742
743 /* build IRC_LOW */
744 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
745 | APIC_DEST_DESTFLD | delivery_mode | vector;
746
747 /* write APIC ICR */
748 lapic.icr_lo = icr_lo;
749 crit_exit();
750 return(1);
751}
752
753#endif
754
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755/*
756 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
757 *
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758 * target is a bitmask of destination cpus. Vector is any
759 * valid system INT vector. Delivery mode may be either
760 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 761 */
41a01a4d 762void
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763selected_apic_ipi(u_int target, int vector, int delivery_mode)
764{
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765 crit_enter();
766 while (target) {
767 int n = bsfl(target);
768 target &= ~(1 << n);
41a01a4d 769 single_apic_ipi(n, vector, delivery_mode);
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770 }
771 crit_exit();
984263bc 772}
984263bc 773
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774/*
775 * Timer code, in development...
776 * - suggested by rgrimes@gndrsh.aac.dev.com
777 */
778
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779/*
780 * Load a 'downcount time' in uSeconds.
781 */
782void
2942ed63 783set_apic_timer(int us)
984263bc 784{
2942ed63 785 u_int count;
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786
787 /*
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788 * When we reach here, lapic timer's frequency
789 * must have been calculated as well as the
790 * divisor (lapic.dcr_timer is setup during the
791 * divisor calculation).
984263bc 792 */
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793 KKASSERT(lapic_timer_freq != 0 &&
794 lapic_timer_divisor_idx >= 0);
795
796 count = ((us * (int64_t)lapic_timer_freq) + 999999) / 1000000;
797 lapic_timer_oneshot(count);
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798}
799
800
801/*
802 * Read remaining time in timer.
803 */
804int
805read_apic_timer(void)
806{
807#if 0
808 /** XXX FIXME: we need to return the actual remaining time,
809 * for now we just return the remaining count.
810 */
811#else
812 return lapic.ccr_timer;
813#endif
814}
815
816
817/*
818 * Spin-style delay, set delay time in uS, spin till it drains.
819 */
820void
821u_sleep(int count)
822{
823 set_apic_timer(count);
824 while (read_apic_timer())
825 /* spin */ ;
826}