lapic timer: Add necessary bits for lapic timer interrupt delivery
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
984263bc
MD
27 */
28
29#include "opt_cpu.h"
984263bc 30
984263bc
MD
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
984263bc
MD
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
984263bc
MD
39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
984263bc
MD
45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
984263bc
MD
51
52#include <machine/smp.h>
a9295349 53#include <machine_base/apic/apicreg.h>
984263bc
MD
54#include <machine/atomic.h>
55#include <machine/cpufunc.h>
a9295349 56#include <machine_base/apic/mpapic.h>
984263bc
MD
57#include <machine/psl.h>
58#include <machine/segments.h>
984263bc
MD
59#include <machine/tss.h>
60#include <machine/specialreg.h>
61#include <machine/globaldata.h>
62
984263bc 63#include <machine/md_var.h> /* setidt() */
a9295349
MD
64#include <machine_base/icu/icu.h> /* IPIs */
65#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 66
1439c090
MD
67#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
68
984263bc
MD
69#define WARMBOOT_TARGET 0
70#define WARMBOOT_OFF (KERNBASE + 0x0467)
71#define WARMBOOT_SEG (KERNBASE + 0x0469)
72
984263bc
MD
73#define BIOS_BASE (0xf0000)
74#define BIOS_SIZE (0x10000)
984263bc
MD
75#define BIOS_COUNT (BIOS_SIZE/4)
76
77#define CMOS_REG (0x70)
78#define CMOS_DATA (0x71)
79#define BIOS_RESET (0x0f)
80#define BIOS_WARM (0x0a)
81
82#define PROCENTRY_FLAG_EN 0x01
83#define PROCENTRY_FLAG_BP 0x02
84#define IOAPICENTRY_FLAG_EN 0x01
85
86
87/* MP Floating Pointer Structure */
88typedef struct MPFPS {
89 char signature[4];
90 void *pap;
91 u_char length;
92 u_char spec_rev;
93 u_char checksum;
94 u_char mpfb1;
95 u_char mpfb2;
96 u_char mpfb3;
97 u_char mpfb4;
98 u_char mpfb5;
99} *mpfps_t;
100
101/* MP Configuration Table Header */
102typedef struct MPCTH {
103 char signature[4];
104 u_short base_table_length;
105 u_char spec_rev;
106 u_char checksum;
107 u_char oem_id[8];
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
111 u_short entry_count;
112 void *apic_address;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
115 u_char reserved;
116} *mpcth_t;
117
118
119typedef struct PROCENTRY {
120 u_char type;
121 u_char apic_id;
122 u_char apic_version;
123 u_char cpu_flags;
124 u_long cpu_signature;
125 u_long feature_flags;
126 u_long reserved1;
127 u_long reserved2;
128} *proc_entry_ptr;
129
130typedef struct BUSENTRY {
131 u_char type;
132 u_char bus_id;
133 char bus_type[6];
134} *bus_entry_ptr;
135
136typedef struct IOAPICENTRY {
137 u_char type;
138 u_char apic_id;
139 u_char apic_version;
140 u_char apic_flags;
141 void *apic_address;
142} *io_apic_entry_ptr;
143
144typedef struct INTENTRY {
145 u_char type;
146 u_char int_type;
147 u_short int_flags;
148 u_char src_bus_id;
149 u_char src_bus_irq;
150 u_char dst_apic_id;
151 u_char dst_apic_int;
152} *int_entry_ptr;
153
154/* descriptions of MP basetable entries */
155typedef struct BASETABLE_ENTRY {
156 u_char type;
157 u_char length;
158 char name[16];
159} basetable_entry;
160
161/*
162 * this code MUST be enabled here and in mpboot.s.
163 * it follows the very early stages of AP boot by placing values in CMOS ram.
164 * it NORMALLY will never be needed and thus the primitive method for enabling.
165 *
984263bc 166 */
7d34994c 167#if defined(CHECK_POINTS)
984263bc
MD
168#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
169#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
170
171#define CHECK_INIT(D); \
172 CHECK_WRITE(0x34, (D)); \
173 CHECK_WRITE(0x35, (D)); \
174 CHECK_WRITE(0x36, (D)); \
175 CHECK_WRITE(0x37, (D)); \
176 CHECK_WRITE(0x38, (D)); \
177 CHECK_WRITE(0x39, (D));
178
179#define CHECK_PRINT(S); \
26be20a0 180 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
984263bc
MD
181 (S), \
182 CHECK_READ(0x34), \
183 CHECK_READ(0x35), \
184 CHECK_READ(0x36), \
185 CHECK_READ(0x37), \
186 CHECK_READ(0x38), \
187 CHECK_READ(0x39));
188
189#else /* CHECK_POINTS */
190
191#define CHECK_INIT(D)
192#define CHECK_PRINT(S)
193
194#endif /* CHECK_POINTS */
195
196/*
197 * Values to send to the POST hardware.
198 */
199#define MP_BOOTADDRESS_POST 0x10
200#define MP_PROBE_POST 0x11
201#define MPTABLE_PASS1_POST 0x12
202
203#define MP_START_POST 0x13
204#define MP_ENABLE_POST 0x14
205#define MPTABLE_PASS2_POST 0x15
206
207#define START_ALL_APS_POST 0x16
208#define INSTALL_AP_TRAMP_POST 0x17
209#define START_AP_POST 0x18
210
211#define MP_ANNOUNCE_POST 0x19
212
984263bc
MD
213static int need_hyperthreading_fixup;
214static u_int logical_cpus;
48add334 215u_int logical_cpus_mask;
984263bc
MD
216
217/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
218int current_postcode;
219
220/** XXX FIXME: what system files declare these??? */
221extern struct region_descriptor r_gdt, r_idt;
222
223int bsp_apic_ready = 0; /* flags useability of BSP apic */
984263bc
MD
224int mp_naps; /* # of Applications processors */
225int mp_nbusses; /* # of busses */
97359a5b 226#ifdef APIC_IO
984263bc 227int mp_napics; /* # of IO APICs */
97359a5b 228#endif
984263bc
MD
229int boot_cpu_id; /* designated BSP */
230vm_offset_t cpu_apic_address;
97359a5b 231#ifdef APIC_IO
984263bc 232vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
97359a5b
MD
233u_int32_t *io_apic_versions;
234#endif
984263bc
MD
235extern int nkpt;
236
237u_int32_t cpu_apic_versions[MAXCPU];
374133e3 238int64_t tsc0_offset;
0b698dca 239extern int64_t tsc_offsets[];
984263bc 240
97359a5b 241#ifdef APIC_IO
8a8d5d85 242struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 243#endif
984263bc 244
984263bc
MD
245/*
246 * APIC ID logical/physical mapping structures.
247 * We oversize these to simplify boot-time config.
248 */
249int cpu_num_to_apic_id[NAPICID];
97359a5b 250#ifdef APIC_IO
984263bc 251int io_num_to_apic_id[NAPICID];
97359a5b 252#endif
984263bc
MD
253int apic_id_to_logical[NAPICID];
254
984263bc
MD
255/* AP uses this during bootstrap. Do not staticize. */
256char *bootSTK;
257static int bootAP;
258
259/* Hotwire a 0->4MB V==P mapping */
260extern pt_entry_t *KPTphys;
261
f13b5eec
MD
262/*
263 * SMP page table page. Setup by locore to point to a page table
264 * page from which we allocate per-cpu privatespace areas io_apics,
265 * and so forth.
266 */
267
268#define IO_MAPPING_START_INDEX \
269 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
270
984263bc 271extern pt_entry_t *SMPpt;
f13b5eec 272static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
984263bc
MD
273
274struct pcb stoppcbs[MAXCPU];
275
984263bc
MD
276/*
277 * Local data and functions.
278 */
279
280static int mp_capable;
281static u_int boot_address;
282static u_int base_memory;
41a01a4d 283static int mp_finish;
984263bc 284
984263bc
MD
285static mpfps_t mpfps;
286static int search_for_sig(u_int32_t target, int count);
287static void mp_enable(u_int boot_addr);
288
984263bc 289static void mptable_hyperthread_fixup(u_int id_mask);
984263bc
MD
290static void mptable_pass1(void);
291static int mptable_pass2(void);
292static void default_mp_table(int type);
293static void fix_mp_table(void);
97359a5b 294#ifdef APIC_IO
984263bc 295static void setup_apic_irq_mapping(void);
97359a5b
MD
296static int apic_int_is_bus_type(int intr, int bus_type);
297#endif
984263bc
MD
298static int start_all_aps(u_int boot_addr);
299static void install_ap_tramp(u_int boot_addr);
0f7a3396 300static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
984263bc 301
41a01a4d 302static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
0f7a3396
MD
303cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
304SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
305
984263bc
MD
306/*
307 * Calculate usable address in base memory for AP trampoline code.
308 */
309u_int
310mp_bootaddress(u_int basemem)
311{
312 POSTCODE(MP_BOOTADDRESS_POST);
313
c0c5de70 314 base_memory = basemem;
984263bc
MD
315
316 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
317 if ((base_memory - boot_address) < bootMP_size)
318 boot_address -= 4096; /* not enough, lower by 4k */
319
320 return boot_address;
321}
322
323
324/*
325 * Look for an Intel MP spec table (ie, SMP capable hardware).
326 */
327int
328mp_probe(void)
329{
330 int x;
331 u_long segment;
332 u_int32_t target;
f13b5eec
MD
333
334 /*
335 * Make sure our SMPpt[] page table is big enough to hold all the
336 * mappings we need.
337 */
338 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
984263bc
MD
339
340 POSTCODE(MP_PROBE_POST);
341
342 /* see if EBDA exists */
343 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
344 /* search first 1K of EBDA */
345 target = (u_int32_t) (segment << 4);
346 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
347 goto found;
348 } else {
349 /* last 1K of base memory, effective 'top of base' passed in */
350 target = (u_int32_t) (base_memory - 0x400);
351 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
352 goto found;
353 }
354
355 /* search the BIOS */
356 target = (u_int32_t) BIOS_BASE;
357 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
358 goto found;
359
360 /* nothing found */
361 mpfps = (mpfps_t)0;
362 mp_capable = 0;
363 return 0;
364
365found:
f13b5eec
MD
366 /*
367 * Calculate needed resources. We can safely map physical
368 * memory into SMPpt after mptable_pass1() completes.
369 */
984263bc
MD
370 mpfps = (mpfps_t)x;
371 mptable_pass1();
372
373 /* flag fact that we are running multiple processors */
374 mp_capable = 1;
375 return 1;
376}
377
378
379/*
380 * Startup the SMP processors.
381 */
382void
383mp_start(void)
384{
385 POSTCODE(MP_START_POST);
386
387 /* look for MP capable motherboard */
388 if (mp_capable)
389 mp_enable(boot_address);
390 else
391 panic("MP hardware not found!");
392}
393
394
395/*
396 * Print various information about the SMP system hardware and setup.
397 */
398void
399mp_announce(void)
400{
401 int x;
402
403 POSTCODE(MP_ANNOUNCE_POST);
404
26be20a0
SW
405 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
406 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
407 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
408 kprintf(", at 0x%08x\n", cpu_apic_address);
984263bc 409 for (x = 1; x <= mp_naps; ++x) {
26be20a0
SW
410 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
411 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
412 kprintf(", at 0x%08x\n", cpu_apic_address);
984263bc
MD
413 }
414
415#if defined(APIC_IO)
416 for (x = 0; x < mp_napics; ++x) {
26be20a0
SW
417 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
418 kprintf(", version: 0x%08x", io_apic_versions[x]);
419 kprintf(", at 0x%08x\n", io_apic_address[x]);
984263bc
MD
420 }
421#else
26be20a0 422 kprintf(" Warning: APIC I/O disabled\n");
984263bc
MD
423#endif /* APIC_IO */
424}
425
426/*
427 * AP cpu's call this to sync up protected mode.
7160572f
MD
428 *
429 * WARNING! We must ensure that the cpu is sufficiently initialized to
430 * be able to use to the FP for our optimized bzero/bcopy code before
431 * we enter more mainstream C code.
a44bdeec
MD
432 *
433 * WARNING! %fs is not set up on entry. This routine sets up %fs.
984263bc
MD
434 */
435void
436init_secondary(void)
437{
438 int gsel_tss;
439 int x, myid = bootAP;
440 u_int cr0;
8a8d5d85 441 struct mdglobaldata *md;
0f7a3396 442 struct privatespace *ps;
984263bc 443
0f7a3396
MD
444 ps = &CPU_prvspace[myid];
445
446 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 447 gdt_segs[GPROC0_SEL].ssd_base =
0f7a3396
MD
448 (int) &ps->mdglobaldata.gd_common_tss;
449 ps->mdglobaldata.mi.gd_prvspace = ps;
984263bc
MD
450
451 for (x = 0; x < NGDT; x++) {
452 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
453 }
454
455 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
456 r_gdt.rd_base = (int) &gdt[myid * NGDT];
457 lgdt(&r_gdt); /* does magic intra-segment return */
458
459 lidt(&r_idt);
460
461 lldt(_default_ldt);
7b95be2a 462 mdcpu->gd_currentldt = _default_ldt;
984263bc
MD
463
464 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
465 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 466
0f7a3396 467 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
MD
468
469 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
470 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
471 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
472 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
473 md->gd_common_tssd = *md->gd_tss_gdt;
984263bc
MD
474 ltr(gsel_tss);
475
476 /*
477 * Set to a known state:
478 * Set by mpboot.s: CR0_PG, CR0_PE
479 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
480 */
481 cr0 = rcr0();
482 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
483 load_cr0(cr0);
7160572f 484 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 485
7160572f
MD
486 /* set up CPU registers and state */
487 cpu_setregs();
488
489 /* set up FPU state on the AP */
490 npxinit(__INITIAL_NPXCW__);
491
492 /* set up SSE registers */
493 enable_sse();
984263bc
MD
494}
495
984263bc
MD
496/*******************************************************************
497 * local functions and data
498 */
499
500/*
501 * start the SMP system
502 */
503static void
504mp_enable(u_int boot_addr)
505{
506 int x;
507#if defined(APIC_IO)
508 int apic;
509 u_int ux;
510#endif /* APIC_IO */
511
512 POSTCODE(MP_ENABLE_POST);
513
514 /* turn on 4MB of V == P addressing so we can get to MP table */
515 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
0f7a3396 516 cpu_invltlb();
984263bc
MD
517
518 /* examine the MP table for needed info, uses physical addresses */
519 x = mptable_pass2();
520
521 *(int *)PTD = 0;
0f7a3396 522 cpu_invltlb();
984263bc
MD
523
524 /* can't process default configs till the CPU APIC is pmapped */
525 if (x)
526 default_mp_table(x);
527
984263bc
MD
528 /* post scan cleanup */
529 fix_mp_table();
984263bc
MD
530
531#if defined(APIC_IO)
532
97359a5b
MD
533 setup_apic_irq_mapping();
534
984263bc
MD
535 /* fill the LOGICAL io_apic_versions table */
536 for (apic = 0; apic < mp_napics; ++apic) {
537 ux = io_apic_read(apic, IOAPIC_VER);
538 io_apic_versions[apic] = ux;
539 io_apic_set_id(apic, IO_TO_ID(apic));
540 }
541
542 /* program each IO APIC in the system */
543 for (apic = 0; apic < mp_napics; ++apic)
544 if (io_apic_setup(apic) < 0)
545 panic("IO APIC setup failure");
546
97359a5b
MD
547#endif /* APIC_IO */
548
549 /*
550 * These are required for SMP operation
551 */
552
984263bc
MD
553 /* install a 'Spurious INTerrupt' vector */
554 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
555 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
556
557 /* install an inter-CPU IPI for TLB invalidation */
558 setidt(XINVLTLB_OFFSET, Xinvltlb,
559 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
560
96728c05
MD
561 /* install an inter-CPU IPI for IPIQ messaging */
562 setidt(XIPIQ_OFFSET, Xipiq,
563 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ
564
565 /* install a timer vector */
566 setidt(XTIMER_OFFSET, Xtimer,
567 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 568
984263bc
MD
569 /* install an inter-CPU IPI for CPU stop/restart */
570 setidt(XCPUSTOP_OFFSET, Xcpustop,
571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572
984263bc
MD
573 /* start each Application Processor */
574 start_all_aps(boot_addr);
575}
576
577
578/*
579 * look for the MP spec signature
580 */
581
582/* string defined by the Intel MP Spec as identifying the MP table */
583#define MP_SIG 0x5f504d5f /* _MP_ */
584#define NEXT(X) ((X) += 4)
585static int
586search_for_sig(u_int32_t target, int count)
587{
588 int x;
589 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
590
591 for (x = 0; x < count; NEXT(x))
592 if (addr[x] == MP_SIG)
593 /* make array index a byte index */
594 return (target + (x * sizeof(u_int32_t)));
595
596 return -1;
597}
598
599
600static basetable_entry basetable_entry_types[] =
601{
602 {0, 20, "Processor"},
603 {1, 8, "Bus"},
604 {2, 8, "I/O APIC"},
605 {3, 8, "I/O INT"},
606 {4, 8, "Local INT"}
607};
608
609typedef struct BUSDATA {
610 u_char bus_id;
611 enum busTypes bus_type;
612} bus_datum;
613
614typedef struct INTDATA {
615 u_char int_type;
616 u_short int_flags;
617 u_char src_bus_id;
618 u_char src_bus_irq;
619 u_char dst_apic_id;
620 u_char dst_apic_int;
621 u_char int_vector;
622} io_int, local_int;
623
624typedef struct BUSTYPENAME {
625 u_char type;
626 char name[7];
627} bus_type_name;
628
629static bus_type_name bus_type_table[] =
630{
631 {CBUS, "CBUS"},
632 {CBUSII, "CBUSII"},
633 {EISA, "EISA"},
634 {MCA, "MCA"},
635 {UNKNOWN_BUSTYPE, "---"},
636 {ISA, "ISA"},
637 {MCA, "MCA"},
638 {UNKNOWN_BUSTYPE, "---"},
639 {UNKNOWN_BUSTYPE, "---"},
640 {UNKNOWN_BUSTYPE, "---"},
641 {UNKNOWN_BUSTYPE, "---"},
642 {UNKNOWN_BUSTYPE, "---"},
643 {PCI, "PCI"},
644 {UNKNOWN_BUSTYPE, "---"},
645 {UNKNOWN_BUSTYPE, "---"},
646 {UNKNOWN_BUSTYPE, "---"},
647 {UNKNOWN_BUSTYPE, "---"},
648 {XPRESS, "XPRESS"},
649 {UNKNOWN_BUSTYPE, "---"}
650};
651/* from MP spec v1.4, table 5-1 */
652static int default_data[7][5] =
653{
654/* nbus, id0, type0, id1, type1 */
655 {1, 0, ISA, 255, 255},
656 {1, 0, EISA, 255, 255},
657 {1, 0, EISA, 255, 255},
658 {1, 0, MCA, 255, 255},
659 {2, 0, ISA, 1, PCI},
660 {2, 0, EISA, 1, PCI},
661 {2, 0, MCA, 1, PCI}
662};
663
664
665/* the bus data */
666static bus_datum *bus_data;
667
97359a5b 668#ifdef APIC_IO
984263bc
MD
669/* the IO INT data, one entry per possible APIC INTerrupt */
670static io_int *io_apic_ints;
984263bc 671static int nintrs;
97359a5b 672#endif
984263bc 673
3ae0cd58
RG
674static int processor_entry (proc_entry_ptr entry, int cpu);
675static int bus_entry (bus_entry_ptr entry, int bus);
97359a5b 676#ifdef APIC_IO
3ae0cd58
RG
677static int io_apic_entry (io_apic_entry_ptr entry, int apic);
678static int int_entry (int_entry_ptr entry, int intr);
97359a5b 679#endif
3ae0cd58 680static int lookup_bus_type (char *name);
984263bc
MD
681
682
683/*
684 * 1st pass on motherboard's Intel MP specification table.
685 *
686 * initializes:
8a8d5d85 687 * ncpus = 1
984263bc
MD
688 *
689 * determines:
690 * cpu_apic_address (common to all CPUs)
691 * io_apic_address[N]
692 * mp_naps
693 * mp_nbusses
694 * mp_napics
695 * nintrs
696 */
697static void
698mptable_pass1(void)
699{
97359a5b 700#ifdef APIC_IO
984263bc 701 int x;
97359a5b 702#endif
984263bc
MD
703 mpcth_t cth;
704 int totalSize;
705 void* position;
706 int count;
707 int type;
984263bc 708 u_int id_mask;
984263bc
MD
709
710 POSTCODE(MPTABLE_PASS1_POST);
711
97359a5b 712#ifdef APIC_IO
984263bc
MD
713 /* clear various tables */
714 for (x = 0; x < NAPICID; ++x) {
715 io_apic_address[x] = ~0; /* IO APIC address table */
716 }
97359a5b 717#endif
984263bc
MD
718
719 /* init everything to empty */
720 mp_naps = 0;
721 mp_nbusses = 0;
97359a5b 722#ifdef APIC_IO
984263bc
MD
723 mp_napics = 0;
724 nintrs = 0;
97359a5b 725#endif
984263bc 726 id_mask = 0;
984263bc
MD
727
728 /* check for use of 'default' configuration */
35408d22 729 if (mpfps->mpfb1 != 0) {
984263bc
MD
730 /* use default addresses */
731 cpu_apic_address = DEFAULT_APIC_BASE;
97359a5b 732#ifdef APIC_IO
984263bc 733 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
97359a5b 734#endif
984263bc
MD
735
736 /* fill in with defaults */
737 mp_naps = 2; /* includes BSP */
35408d22 738 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
984263bc
MD
739#if defined(APIC_IO)
740 mp_napics = 1;
741 nintrs = 16;
742#endif /* APIC_IO */
743 }
744 else {
745 if ((cth = mpfps->pap) == 0)
746 panic("MP Configuration Table Header MISSING!");
747
748 cpu_apic_address = (vm_offset_t) cth->apic_address;
749
750 /* walk the table, recording info of interest */
751 totalSize = cth->base_table_length - sizeof(struct MPCTH);
752 position = (u_char *) cth + sizeof(struct MPCTH);
753 count = cth->entry_count;
754
755 while (count--) {
756 switch (type = *(u_char *) position) {
757 case 0: /* processor_entry */
758 if (((proc_entry_ptr)position)->cpu_flags
759 & PROCENTRY_FLAG_EN) {
760 ++mp_naps;
984263bc
MD
761 id_mask |= 1 <<
762 ((proc_entry_ptr)position)->apic_id;
984263bc
MD
763 }
764 break;
765 case 1: /* bus_entry */
766 ++mp_nbusses;
767 break;
768 case 2: /* io_apic_entry */
97359a5b 769#ifdef APIC_IO
984263bc
MD
770 if (((io_apic_entry_ptr)position)->apic_flags
771 & IOAPICENTRY_FLAG_EN)
772 io_apic_address[mp_napics++] =
773 (vm_offset_t)((io_apic_entry_ptr)
774 position)->apic_address;
97359a5b 775#endif
984263bc
MD
776 break;
777 case 3: /* int_entry */
97359a5b 778#ifdef APIC_IO
984263bc 779 ++nintrs;
97359a5b 780#endif
984263bc
MD
781 break;
782 case 4: /* int_entry */
783 break;
784 default:
785 panic("mpfps Base Table HOSED!");
786 /* NOTREACHED */
787 }
788
789 totalSize -= basetable_entry_types[type].length;
7a9b7292
JS
790 position = (uint8_t *)position +
791 basetable_entry_types[type].length;
984263bc
MD
792 }
793 }
794
795 /* qualify the numbers */
796 if (mp_naps > MAXCPU) {
26be20a0 797 kprintf("Warning: only using %d of %d available CPUs!\n",
984263bc
MD
798 MAXCPU, mp_naps);
799 mp_naps = MAXCPU;
800 }
801
984263bc
MD
802 /* See if we need to fixup HT logical CPUs. */
803 mptable_hyperthread_fixup(id_mask);
984263bc
MD
804
805 /*
806 * Count the BSP.
807 * This is also used as a counter while starting the APs.
808 */
8a8d5d85 809 ncpus = 1;
984263bc
MD
810
811 --mp_naps; /* subtract the BSP */
812}
813
814
815/*
816 * 2nd pass on motherboard's Intel MP specification table.
817 *
818 * sets:
819 * boot_cpu_id
820 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
821 * CPU_TO_ID(N), logical CPU to APIC ID table
822 * IO_TO_ID(N), logical IO to APIC ID table
823 * bus_data[N]
824 * io_apic_ints[N]
825 */
826static int
827mptable_pass2(void)
828{
984263bc 829 struct PROCENTRY proc;
984263bc
MD
830 int x;
831 mpcth_t cth;
832 int totalSize;
833 void* position;
834 int count;
835 int type;
836 int apic, bus, cpu, intr;
f13b5eec 837 int i;
984263bc
MD
838
839 POSTCODE(MPTABLE_PASS2_POST);
840
984263bc
MD
841 /* Initialize fake proc entry for use with HT fixup. */
842 bzero(&proc, sizeof(proc));
843 proc.type = 0;
844 proc.cpu_flags = PROCENTRY_FLAG_EN;
984263bc 845
97359a5b 846#ifdef APIC_IO
984263bc
MD
847 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
848 M_DEVBUF, M_WAITOK);
849 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 850 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 851 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc 852 M_DEVBUF, M_WAITOK);
97359a5b 853#endif
984263bc
MD
854 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
855 M_DEVBUF, M_WAITOK);
856
97359a5b 857#ifdef APIC_IO
984263bc 858 for (i = 0; i < mp_napics; i++) {
f13b5eec 859 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
984263bc 860 }
97359a5b 861#endif
984263bc
MD
862
863 /* clear various tables */
864 for (x = 0; x < NAPICID; ++x) {
984263bc 865 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
97359a5b
MD
866#ifdef APIC_IO
867 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc 868 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
97359a5b 869#endif
984263bc
MD
870 }
871
872 /* clear bus data table */
873 for (x = 0; x < mp_nbusses; ++x)
874 bus_data[x].bus_id = 0xff;
875
97359a5b 876#ifdef APIC_IO
984263bc
MD
877 /* clear IO APIC INT table */
878 for (x = 0; x < (nintrs + 1); ++x) {
879 io_apic_ints[x].int_type = 0xff;
880 io_apic_ints[x].int_vector = 0xff;
881 }
97359a5b 882#endif
984263bc
MD
883
884 /* setup the cpu/apic mapping arrays */
885 boot_cpu_id = -1;
886
887 /* record whether PIC or virtual-wire mode */
e96ee753 888 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
984263bc
MD
889
890 /* check for use of 'default' configuration */
35408d22
MD
891 if (mpfps->mpfb1 != 0)
892 return mpfps->mpfb1; /* return default configuration type */
984263bc
MD
893
894 if ((cth = mpfps->pap) == 0)
895 panic("MP Configuration Table Header MISSING!");
896
897 /* walk the table, recording info of interest */
898 totalSize = cth->base_table_length - sizeof(struct MPCTH);
899 position = (u_char *) cth + sizeof(struct MPCTH);
900 count = cth->entry_count;
901 apic = bus = intr = 0;
902 cpu = 1; /* pre-count the BSP */
903
904 while (count--) {
905 switch (type = *(u_char *) position) {
906 case 0:
907 if (processor_entry(position, cpu))
908 ++cpu;
909
984263bc
MD
910 if (need_hyperthreading_fixup) {
911 /*
912 * Create fake mptable processor entries
913 * and feed them to processor_entry() to
914 * enumerate the logical CPUs.
915 */
916 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
917 for (i = 1; i < logical_cpus; i++) {
918 proc.apic_id++;
09e6e929 919 processor_entry(&proc, cpu);
48add334 920 logical_cpus_mask |= (1 << cpu);
984263bc
MD
921 cpu++;
922 }
923 }
984263bc
MD
924 break;
925 case 1:
926 if (bus_entry(position, bus))
927 ++bus;
928 break;
929 case 2:
97359a5b 930#ifdef APIC_IO
984263bc
MD
931 if (io_apic_entry(position, apic))
932 ++apic;
97359a5b 933#endif
984263bc
MD
934 break;
935 case 3:
97359a5b 936#ifdef APIC_IO
984263bc
MD
937 if (int_entry(position, intr))
938 ++intr;
97359a5b 939#endif
984263bc
MD
940 break;
941 case 4:
942 /* int_entry(position); */
943 break;
944 default:
945 panic("mpfps Base Table HOSED!");
946 /* NOTREACHED */
947 }
948
949 totalSize -= basetable_entry_types[type].length;
7a9b7292 950 position = (uint8_t *)position + basetable_entry_types[type].length;
984263bc
MD
951 }
952
953 if (boot_cpu_id == -1)
954 panic("NO BSP found!");
955
956 /* report fact that its NOT a default configuration */
957 return 0;
958}
959
984263bc
MD
960/*
961 * Check if we should perform a hyperthreading "fix-up" to
962 * enumerate any logical CPU's that aren't already listed
963 * in the table.
964 *
965 * XXX: We assume that all of the physical CPUs in the
966 * system have the same number of logical CPUs.
967 *
968 * XXX: We assume that APIC ID's are allocated such that
969 * the APIC ID's for a physical processor are aligned
970 * with the number of logical CPU's in the processor.
971 */
972static void
973mptable_hyperthread_fixup(u_int id_mask)
974{
975 u_int i, id;
976
977 /* Nothing to do if there is no HTT support. */
978 if ((cpu_feature & CPUID_HTT) == 0)
979 return;
980 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
981 if (logical_cpus <= 1)
982 return;
983
984 /*
985 * For each APIC ID of a CPU that is set in the mask,
986 * scan the other candidate APIC ID's for this
987 * physical processor. If any of those ID's are
988 * already in the table, then kill the fixup.
989 */
990 for (id = 0; id <= MAXCPU; id++) {
991 if ((id_mask & 1 << id) == 0)
992 continue;
993 /* First, make sure we are on a logical_cpus boundary. */
994 if (id % logical_cpus != 0)
995 return;
996 for (i = id + 1; i < id + logical_cpus; i++)
997 if ((id_mask & 1 << i) != 0)
998 return;
999 }
1000
1001 /*
1002 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1003 * mp_naps right now.
1004 */
1005 need_hyperthreading_fixup = 1;
1006 mp_naps *= logical_cpus;
1007}
984263bc 1008
97359a5b
MD
1009#ifdef APIC_IO
1010
984263bc
MD
1011void
1012assign_apic_irq(int apic, int intpin, int irq)
1013{
1014 int x;
1015
1016 if (int_to_apicintpin[irq].ioapic != -1)
1017 panic("assign_apic_irq: inconsistent table");
1018
1019 int_to_apicintpin[irq].ioapic = apic;
1020 int_to_apicintpin[irq].int_pin = intpin;
1021 int_to_apicintpin[irq].apic_address = ioapic[apic];
1022 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1023
1024 for (x = 0; x < nintrs; x++) {
1025 if ((io_apic_ints[x].int_type == 0 ||
1026 io_apic_ints[x].int_type == 3) &&
1027 io_apic_ints[x].int_vector == 0xff &&
1028 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1029 io_apic_ints[x].dst_apic_int == intpin)
1030 io_apic_ints[x].int_vector = irq;
1031 }
1032}
1033
1034void
1035revoke_apic_irq(int irq)
1036{
1037 int x;
1038 int oldapic;
1039 int oldintpin;
1040
1041 if (int_to_apicintpin[irq].ioapic == -1)
1042 panic("revoke_apic_irq: inconsistent table");
1043
1044 oldapic = int_to_apicintpin[irq].ioapic;
1045 oldintpin = int_to_apicintpin[irq].int_pin;
1046
1047 int_to_apicintpin[irq].ioapic = -1;
1048 int_to_apicintpin[irq].int_pin = 0;
1049 int_to_apicintpin[irq].apic_address = NULL;
1050 int_to_apicintpin[irq].redirindex = 0;
1051
1052 for (x = 0; x < nintrs; x++) {
1053 if ((io_apic_ints[x].int_type == 0 ||
1054 io_apic_ints[x].int_type == 3) &&
1055 io_apic_ints[x].int_vector != 0xff &&
1056 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1057 io_apic_ints[x].dst_apic_int == oldintpin)
1058 io_apic_ints[x].int_vector = 0xff;
1059 }
1060}
1061
1439c090
MD
1062/*
1063 * Allocate an IRQ
1064 */
984263bc
MD
1065static void
1066allocate_apic_irq(int intr)
1067{
1068 int apic;
1069 int intpin;
1070 int irq;
1071
1072 if (io_apic_ints[intr].int_vector != 0xff)
1073 return; /* Interrupt handler already assigned */
1074
1075 if (io_apic_ints[intr].int_type != 0 &&
1076 (io_apic_ints[intr].int_type != 3 ||
1077 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1078 io_apic_ints[intr].dst_apic_int == 0)))
1079 return; /* Not INT or ExtInt on != (0, 0) */
1080
1081 irq = 0;
1082 while (irq < APIC_INTMAPSIZE &&
1083 int_to_apicintpin[irq].ioapic != -1)
1084 irq++;
1085
1086 if (irq >= APIC_INTMAPSIZE)
1087 return; /* No free interrupt handlers */
1088
1089 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1090 intpin = io_apic_ints[intr].dst_apic_int;
1091
1092 assign_apic_irq(apic, intpin, irq);
1093 io_apic_setup_intpin(apic, intpin);
1094}
1095
1096
1097static void
1098swap_apic_id(int apic, int oldid, int newid)
1099{
1100 int x;
1101 int oapic;
1102
1103
1104 if (oldid == newid)
1105 return; /* Nothing to do */
1106
26be20a0 1107 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD
1108 apic, oldid, newid);
1109
1110 /* Swap physical APIC IDs in interrupt entries */
1111 for (x = 0; x < nintrs; x++) {
1112 if (io_apic_ints[x].dst_apic_id == oldid)
1113 io_apic_ints[x].dst_apic_id = newid;
1114 else if (io_apic_ints[x].dst_apic_id == newid)
1115 io_apic_ints[x].dst_apic_id = oldid;
1116 }
1117
1118 /* Swap physical APIC IDs in IO_TO_ID mappings */
1119 for (oapic = 0; oapic < mp_napics; oapic++)
1120 if (IO_TO_ID(oapic) == newid)
1121 break;
1122
1123 if (oapic < mp_napics) {
26be20a0 1124 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD
1125 "%d to %d in MP table\n",
1126 oapic, newid, oldid);
1127 IO_TO_ID(oapic) = oldid;
1128 }
1129 IO_TO_ID(apic) = newid;
1130}
1131
1132
1133static void
1134fix_id_to_io_mapping(void)
1135{
1136 int x;
1137
1138 for (x = 0; x < NAPICID; x++)
1139 ID_TO_IO(x) = -1;
1140
1141 for (x = 0; x <= mp_naps; x++)
1142 if (CPU_TO_ID(x) < NAPICID)
1143 ID_TO_IO(CPU_TO_ID(x)) = x;
1144
1145 for (x = 0; x < mp_napics; x++)
1146 if (IO_TO_ID(x) < NAPICID)
1147 ID_TO_IO(IO_TO_ID(x)) = x;
1148}
1149
1150
1151static int
1152first_free_apic_id(void)
1153{
1154 int freeid, x;
1155
1156 for (freeid = 0; freeid < NAPICID; freeid++) {
1157 for (x = 0; x <= mp_naps; x++)
1158 if (CPU_TO_ID(x) == freeid)
1159 break;
1160 if (x <= mp_naps)
1161 continue;
1162 for (x = 0; x < mp_napics; x++)
1163 if (IO_TO_ID(x) == freeid)
1164 break;
1165 if (x < mp_napics)
1166 continue;
1167 return freeid;
1168 }
1169 return freeid;
1170}
1171
1172
1173static int
1174io_apic_id_acceptable(int apic, int id)
1175{
1176 int cpu; /* Logical CPU number */
1177 int oapic; /* Logical IO APIC number for other IO APIC */
1178
1179 if (id >= NAPICID)
1180 return 0; /* Out of range */
1181
1182 for (cpu = 0; cpu <= mp_naps; cpu++)
1183 if (CPU_TO_ID(cpu) == id)
1184 return 0; /* Conflict with CPU */
1185
1186 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1187 if (IO_TO_ID(oapic) == id)
1188 return 0; /* Conflict with other APIC */
1189
1190 return 1; /* ID is acceptable for IO APIC */
1191}
1192
1439c090
MD
1193static
1194io_int *
1195io_apic_find_int_entry(int apic, int pin)
1196{
1197 int x;
1198
1199 /* search each of the possible INTerrupt sources */
1200 for (x = 0; x < nintrs; ++x) {
1201 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1202 (pin == io_apic_ints[x].dst_apic_int))
1203 return (&io_apic_ints[x]);
1204 }
1205 return NULL;
1206}
1207
97359a5b 1208#endif
984263bc
MD
1209
1210/*
1211 * parse an Intel MP specification table
1212 */
1213static void
1214fix_mp_table(void)
1215{
1216 int x;
97359a5b 1217#ifdef APIC_IO
984263bc 1218 int id;
984263bc
MD
1219 int apic; /* IO APIC unit number */
1220 int freeid; /* Free physical APIC ID */
1221 int physid; /* Current physical IO APIC ID */
1439c090 1222 io_int *io14;
97359a5b
MD
1223#endif
1224 int bus_0 = 0; /* Stop GCC warning */
1225 int bus_pci = 0; /* Stop GCC warning */
1226 int num_pci_bus;
984263bc
MD
1227
1228 /*
1229 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1230 * did it wrong. The MP spec says that when more than 1 PCI bus
1231 * exists the BIOS must begin with bus entries for the PCI bus and use
1232 * actual PCI bus numbering. This implies that when only 1 PCI bus
1233 * exists the BIOS can choose to ignore this ordering, and indeed many
1234 * MP motherboards do ignore it. This causes a problem when the PCI
1235 * sub-system makes requests of the MP sub-system based on PCI bus
1236 * numbers. So here we look for the situation and renumber the
1237 * busses and associated INTs in an effort to "make it right".
1238 */
1239
1240 /* find bus 0, PCI bus, count the number of PCI busses */
1241 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1242 if (bus_data[x].bus_id == 0) {
1243 bus_0 = x;
1244 }
1245 if (bus_data[x].bus_type == PCI) {
1246 ++num_pci_bus;
1247 bus_pci = x;
1248 }
1249 }
1250 /*
1251 * bus_0 == slot of bus with ID of 0
1252 * bus_pci == slot of last PCI bus encountered
1253 */
1254
1255 /* check the 1 PCI bus case for sanity */
1256 /* if it is number 0 all is well */
1257 if (num_pci_bus == 1 &&
1258 bus_data[bus_pci].bus_id != 0) {
1259
1260 /* mis-numbered, swap with whichever bus uses slot 0 */
1261
1262 /* swap the bus entry types */
1263 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1264 bus_data[bus_0].bus_type = PCI;
1265
97359a5b 1266#ifdef APIC_IO
984263bc
MD
1267 /* swap each relavant INTerrupt entry */
1268 id = bus_data[bus_pci].bus_id;
1269 for (x = 0; x < nintrs; ++x) {
1270 if (io_apic_ints[x].src_bus_id == id) {
1271 io_apic_ints[x].src_bus_id = 0;
1272 }
1273 else if (io_apic_ints[x].src_bus_id == 0) {
1274 io_apic_ints[x].src_bus_id = id;
1275 }
1276 }
97359a5b 1277#endif
984263bc
MD
1278 }
1279
97359a5b 1280#ifdef APIC_IO
984263bc
MD
1281 /* Assign IO APIC IDs.
1282 *
1283 * First try the existing ID. If a conflict is detected, try
1284 * the ID in the MP table. If a conflict is still detected, find
1285 * a free id.
1286 *
1287 * We cannot use the ID_TO_IO table before all conflicts has been
1288 * resolved and the table has been corrected.
1289 */
1290 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1291
1292 /* First try to use the value set by the BIOS */
1293 physid = io_apic_get_id(apic);
1294 if (io_apic_id_acceptable(apic, physid)) {
1295 if (IO_TO_ID(apic) != physid)
1296 swap_apic_id(apic, IO_TO_ID(apic), physid);
1297 continue;
1298 }
1299
1300 /* Then check if the value in the MP table is acceptable */
1301 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1302 continue;
1303
1304 /* Last resort, find a free APIC ID and use it */
1305 freeid = first_free_apic_id();
1306 if (freeid >= NAPICID)
1307 panic("No free physical APIC IDs found");
1308
1309 if (io_apic_id_acceptable(apic, freeid)) {
1310 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1311 continue;
1312 }
1313 panic("Free physical APIC ID not usable");
1314 }
1315 fix_id_to_io_mapping();
97359a5b 1316#endif
984263bc 1317
97359a5b 1318#ifdef APIC_IO
984263bc
MD
1319 /* detect and fix broken Compaq MP table */
1320 if (apic_int_type(0, 0) == -1) {
26be20a0 1321 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD
1322 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1323 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1324 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1325 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1326 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1327 nintrs++;
ad12f88c 1328 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1329 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP
1330 for (x = 0; x < nintrs; ++x)
1331 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1332 (0 == io_apic_ints[x].dst_apic_int)) {
1333 io_apic_ints[x].int_type = 3;
1334 io_apic_ints[x].int_vector = 0xff;
1335 break;
1336 }
984263bc 1337 }
1439c090
MD
1338
1339 /*
1340 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1341 * controllers universally come in pairs. If IRQ 14 is specified
1342 * as an ISA interrupt, then IRQ 15 had better be too.
1343 *
1344 * [ Shuttle XPC / AMD Athlon X2 ]
1345 * The MPTable is missing an entry for IRQ 15. Note that the
1346 * ACPI table has an entry for both 14 and 15.
1347 */
1348 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1349 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD
1350 io14 = io_apic_find_int_entry(0, 14);
1351 io_apic_ints[nintrs] = *io14;
1352 io_apic_ints[nintrs].src_bus_irq = 15;
1353 io_apic_ints[nintrs].dst_apic_int = 15;
1354 nintrs++;
1355 }
97359a5b 1356#endif
984263bc
MD
1357}
1358
97359a5b 1359#ifdef APIC_IO
984263bc
MD
1360
1361/* Assign low level interrupt handlers */
1362static void
1363setup_apic_irq_mapping(void)
1364{
1365 int x;
1366 int int_vector;
1367
1368 /* Clear array */
1369 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1370 int_to_apicintpin[x].ioapic = -1;
1371 int_to_apicintpin[x].int_pin = 0;
1372 int_to_apicintpin[x].apic_address = NULL;
1373 int_to_apicintpin[x].redirindex = 0;
1374 }
1375
1376 /* First assign ISA/EISA interrupts */
1377 for (x = 0; x < nintrs; x++) {
1378 int_vector = io_apic_ints[x].src_bus_irq;
1379 if (int_vector < APIC_INTMAPSIZE &&
1380 io_apic_ints[x].int_vector == 0xff &&
1381 int_to_apicintpin[int_vector].ioapic == -1 &&
1382 (apic_int_is_bus_type(x, ISA) ||
1383 apic_int_is_bus_type(x, EISA)) &&
1384 io_apic_ints[x].int_type == 0) {
1385 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1386 io_apic_ints[x].dst_apic_int,
1387 int_vector);
1388 }
1389 }
1390
1391 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1392 for (x = 0; x < nintrs; x++) {
1393 if (io_apic_ints[x].dst_apic_int == 0 &&
1394 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1395 io_apic_ints[x].int_vector == 0xff &&
1396 int_to_apicintpin[0].ioapic == -1 &&
1397 io_apic_ints[x].int_type == 3) {
1398 assign_apic_irq(0, 0, 0);
1399 break;
1400 }
1401 }
1402 /* PCI interrupt assignment is deferred */
1403}
1404
97359a5b 1405#endif
984263bc
MD
1406
1407static int
1408processor_entry(proc_entry_ptr entry, int cpu)
1409{
1410 /* check for usability */
1411 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1412 return 0;
1413
1414 if(entry->apic_id >= NAPICID)
1415 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1416 /* check for BSP flag */
1417 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1418 boot_cpu_id = entry->apic_id;
1419 CPU_TO_ID(0) = entry->apic_id;
1420 ID_TO_CPU(entry->apic_id) = 0;
1421 return 0; /* its already been counted */
1422 }
1423
1424 /* add another AP to list, if less than max number of CPUs */
1425 else if (cpu < MAXCPU) {
1426 CPU_TO_ID(cpu) = entry->apic_id;
1427 ID_TO_CPU(entry->apic_id) = cpu;
1428 return 1;
1429 }
1430
1431 return 0;
1432}
1433
1434
1435static int
1436bus_entry(bus_entry_ptr entry, int bus)
1437{
1438 int x;
1439 char c, name[8];
1440
1441 /* encode the name into an index */
1442 for (x = 0; x < 6; ++x) {
1443 if ((c = entry->bus_type[x]) == ' ')
1444 break;
1445 name[x] = c;
1446 }
1447 name[x] = '\0';
1448
1449 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1450 panic("unknown bus type: '%s'", name);
1451
1452 bus_data[bus].bus_id = entry->bus_id;
1453 bus_data[bus].bus_type = x;
1454
1455 return 1;
1456}
1457
97359a5b 1458#ifdef APIC_IO
984263bc
MD
1459
1460static int
1461io_apic_entry(io_apic_entry_ptr entry, int apic)
1462{
1463 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1464 return 0;
1465
1466 IO_TO_ID(apic) = entry->apic_id;
1467 if (entry->apic_id < NAPICID)
1468 ID_TO_IO(entry->apic_id) = apic;
1469
1470 return 1;
1471}
1472
97359a5b 1473#endif
984263bc
MD
1474
1475static int
1476lookup_bus_type(char *name)
1477{
1478 int x;
1479
1480 for (x = 0; x < MAX_BUSTYPE; ++x)
1481 if (strcmp(bus_type_table[x].name, name) == 0)
1482 return bus_type_table[x].type;
1483
1484 return UNKNOWN_BUSTYPE;
1485}
1486
97359a5b 1487#ifdef APIC_IO
984263bc
MD
1488
1489static int
1490int_entry(int_entry_ptr entry, int intr)
1491{
1492 int apic;
1493
1494 io_apic_ints[intr].int_type = entry->int_type;
1495 io_apic_ints[intr].int_flags = entry->int_flags;
1496 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1497 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1498 if (entry->dst_apic_id == 255) {
1499 /* This signal goes to all IO APICS. Select an IO APIC
1500 with sufficient number of interrupt pins */
1501 for (apic = 0; apic < mp_napics; apic++)
1502 if (((io_apic_read(apic, IOAPIC_VER) &
1503 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1504 entry->dst_apic_int)
1505 break;
1506 if (apic < mp_napics)
1507 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1508 else
1509 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1510 } else
1511 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1512 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1513
1514 return 1;
1515}
1516
984263bc
MD
1517static int
1518apic_int_is_bus_type(int intr, int bus_type)
1519{
1520 int bus;
1521
1522 for (bus = 0; bus < mp_nbusses; ++bus)
1523 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1524 && ((int) bus_data[bus].bus_type == bus_type))
1525 return 1;
1526
1527 return 0;
1528}
1529
984263bc
MD
1530/*
1531 * Given a traditional ISA INT mask, return an APIC mask.
1532 */
1533u_int
1534isa_apic_mask(u_int isa_mask)
1535{
1536 int isa_irq;
1537 int apic_pin;
1538
1539#if defined(SKIP_IRQ15_REDIRECT)
1540 if (isa_mask == (1 << 15)) {
26be20a0 1541 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD
1542 return isa_mask;
1543 }
1544#endif /* SKIP_IRQ15_REDIRECT */
1545
1546 isa_irq = ffs(isa_mask); /* find its bit position */
1547 if (isa_irq == 0) /* doesn't exist */
1548 return 0;
1549 --isa_irq; /* make it zero based */
1550
1551 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1552 if (apic_pin == -1)
1553 return 0;
1554
1555 return (1 << apic_pin); /* convert pin# to a mask */
1556}
1557
984263bc
MD
1558/*
1559 * Determine which APIC pin an ISA/EISA INT is attached to.
1560 */
1561#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1562#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1563#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1564#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1565
1566#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1567int
1568isa_apic_irq(int isa_irq)
1569{
1570 int intr;
1571
1572 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1573 if (INTTYPE(intr) == 0) { /* standard INT */
1574 if (SRCBUSIRQ(intr) == isa_irq) {
1575 if (apic_int_is_bus_type(intr, ISA) ||
1576 apic_int_is_bus_type(intr, EISA)) {
1577 if (INTIRQ(intr) == 0xff)
1578 return -1; /* unassigned */
1579 return INTIRQ(intr); /* found */
1580 }
1581 }
1582 }
1583 }
1584 return -1; /* NOT found */
1585}
1586
1587
1588/*
1589 * Determine which APIC pin a PCI INT is attached to.
1590 */
1591#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1592#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1593#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1594int
1595pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1596{
1597 int intr;
1598
1599 --pciInt; /* zero based */
1600
1439c090 1601 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD
1602 if ((INTTYPE(intr) == 0) /* standard INT */
1603 && (SRCBUSID(intr) == pciBus)
1604 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1605 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc
MD
1606 if (apic_int_is_bus_type(intr, PCI)) {
1607 if (INTIRQ(intr) == 0xff)
1608 allocate_apic_irq(intr);
1609 if (INTIRQ(intr) == 0xff)
1610 return -1; /* unassigned */
1611 return INTIRQ(intr); /* exact match */
1612 }
1439c090
MD
1613 }
1614 }
984263bc
MD
1615
1616 return -1; /* NOT found */
1617}
1618
1619int
1620next_apic_irq(int irq)
1621{
1622 int intr, ointr;
1623 int bus, bustype;
1624
1625 bus = 0;
1626 bustype = 0;
1627 for (intr = 0; intr < nintrs; intr++) {
1628 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1629 continue;
1630 bus = SRCBUSID(intr);
1631 bustype = apic_bus_type(bus);
1632 if (bustype != ISA &&
1633 bustype != EISA &&
1634 bustype != PCI)
1635 continue;
1636 break;
1637 }
1638 if (intr >= nintrs) {
1639 return -1;
1640 }
1641 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1642 if (INTTYPE(ointr) != 0)
1643 continue;
1644 if (bus != SRCBUSID(ointr))
1645 continue;
1646 if (bustype == PCI) {
1647 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1648 continue;
1649 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1650 continue;
1651 }
1652 if (bustype == ISA || bustype == EISA) {
1653 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1654 continue;
1655 }
1656 if (INTPIN(intr) == INTPIN(ointr))
1657 continue;
1658 break;
1659 }
1660 if (ointr >= nintrs) {
1661 return -1;
1662 }
1663 return INTIRQ(ointr);
1664}
1665#undef SRCBUSLINE
1666#undef SRCBUSDEVICE
1667#undef SRCBUSID
1668#undef SRCBUSIRQ
1669
1670#undef INTPIN
1671#undef INTIRQ
1672#undef INTAPIC
1673#undef INTTYPE
1674
97359a5b 1675#endif
984263bc
MD
1676
1677/*
1678 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1679 *
1680 * XXX FIXME:
1681 * Exactly what this means is unclear at this point. It is a solution
1682 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1683 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1684 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1685 * option.
1686 */
1687int
1688undirect_isa_irq(int rirq)
1689{
1690#if defined(READY)
1691 if (bootverbose)
26be20a0 1692 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1693 /** FIXME: tickle the MB redirector chip */
c044141b 1694 return /* XXX */;
984263bc
MD
1695#else
1696 if (bootverbose)
26be20a0 1697 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
984263bc
MD
1698 return 0;
1699#endif /* READY */
1700}
1701
1702
1703/*
1704 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1705 */
1706int
1707undirect_pci_irq(int rirq)
1708{
1709#if defined(READY)
1710 if (bootverbose)
26be20a0 1711 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD
1712
1713 /** FIXME: tickle the MB redirector chip */
c044141b 1714 return /* XXX */;
984263bc
MD
1715#else
1716 if (bootverbose)
26be20a0 1717 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD
1718 rirq);
1719 return 0;
1720#endif /* READY */
1721}
1722
1723
1724/*
1725 * given a bus ID, return:
1726 * the bus type if found
1727 * -1 if NOT found
1728 */
1729int
1730apic_bus_type(int id)
1731{
1732 int x;
1733
1734 for (x = 0; x < mp_nbusses; ++x)
1735 if (bus_data[x].bus_id == id)
1736 return bus_data[x].bus_type;
1737
1738 return -1;
1739}
1740
97359a5b 1741#ifdef APIC_IO
984263bc
MD
1742
1743/*
1744 * given a LOGICAL APIC# and pin#, return:
1745 * the associated src bus ID if found
1746 * -1 if NOT found
1747 */
1748int
1749apic_src_bus_id(int apic, int pin)
1750{
1751 int x;
1752
1753 /* search each of the possible INTerrupt sources */
1754 for (x = 0; x < nintrs; ++x)
1755 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1756 (pin == io_apic_ints[x].dst_apic_int))
1757 return (io_apic_ints[x].src_bus_id);
1758
1759 return -1; /* NOT found */
1760}
1761
984263bc
MD
1762/*
1763 * given a LOGICAL APIC# and pin#, return:
1764 * the associated src bus IRQ if found
1765 * -1 if NOT found
1766 */
1767int
1768apic_src_bus_irq(int apic, int pin)
1769{
1770 int x;
1771
1772 for (x = 0; x < nintrs; x++)
1773 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1774 (pin == io_apic_ints[x].dst_apic_int))
1775 return (io_apic_ints[x].src_bus_irq);
1776
1777 return -1; /* NOT found */
1778}
1779
1780
1781/*
1782 * given a LOGICAL APIC# and pin#, return:
1783 * the associated INTerrupt type if found
1784 * -1 if NOT found
1785 */
1786int
1787apic_int_type(int apic, int pin)
1788{
1789 int x;
1790
1791 /* search each of the possible INTerrupt sources */
1439c090 1792 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1793 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1794 (pin == io_apic_ints[x].dst_apic_int))
1795 return (io_apic_ints[x].int_type);
1439c090 1796 }
984263bc
MD
1797 return -1; /* NOT found */
1798}
1799
1439c090
MD
1800/*
1801 * Return the IRQ associated with an APIC pin
1802 */
984263bc
MD
1803int
1804apic_irq(int apic, int pin)
1805{
1806 int x;
1807 int res;
1808
1439c090 1809 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1810 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1811 (pin == io_apic_ints[x].dst_apic_int)) {
1812 res = io_apic_ints[x].int_vector;
1813 if (res == 0xff)
1814 return -1;
1815 if (apic != int_to_apicintpin[res].ioapic)
1439c090 1816 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
984263bc
MD
1817 if (pin != int_to_apicintpin[res].int_pin)
1818 panic("apic_irq inconsistent table (2)");
1819 return res;
1820 }
1439c090 1821 }
984263bc
MD
1822 return -1;
1823}
1824
1825
1826/*
1827 * given a LOGICAL APIC# and pin#, return:
1828 * the associated trigger mode if found
1829 * -1 if NOT found
1830 */
1831int
1832apic_trigger(int apic, int pin)
1833{
1834 int x;
1835
1836 /* search each of the possible INTerrupt sources */
1837 for (x = 0; x < nintrs; ++x)
1838 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1839 (pin == io_apic_ints[x].dst_apic_int))
1840 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1841
1842 return -1; /* NOT found */
1843}
1844
1845
1846/*
1847 * given a LOGICAL APIC# and pin#, return:
1848 * the associated 'active' level if found
1849 * -1 if NOT found
1850 */
1851int
1852apic_polarity(int apic, int pin)
1853{
1854 int x;
1855
1856 /* search each of the possible INTerrupt sources */
1857 for (x = 0; x < nintrs; ++x)
1858 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1859 (pin == io_apic_ints[x].dst_apic_int))
1860 return (io_apic_ints[x].int_flags & 0x03);
1861
1862 return -1; /* NOT found */
1863}
1864
97359a5b 1865#endif
984263bc
MD
1866
1867/*
1868 * set data according to MP defaults
1869 * FIXME: probably not complete yet...
1870 */
1871static void
1872default_mp_table(int type)
1873{
1874 int ap_cpu_id;
1875#if defined(APIC_IO)
1876 int io_apic_id;
1877 int pin;
1878#endif /* APIC_IO */
1879
1880#if 0
26be20a0 1881 kprintf(" MP default config type: %d\n", type);
984263bc
MD
1882 switch (type) {
1883 case 1:
26be20a0 1884 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD
1885 break;
1886 case 2:
26be20a0 1887 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
1888 break;
1889 case 3:
26be20a0 1890 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
1891 break;
1892 case 4:
26be20a0 1893 kprintf(" bus: MCA, APIC: 82489DX\n");
984263bc
MD
1894 break;
1895 case 5:
26be20a0 1896 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD
1897 break;
1898 case 6:
26be20a0 1899 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD
1900 break;
1901 case 7:
26be20a0 1902 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD
1903 break;
1904 default:
26be20a0 1905 kprintf(" future type\n");
984263bc
MD
1906 break;
1907 /* NOTREACHED */
1908 }
1909#endif /* 0 */
1910
1911 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1912 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1913
1914 /* BSP */
1915 CPU_TO_ID(0) = boot_cpu_id;
1916 ID_TO_CPU(boot_cpu_id) = 0;
1917
1918 /* one and only AP */
1919 CPU_TO_ID(1) = ap_cpu_id;
1920 ID_TO_CPU(ap_cpu_id) = 1;
1921
1922#if defined(APIC_IO)
1923 /* one and only IO APIC */
1924 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1925
1926 /*
1927 * sanity check, refer to MP spec section 3.6.6, last paragraph
1928 * necessary as some hardware isn't properly setting up the IO APIC
1929 */
1930#if defined(REALLY_ANAL_IOAPICID_VALUE)
1931 if (io_apic_id != 2) {
1932#else
1933 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1934#endif /* REALLY_ANAL_IOAPICID_VALUE */
1935 io_apic_set_id(0, 2);
1936 io_apic_id = 2;
1937 }
1938 IO_TO_ID(0) = io_apic_id;
1939 ID_TO_IO(io_apic_id) = 0;
1940#endif /* APIC_IO */
1941
1942 /* fill out bus entries */
1943 switch (type) {
1944 case 1:
1945 case 2:
1946 case 3:
1947 case 4:
1948 case 5:
1949 case 6:
1950 case 7:
1951 bus_data[0].bus_id = default_data[type - 1][1];
1952 bus_data[0].bus_type = default_data[type - 1][2];
1953 bus_data[1].bus_id = default_data[type - 1][3];
1954 bus_data[1].bus_type = default_data[type - 1][4];
1955 break;
1956
1957 /* case 4: case 7: MCA NOT supported */
1958 default: /* illegal/reserved */
1959 panic("BAD default MP config: %d", type);
1960 /* NOTREACHED */
1961 }
1962
1963#if defined(APIC_IO)
1964 /* general cases from MP v1.4, table 5-2 */
1965 for (pin = 0; pin < 16; ++pin) {
1966 io_apic_ints[pin].int_type = 0;
1967 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1968 io_apic_ints[pin].src_bus_id = 0;
1969 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1970 io_apic_ints[pin].dst_apic_id = io_apic_id;
1971 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1972 }
1973
1974 /* special cases from MP v1.4, table 5-2 */
1975 if (type == 2) {
1976 io_apic_ints[2].int_type = 0xff; /* N/C */
1977 io_apic_ints[13].int_type = 0xff; /* N/C */
1978#if !defined(APIC_MIXED_MODE)
1979 /** FIXME: ??? */
1980 panic("sorry, can't support type 2 default yet");
1981#endif /* APIC_MIXED_MODE */
1982 }
1983 else
1984 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1985
1986 if (type == 7)
1987 io_apic_ints[0].int_type = 0xff; /* N/C */
1988 else
1989 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1990#endif /* APIC_IO */
1991}
1992
984263bc 1993/*
f13b5eec
MD
1994 * Map a physical memory address representing I/O into KVA. The I/O
1995 * block is assumed not to cross a page boundary.
1996 */
1997void *
1998permanent_io_mapping(vm_paddr_t pa)
1999{
2000 vm_offset_t vaddr;
2001 int pgeflag;
2002 int i;
2003
2004 KKASSERT(pa < 0x100000000LL);
2005
2006 pgeflag = 0; /* not used for SMP yet */
2007
2008 /*
2009 * If the requested physical address has already been incidently
2010 * mapped, just use the existing mapping. Otherwise create a new
2011 * mapping.
2012 */
2013 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2014 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2015 ((vm_offset_t)pa & PG_FRAME)) {
2016 break;
2017 }
2018 }
2019 if (i == SMPpt_alloc_index) {
2020 if (i == NPTEPG - 2) {
2021 panic("permanent_io_mapping: We ran out of space"
2022 " in SMPpt[]!");
2023 }
2024 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2025 ((vm_offset_t)pa & PG_FRAME));
2026 ++SMPpt_alloc_index;
2027 }
2028 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2029 ((vm_offset_t)pa & PAGE_MASK);
2030 return ((void *)vaddr);
2031}
2032
2033/*
984263bc
MD
2034 * start each AP in our list
2035 */
2036static int
2037start_all_aps(u_int boot_addr)
2038{
b45759e1
MD
2039 int x, i, pg;
2040 int shift;
984263bc
MD
2041 u_char mpbiosreason;
2042 u_long mpbioswarmvec;
8a8d5d85 2043 struct mdglobaldata *gd;
0f7a3396 2044 struct privatespace *ps;
984263bc
MD
2045 char *stack;
2046 uintptr_t kptbase;
2047
2048 POSTCODE(START_ALL_APS_POST);
2049
b52c8db0
SZ
2050 /* Initialize BSP's local APIC */
2051 apic_initialize(TRUE);
984263bc
MD
2052 bsp_apic_ready = 1;
2053
2054 /* install the AP 1st level boot code */
2055 install_ap_tramp(boot_addr);
2056
2057
2058 /* save the current value of the warm-start vector */
2059 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
2060 outb(CMOS_REG, BIOS_RESET);
2061 mpbiosreason = inb(CMOS_DATA);
984263bc 2062
984263bc
MD
2063 /* set up temporary P==V mapping for AP boot */
2064 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2065 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2066 for (x = 0; x < NKPT; x++) {
984263bc
MD
2067 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2068 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2069 }
0f7a3396 2070 cpu_invltlb();
984263bc
MD
2071
2072 /* start each AP */
2073 for (x = 1; x <= mp_naps; ++x) {
2074
2075 /* This is a bit verbose, it will go away soon. */
2076
2077 /* first page of AP's private space */
2078 pg = x * i386_btop(sizeof(struct privatespace));
2079
81c04d07 2080 /* allocate new private data page(s) */
e4846942 2081 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2082 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2083 /* wire it into the private page table page */
81c04d07
MD
2084 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2085 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2086 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2087 }
2088 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2089
2090 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2091 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2092 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2093 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
2094
2095 /* allocate and set up an idle stack data page */
e4846942 2096 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2097 for (i = 0; i < UPAGES; i++) {
81c04d07 2098 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2099 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2100 }
984263bc 2101
8a8d5d85
MD
2102 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2103 bzero(gd, sizeof(*gd));
0f7a3396 2104 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2105
984263bc 2106 /* prime data page for it to use */
8a8d5d85 2107 mi_gdinit(&gd->mi, x);
8ad65e08 2108 cpu_gdinit(gd, x);
81c04d07
MD
2109 gd->gd_CMAP1 = &SMPpt[pg + 0];
2110 gd->gd_CMAP2 = &SMPpt[pg + 1];
2111 gd->gd_CMAP3 = &SMPpt[pg + 2];
2112 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
2113 gd->gd_CADDR1 = ps->CPAGE1;
2114 gd->gd_CADDR2 = ps->CPAGE2;
2115 gd->gd_CADDR3 = ps->CPAGE3;
2116 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
e4846942 2117 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2118 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc
MD
2119
2120 /* setup a vector to our boot code */
2121 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2122 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
984263bc
MD
2123 outb(CMOS_REG, BIOS_RESET);
2124 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
984263bc 2125
8a8d5d85
MD
2126 /*
2127 * Setup the AP boot stack
2128 */
0f7a3396 2129 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2130 bootAP = x;
2131
2132 /* attempt to start the Application Processor */
2133 CHECK_INIT(99); /* setup checkpoints */
0f7a3396 2134 if (!start_ap(gd, boot_addr)) {
26be20a0 2135 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
2136 CHECK_PRINT("trace"); /* show checkpoints */
2137 /* better panic as the AP may be running loose */
26be20a0 2138 kprintf("panic y/n? [y] ");
984263bc
MD
2139 if (cngetc() != 'n')
2140 panic("bye-bye");
2141 }
2142 CHECK_PRINT("trace"); /* show checkpoints */
2143
2144 /* record its version info */
2145 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD
2146 }
2147
0f7a3396
MD
2148 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2149 ncpus = x;
2150
b45759e1
MD
2151 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2152 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2153 ;
2154 --shift;
2155 ncpus2_shift = shift;
2156 ncpus2 = 1 << shift;
90100055
JH
2157 ncpus2_mask = ncpus2 - 1;
2158
b45759e1
MD
2159 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2160 if ((1 << shift) < ncpus)
2161 ++shift;
2162 ncpus_fit = 1 << shift;
2163 ncpus_fit_mask = ncpus_fit - 1;
2164
984263bc 2165 /* build our map of 'other' CPUs */
0f7a3396 2166 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2167 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2168 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2169
2170 /* fill in our (BSP) APIC version */
2171 cpu_apic_versions[0] = lapic.version;
2172
2173 /* restore the warmstart vector */
2174 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
2175 outb(CMOS_REG, BIOS_RESET);
2176 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
2177
2178 /*
8a8d5d85
MD
2179 * NOTE! The idlestack for the BSP was setup by locore. Finish
2180 * up, clean out the P==V mapping we did earlier.
984263bc 2181 */
984263bc
MD
2182 for (x = 0; x < NKPT; x++)
2183 PTD[x] = 0;
2184 pmap_set_opt();
2185
2186 /* number of APs actually started */
8a8d5d85 2187 return ncpus - 1;
984263bc
MD
2188}
2189
2190
2191/*
2192 * load the 1st level AP boot code into base memory.
2193 */
2194
2195/* targets for relocation */
2196extern void bigJump(void);
2197extern void bootCodeSeg(void);
2198extern void bootDataSeg(void);
2199extern void MPentry(void);
2200extern u_int MP_GDT;
2201extern u_int mp_gdtbase;
2202
2203static void
2204install_ap_tramp(u_int boot_addr)
2205{
2206 int x;
2207 int size = *(int *) ((u_long) & bootMP_size);
2208 u_char *src = (u_char *) ((u_long) bootMP);
2209 u_char *dst = (u_char *) boot_addr + KERNBASE;
2210 u_int boot_base = (u_int) bootMP;
2211 u_int8_t *dst8;
2212 u_int16_t *dst16;
2213 u_int32_t *dst32;
2214
2215 POSTCODE(INSTALL_AP_TRAMP_POST);
2216
2217 for (x = 0; x < size; ++x)
2218 *dst++ = *src++;
2219
2220 /*
2221 * modify addresses in code we just moved to basemem. unfortunately we
2222 * need fairly detailed info about mpboot.s for this to work. changes
2223 * to mpboot.s might require changes here.
2224 */
2225
2226 /* boot code is located in KERNEL space */
2227 dst = (u_char *) boot_addr + KERNBASE;
2228
2229 /* modify the lgdt arg */
2230 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2231 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2232
2233 /* modify the ljmp target for MPentry() */
2234 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2235 *dst32 = ((u_int) MPentry - KERNBASE);
2236
2237 /* modify the target for boot code segment */
2238 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2239 dst8 = (u_int8_t *) (dst16 + 1);
2240 *dst16 = (u_int) boot_addr & 0xffff;
2241 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2242
2243 /* modify the target for boot data segment */
2244 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2245 dst8 = (u_int8_t *) (dst16 + 1);
2246 *dst16 = (u_int) boot_addr & 0xffff;
2247 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2248}
2249
2250
2251/*
2252 * this function starts the AP (application processor) identified
2253 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2254 * to accomplish this. This is necessary because of the nuances
2255 * of the different hardware we might encounter. It ain't pretty,
2256 * but it seems to work.
a108bf71
MD
2257 *
2258 * NOTE: eventually an AP gets to ap_init(), which is called just
2259 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
2260 */
2261static int
0f7a3396 2262start_ap(struct mdglobaldata *gd, u_int boot_addr)
984263bc
MD
2263{
2264 int physical_cpu;
2265 int vector;
984263bc
MD
2266 u_long icr_lo, icr_hi;
2267
2268 POSTCODE(START_AP_POST);
2269
2270 /* get the PHYSICAL APIC ID# */
0f7a3396 2271 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
2272
2273 /* calculate the vector */
2274 vector = (boot_addr >> 12) & 0xff;
2275
8a8d5d85
MD
2276 /* Make sure the target cpu sees everything */
2277 wbinvd();
984263bc
MD
2278
2279 /*
2280 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2281 * and running the target CPU. OR this INIT IPI might be latched (P5
2282 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2283 * ignored.
2284 */
2285
2286 /* setup the address for the target AP */
2287 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2288 icr_hi |= (physical_cpu << 24);
2289 lapic.icr_hi = icr_hi;
2290
2291 /* do an INIT IPI: assert RESET */
2292 icr_lo = lapic.icr_lo & 0xfff00000;
2293 lapic.icr_lo = icr_lo | 0x0000c500;
2294
2295 /* wait for pending status end */
2296 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2297 /* spin */ ;
2298
2299 /* do an INIT IPI: deassert RESET */
2300 lapic.icr_lo = icr_lo | 0x00008500;
2301
2302 /* wait for pending status end */
2303 u_sleep(10000); /* wait ~10mS */
2304 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2305 /* spin */ ;
2306
2307 /*
2308 * next we do a STARTUP IPI: the previous INIT IPI might still be
2309 * latched, (P5 bug) this 1st STARTUP would then terminate
2310 * immediately, and the previously started INIT IPI would continue. OR
2311 * the previous INIT IPI has already run. and this STARTUP IPI will
2312 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2313 * will run.
2314 */
2315
2316 /* do a STARTUP IPI */
2317 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2318 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2319 /* spin */ ;
2320 u_sleep(200); /* wait ~200uS */
2321
2322 /*
2323 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2324 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2325 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2326 * recognized after hardware RESET or INIT IPI.
2327 */
2328
2329 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2330 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2331 /* spin */ ;
2332 u_sleep(200); /* wait ~200uS */
2333
8a8d5d85 2334 /* wait for it to start, see ap_init() */
984263bc 2335 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2336 while (read_apic_timer()) {
0f7a3396 2337 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2338 return 1; /* return SUCCESS */
8a8d5d85 2339 }
984263bc
MD
2340 return 0; /* return FAILURE */
2341}
2342
2343
2344/*
0f7a3396 2345 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2346 *
0f7a3396
MD
2347 * If for some reason we were unable to start all cpus we cannot safely
2348 * use broadcast IPIs.
984263bc
MD
2349 */
2350void
2351smp_invltlb(void)
2352{
97359a5b 2353#ifdef SMP
0f7a3396 2354 if (smp_startup_mask == smp_active_mask) {
984263bc 2355 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396
MD
2356 } else {
2357 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2358 APIC_DELMODE_FIXED);
2359 }
97359a5b 2360#endif
984263bc
MD
2361}
2362
984263bc
MD
2363/*
2364 * When called the executing CPU will send an IPI to all other CPUs
2365 * requesting that they halt execution.
2366 *
2367 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2368 *
2369 * - Signals all CPUs in map to stop.
2370 * - Waits for each to stop.
2371 *
2372 * Returns:
2373 * -1: error
2374 * 0: NA
2375 * 1: ok
2376 *
2377 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2378 * from executing at same time.
2379 */
2380int
2381stop_cpus(u_int map)
2382{
0f7a3396 2383 map &= smp_active_mask;
984263bc
MD
2384
2385 /* send the Xcpustop IPI to all CPUs in map */
2386 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2387
2388 while ((stopped_cpus & map) != map)
2389 /* spin */ ;
2390
2391 return 1;
2392}
2393
2394
2395/*
2396 * Called by a CPU to restart stopped CPUs.
2397 *
2398 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2399 *
2400 * - Signals all CPUs in map to restart.
2401 * - Waits for each to restart.
2402 *
2403 * Returns:
2404 * -1: error
2405 * 0: NA
2406 * 1: ok
2407 */
2408int
2409restart_cpus(u_int map)
2410{
0f7a3396
MD
2411 /* signal other cpus to restart */
2412 started_cpus = map & smp_active_mask;
984263bc
MD
2413
2414 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2415 /* spin */ ;
2416
2417 return 1;
2418}
2419
984263bc 2420/*
8a8d5d85
MD
2421 * This is called once the mpboot code has gotten us properly relocated
2422 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2423 * and when it returns the scheduler will call the real cpu_idle() main
2424 * loop for the idlethread. Interrupts are disabled on entry and should
2425 * remain disabled at return.
984263bc 2426 */
984263bc 2427void
8a8d5d85 2428ap_init(void)
984263bc
MD
2429{
2430 u_int apic_id;
2431
8a8d5d85 2432 /*
0f7a3396
MD
2433 * Adjust smp_startup_mask to signal the BSP that we have started
2434 * up successfully. Note that we do not yet hold the BGL. The BSP
2435 * is waiting for our signal.
2436 *
2437 * We can't set our bit in smp_active_mask yet because we are holding
2438 * interrupts physically disabled and remote cpus could deadlock
2439 * trying to send us an IPI.
8a8d5d85 2440 */
0f7a3396 2441 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2442 cpu_mfence();
8a8d5d85
MD
2443
2444 /*
41a01a4d
MD
2445 * Interlock for finalization. Wait until mp_finish is non-zero,
2446 * then get the MP lock.
2447 *
2448 * Note: We are in a critical section.
2449 *
2450 * Note: We have to synchronize td_mpcount to our desired MP state
2451 * before calling cpu_try_mplock().
2452 *
2453 * Note: we are the idle thread, we can only spin.
2454 *
35238fa5
MD
2455 * Note: The load fence is memory volatile and prevents the compiler
2456 * from improperly caching mp_finish, and the cpu from improperly
2457 * caching it.
8a8d5d85 2458 */
41a01a4d 2459 while (mp_finish == 0)
35238fa5 2460 cpu_lfence();
d9ebdce5 2461 ++curthread->td_mpcount;
8a8d5d85
MD
2462 while (cpu_try_mplock() == 0)
2463 ;
2464
374133e3
MD
2465 if (cpu_feature & CPUID_TSC) {
2466 /*
2467 * The BSP is constantly updating tsc0_offset, figure out the
2468 * relative difference to synchronize ktrdump.
2469 */
2470 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2471 }
2472
984263bc
MD
2473 /* BSP may have changed PTD while we're waiting for the lock */
2474 cpu_invltlb();
2475
984263bc
MD
2476#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2477 lidt(&r_idt);
2478#endif
2479
2480 /* Build our map of 'other' CPUs. */
0f7a3396 2481 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2482
26be20a0 2483 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2484
984263bc
MD
2485 /* A quick check from sanity claus */
2486 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2487 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
2488 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2489 kprintf("SMP: apic_id = %d\n", apic_id);
2490 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
2491 panic("cpuid mismatch! boom!!");
2492 }
2493
b52c8db0
SZ
2494 /* Initialize AP's local APIC for irq's */
2495 apic_initialize(FALSE);
984263bc
MD
2496
2497 /* Set memory range attributes for this CPU to match the BSP */
2498 mem_range_AP_init();
2499
a2a5ad0d 2500 /*
4c9f5a7f
MD
2501 * Once we go active we must process any IPIQ messages that may
2502 * have been queued, because no actual IPI will occur until we
2503 * set our bit in the smp_active_mask. If we don't the IPI
2504 * message interlock could be left set which would also prevent
2505 * further IPIs.
2506 *
8a8d5d85
MD
2507 * The idle loop doesn't expect the BGL to be held and while
2508 * lwkt_switch() normally cleans things up this is a special case
2509 * because we returning almost directly into the idle loop.
41a01a4d
MD
2510 *
2511 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2512 * nothing we've done put it there.
8a8d5d85 2513 */
96728c05 2514 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2515 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD
2516
2517 /*
2518 * Enable interrupts here. idle_restore will also do it, but
2519 * doing it here lets us clean up any strays that got posted to
2520 * the CPU during the AP boot while we are still in a critical
2521 * section.
2522 */
2523 __asm __volatile("sti; pause; pause"::);
2524 mdcpu->gd_fpending = 0;
2525 mdcpu->gd_ipending = 0;
2526
4a19580d 2527 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2528 lwkt_process_ipiq();
d19f6edf
MD
2529
2530 /*
2531 * Releasing the mp lock lets the BSP finish up the SMP init
2532 */
96728c05 2533 rel_mplock();
41a01a4d 2534 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
2535}
2536
41a01a4d
MD
2537/*
2538 * Get SMP fully working before we start initializing devices.
2539 */
2540static
2541void
2542ap_finish(void)
2543{
2544 mp_finish = 1;
2545 if (bootverbose)
26be20a0 2546 kprintf("Finish MP startup\n");
374133e3
MD
2547 if (cpu_feature & CPUID_TSC)
2548 tsc0_offset = rdtsc();
2549 tsc_offsets[0] = 0;
41a01a4d 2550 rel_mplock();
374133e3 2551 while (smp_active_mask != smp_startup_mask) {
35238fa5 2552 cpu_lfence();
374133e3
MD
2553 if (cpu_feature & CPUID_TSC)
2554 tsc0_offset = rdtsc();
2555 }
4da43e1f 2556 while (try_mplock() == 0)
41a01a4d
MD
2557 ;
2558 if (bootverbose)
26be20a0 2559 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
2560}
2561
ba39e2e0 2562SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2563
96728c05
MD
2564void
2565cpu_send_ipiq(int dcpu)
2566{
41a01a4d
MD
2567 if ((1 << dcpu) & smp_active_mask)
2568 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2569}
41a01a4d
MD
2570
2571#if 0 /* single_apic_ipi_passive() not working yet */
2572/*
2573 * Returns 0 on failure, 1 on success
2574 */
2575int
2576cpu_send_ipiq_passive(int dcpu)
2577{
2578 int r = 0;
2579 if ((1 << dcpu) & smp_active_mask) {
2580 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2581 APIC_DELMODE_FIXED);
2582 }
2583 return(r);
2584}
2585#endif
2586