em: Pack boolean fields into flags
[dragonfly.git] / sys / dev / netif / em / if_em.c
CommitLineData
78195a76 1/*
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2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
9c80d176 4 * Copyright (c) 2001-2008, Intel Corporation
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5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
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10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
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13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
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17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
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36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
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39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
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43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
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53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
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66 */
67/*
68 * SERIALIZATION API RULES:
69 *
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
9c80d176 72 * driver.
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73 *
74 * - ifmedia entry points will be serialized by the ifmedia code using the
75 * ifnet serializer.
76 *
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
79 *
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
82 *
83 * - The device driver typically holds the serializer at the time it wishes
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84 * to call if_input.
85 *
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
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90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
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95
96#include "opt_polling.h"
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97
98#include <sys/param.h>
99#include <sys/bus.h>
100#include <sys/endian.h>
9db4b353 101#include <sys/interrupt.h>
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102#include <sys/kernel.h>
103#include <sys/ktr.h>
104#include <sys/malloc.h>
105#include <sys/mbuf.h>
9c80d176 106#include <sys/proc.h>
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107#include <sys/rman.h>
108#include <sys/serialize.h>
109#include <sys/socket.h>
110#include <sys/sockio.h>
111#include <sys/sysctl.h>
9c80d176 112#include <sys/systm.h>
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113
114#include <net/bpf.h>
115#include <net/ethernet.h>
116#include <net/if.h>
117#include <net/if_arp.h>
118#include <net/if_dl.h>
119#include <net/if_media.h>
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120#include <net/ifq_var.h>
121#include <net/vlan/if_vlan_var.h>
b637f170 122#include <net/vlan/if_vlan_ether.h>
87307ba1 123
87307ba1 124#include <netinet/in_systm.h>
9c80d176 125#include <netinet/in.h>
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126#include <netinet/ip.h>
127#include <netinet/tcp.h>
128#include <netinet/udp.h>
984263bc 129
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130#include <bus/pci/pcivar.h>
131#include <bus/pci/pcireg.h>
984263bc 132
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133#include <dev/netif/ig_hal/e1000_api.h>
134#include <dev/netif/ig_hal/e1000_82571.h>
135#include <dev/netif/em/if_em.h>
984263bc 136
9c80d176 137#define EM_NAME "Intel(R) PRO/1000 Network Connection "
6d5e2922 138#define EM_VER " 7.2.4"
9c80d176 139
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140#define _EM_DEVICE(id, ret) \
141 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
142#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
143#define EM_DEVICE(id) _EM_DEVICE(id, 0)
144#define EM_DEVICE_NULL { 0, 0, 0, NULL }
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145
146static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM),
148 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP),
150 EM_DEVICE(82540EP_LOM),
151 EM_DEVICE(82540EP_LP),
152
153 EM_DEVICE(82541EI),
154 EM_DEVICE(82541ER),
155 EM_DEVICE(82541ER_LOM),
156 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI),
158 EM_DEVICE(82541GI_LF),
159 EM_DEVICE(82541GI_MOBILE),
160
161 EM_DEVICE(82542),
162
163 EM_DEVICE(82543GC_FIBER),
164 EM_DEVICE(82543GC_COPPER),
165
166 EM_DEVICE(82544EI_COPPER),
167 EM_DEVICE(82544EI_FIBER),
168 EM_DEVICE(82544GC_COPPER),
169 EM_DEVICE(82544GC_LOM),
170
171 EM_DEVICE(82545EM_COPPER),
172 EM_DEVICE(82545EM_FIBER),
173 EM_DEVICE(82545GM_COPPER),
174 EM_DEVICE(82545GM_FIBER),
175 EM_DEVICE(82545GM_SERDES),
176
177 EM_DEVICE(82546EB_COPPER),
178 EM_DEVICE(82546EB_FIBER),
179 EM_DEVICE(82546EB_QUAD_COPPER),
180 EM_DEVICE(82546GB_COPPER),
181 EM_DEVICE(82546GB_FIBER),
182 EM_DEVICE(82546GB_SERDES),
183 EM_DEVICE(82546GB_PCIE),
184 EM_DEVICE(82546GB_QUAD_COPPER),
185 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186
187 EM_DEVICE(82547EI),
188 EM_DEVICE(82547EI_MOBILE),
189 EM_DEVICE(82547GI),
190
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191 EM_EMX_DEVICE(82571EB_COPPER),
192 EM_EMX_DEVICE(82571EB_FIBER),
193 EM_EMX_DEVICE(82571EB_SERDES),
194 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
195 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
199 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
200 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201
202 EM_EMX_DEVICE(82572EI_COPPER),
203 EM_EMX_DEVICE(82572EI_FIBER),
204 EM_EMX_DEVICE(82572EI_SERDES),
205 EM_EMX_DEVICE(82572EI),
206
207 EM_EMX_DEVICE(82573E),
208 EM_EMX_DEVICE(82573E_IAMT),
209 EM_EMX_DEVICE(82573L),
210
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211 EM_DEVICE(82583V),
212
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213 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
215 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
216 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
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217
218 EM_DEVICE(ICH8_IGP_M_AMT),
219 EM_DEVICE(ICH8_IGP_AMT),
220 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE),
222 EM_DEVICE(ICH8_IFE_GT),
223 EM_DEVICE(ICH8_IFE_G),
224 EM_DEVICE(ICH8_IGP_M),
2d0e5700 225 EM_DEVICE(ICH8_82567V_3),
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226
227 EM_DEVICE(ICH9_IGP_M_AMT),
228 EM_DEVICE(ICH9_IGP_AMT),
229 EM_DEVICE(ICH9_IGP_C),
230 EM_DEVICE(ICH9_IGP_M),
231 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE),
233 EM_DEVICE(ICH9_IFE_GT),
234 EM_DEVICE(ICH9_IFE_G),
235 EM_DEVICE(ICH9_BM),
236
96ced48a 237 EM_EMX_DEVICE(82574L),
2d0e5700 238 EM_EMX_DEVICE(82574LA),
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239
240 EM_DEVICE(ICH10_R_BM_LM),
241 EM_DEVICE(ICH10_R_BM_LF),
242 EM_DEVICE(ICH10_R_BM_V),
243 EM_DEVICE(ICH10_D_BM_LM),
244 EM_DEVICE(ICH10_D_BM_LF),
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245 EM_DEVICE(ICH10_D_BM_V),
246
247 EM_DEVICE(PCH_M_HV_LM),
248 EM_DEVICE(PCH_M_HV_LC),
249 EM_DEVICE(PCH_D_HV_DM),
250 EM_DEVICE(PCH_D_HV_DC),
251
252 EM_DEVICE(PCH2_LV_LM),
253 EM_DEVICE(PCH2_LV_V),
984263bc 254
f647ad3d 255 /* required last entry */
9c80d176 256 EM_DEVICE_NULL
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257};
258
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259static int em_probe(device_t);
260static int em_attach(device_t);
261static int em_detach(device_t);
262static int em_shutdown(device_t);
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263static int em_suspend(device_t);
264static int em_resume(device_t);
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265
266static void em_init(void *);
267static void em_stop(struct adapter *);
f647ad3d 268static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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269static void em_start(struct ifnet *);
270#ifdef DEVICE_POLLING
271static void em_poll(struct ifnet *, enum poll_cmd, int);
272#endif
f647ad3d 273static void em_watchdog(struct ifnet *);
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274static void em_media_status(struct ifnet *, struct ifmediareq *);
275static int em_media_change(struct ifnet *);
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276static void em_timer(void *);
277
278static void em_intr(void *);
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279static void em_intr_mask(void *);
280static void em_intr_body(struct adapter *, boolean_t);
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281static void em_rxeof(struct adapter *, int);
282static void em_txeof(struct adapter *);
9f60d74b 283static void em_tx_collect(struct adapter *);
9c80d176 284static void em_tx_purge(struct adapter *);
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285static void em_enable_intr(struct adapter *);
286static void em_disable_intr(struct adapter *);
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287
288static int em_dma_malloc(struct adapter *, bus_size_t,
289 struct em_dma_alloc *);
290static void em_dma_free(struct adapter *, struct em_dma_alloc *);
291static void em_init_tx_ring(struct adapter *);
292static int em_init_rx_ring(struct adapter *);
293static int em_create_tx_ring(struct adapter *);
294static int em_create_rx_ring(struct adapter *);
295static void em_destroy_tx_ring(struct adapter *, int);
296static void em_destroy_rx_ring(struct adapter *, int);
297static int em_newbuf(struct adapter *, int, int);
298static int em_encap(struct adapter *, struct mbuf **);
299static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
300 struct mbuf *);
002b3a05 301static int em_txcsum_pullup(struct adapter *, struct mbuf **);
9f60d74b 302static int em_txcsum(struct adapter *, struct mbuf *,
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303 uint32_t *, uint32_t *);
304
305static int em_get_hw_info(struct adapter *);
306static int em_is_valid_eaddr(const uint8_t *);
307static int em_alloc_pci_res(struct adapter *);
308static void em_free_pci_res(struct adapter *);
2d0e5700 309static int em_reset(struct adapter *);
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310static void em_setup_ifp(struct adapter *);
311static void em_init_tx_unit(struct adapter *);
312static void em_init_rx_unit(struct adapter *);
313static void em_update_stats(struct adapter *);
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314static void em_set_promisc(struct adapter *);
315static void em_disable_promisc(struct adapter *);
316static void em_set_multi(struct adapter *);
87307ba1 317static void em_update_link_status(struct adapter *);
f647ad3d 318static void em_smartspeed(struct adapter *);
2d0e5700 319static void em_set_itr(struct adapter *, uint32_t);
6d5e2922 320static void em_disable_aspm(struct adapter *);
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321
322/* Hardware workarounds */
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323static int em_82547_fifo_workaround(struct adapter *, int);
324static void em_82547_update_fifo_head(struct adapter *, int);
325static int em_82547_tx_fifo_reset(struct adapter *);
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326static void em_82547_move_tail(void *);
327static void em_82547_move_tail_serialized(struct adapter *);
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328static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
329
f647ad3d 330static void em_print_debug_info(struct adapter *);
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331static void em_print_nvm_info(struct adapter *);
332static void em_print_hw_stats(struct adapter *);
333
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334static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
335static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 336static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 337static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 338static void em_add_sysctl(struct adapter *adapter);
984263bc 339
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340/* Management and WOL Support */
341static void em_get_mgmt(struct adapter *);
342static void em_rel_mgmt(struct adapter *);
343static void em_get_hw_control(struct adapter *);
344static void em_rel_hw_control(struct adapter *);
345static void em_enable_wol(device_t);
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346
347static device_method_t em_methods[] = {
348 /* Device interface */
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349 DEVMETHOD(device_probe, em_probe),
350 DEVMETHOD(device_attach, em_attach),
351 DEVMETHOD(device_detach, em_detach),
352 DEVMETHOD(device_shutdown, em_shutdown),
353 DEVMETHOD(device_suspend, em_suspend),
354 DEVMETHOD(device_resume, em_resume),
355 { 0, 0 }
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356};
357
358static driver_t em_driver = {
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359 "em",
360 em_methods,
361 sizeof(struct adapter),
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362};
363
364static devclass_t em_devclass;
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365
366DECLARE_DUMMY_MODULE(if_em);
9c80d176 367MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 368DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 369
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370/*
371 * Tunables
372 */
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373static int em_int_throttle_ceil = EM_DEFAULT_ITR;
374static int em_rxd = EM_DEFAULT_RXD;
375static int em_txd = EM_DEFAULT_TXD;
053f3ae6 376static int em_smart_pwr_down = 0;
0d366ee7 377
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378/* Controls whether promiscuous also shows bad packets */
379static int em_debug_sbp = FALSE;
0d366ee7 380
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381static int em_82573_workaround = 1;
382static int em_msi_enable = 1;
05580856 383
d0870c72 384TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
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385TUNABLE_INT("hw.em.rxd", &em_rxd);
386TUNABLE_INT("hw.em.txd", &em_txd);
387TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 388TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 389TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
053f3ae6 390TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
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391
392/* Global used in WOL setup with multiport cards */
393static int em_global_quad_port_a = 0;
394
395/* Set this to one to display debug statistics */
396static int em_display_debug_stats = 0;
0d366ee7 397
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398#if !defined(KTR_IF_EM)
399#define KTR_IF_EM KTR_ALL
400#endif
401KTR_INFO_MASTER(if_em);
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402KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
403KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
404KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
405KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
406KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
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407#define logif(name) KTR_LOG(if_em_ ## name)
408
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409static int
410em_probe(device_t dev)
411{
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412 const struct em_vendor_info *ent;
413 uint16_t vid, did;
984263bc 414
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415 vid = pci_get_vendor(dev);
416 did = pci_get_device(dev);
984263bc 417
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418 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
419 if (vid == ent->vendor_id && did == ent->device_id) {
420 device_set_desc(dev, ent->desc);
dbcd0c9b 421 device_set_async_attach(dev, TRUE);
96ced48a 422 return (ent->ret);
984263bc 423 }
984263bc 424 }
87307ba1 425 return (ENXIO);
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426}
427
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428static int
429em_attach(device_t dev)
430{
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431 struct adapter *adapter = device_get_softc(dev);
432 struct ifnet *ifp = &adapter->arpcom.ac_if;
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433 int tsize, rsize;
434 int error = 0;
2d0e5700 435 uint16_t eeprom_data, device_id, apme_mask;
87ab432b 436 driver_intr_t *intr_func;
984263bc 437
9c80d176 438 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 439
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440 callout_init_mp(&adapter->timer);
441 callout_init_mp(&adapter->tx_fifo_timer);
af82d4bb 442
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443 /* Determine hardware and mac info */
444 error = em_get_hw_info(adapter);
445 if (error) {
446 device_printf(dev, "Identify hardware failed\n");
447 goto fail;
f647ad3d
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448 }
449
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450 /* Setup PCI resources */
451 error = em_alloc_pci_res(adapter);
452 if (error) {
453 device_printf(dev, "Allocation of PCI resources failed\n");
454 goto fail;
455 }
984263bc 456
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457 /*
458 * For ICH8 and family we need to map the flash memory,
459 * and this must happen after the MAC is identified.
460 */
461 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 462 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 463 adapter->hw.mac.type == e1000_ich10lan ||
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464 adapter->hw.mac.type == e1000_pchlan ||
465 adapter->hw.mac.type == e1000_pch2lan) {
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466 adapter->flash_rid = EM_BAR_FLASH;
467
468 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &adapter->flash_rid, RF_ACTIVE);
470 if (adapter->flash == NULL) {
471 device_printf(dev, "Mapping of Flash failed\n");
472 error = ENXIO;
473 goto fail;
474 }
475 adapter->osdep.flash_bus_space_tag =
476 rman_get_bustag(adapter->flash);
477 adapter->osdep.flash_bus_space_handle =
478 rman_get_bushandle(adapter->flash);
984263bc 479
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480 /*
481 * This is used in the shared code
482 * XXX this goof is actually not used.
483 */
484 adapter->hw.flash_address = (uint8_t *)adapter->flash;
485 }
0d366ee7 486
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487 /* Do Shared Code initialization */
488 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
489 device_printf(dev, "Setup of Shared code failed\n");
490 error = ENXIO;
491 goto fail;
f647ad3d 492 }
7ea52455 493
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494 e1000_get_bus_info(&adapter->hw);
495
1eca7b82 496 /*
9c80d176 497 * Validate number of transmit and receive descriptors. It
1eca7b82 498 * must not exceed hardware maximum, and must be multiple
9c80d176 499 * of E1000_DBA_ALIGN.
1eca7b82 500 */
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501 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
502 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
503 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
504 em_txd < EM_MIN_TXD) {
1eca7b82 505 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
9c80d176 506 EM_DEFAULT_TXD, em_txd);
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507 adapter->num_tx_desc = EM_DEFAULT_TXD;
508 } else {
509 adapter->num_tx_desc = em_txd;
510 }
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511 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
512 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
513 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
514 em_rxd < EM_MIN_RXD) {
1eca7b82 515 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
9c80d176 516 EM_DEFAULT_RXD, em_rxd);
1eca7b82
SZ
517 adapter->num_rx_desc = EM_DEFAULT_RXD;
518 } else {
519 adapter->num_rx_desc = em_rxd;
520 }
521
9c80d176
SZ
522 adapter->hw.mac.autoneg = DO_AUTO_NEG;
523 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
524 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
525 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 526
9c80d176
SZ
527 /*
528 * Interrupt throttle rate
529 */
530 if (em_int_throttle_ceil == 0) {
531 adapter->int_throttle_ceil = 0;
532 } else {
533 int throttle = em_int_throttle_ceil;
f647ad3d 534
9c80d176
SZ
535 if (throttle < 0)
536 throttle = EM_DEFAULT_ITR;
0d366ee7 537
9c80d176
SZ
538 /* Recalculate the tunable value to get the exact frequency. */
539 throttle = 1000000000 / 256 / throttle;
664c7645
SZ
540
541 /* Upper 16bits of ITR is reserved and should be zero */
542 if (throttle & 0xffff0000)
543 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
544
9c80d176
SZ
545 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
546 }
984263bc 547
9c80d176
SZ
548 e1000_init_script_state_82541(&adapter->hw, TRUE);
549 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
550
551 /* Copper options */
552 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
553 adapter->hw.phy.mdix = AUTO_ALL_MODES;
554 adapter->hw.phy.disable_polarity_correction = FALSE;
555 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
556 }
557
558 /* Set the frame limits assuming standard ethernet sized frames. */
559 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
560 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 561
9c80d176
SZ
562 /* This controls when hardware reports transmit completion status. */
563 adapter->hw.mac.report_tx_early = 1;
984263bc 564
87307ba1 565 /*
9c80d176 566 * Create top level busdma tag
984263bc 567 */
9c80d176
SZ
568 error = bus_dma_tag_create(NULL, 1, 0,
569 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
570 NULL, NULL,
571 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
572 0, &adapter->parent_dtag);
573 if (error) {
574 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 575 goto fail;
9c80d176 576 }
af82d4bb 577
9c80d176
SZ
578 /*
579 * Allocate Transmit Descriptor ring
580 */
581 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 582 EM_DBA_ALIGN);
87307ba1
SZ
583 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
584 if (error) {
9c80d176 585 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 586 goto fail;
984263bc 587 }
9c80d176 588 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 589
9c80d176
SZ
590 /*
591 * Allocate Receive Descriptor ring
592 */
593 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 594 EM_DBA_ALIGN);
87307ba1
SZ
595 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
596 if (error) {
9ccd8c1f 597 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 598 goto fail;
984263bc 599 }
9c80d176
SZ
600 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
601
2d0e5700
SZ
602 /* Allocate multicast array memory. */
603 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
604 M_DEVBUF, M_WAITOK);
605
606 /* Indicate SOL/IDER usage */
607 if (e1000_check_reset_block(&adapter->hw)) {
608 device_printf(dev,
609 "PHY reset is blocked due to SOL/IDER session.\n");
610 }
611
612 /*
613 * Start from a known state, this is important in reading the
614 * nvm and mac from that.
615 */
616 e1000_reset_hw(&adapter->hw);
617
9c80d176
SZ
618 /* Make sure we have a good EEPROM before we read from it */
619 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
620 /*
621 * Some PCI-E parts fail the first check due to
622 * the link being in sleep state, call it again,
623 * if it fails a second time its a real issue.
624 */
625 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
626 device_printf(dev,
627 "The EEPROM Checksum Is Not Valid\n");
628 error = EIO;
629 goto fail;
630 }
631 }
984263bc 632
984263bc 633 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ
634 if (e1000_read_mac_addr(&adapter->hw) < 0) {
635 device_printf(dev, "EEPROM read error while reading MAC"
636 " address\n");
984263bc 637 error = EIO;
af82d4bb 638 goto fail;
984263bc 639 }
9c80d176 640 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 641 device_printf(dev, "Invalid MAC address\n");
984263bc 642 error = EIO;
af82d4bb 643 goto fail;
984263bc
MD
644 }
645
9c80d176
SZ
646 /* Allocate transmit descriptors and buffers */
647 error = em_create_tx_ring(adapter);
648 if (error) {
649 device_printf(dev, "Could not setup transmit structures\n");
650 goto fail;
651 }
652
653 /* Allocate receive descriptors and buffers */
654 error = em_create_rx_ring(adapter);
655 if (error) {
656 device_printf(dev, "Could not setup receive structures\n");
657 goto fail;
658 }
659
660 /* Manually turn off all interrupts */
661 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
662
9c80d176 663 /* Determine if we have to control management hardware */
79878f87
SZ
664 if (e1000_enable_mng_pass_thru(&adapter->hw))
665 adapter->flags |= EM_FLAG_HAS_MGMT;
9c80d176
SZ
666
667 /*
668 * Setup Wake-on-Lan
669 */
2d0e5700
SZ
670 apme_mask = EM_EEPROM_APME;
671 eeprom_data = 0;
9c80d176
SZ
672 switch (adapter->hw.mac.type) {
673 case e1000_82542:
674 case e1000_82543:
675 break;
676
2d0e5700
SZ
677 case e1000_82573:
678 case e1000_82583:
79878f87 679 adapter->flags |= EM_FLAG_HAS_AMT;
2d0e5700
SZ
680 /* FALL THROUGH */
681
9c80d176
SZ
682 case e1000_82546:
683 case e1000_82546_rev_3:
684 case e1000_82571:
2d0e5700 685 case e1000_82572:
9c80d176
SZ
686 case e1000_80003es2lan:
687 if (adapter->hw.bus.func == 1) {
688 e1000_read_nvm(&adapter->hw,
689 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
690 } else {
691 e1000_read_nvm(&adapter->hw,
692 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
693 }
2d0e5700
SZ
694 break;
695
696 case e1000_ich8lan:
697 case e1000_ich9lan:
698 case e1000_ich10lan:
699 case e1000_pchlan:
700 case e1000_pch2lan:
701 apme_mask = E1000_WUC_APME;
79878f87 702 adapter->flags |= EM_FLAG_HAS_AMT;
2d0e5700 703 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ
704 break;
705
706 default:
2d0e5700
SZ
707 e1000_read_nvm(&adapter->hw,
708 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ
709 break;
710 }
2d0e5700
SZ
711 if (eeprom_data & apme_mask)
712 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
713
9c80d176
SZ
714 /*
715 * We have the eeprom settings, now apply the special cases
716 * where the eeprom may be wrong or the board won't support
717 * wake on lan on a particular port
718 */
719 device_id = pci_get_device(dev);
720 switch (device_id) {
721 case E1000_DEV_ID_82546GB_PCIE:
722 adapter->wol = 0;
723 break;
724
725 case E1000_DEV_ID_82546EB_FIBER:
726 case E1000_DEV_ID_82546GB_FIBER:
727 case E1000_DEV_ID_82571EB_FIBER:
728 /*
729 * Wake events only supported on port A for dual fiber
730 * regardless of eeprom setting
731 */
732 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
733 E1000_STATUS_FUNC_1)
734 adapter->wol = 0;
735 break;
736
737 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
738 case E1000_DEV_ID_82571EB_QUAD_COPPER:
739 case E1000_DEV_ID_82571EB_QUAD_FIBER:
740 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
741 /* if quad port adapter, disable WoL on all but port A */
742 if (em_global_quad_port_a != 0)
743 adapter->wol = 0;
744 /* Reset for multiple quad port adapters */
745 if (++em_global_quad_port_a == 4)
746 em_global_quad_port_a = 0;
747 break;
748 }
749
750 /* XXX disable wol */
751 adapter->wol = 0;
752
2d0e5700
SZ
753 /* Setup OS specific network interface */
754 em_setup_ifp(adapter);
755
756 /* Add sysctl tree, must after em_setup_ifp() */
757 em_add_sysctl(adapter);
758
759 /* Reset the hardware */
760 error = em_reset(adapter);
761 if (error) {
762 device_printf(dev, "Unable to reset the hardware\n");
763 goto fail;
764 }
765
766 /* Initialize statistics */
767 em_update_stats(adapter);
768
769 adapter->hw.mac.get_link_status = 1;
770 em_update_link_status(adapter);
771
9c80d176
SZ
772 /* Do we need workaround for 82544 PCI-X adapter? */
773 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
774 adapter->hw.mac.type == e1000_82544)
f647ad3d 775 adapter->pcix_82544 = TRUE;
87307ba1 776 else
f647ad3d 777 adapter->pcix_82544 = FALSE;
af82d4bb 778
9c80d176
SZ
779 if (adapter->pcix_82544) {
780 /*
781 * 82544 on PCI-X may split one TX segment
782 * into two TX descs, so we double its number
783 * of spare TX desc here.
784 */
785 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
786 } else {
787 adapter->spare_tx_desc = EM_TX_SPARE;
788 }
789
9f60d74b
SZ
790 /*
791 * Keep following relationship between spare_tx_desc, oact_tx_desc
792 * and tx_int_nsegs:
793 * (spare_tx_desc + EM_TX_RESERVED) <=
794 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
795 */
796 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
797 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
798 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
799 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
800 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
801
802 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
803 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
804 adapter->tx_int_nsegs = adapter->oact_tx_desc;
805
2d0e5700 806 /* Non-AMT based hardware can now take control from firmware */
79878f87
SZ
807 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
808 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571)
2d0e5700
SZ
809 em_get_hw_control(adapter);
810
87ab432b
SZ
811 /*
812 * Missing Interrupt Following ICR read:
813 *
a835687d
SZ
814 * 82571/82572 specification update errata #76
815 * 82573 specification update errata #31
816 * 82574 specification update errata #12
817 * 82583 specification update errata #4
87ab432b
SZ
818 */
819 intr_func = em_intr;
820 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
821 (adapter->hw.mac.type == e1000_82571 ||
822 adapter->hw.mac.type == e1000_82572 ||
823 adapter->hw.mac.type == e1000_82573 ||
824 adapter->hw.mac.type == e1000_82574 ||
825 adapter->hw.mac.type == e1000_82583))
826 intr_func = em_intr_mask;
827
9c80d176 828 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
87ab432b 829 intr_func, adapter, &adapter->intr_tag,
9c80d176 830 ifp->if_serializer);
af82d4bb 831 if (error) {
9c80d176
SZ
832 device_printf(dev, "Failed to register interrupt handler");
833 ether_ifdetach(&adapter->arpcom.ac_if);
af82d4bb
JS
834 goto fail;
835 }
836
a749d1d2 837 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res);
9db4b353 838 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
9c80d176 839 return (0);
af82d4bb
JS
840fail:
841 em_detach(dev);
9c80d176 842 return (error);
984263bc
MD
843}
844
984263bc
MD
845static int
846em_detach(device_t dev)
847{
78195a76 848 struct adapter *adapter = device_get_softc(dev);
984263bc 849
af82d4bb 850 if (device_is_attached(dev)) {
9c80d176 851 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ
852
853 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 854
af82d4bb 855 em_stop(adapter);
9c80d176
SZ
856
857 e1000_phy_hw_reset(&adapter->hw);
858
859 em_rel_mgmt(adapter);
2d0e5700 860 em_rel_hw_control(adapter);
9c80d176
SZ
861
862 if (adapter->wol) {
863 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
864 E1000_WUC_PME_EN);
865 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
866 em_enable_wol(dev);
867 }
868
869 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
870
cdf89432
SZ
871 lwkt_serialize_exit(ifp->if_serializer);
872
873 ether_ifdetach(ifp);
a19a8754 874 } else if (adapter->memory != NULL) {
2d0e5700 875 em_rel_hw_control(adapter);
7ea52455 876 }
cdf89432
SZ
877 bus_generic_detach(dev);
878
9c80d176
SZ
879 em_free_pci_res(adapter);
880
881 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
882 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 883
984263bc 884 /* Free Transmit Descriptor ring */
9c80d176 885 if (adapter->tx_desc_base)
9ccd8c1f 886 em_dma_free(adapter, &adapter->txdma);
984263bc 887
984263bc 888 /* Free Receive Descriptor ring */
9c80d176 889 if (adapter->rx_desc_base)
9ccd8c1f 890 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ
891
892 /* Free top level busdma tag */
893 if (adapter->parent_dtag != NULL)
894 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 895
1eca7b82 896 /* Free sysctl tree */
9c80d176 897 if (adapter->sysctl_tree != NULL)
1eca7b82 898 sysctl_ctx_free(&adapter->sysctl_ctx);
984263bc 899
a19a8754
SZ
900 if (adapter->mta != NULL)
901 kfree(adapter->mta, M_DEVBUF);
902
87307ba1 903 return (0);
984263bc
MD
904}
905
984263bc
MD
906static int
907em_shutdown(device_t dev)
908{
9c80d176 909 return em_suspend(dev);
87307ba1
SZ
910}
911
87307ba1
SZ
912static int
913em_suspend(device_t dev)
914{
915 struct adapter *adapter = device_get_softc(dev);
9c80d176 916 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
917
918 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 919
87307ba1 920 em_stop(adapter);
9c80d176
SZ
921
922 em_rel_mgmt(adapter);
2d0e5700 923 em_rel_hw_control(adapter);
9c80d176 924
2d0e5700 925 if (adapter->wol) {
9c80d176
SZ
926 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
927 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
928 em_enable_wol(dev);
2d0e5700 929 }
9c80d176 930
87307ba1 931 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ
932
933 return bus_generic_suspend(dev);
87307ba1
SZ
934}
935
936static int
937em_resume(device_t dev)
938{
939 struct adapter *adapter = device_get_softc(dev);
9c80d176 940 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
941
942 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 943
87307ba1 944 em_init(adapter);
9c80d176 945 em_get_mgmt(adapter);
9db4b353 946 if_devstart(ifp);
9c80d176 947
87307ba1
SZ
948 lwkt_serialize_exit(ifp->if_serializer);
949
950 return bus_generic_resume(dev);
984263bc
MD
951}
952
984263bc
MD
953static void
954em_start(struct ifnet *ifp)
955{
f647ad3d 956 struct adapter *adapter = ifp->if_softc;
9c80d176 957 struct mbuf *m_head;
984263bc 958
1eca7b82 959 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 960
87307ba1
SZ
961 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
962 return;
9c80d176 963
9db4b353
SZ
964 if (!adapter->link_active) {
965 ifq_purge(&ifp->if_snd);
f647ad3d 966 return;
9db4b353 967 }
9c80d176 968
e26dc3e9 969 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ
970 /* Now do we at least have a minimal? */
971 if (EM_IS_OACTIVE(adapter)) {
972 em_tx_collect(adapter);
9c80d176 973 if (EM_IS_OACTIVE(adapter)) {
9c80d176 974 ifp->if_flags |= IFF_OACTIVE;
9f60d74b 975 adapter->no_tx_desc_avail1++;
9c80d176
SZ
976 break;
977 }
978 }
979
980 logif(pkt_txqueue);
9db4b353 981 m_head = ifq_dequeue(&ifp->if_snd, NULL);
f647ad3d
JS
982 if (m_head == NULL)
983 break;
984263bc 984
9c80d176 985 if (em_encap(adapter, &m_head)) {
002b3a05 986 ifp->if_oerrors++;
9f60d74b
SZ
987 em_tx_collect(adapter);
988 continue;
f647ad3d 989 }
984263bc
MD
990
991 /* Send a copy of the frame to the BPF listener */
b637f170 992 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ
993
994 /* Set timeout in case hardware has problems transmitting. */
995 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 996 }
984263bc
MD
997}
998
984263bc 999static int
bd4539cc 1000em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1001{
f647ad3d 1002 struct adapter *adapter = ifp->if_softc;
9c80d176 1003 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 1004 uint16_t eeprom_data = 0;
9c80d176
SZ
1005 int max_frame_size, mask, reinit;
1006 int error = 0;
0d366ee7 1007
9c80d176 1008 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 1009
984263bc 1010 switch (command) {
984263bc 1011 case SIOCSIFMTU:
9c80d176
SZ
1012 switch (adapter->hw.mac.type) {
1013 case e1000_82573:
1eca7b82
SZ
1014 /*
1015 * 82573 only supports jumbo frames
1016 * if ASPM is disabled.
1017 */
9c80d176
SZ
1018 e1000_read_nvm(&adapter->hw,
1019 NVM_INIT_3GIO_3, 1, &eeprom_data);
1020 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ
1021 max_frame_size = ETHER_MAX_LEN;
1022 break;
1023 }
9c80d176
SZ
1024 /* FALL THROUGH */
1025
1026 /* Limit Jumbo Frame size */
1027 case e1000_82571:
1028 case e1000_82572:
1029 case e1000_ich9lan:
1030 case e1000_ich10lan:
2d0e5700 1031 case e1000_pch2lan:
9c80d176 1032 case e1000_82574:
6d5e2922 1033 case e1000_82583:
9c80d176 1034 case e1000_80003es2lan:
1eca7b82 1035 max_frame_size = 9234;
7ea52455 1036 break;
9c80d176 1037
2d0e5700
SZ
1038 case e1000_pchlan:
1039 max_frame_size = 4096;
1040 break;
1041
9c80d176
SZ
1042 /* Adapters that do not support jumbo frames */
1043 case e1000_82542:
1044 case e1000_ich8lan:
7ea52455
SZ
1045 max_frame_size = ETHER_MAX_LEN;
1046 break;
9c80d176 1047
7ea52455
SZ
1048 default:
1049 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1050 break;
1051 }
9c80d176
SZ
1052 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1053 ETHER_CRC_LEN) {
984263bc 1054 error = EINVAL;
9c80d176 1055 break;
984263bc 1056 }
9c80d176
SZ
1057
1058 ifp->if_mtu = ifr->ifr_mtu;
1059 adapter->max_frame_size =
1060 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1061
1062 if (ifp->if_flags & IFF_RUNNING)
1063 em_init(adapter);
984263bc 1064 break;
9c80d176 1065
984263bc 1066 case SIOCSIFFLAGS:
984263bc 1067 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ
1068 if ((ifp->if_flags & IFF_RUNNING)) {
1069 if ((ifp->if_flags ^ adapter->if_flags) &
1070 (IFF_PROMISC | IFF_ALLMULTI)) {
1071 em_disable_promisc(adapter);
1072 em_set_promisc(adapter);
1073 }
1074 } else {
78195a76 1075 em_init(adapter);
87307ba1 1076 }
9c80d176
SZ
1077 } else if (ifp->if_flags & IFF_RUNNING) {
1078 em_stop(adapter);
984263bc 1079 }
87307ba1 1080 adapter->if_flags = ifp->if_flags;
984263bc 1081 break;
9c80d176 1082
984263bc
MD
1083 case SIOCADDMULTI:
1084 case SIOCDELMULTI:
984263bc
MD
1085 if (ifp->if_flags & IFF_RUNNING) {
1086 em_disable_intr(adapter);
1087 em_set_multi(adapter);
9c80d176
SZ
1088 if (adapter->hw.mac.type == e1000_82542 &&
1089 adapter->hw.revision_id == E1000_REVISION_2)
1090 em_init_rx_unit(adapter);
1eca7b82 1091#ifdef DEVICE_POLLING
9c80d176 1092 if (!(ifp->if_flags & IFF_POLLING))
1eca7b82 1093#endif
9c80d176 1094 em_enable_intr(adapter);
984263bc
MD
1095 }
1096 break;
9c80d176 1097
984263bc 1098 case SIOCSIFMEDIA:
87307ba1 1099 /* Check SOL/IDER usage */
9c80d176
SZ
1100 if (e1000_check_reset_block(&adapter->hw)) {
1101 device_printf(adapter->dev, "Media change is"
1102 " blocked due to SOL/IDER session.\n");
87307ba1
SZ
1103 break;
1104 }
9c80d176
SZ
1105 /* FALL THROUGH */
1106
984263bc 1107 case SIOCGIFMEDIA:
984263bc
MD
1108 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1109 break;
9c80d176 1110
984263bc 1111 case SIOCSIFCAP:
9c80d176 1112 reinit = 0;
984263bc
MD
1113 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1114 if (mask & IFCAP_HWCSUM) {
9c80d176 1115 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1eca7b82 1116 reinit = 1;
984263bc 1117 }
1eca7b82
SZ
1118 if (mask & IFCAP_VLAN_HWTAGGING) {
1119 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1120 reinit = 1;
1121 }
9c80d176 1122 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1123 em_init(adapter);
984263bc 1124 break;
9c80d176 1125
984263bc 1126 default:
1eca7b82
SZ
1127 error = ether_ioctl(ifp, command, data);
1128 break;
984263bc 1129 }
87307ba1 1130 return (error);
984263bc
MD
1131}
1132
984263bc
MD
1133static void
1134em_watchdog(struct ifnet *ifp)
1135{
1eca7b82 1136 struct adapter *adapter = ifp->if_softc;
984263bc 1137
9c80d176
SZ
1138 ASSERT_SERIALIZED(ifp->if_serializer);
1139
1140 /*
1141 * The timer is set to 5 every time start queues a packet.
1142 * Then txeof keeps resetting it as long as it cleans at
1143 * least one descriptor.
1144 * Finally, anytime all descriptors are clean the timer is
1145 * set to 0.
1146 */
1147
9f60d74b
SZ
1148 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1149 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1150 /*
1151 * If we reach here, all TX jobs are completed and
1152 * the TX engine should have been idled for some time.
1153 * We don't need to call if_devstart() here.
1154 */
1155 ifp->if_flags &= ~IFF_OACTIVE;
1156 ifp->if_timer = 0;
1157 return;
1158 }
1159
1eca7b82
SZ
1160 /*
1161 * If we are in this routine because of pause frames, then
984263bc
MD
1162 * don't reset the hardware.
1163 */
9c80d176
SZ
1164 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1165 E1000_STATUS_TXOFF) {
984263bc
MD
1166 ifp->if_timer = EM_TX_TIMEOUT;
1167 return;
1168 }
1169
9c80d176 1170 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1171 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1172
9c80d176
SZ
1173 ifp->if_oerrors++;
1174 adapter->watchdog_events++;
1175
984263bc
MD
1176 em_init(adapter);
1177
9c80d176
SZ
1178 if (!ifq_is_empty(&ifp->if_snd))
1179 if_devstart(ifp);
984263bc
MD
1180}
1181
984263bc 1182static void
9c80d176 1183em_init(void *xsc)
984263bc 1184{
9c80d176
SZ
1185 struct adapter *adapter = xsc;
1186 struct ifnet *ifp = &adapter->arpcom.ac_if;
1187 device_t dev = adapter->dev;
eac00e59 1188 uint32_t pba;
984263bc 1189
87307ba1
SZ
1190 ASSERT_SERIALIZED(ifp->if_serializer);
1191
984263bc
MD
1192 em_stop(adapter);
1193
eac00e59
SZ
1194 /*
1195 * Packet Buffer Allocation (PBA)
1196 * Writing PBA sets the receive portion of the buffer
1197 * the remainder is used for the transmit buffer.
1eca7b82
SZ
1198 *
1199 * Devices before the 82547 had a Packet Buffer of 64K.
1200 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1201 * After the 82547 the buffer was reduced to 40K.
1202 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1203 * Note: default does not leave enough room for Jumbo Frame >10k.
eac00e59 1204 */
9c80d176
SZ
1205 switch (adapter->hw.mac.type) {
1206 case e1000_82547:
1207 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1208 if (adapter->max_frame_size > 8192)
eac00e59 1209 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
7ea52455
SZ
1210 else
1211 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
eac00e59
SZ
1212 adapter->tx_fifo_head = 0;
1213 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1214 adapter->tx_fifo_size =
9c80d176 1215 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
7ea52455 1216 break;
9c80d176 1217
87307ba1 1218 /* Total Packet Buffer on these is 48K */
9c80d176
SZ
1219 case e1000_82571:
1220 case e1000_82572:
1221 case e1000_80003es2lan:
7ea52455
SZ
1222 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1223 break;
9c80d176
SZ
1224
1225 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
7ea52455
SZ
1226 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1227 break;
9c80d176
SZ
1228
1229 case e1000_82574:
2d0e5700 1230 case e1000_82583:
9c80d176 1231 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1eca7b82 1232 break;
9c80d176 1233
2d0e5700
SZ
1234 case e1000_ich8lan:
1235 pba = E1000_PBA_8K;
1236 break;
1237
9c80d176
SZ
1238 case e1000_ich9lan:
1239 case e1000_ich10lan:
1240#define E1000_PBA_10K 0x000A
b0ff1d56
MS
1241 pba = E1000_PBA_10K;
1242 break;
9c80d176 1243
2d0e5700
SZ
1244 case e1000_pchlan:
1245 case e1000_pch2lan:
1246 pba = E1000_PBA_26K;
9c80d176
SZ
1247 break;
1248
7ea52455
SZ
1249 default:
1250 /* Devices before 82547 had a Packet Buffer of 64K. */
9c80d176 1251 if (adapter->max_frame_size > 8192)
7ea52455
SZ
1252 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1253 else
1254 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
eac00e59 1255 }
9c80d176 1256 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
a4a205fa 1257
0d366ee7 1258 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ
1259 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1260
1261 /* Put the address into the Receive Address Array */
1262 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1263
1264 /*
1265 * With the 82571 adapter, RAR[0] may be overwritten
1266 * when the other port is reset, we make a duplicate
1267 * in RAR[14] for that eventuality, this assures
1268 * the interface continues to function.
1269 */
1270 if (adapter->hw.mac.type == e1000_82571) {
1271 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1272 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1273 E1000_RAR_ENTRIES - 1);
1274 }
0d366ee7 1275
2d0e5700
SZ
1276 /* Reset the hardware */
1277 if (em_reset(adapter)) {
1278 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1279 /* XXX em_stop()? */
984263bc
MD
1280 return;
1281 }
87307ba1 1282 em_update_link_status(adapter);
984263bc 1283
9c80d176
SZ
1284 /* Setup VLAN support, basic and offload if available */
1285 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1286
9c80d176
SZ
1287 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1288 uint32_t ctrl;
1289
1290 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1291 ctrl |= E1000_CTRL_VME;
1292 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ
1293 }
1294
9c80d176
SZ
1295 /* Set hardware offload abilities */
1296 if (ifp->if_capenable & IFCAP_TXCSUM)
1297 ifp->if_hwassist = EM_CSUM_FEATURES;
1298 else
1299 ifp->if_hwassist = 0;
1300
1301 /* Configure for OS presence */
1302 em_get_mgmt(adapter);
1303
984263bc 1304 /* Prepare transmit descriptors and buffers */
9c80d176
SZ
1305 em_init_tx_ring(adapter);
1306 em_init_tx_unit(adapter);
984263bc
MD
1307
1308 /* Setup Multicast table */
1309 em_set_multi(adapter);
1310
1311 /* Prepare receive descriptors and buffers */
9c80d176
SZ
1312 if (em_init_rx_ring(adapter)) {
1313 device_printf(dev, "Could not setup receive structures\n");
984263bc 1314 em_stop(adapter);
984263bc
MD
1315 return;
1316 }
9c80d176 1317 em_init_rx_unit(adapter);
7ea52455 1318
87307ba1 1319 /* Don't lose promiscuous settings */
0d366ee7 1320 em_set_promisc(adapter);
984263bc 1321
984263bc
MD
1322 ifp->if_flags |= IFF_RUNNING;
1323 ifp->if_flags &= ~IFF_OACTIVE;
1324
9c80d176
SZ
1325 callout_reset(&adapter->timer, hz, em_timer, adapter);
1326 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1327
1328 /* MSI/X configuration for 82574 */
1329 if (adapter->hw.mac.type == e1000_82574) {
1330 int tmp;
1331
1332 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1333 tmp |= E1000_CTRL_EXT_PBA_CLR;
1334 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1335 /*
2d0e5700 1336 * XXX MSIX
9c80d176
SZ
1337 * Set the IVAR - interrupt vector routing.
1338 * Each nibble represents a vector, high bit
1339 * is enable, other 3 bits are the MSIX table
1340 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1341 * Link (other) to 2, hence the magic number.
1342 */
1343 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1344 }
1eca7b82
SZ
1345
1346#ifdef DEVICE_POLLING
9c80d176
SZ
1347 /*
1348 * Only enable interrupts if we are not polling, make sure
1349 * they are off otherwise.
1350 */
1eca7b82
SZ
1351 if (ifp->if_flags & IFF_POLLING)
1352 em_disable_intr(adapter);
1353 else
9c80d176
SZ
1354#endif /* DEVICE_POLLING */
1355 em_enable_intr(adapter);
0d366ee7 1356
2d0e5700 1357 /* AMT based hardware can now take control from firmware */
79878f87
SZ
1358 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
1359 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) &&
2d0e5700
SZ
1360 adapter->hw.mac.type >= e1000_82571)
1361 em_get_hw_control(adapter);
1362
0d366ee7 1363 /* Don't reset the phy next time init gets called */
9c80d176 1364 adapter->hw.phy.reset_disable = TRUE;
984263bc
MD
1365}
1366
984263bc 1367#ifdef DEVICE_POLLING
f647ad3d
JS
1368
1369static void
984263bc
MD
1370em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1371{
f647ad3d
JS
1372 struct adapter *adapter = ifp->if_softc;
1373 uint32_t reg_icr;
984263bc 1374
78195a76
MD
1375 ASSERT_SERIALIZED(ifp->if_serializer);
1376
9c80d176 1377 switch (cmd) {
9c095379
MD
1378 case POLL_REGISTER:
1379 em_disable_intr(adapter);
1380 break;
9c80d176 1381
9c095379 1382 case POLL_DEREGISTER:
f647ad3d 1383 em_enable_intr(adapter);
9c095379 1384 break;
9c80d176 1385
9c095379 1386 case POLL_AND_CHECK_STATUS:
9c80d176 1387 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1388 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1389 callout_stop(&adapter->timer);
9c80d176 1390 adapter->hw.mac.get_link_status = 1;
87307ba1 1391 em_update_link_status(adapter);
9c80d176 1392 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1393 }
9c80d176 1394 /* FALL THROUGH */
9c095379
MD
1395 case POLL_ONLY:
1396 if (ifp->if_flags & IFF_RUNNING) {
87307ba1
SZ
1397 em_rxeof(adapter, count);
1398 em_txeof(adapter);
1eca7b82 1399
9c095379 1400 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1401 if_devstart(ifp);
9c095379
MD
1402 }
1403 break;
f647ad3d 1404 }
984263bc 1405}
9c095379 1406
984263bc
MD
1407#endif /* DEVICE_POLLING */
1408
984263bc 1409static void
9c80d176 1410em_intr(void *xsc)
984263bc 1411{
87ab432b
SZ
1412 em_intr_body(xsc, TRUE);
1413}
1414
1415static void
1416em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1417{
9c80d176 1418 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1419 uint32_t reg_icr;
984263bc 1420
07855a48 1421 logif(intr_beg);
78195a76
MD
1422 ASSERT_SERIALIZED(ifp->if_serializer);
1423
9c80d176
SZ
1424 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1425
87ab432b
SZ
1426 if (chk_asserted &&
1427 ((adapter->hw.mac.type >= e1000_82571 &&
1428 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1429 reg_icr == 0)) {
07855a48 1430 logif(intr_end);
984263bc 1431 return;
07855a48 1432 }
984263bc 1433
87307ba1 1434 /*
9c80d176
SZ
1435 * XXX: some laptops trigger several spurious interrupts
1436 * on em(4) when in the resume cycle. The ICR register
1437 * reports all-ones value in this case. Processing such
1438 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ
1439 */
1440 if (reg_icr == 0xffffffff) {
1441 logif(intr_end);
1442 return;
984263bc
MD
1443 }
1444
79938e61 1445 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1446 if (reg_icr &
6643d744 1447 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1448 em_rxeof(adapter, -1);
6643d744 1449 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ
1450 em_txeof(adapter);
1451 if (!ifq_is_empty(&ifp->if_snd))
1452 if_devstart(ifp);
1453 }
f647ad3d 1454 }
984263bc 1455
87307ba1
SZ
1456 /* Link status change */
1457 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1458 callout_stop(&adapter->timer);
9c80d176 1459 adapter->hw.mac.get_link_status = 1;
87307ba1 1460 em_update_link_status(adapter);
9c80d176
SZ
1461
1462 /* Deal with TX cruft when link lost */
1463 em_tx_purge(adapter);
1464
1465 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ
1466 }
1467
1468 if (reg_icr & E1000_ICR_RXO)
1469 adapter->rx_overruns++;
1470
07855a48 1471 logif(intr_end);
984263bc
MD
1472}
1473
984263bc 1474static void
87ab432b
SZ
1475em_intr_mask(void *xsc)
1476{
1477 struct adapter *adapter = xsc;
1478
1479 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1480 /*
1481 * NOTE:
1482 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1483 * so don't check it.
1484 */
1485 em_intr_body(adapter, FALSE);
1486 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1487}
1488
1489static void
984263bc
MD
1490em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1491{
87307ba1 1492 struct adapter *adapter = ifp->if_softc;
1eca7b82 1493 u_char fiber_type = IFM_1000_SX;
984263bc 1494
78195a76
MD
1495 ASSERT_SERIALIZED(ifp->if_serializer);
1496
87307ba1 1497 em_update_link_status(adapter);
984263bc
MD
1498
1499 ifmr->ifm_status = IFM_AVALID;
1500 ifmr->ifm_active = IFM_ETHER;
1501
1502 if (!adapter->link_active)
1503 return;
1504
1505 ifmr->ifm_status |= IFM_ACTIVE;
1506
9c80d176
SZ
1507 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1508 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1509 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
1510 fiber_type = IFM_1000_LX;
1511 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD
1512 } else {
1513 switch (adapter->link_speed) {
1514 case 10:
1515 ifmr->ifm_active |= IFM_10_T;
1516 break;
1517 case 100:
1518 ifmr->ifm_active |= IFM_100_TX;
1519 break;
9c80d176 1520
984263bc 1521 case 1000:
7f259627 1522 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD
1523 break;
1524 }
1525 if (adapter->link_duplex == FULL_DUPLEX)
1526 ifmr->ifm_active |= IFM_FDX;
1527 else
1528 ifmr->ifm_active |= IFM_HDX;
1529 }
984263bc
MD
1530}
1531
984263bc
MD
1532static int
1533em_media_change(struct ifnet *ifp)
1534{
87307ba1
SZ
1535 struct adapter *adapter = ifp->if_softc;
1536 struct ifmedia *ifm = &adapter->media;
984263bc 1537
78195a76 1538 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1539
87307ba1
SZ
1540 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1541 return (EINVAL);
1542
984263bc
MD
1543 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1544 case IFM_AUTO:
9c80d176
SZ
1545 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1546 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1547 break;
9c80d176 1548
1eca7b82 1549 case IFM_1000_LX:
984263bc 1550 case IFM_1000_SX:
7f259627 1551 case IFM_1000_T:
9c80d176
SZ
1552 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1553 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1554 break;
9c80d176 1555
984263bc 1556 case IFM_100_TX:
9c80d176
SZ
1557 adapter->hw.mac.autoneg = FALSE;
1558 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1559 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1560 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
984263bc 1561 else
9c80d176 1562 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
984263bc 1563 break;
9c80d176 1564
984263bc 1565 case IFM_10_T:
9c80d176
SZ
1566 adapter->hw.mac.autoneg = FALSE;
1567 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1568 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1569 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
984263bc 1570 else
9c80d176 1571 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
984263bc 1572 break;
9c80d176 1573
984263bc 1574 default:
f647ad3d 1575 if_printf(ifp, "Unsupported media type\n");
9c80d176 1576 break;
984263bc 1577 }
9c80d176 1578
f647ad3d 1579 /*
9c80d176 1580 * As the speed/duplex settings my have changed we need to
f647ad3d
JS
1581 * reset the PHY.
1582 */
9c80d176 1583 adapter->hw.phy.reset_disable = FALSE;
984263bc 1584
78195a76 1585 em_init(adapter);
984263bc 1586
9c80d176 1587 return (0);
9ccd8c1f
JS
1588}
1589
984263bc 1590static int
9c80d176 1591em_encap(struct adapter *adapter, struct mbuf **m_headp)
9ccd8c1f 1592{
9c80d176 1593 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1594 bus_dmamap_t map;
9c80d176
SZ
1595 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1596 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1597 struct mbuf *m_head = *m_headp;
9f60d74b 1598 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1599 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1600
3752657e 1601 if (m_head->m_len < EM_TXCSUM_MINHL &&
002b3a05
SZ
1602 (m_head->m_flags & EM_CSUM_FEATURES)) {
1603 /*
1604 * Make sure that ethernet header and ip.ip_hl are in
1605 * contiguous memory, since if TXCSUM is enabled, later
1606 * TX context descriptor's setup need to access ip.ip_hl.
1607 */
1608 error = em_txcsum_pullup(adapter, m_headp);
1609 if (error) {
1610 KKASSERT(*m_headp == NULL);
1611 return error;
1612 }
1613 m_head = *m_headp;
1614 }
1615
9c80d176
SZ
1616 txd_upper = txd_lower = 0;
1617 txd_used = 0;
87307ba1
SZ
1618
1619 /*
9c80d176
SZ
1620 * Capture the first descriptor index, this descriptor
1621 * will have the index of the EOP which is the only one
1622 * that now gets a DONE bit writeback.
87307ba1 1623 */
9c80d176
SZ
1624 first = adapter->next_avail_tx_desc;
1625 tx_buffer = &adapter->tx_buffer_area[first];
1626 tx_buffer_mapped = tx_buffer;
1627 map = tx_buffer->map;
87307ba1 1628
9c80d176
SZ
1629 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1630 KASSERT(maxsegs >= adapter->spare_tx_desc,
ed20d0e3 1631 ("not enough spare TX desc"));
9c80d176
SZ
1632 if (adapter->pcix_82544) {
1633 /* Half it; see the comment in em_attach() */
1634 maxsegs >>= 1;
9ccd8c1f 1635 }
9c80d176
SZ
1636 if (maxsegs > EM_MAX_SCATTER)
1637 maxsegs = EM_MAX_SCATTER;
984263bc 1638
9c80d176
SZ
1639 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1640 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1641 if (error) {
1642 if (error == ENOBUFS)
1643 adapter->mbuf_alloc_failed++;
1644 else
1645 adapter->no_tx_dma_setup++;
984263bc 1646
9c80d176
SZ
1647 m_freem(*m_headp);
1648 *m_headp = NULL;
1649 return error;
7ea52455 1650 }
9c80d176 1651 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1652
9c80d176 1653 m_head = *m_headp;
9f60d74b 1654 adapter->tx_nsegs += nsegs;
9c80d176 1655
002b3a05 1656 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1657 /* TX csum offloading will consume one TX desc */
9f60d74b
SZ
1658 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1659 &txd_upper, &txd_lower);
9c80d176 1660 }
984263bc 1661 i = adapter->next_avail_tx_desc;
87307ba1
SZ
1662
1663 /* Set up our transmit descriptors */
9c80d176 1664 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS
1665 /* If adapter is 82544 and on PCIX bus */
1666 if(adapter->pcix_82544) {
87307ba1
SZ
1667 DESC_ARRAY desc_array;
1668 uint32_t array_elements, counter;
1669
9c80d176 1670 /*
f647ad3d
JS
1671 * Check the Address and Length combination and
1672 * split the data accordingly
9ccd8c1f 1673 */
9c80d176
SZ
1674 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1675 segs[j].ds_len, &desc_array);
9ccd8c1f 1676 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ
1677 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1678
9ccd8c1f 1679 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ
1680 ctxd = &adapter->tx_desc_base[i];
1681
1682 ctxd->buffer_addr = htole64(
1683 desc_array.descriptor[counter].address);
1684 ctxd->lower.data = htole32(
2af74b85 1685 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ
1686 desc_array.descriptor[counter].length);
1687 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ
1688
1689 last = i;
9ccd8c1f
JS
1690 if (++i == adapter->num_tx_desc)
1691 i = 0;
1692
9ccd8c1f 1693 txd_used++;
9c80d176 1694 }
9ccd8c1f 1695 } else {
0d366ee7 1696 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1697 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1698
9c80d176 1699 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1700 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ
1701 txd_lower | segs[j].ds_len);
1702 ctxd->upper.data = htole32(txd_upper);
984263bc 1703
87307ba1 1704 last = i;
0d366ee7
MD
1705 if (++i == adapter->num_tx_desc)
1706 i = 0;
0d366ee7 1707 }
984263bc 1708 }
9ccd8c1f 1709
984263bc 1710 adapter->next_avail_tx_desc = i;
9c80d176
SZ
1711 if (adapter->pcix_82544) {
1712 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1713 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ
1714 } else {
1715 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1716 adapter->num_tx_desc_avail -= nsegs;
1717 }
984263bc 1718
9c80d176 1719 /* Handle VLAN tag */
83790f85 1720 if (m_head->m_flags & M_VLANTAG) {
9c80d176
SZ
1721 /* Set the vlan id. */
1722 ctxd->upper.fields.special =
1723 htole16(m_head->m_pkthdr.ether_vlantag);
9ccd8c1f 1724
f647ad3d 1725 /* Tell hardware to add tag */
9c80d176 1726 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
f647ad3d 1727 }
984263bc
MD
1728
1729 tx_buffer->m_head = m_head;
9c80d176 1730 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1731 tx_buffer->map = map;
9ccd8c1f 1732
9f60d74b
SZ
1733 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1734 adapter->tx_nsegs = 0;
4e4e8481
SZ
1735
1736 /*
1737 * Report Status (RS) is turned on
1738 * every tx_int_nsegs descriptors.
1739 */
9f60d74b
SZ
1740 cmd = E1000_TXD_CMD_RS;
1741
b4b0a2b4
SZ
1742 /*
1743 * Keep track of the descriptor, which will
1744 * be written back by hardware.
1745 */
9f60d74b
SZ
1746 adapter->tx_dd[adapter->tx_dd_tail] = last;
1747 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1748 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1749 }
1750
9ccd8c1f 1751 /*
984263bc 1752 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1753 */
9f60d74b 1754 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1
SZ
1755
1756 /*
9c80d176 1757 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
984263bc
MD
1758 * that this frame is available to transmit.
1759 */
9c80d176 1760 if (adapter->hw.mac.type == e1000_82547 &&
984263bc 1761 adapter->link_duplex == HALF_DUPLEX) {
cfefda96 1762 em_82547_move_tail_serialized(adapter);
9ccd8c1f 1763 } else {
9c80d176
SZ
1764 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1765 if (adapter->hw.mac.type == e1000_82547) {
cfefda96 1766 em_82547_update_fifo_head(adapter,
9c80d176 1767 m_head->m_pkthdr.len);
984263bc
MD
1768 }
1769 }
87307ba1 1770 return (0);
984263bc
MD
1771}
1772
9c80d176 1773/*
984263bc 1774 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1775 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ
1776 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1777 * in this case. We do that only when FIFO is quiescent.
1778 */
9c095379 1779static void
1eca7b82 1780em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1781{
9c80d176
SZ
1782 struct e1000_tx_desc *tx_desc;
1783 uint16_t hw_tdt, sw_tdt, length = 0;
1784 bool eop = 0;
984263bc 1785
9c80d176
SZ
1786 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1787
1788 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1789 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1790
984263bc
MD
1791 while (hw_tdt != sw_tdt) {
1792 tx_desc = &adapter->tx_desc_base[hw_tdt];
1793 length += tx_desc->lower.flags.length;
1794 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1795 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD
1796 hw_tdt = 0;
1797
87307ba1 1798 if (eop) {
984263bc 1799 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1800 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS
1801 callout_reset(&adapter->tx_fifo_timer, 1,
1802 em_82547_move_tail, adapter);
1803 break;
984263bc 1804 }
9c80d176 1805 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS
1806 em_82547_update_fifo_head(adapter, length);
1807 length = 0;
984263bc 1808 }
9c80d176
SZ
1809 }
1810}
1811
1812static void
1813em_82547_move_tail(void *xsc)
1814{
1815 struct adapter *adapter = xsc;
1816 struct ifnet *ifp = &adapter->arpcom.ac_if;
1817
1818 lwkt_serialize_enter(ifp->if_serializer);
1819 em_82547_move_tail_serialized(adapter);
1820 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1821}
1822
1823static int
1824em_82547_fifo_workaround(struct adapter *adapter, int len)
1825{
1826 int fifo_space, fifo_pkt_len;
1827
1eca7b82 1828 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD
1829
1830 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1831 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD
1832
1833 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1834 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1835 return (0);
f647ad3d 1836 else
87307ba1 1837 return (1);
984263bc
MD
1838 }
1839 }
87307ba1 1840 return (0);
984263bc
MD
1841}
1842
1843static void
1844em_82547_update_fifo_head(struct adapter *adapter, int len)
1845{
1eca7b82 1846 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1847
984263bc
MD
1848 /* tx_fifo_head is always 16 byte aligned */
1849 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ
1850 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1851 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD
1852}
1853
984263bc
MD
1854static int
1855em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1856{
984263bc
MD
1857 uint32_t tctl;
1858
9c80d176
SZ
1859 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1860 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1861 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1862 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1863 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1864 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1865 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1866 /* Disable TX unit */
9c80d176
SZ
1867 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1868 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1869 tctl & ~E1000_TCTL_EN);
984263bc
MD
1870
1871 /* Reset FIFO pointers */
9c80d176
SZ
1872 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1873 adapter->tx_head_addr);
1874 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1875 adapter->tx_head_addr);
1876 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1877 adapter->tx_head_addr);
1878 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1879 adapter->tx_head_addr);
984263bc
MD
1880
1881 /* Re-enable TX unit */
9c80d176 1882 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
1883 E1000_WRITE_FLUSH(&adapter->hw);
1884
1885 adapter->tx_fifo_head = 0;
eac00e59 1886 adapter->tx_fifo_reset_cnt++;
984263bc 1887
87307ba1 1888 return (TRUE);
eac00e59 1889 } else {
87307ba1 1890 return (FALSE);
984263bc
MD
1891 }
1892}
1893
1894static void
f647ad3d 1895em_set_promisc(struct adapter *adapter)
984263bc 1896{
9c80d176 1897 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1898 uint32_t reg_rctl;
984263bc 1899
9c80d176 1900 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD
1901
1902 if (ifp->if_flags & IFF_PROMISC) {
1903 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ
1904 /* Turn this on if you want to see bad packets */
1905 if (em_debug_sbp)
1906 reg_rctl |= E1000_RCTL_SBP;
1907 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1908 } else if (ifp->if_flags & IFF_ALLMULTI) {
1909 reg_rctl |= E1000_RCTL_MPE;
1910 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1911 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1912 }
984263bc
MD
1913}
1914
1915static void
f647ad3d 1916em_disable_promisc(struct adapter *adapter)
984263bc 1917{
f647ad3d 1918 uint32_t reg_rctl;
984263bc 1919
9c80d176 1920 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 1921
9c80d176
SZ
1922 reg_rctl &= ~E1000_RCTL_UPE;
1923 reg_rctl &= ~E1000_RCTL_MPE;
1924 reg_rctl &= ~E1000_RCTL_SBP;
1925 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1926}
1927
984263bc 1928static void
f647ad3d 1929em_set_multi(struct adapter *adapter)
984263bc 1930{
9c80d176 1931 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1932 struct ifmultiaddr *ifma;
9c80d176 1933 uint32_t reg_rctl = 0;
2d0e5700 1934 uint8_t *mta;
f647ad3d 1935 int mcnt = 0;
f647ad3d 1936
2d0e5700
SZ
1937 mta = adapter->mta;
1938 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1939
9c80d176
SZ
1940 if (adapter->hw.mac.type == e1000_82542 &&
1941 adapter->hw.revision_id == E1000_REVISION_2) {
1942 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1943 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1944 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 1945 reg_rctl |= E1000_RCTL_RST;
9c80d176 1946 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS
1947 msec_delay(5);
1948 }
984263bc 1949
441d34b2 1950 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS
1951 if (ifma->ifma_addr->sa_family != AF_LINK)
1952 continue;
1953
1954 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1955 break;
984263bc 1956
f647ad3d 1957 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 1958 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS
1959 mcnt++;
1960 }
1961
1962 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 1963 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1964 reg_rctl |= E1000_RCTL_MPE;
9c80d176 1965 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 1966 } else {
6a5a645e 1967 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 1968 }
f647ad3d 1969
9c80d176
SZ
1970 if (adapter->hw.mac.type == e1000_82542 &&
1971 adapter->hw.revision_id == E1000_REVISION_2) {
1972 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1973 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 1974 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 1975 msec_delay(5);
9c80d176
SZ
1976 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1977 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS
1978 }
1979}
984263bc 1980
9c80d176
SZ
1981/*
1982 * This routine checks for link status and updates statistics.
1983 */
984263bc 1984static void
9c80d176 1985em_timer(void *xsc)
984263bc 1986{
9c80d176
SZ
1987 struct adapter *adapter = xsc;
1988 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 1989
78195a76 1990 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1991
87307ba1 1992 em_update_link_status(adapter);
9c80d176
SZ
1993 em_update_stats(adapter);
1994
1995 /* Reset LAA into RAR[0] on 82571 */
1996 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1997 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1998
1999 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 2000 em_print_hw_stats(adapter);
9c80d176 2001
984263bc
MD
2002 em_smartspeed(adapter);
2003
9c80d176 2004 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 2005
78195a76 2006 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2007}
2008
2009static void
87307ba1 2010em_update_link_status(struct adapter *adapter)
984263bc 2011{
9c80d176
SZ
2012 struct e1000_hw *hw = &adapter->hw;
2013 struct ifnet *ifp = &adapter->arpcom.ac_if;
2014 device_t dev = adapter->dev;
2015 uint32_t link_check = 0;
2016
2017 /* Get the cached link value or read phy for real */
2018 switch (hw->phy.media_type) {
2019 case e1000_media_type_copper:
2020 if (hw->mac.get_link_status) {
2021 /* Do the work to read phy */
2022 e1000_check_for_link(hw);
2023 link_check = !hw->mac.get_link_status;
2024 if (link_check) /* ESB2 fix */
2025 e1000_cfg_on_link_up(hw);
2026 } else {
2027 link_check = TRUE;
984263bc 2028 }
9c80d176
SZ
2029 break;
2030
2031 case e1000_media_type_fiber:
2032 e1000_check_for_link(hw);
2033 link_check =
2034 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2035 break;
2036
2037 case e1000_media_type_internal_serdes:
2038 e1000_check_for_link(hw);
2039 link_check = adapter->hw.mac.serdes_has_link;
2040 break;
2041
2042 case e1000_media_type_unknown:
2043 default:
2044 break;
2045 }
2046
2047 /* Now check for a transition */
2048 if (link_check && adapter->link_active == 0) {
2049 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2050 &adapter->link_duplex);
cb5a6be6
SZ
2051
2052 /*
2053 * Check if we should enable/disable SPEED_MODE bit on
2054 * 82571/82572
2055 */
2d0e5700
SZ
2056 if (adapter->link_speed != SPEED_1000 &&
2057 (hw->mac.type == e1000_82571 ||
2058 hw->mac.type == e1000_82572)) {
9c80d176
SZ
2059 int tarc0;
2060
2061 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2062 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2063 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2064 }
9c80d176
SZ
2065 if (bootverbose) {
2066 device_printf(dev, "Link is up %d Mbps %s\n",
2067 adapter->link_speed,
2068 ((adapter->link_duplex == FULL_DUPLEX) ?
2069 "Full Duplex" : "Half Duplex"));
2070 }
2071 adapter->link_active = 1;
2072 adapter->smartspeed = 0;
2073 ifp->if_baudrate = adapter->link_speed * 1000000;
2074 ifp->if_link_state = LINK_STATE_UP;
2075 if_link_state_change(ifp);
2076 } else if (!link_check && adapter->link_active == 1) {
2077 ifp->if_baudrate = adapter->link_speed = 0;
2078 adapter->link_duplex = 0;
2079 if (bootverbose)
2080 device_printf(dev, "Link is Down\n");
2081 adapter->link_active = 0;
2082#if 0
2083 /* Link down, disable watchdog */
2084 if->if_timer = 0;
2085#endif
2086 ifp->if_link_state = LINK_STATE_DOWN;
2087 if_link_state_change(ifp);
984263bc 2088 }
984263bc
MD
2089}
2090
984263bc 2091static void
9c80d176 2092em_stop(struct adapter *adapter)
984263bc 2093{
9c80d176
SZ
2094 struct ifnet *ifp = &adapter->arpcom.ac_if;
2095 int i;
984263bc 2096
1eca7b82
SZ
2097 ASSERT_SERIALIZED(ifp->if_serializer);
2098
984263bc 2099 em_disable_intr(adapter);
9c80d176 2100
9ccd8c1f
JS
2101 callout_stop(&adapter->timer);
2102 callout_stop(&adapter->tx_fifo_timer);
984263bc 2103
984263bc 2104 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af82d4bb 2105 ifp->if_timer = 0;
9c80d176
SZ
2106
2107 e1000_reset_hw(&adapter->hw);
2108 if (adapter->hw.mac.type >= e1000_82544)
2109 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2110
2111 for (i = 0; i < adapter->num_tx_desc; i++) {
2112 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2113
2114 if (tx_buffer->m_head != NULL) {
2115 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2116 m_freem(tx_buffer->m_head);
2117 tx_buffer->m_head = NULL;
2118 }
9c80d176
SZ
2119 }
2120
2121 for (i = 0; i < adapter->num_rx_desc; i++) {
2122 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2123
2124 if (rx_buffer->m_head != NULL) {
2125 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2126 m_freem(rx_buffer->m_head);
2127 rx_buffer->m_head = NULL;
2128 }
2129 }
c9ff32cc
SZ
2130
2131 if (adapter->fmp != NULL)
2132 m_freem(adapter->fmp);
2133 adapter->fmp = NULL;
2134 adapter->lmp = NULL;
51e6819f
SZ
2135
2136 adapter->csum_flags = 0;
2137 adapter->csum_ehlen = 0;
2138 adapter->csum_iphlen = 0;
9f60d74b
SZ
2139
2140 adapter->tx_dd_head = 0;
2141 adapter->tx_dd_tail = 0;
2142 adapter->tx_nsegs = 0;
984263bc
MD
2143}
2144
9c80d176
SZ
2145static int
2146em_get_hw_info(struct adapter *adapter)
984263bc
MD
2147{
2148 device_t dev = adapter->dev;
2149
984263bc
MD
2150 /* Save off the information about this board */
2151 adapter->hw.vendor_id = pci_get_vendor(dev);
2152 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS
2153 adapter->hw.revision_id = pci_get_revid(dev);
2154 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2155 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2156
9c80d176
SZ
2157 /* Do Shared Code Init and Setup */
2158 if (e1000_set_mac_type(&adapter->hw))
2159 return ENXIO;
2160 return 0;
984263bc
MD
2161}
2162
1eca7b82 2163static int
9c80d176 2164em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2165{
9c80d176 2166 device_t dev = adapter->dev;
053f3ae6 2167 u_int intr_flags;
84e26aaa 2168 int val, rid, msi_enable;
9c80d176
SZ
2169
2170 /* Enable bus mastering */
2171 pci_enable_busmaster(dev);
1eca7b82 2172
9c80d176
SZ
2173 adapter->memory_rid = EM_BAR_MEM;
2174 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2175 &adapter->memory_rid, RF_ACTIVE);
2176 if (adapter->memory == NULL) {
1eca7b82 2177 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2178 return (ENXIO);
1eca7b82
SZ
2179 }
2180 adapter->osdep.mem_bus_space_tag =
9c80d176 2181 rman_get_bustag(adapter->memory);
1eca7b82 2182 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ
2183 rman_get_bushandle(adapter->memory);
2184
2185 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ
2186 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2187
9c80d176
SZ
2188 /* Only older adapters use IO mapping */
2189 if (adapter->hw.mac.type > e1000_82543 &&
2190 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2191 /* Figure our where our IO BAR is ? */
9c80d176 2192 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2193 val = pci_read_config(dev, rid, 4);
87307ba1 2194 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ
2195 adapter->io_rid = rid;
2196 break;
2197 }
2198 rid += 4;
87307ba1
SZ
2199 /* check for 64bit BAR */
2200 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2201 rid += 4;
1eca7b82 2202 }
9c80d176 2203 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ
2204 device_printf(dev, "Unable to locate IO BAR\n");
2205 return (ENXIO);
9c80d176
SZ
2206 }
2207 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2208 &adapter->io_rid, RF_ACTIVE);
2209 if (adapter->ioport == NULL) {
1eca7b82 2210 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2211 "ioport\n");
2212 return (ENXIO);
1eca7b82 2213 }
87307ba1
SZ
2214 adapter->hw.io_base = 0;
2215 adapter->osdep.io_bus_space_tag =
9c80d176 2216 rman_get_bustag(adapter->ioport);
87307ba1 2217 adapter->osdep.io_bus_space_handle =
9c80d176 2218 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ
2219 }
2220
84e26aaa 2221 /*
a835687d
SZ
2222 * Don't enable MSI-X on 82574, see:
2223 * 82574 specification update errata #15
2224 *
84e26aaa 2225 * Don't enable MSI on PCI/PCI-X chips, see:
a835687d
SZ
2226 * 82540 specification update errata #6
2227 * 82545 specification update errata #4
84e26aaa
SZ
2228 *
2229 * Don't enable MSI on 82571/82572, see:
a835687d 2230 * 82571/82572 specification update errata #63
84e26aaa
SZ
2231 */
2232 msi_enable = em_msi_enable;
2233 if (msi_enable &&
2234 (!pci_is_pcie(dev) ||
2235 adapter->hw.mac.type == e1000_82571 ||
2236 adapter->hw.mac.type == e1000_82572))
2237 msi_enable = 0;
2238
2239 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
053f3ae6
SZ
2240 &adapter->intr_rid, &intr_flags);
2241
87ab432b
SZ
2242 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2243 int unshared;
2244
2245 unshared = device_getenv_int(dev, "irq.unshared", 0);
2246 if (!unshared) {
2247 adapter->flags |= EM_FLAG_SHARED_INTR;
2248 if (bootverbose)
2249 device_printf(dev, "IRQ shared\n");
2250 } else {
2251 intr_flags &= ~RF_SHAREABLE;
2252 if (bootverbose)
2253 device_printf(dev, "IRQ unshared\n");
2254 }
2255 }
2256
9c80d176 2257 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
053f3ae6 2258 &adapter->intr_rid, intr_flags);
9c80d176 2259 if (adapter->intr_res == NULL) {
1eca7b82 2260 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2261 "interrupt\n");
2262 return (ENXIO);
1eca7b82
SZ
2263 }
2264
9c80d176 2265 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2266 adapter->hw.back = &adapter->osdep;
a483bd34 2267 return (0);
1eca7b82
SZ
2268}
2269
2270static void
9c80d176 2271em_free_pci_res(struct adapter *adapter)
1eca7b82 2272{
9c80d176 2273 device_t dev = adapter->dev;
1eca7b82 2274
9c80d176
SZ
2275 if (adapter->intr_res != NULL) {
2276 bus_release_resource(dev, SYS_RES_IRQ,
2277 adapter->intr_rid, adapter->intr_res);
1eca7b82 2278 }
9c80d176 2279
053f3ae6
SZ
2280 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2281 pci_release_msi(dev);
2282
9c80d176
SZ
2283 if (adapter->memory != NULL) {
2284 bus_release_resource(dev, SYS_RES_MEMORY,
2285 adapter->memory_rid, adapter->memory);
1eca7b82
SZ
2286 }
2287
9c80d176
SZ
2288 if (adapter->flash != NULL) {
2289 bus_release_resource(dev, SYS_RES_MEMORY,
2290 adapter->flash_rid, adapter->flash);
1eca7b82
SZ
2291 }
2292
9c80d176
SZ
2293 if (adapter->ioport != NULL) {
2294 bus_release_resource(dev, SYS_RES_IOPORT,
2295 adapter->io_rid, adapter->ioport);
1eca7b82
SZ
2296 }
2297}
2298
984263bc 2299static int
2d0e5700 2300em_reset(struct adapter *adapter)
984263bc 2301{
9c80d176
SZ
2302 device_t dev = adapter->dev;
2303 uint16_t rx_buffer_size;
7ea52455 2304
984263bc
MD
2305 /* When hardware is reset, fifo_head is also reset */
2306 adapter->tx_fifo_head = 0;
2307
87307ba1 2308 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2309 if (!em_smart_pwr_down &&
9c80d176
SZ
2310 (adapter->hw.mac.type == e1000_82571 ||
2311 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ
2312 uint16_t phy_tmp = 0;
2313
87307ba1 2314 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ
2315 e1000_read_phy_reg(&adapter->hw,
2316 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2317 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ
2318 e1000_write_phy_reg(&adapter->hw,
2319 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ
2320 }
2321
7ea52455 2322 /*
87307ba1
SZ
2323 * These parameters control the automatic generation (Tx) and
2324 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ
2325 * - High water mark should allow for at least two frames to be
2326 * received after sending an XOFF.
2327 * - Low water mark works best when it is very near the high water mark.
2328 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ
2329 * drained a bit. Here we use an arbitary value of 1500 which will
2330 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ
2331 * could be several smaller frames in the buffer and if so they will
2332 * not trigger the XON until their total number reduces the buffer
2333 * by 1500.
2334 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2335 */
9c80d176
SZ
2336 rx_buffer_size =
2337 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2338
9c80d176
SZ
2339 adapter->hw.fc.high_water = rx_buffer_size -
2340 roundup2(adapter->max_frame_size, 1024);
2341 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2342
2343 if (adapter->hw.mac.type == e1000_80003es2lan)
2344 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2345 else
9c80d176 2346 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2347
9c80d176 2348 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2349
9c80d176 2350 adapter->hw.fc.requested_mode = e1000_fc_full;
7ea52455 2351
2d0e5700
SZ
2352 /* Workaround: no TX flow ctrl for PCH */
2353 if (adapter->hw.mac.type == e1000_pchlan)
2354 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2355
2356 /* Override - settings for PCH2LAN, ya its magic :) */
2357 if (adapter->hw.mac.type == e1000_pch2lan) {
2358 adapter->hw.fc.high_water = 0x5C20;
2359 adapter->hw.fc.low_water = 0x5048;
2360 adapter->hw.fc.pause_time = 0x0650;
2361 adapter->hw.fc.refresh_time = 0x0400;
2362
2363 /* Jumbos need adjusted PBA */
2364 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2365 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2366 else
2367 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2368 }
2369
2370 /* Issue a global reset */
2371 e1000_reset_hw(&adapter->hw);
2372 if (adapter->hw.mac.type >= e1000_82544)
2373 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
6d5e2922 2374 em_disable_aspm(adapter);
2d0e5700 2375
9c80d176
SZ
2376 if (e1000_init_hw(&adapter->hw) < 0) {
2377 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2378 return (EIO);
984263bc
MD
2379 }
2380
2d0e5700
SZ
2381 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2382 e1000_get_phy_info(&adapter->hw);
9c80d176 2383 e1000_check_for_link(&adapter->hw);
984263bc 2384
87307ba1 2385 return (0);
984263bc
MD
2386}
2387
984263bc 2388static void
9c80d176 2389em_setup_ifp(struct adapter *adapter)
984263bc 2390{
9c80d176 2391 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2392
9c80d176
SZ
2393 if_initname(ifp, device_get_name(adapter->dev),
2394 device_get_unit(adapter->dev));
984263bc
MD
2395 ifp->if_softc = adapter;
2396 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2397 ifp->if_init = em_init;
984263bc
MD
2398 ifp->if_ioctl = em_ioctl;
2399 ifp->if_start = em_start;
9c095379
MD
2400#ifdef DEVICE_POLLING
2401 ifp->if_poll = em_poll;
2402#endif
984263bc 2403 ifp->if_watchdog = em_watchdog;
e26dc3e9 2404 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2405 ifq_set_ready(&ifp->if_snd);
984263bc 2406
9c80d176 2407 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2408
9c80d176
SZ
2409 if (adapter->hw.mac.type >= e1000_82543)
2410 ifp->if_capabilities = IFCAP_HWCSUM;
e095c7aa 2411
9c80d176
SZ
2412 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2413 ifp->if_capenable = ifp->if_capabilities;
984263bc 2414
9c80d176
SZ
2415 if (ifp->if_capenable & IFCAP_TXCSUM)
2416 ifp->if_hwassist = EM_CSUM_FEATURES;
21fa6062 2417
f647ad3d
JS
2418 /*
2419 * Tell the upper layer(s) we support long frames.
2420 */
2421 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2422
87307ba1 2423 /*
984263bc
MD
2424 * Specify the media types supported by this adapter and register
2425 * callbacks to update media and link information
2426 */
9c80d176
SZ
2427 ifmedia_init(&adapter->media, IFM_IMASK,
2428 em_media_change, em_media_status);
2429 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2430 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2431 u_char fiber_type = IFM_1000_SX; /* default type */
2432
2433 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
2434 fiber_type = IFM_1000_LX;
2435 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2436 0, NULL);
87307ba1 2437 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
984263bc
MD
2438 } else {
2439 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2440 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2441 0, NULL);
87307ba1 2442 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2443 0, NULL);
87307ba1 2444 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2445 0, NULL);
9c80d176
SZ
2446 if (adapter->hw.phy.type != e1000_phy_ife) {
2447 ifmedia_add(&adapter->media,
2448 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2449 ifmedia_add(&adapter->media,
2450 IFM_ETHER | IFM_1000_T, 0, NULL);
2451 }
984263bc
MD
2452 }
2453 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2454 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
984263bc
MD
2455}
2456
9c80d176
SZ
2457
2458/*
2459 * Workaround for SmartSpeed on 82541 and 82547 controllers
2460 */
984263bc
MD
2461static void
2462em_smartspeed(struct adapter *adapter)
2463{
f647ad3d
JS
2464 uint16_t phy_tmp;
2465
9c80d176
SZ
2466 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2467 adapter->hw.mac.autoneg == 0 ||
2468 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD
2469 return;
2470
f647ad3d
JS
2471 if (adapter->smartspeed == 0) {
2472 /*
2473 * If Master/Slave config fault is asserted twice,
9c80d176 2474 * we assume back-to-back
f647ad3d 2475 */
9c80d176 2476 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS
2477 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2478 return;
9c80d176 2479 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2480 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ
2481 e1000_read_phy_reg(&adapter->hw,
2482 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS
2483 if (phy_tmp & CR_1000T_MS_ENABLE) {
2484 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ
2485 e1000_write_phy_reg(&adapter->hw,
2486 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2487 adapter->smartspeed++;
9c80d176
SZ
2488 if (adapter->hw.mac.autoneg &&
2489 !e1000_phy_setup_autoneg(&adapter->hw) &&
2490 !e1000_read_phy_reg(&adapter->hw,
2491 PHY_CONTROL, &phy_tmp)) {
2492 phy_tmp |= MII_CR_AUTO_NEG_EN |
2493 MII_CR_RESTART_AUTO_NEG;
2494 e1000_write_phy_reg(&adapter->hw,
2495 PHY_CONTROL, phy_tmp);
f647ad3d
JS
2496 }
2497 }
2498 }
87307ba1 2499 return;
f647ad3d
JS
2500 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2501 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2502 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2503 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ
2504 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2505 if (adapter->hw.mac.autoneg &&
2506 !e1000_phy_setup_autoneg(&adapter->hw) &&
2507 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2508 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2509 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS
2510 }
2511 }
9c80d176 2512
f647ad3d
JS
2513 /* Restart process after EM_SMARTSPEED_MAX iterations */
2514 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2515 adapter->smartspeed = 0;
984263bc
MD
2516}
2517
9ccd8c1f
JS
2518static int
2519em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2520 struct em_dma_alloc *dma)
9ccd8c1f 2521{
9c80d176
SZ
2522 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2523 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2524 &dma->dma_tag, &dma->dma_map,
2525 &dma->dma_paddr);
2526 if (dma->dma_vaddr == NULL)
2527 return ENOMEM;
2528 else
2529 return 0;
9ccd8c1f
JS
2530}
2531
2532static void
2533em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2534{
9c80d176
SZ
2535 if (dma->dma_tag == NULL)
2536 return;
2537 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2538 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2539 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD
2540}
2541
984263bc 2542static int
9c80d176 2543em_create_tx_ring(struct adapter *adapter)
984263bc 2544{
9c80d176 2545 device_t dev = adapter->dev;
1eca7b82 2546 struct em_buffer *tx_buffer;
1eca7b82
SZ
2547 int error, i;
2548
87307ba1
SZ
2549 adapter->tx_buffer_area =
2550 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2551 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2552
9c80d176
SZ
2553 /*
2554 * Create DMA tags for tx buffers
2555 */
2556 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2557 1, 0, /* alignment, bounds */
2558 BUS_SPACE_MAXADDR, /* lowaddr */
2559 BUS_SPACE_MAXADDR, /* highaddr */
2560 NULL, NULL, /* filter, filterarg */
2561 EM_TSO_SIZE, /* maxsize */
2562 EM_MAX_SCATTER, /* nsegments */
2563 EM_MAX_SEGSIZE, /* maxsegsize */
2564 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2565 BUS_DMA_ONEBPAGE, /* flags */
2566 &adapter->txtag);
2567 if (error) {
2568 device_printf(dev, "Unable to allocate TX DMA tag\n");
2569 kfree(adapter->tx_buffer_area, M_DEVBUF);
2570 adapter->tx_buffer_area = NULL;
2571 return error;
2572 }
2573
2574 /*
2575 * Create DMA maps for tx buffers
2576 */
1eca7b82 2577 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ
2578 tx_buffer = &adapter->tx_buffer_area[i];
2579
2580 error = bus_dmamap_create(adapter->txtag,
2581 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2582 &tx_buffer->map);
1eca7b82 2583 if (error) {
9c80d176
SZ
2584 device_printf(dev, "Unable to create TX DMA map\n");
2585 em_destroy_tx_ring(adapter, i);
2586 return error;
1eca7b82 2587 }
1eca7b82 2588 }
9c80d176
SZ
2589 return (0);
2590}
9ccd8c1f 2591
9c80d176
SZ
2592static void
2593em_init_tx_ring(struct adapter *adapter)
2594{
2595 /* Clear the old ring contents */
2596 bzero(adapter->tx_desc_base,
2597 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2598
2599 /* Reset state */
87307ba1
SZ
2600 adapter->next_avail_tx_desc = 0;
2601 adapter->next_tx_to_clean = 0;
984263bc 2602 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD
2603}
2604
984263bc 2605static void
9c80d176 2606em_init_tx_unit(struct adapter *adapter)
984263bc 2607{
9c80d176 2608 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS
2609 uint64_t bus_addr;
2610
984263bc 2611 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2612 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ
2613 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2614 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2615 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2616 (uint32_t)(bus_addr >> 32));
2617 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2618 (uint32_t)bus_addr);
984263bc 2619 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ
2620 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2621 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2622
984263bc 2623 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ
2624 switch (adapter->hw.mac.type) {
2625 case e1000_82542:
2626 tipg = DEFAULT_82542_TIPG_IPGT;
2627 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2628 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2629 break;
9c80d176
SZ
2630
2631 case e1000_80003es2lan:
2632 tipg = DEFAULT_82543_TIPG_IPGR1;
2633 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2634 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2635 break;
9c80d176 2636
984263bc 2637 default:
9c80d176
SZ
2638 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2639 adapter->hw.phy.media_type ==
2640 e1000_media_type_internal_serdes)
2641 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2642 else
9c80d176
SZ
2643 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2644 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2645 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2646 break;
2647 }
2648
2649 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ
2650
2651 /* NOTE: 0 is not allowed for TIDV */
2652 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2653 if(adapter->hw.mac.type >= e1000_82540)
2654 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2655
9c80d176
SZ
2656 if (adapter->hw.mac.type == e1000_82571 ||
2657 adapter->hw.mac.type == e1000_82572) {
2658 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2659 tarc |= SPEED_MODE_BIT;
2660 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2661 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2662 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2663 tarc |= 1;
2664 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2665 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2666 tarc |= 1;
2667 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ
2668 }
2669
984263bc 2670 /* Program the Transmit Control Register */
9c80d176
SZ
2671 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2672 tctl &= ~E1000_TCTL_CT;
2673 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2674 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2675
2676 if (adapter->hw.mac.type >= e1000_82571)
2677 tctl |= E1000_TCTL_MULR;
1eca7b82 2678
87307ba1 2679 /* This write will effectively turn on the transmit unit. */
9c80d176 2680 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
2681}
2682
984263bc 2683static void
9c80d176 2684em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2685{
f647ad3d
JS
2686 struct em_buffer *tx_buffer;
2687 int i;
984263bc 2688
9c80d176
SZ
2689 if (adapter->tx_buffer_area == NULL)
2690 return;
984263bc 2691
9c80d176
SZ
2692 for (i = 0; i < ndesc; i++) {
2693 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2694
9c80d176
SZ
2695 KKASSERT(tx_buffer->m_head == NULL);
2696 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2697 }
9c80d176
SZ
2698 bus_dma_tag_destroy(adapter->txtag);
2699
2700 kfree(adapter->tx_buffer_area, M_DEVBUF);
2701 adapter->tx_buffer_area = NULL;
984263bc
MD
2702}
2703
9c80d176
SZ
2704/*
2705 * The offload context needs to be set when we transfer the first
2706 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2707 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ
2708 *
2709 * If the new packet's ether header length, ip header length and
2710 * csum offloading type are same as the previous packet, we should
2711 * avoid allocating a new csum context descriptor; mainly to take
2712 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ
2713 *
2714 * This function returns number of TX descrptors allocated for
2715 * csum context.
9c80d176 2716 */
9f60d74b 2717static int
9c80d176
SZ
2718em_txcsum(struct adapter *adapter, struct mbuf *mp,
2719 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2720{
9c80d176 2721 struct e1000_context_desc *TXD;
984263bc 2722 struct em_buffer *tx_buffer;
9c80d176 2723 struct ether_vlan_header *eh;
51e6819f
SZ
2724 struct ip *ip;
2725 int curr_txd, ehdrlen, csum_flags;
9c80d176
SZ
2726 uint32_t cmd, hdr_len, ip_hlen;
2727 uint16_t etype;
9c80d176 2728
9c80d176
SZ
2729 /*
2730 * Determine where frame payload starts.
2731 * Jump over vlan headers if already present,
2732 * helpful for QinQ too.
2733 */
252dfd0d 2734 KASSERT(mp->m_len >= ETHER_HDR_LEN,
ed20d0e3 2735 ("em_txcsum_pullup is not called (eh)?"));
9c80d176
SZ
2736 eh = mtod(mp, struct ether_vlan_header *);
2737 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
252dfd0d 2738 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
ed20d0e3 2739 ("em_txcsum_pullup is not called (evh)?"));
9c80d176
SZ
2740 etype = ntohs(eh->evl_proto);
2741 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
984263bc 2742 } else {
9c80d176
SZ
2743 etype = ntohs(eh->evl_encap_proto);
2744 ehdrlen = ETHER_HDR_LEN;
984263bc
MD
2745 }
2746
1eca7b82 2747 /*
002b3a05 2748 * We only support TCP/UDP for IPv4 for the moment.
9c80d176 2749 * TODO: Support SCTP too when it hits the tree.
984263bc 2750 */
51e6819f 2751 if (etype != ETHERTYPE_IP)
9f60d74b 2752 return 0;
002b3a05 2753
51e6819f 2754 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
ed20d0e3 2755 ("em_txcsum_pullup is not called (eh+ip_vhl)?"));
9c80d176 2756
51e6819f
SZ
2757 /* NOTE: We could only safely access ip.ip_vhl part */
2758 ip = (struct ip *)(mp->m_data + ehdrlen);
2759 ip_hlen = ip->ip_hl << 2;
984263bc 2760
51e6819f
SZ
2761 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2762
2763 if (adapter->csum_ehlen == ehdrlen &&
2764 adapter->csum_iphlen == ip_hlen &&
2765 adapter->csum_flags == csum_flags) {
2766 /*
2767 * Same csum offload context as the previous packets;
2768 * just return.
2769 */
2770 *txd_upper = adapter->csum_txd_upper;
2771 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2772 return 0;
984263bc
MD
2773 }
2774
51e6819f
SZ
2775 /*
2776 * Setup a new csum offload context.
2777 */
2778
2779 curr_txd = adapter->next_avail_tx_desc;
2780 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2781 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2782
2783 cmd = 0;
2784
2785 /* Setup of IP header checksum. */
2786 if (csum_flags & CSUM_IP) {
2787 /*
2788 * Start offset for header checksum calculation.
2789 * End offset for header checksum calculation.
2790 * Offset of place to put the checksum.
2791 */
2792 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2793 TXD->lower_setup.ip_fields.ipcse =
2794 htole16(ehdrlen + ip_hlen - 1);
2795 TXD->lower_setup.ip_fields.ipcso =
2796 ehdrlen + offsetof(struct ip, ip_sum);
2797 cmd |= E1000_TXD_CMD_IP;
2798 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2799 }
2800 hdr_len = ehdrlen + ip_hlen;
2801
2802 if (csum_flags & CSUM_TCP) {
002b3a05
SZ
2803 /*
2804 * Start offset for payload checksum calculation.
2805 * End offset for payload checksum calculation.
2806 * Offset of place to put the checksum.
2807 */
2808 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2809 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2810 TXD->upper_setup.tcp_fields.tucso =
2811 hdr_len + offsetof(struct tcphdr, th_sum);
2812 cmd |= E1000_TXD_CMD_TCP;
2813 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2814 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ
2815 /*
2816 * Start offset for header checksum calculation.
2817 * End offset for header checksum calculation.
2818 * Offset of place to put the checksum.
2819 */
2820 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2821 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2822 TXD->upper_setup.tcp_fields.tucso =
2823 hdr_len + offsetof(struct udphdr, uh_sum);
2824 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ
2825 }
2826
2827 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2828 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ
2829
2830 /* Save the information for this csum offloading context */
2831 adapter->csum_ehlen = ehdrlen;
2832 adapter->csum_iphlen = ip_hlen;
2833 adapter->csum_flags = csum_flags;
2834 adapter->csum_txd_upper = *txd_upper;
2835 adapter->csum_txd_lower = *txd_lower;
2836
9c80d176
SZ
2837 TXD->tcp_seg_setup.data = htole32(0);
2838 TXD->cmd_and_length =
2af74b85 2839 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD
2840
2841 if (++curr_txd == adapter->num_tx_desc)
2842 curr_txd = 0;
2843
9c80d176 2844 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 2845 adapter->num_tx_desc_avail--;
9c80d176 2846
984263bc 2847 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 2848 return 1;
984263bc
MD
2849}
2850
002b3a05
SZ
2851static int
2852em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2853{
2854 struct mbuf *m = *m0;
2855 struct ether_header *eh;
2856 int len;
2857
2858 adapter->tx_csum_try_pullup++;
2859
2860 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2861
2862 if (__predict_false(!M_WRITABLE(m))) {
2863 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2864 adapter->tx_csum_drop1++;
2865 m_freem(m);
2866 *m0 = NULL;
2867 return ENOBUFS;
2868 }
2869 eh = mtod(m, struct ether_header *);
2870
2871 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2872 len += EVL_ENCAPLEN;
2873
3752657e 2874 if (m->m_len < len) {
002b3a05
SZ
2875 adapter->tx_csum_drop2++;
2876 m_freem(m);
2877 *m0 = NULL;
2878 return ENOBUFS;
2879 }
2880 return 0;
2881 }
2882
2883 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2884 adapter->tx_csum_pullup1++;
2885 m = m_pullup(m, ETHER_HDR_LEN);
2886 if (m == NULL) {
2887 adapter->tx_csum_pullup1_failed++;
2888 *m0 = NULL;
2889 return ENOBUFS;
2890 }
2891 *m0 = m;
2892 }
2893 eh = mtod(m, struct ether_header *);
2894
2895 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2896 len += EVL_ENCAPLEN;
2897
3752657e 2898 if (m->m_len < len) {
002b3a05
SZ
2899 adapter->tx_csum_pullup2++;
2900 m = m_pullup(m, len);
2901 if (m == NULL) {
2902 adapter->tx_csum_pullup2_failed++;
2903 *m0 = NULL;
2904 return ENOBUFS;
2905 }
2906 *m0 = m;
2907 }
2908 return 0;
2909}
2910
984263bc 2911static void
87307ba1 2912em_txeof(struct adapter *adapter)
984263bc 2913{
9c80d176 2914 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2915 struct em_buffer *tx_buffer;
2916 int first, num_avail;
2917
2918 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2919 return;
984263bc 2920
f647ad3d
JS
2921 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2922 return;
984263bc 2923
9c80d176 2924 num_avail = adapter->num_tx_desc_avail;
87307ba1 2925 first = adapter->next_tx_to_clean;
9c80d176 2926
9f60d74b 2927 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 2928 struct e1000_tx_desc *tx_desc;
9f60d74b 2929 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 2930
9f60d74b 2931 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ
2932 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2933 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 2934
9f60d74b
SZ
2935 if (++dd_idx == adapter->num_tx_desc)
2936 dd_idx = 0;
9c80d176 2937
9f60d74b 2938 while (first != dd_idx) {
edbfa193
SZ
2939 logif(pkt_txclean);
2940
9f60d74b
SZ
2941 num_avail++;
2942
4e499730 2943 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2944 if (tx_buffer->m_head) {
2945 ifp->if_opackets++;
2946 bus_dmamap_unload(adapter->txtag,
2947 tx_buffer->map);
2948 m_freem(tx_buffer->m_head);
2949 tx_buffer->m_head = NULL;
2950 }
2951
2952 if (++first == adapter->num_tx_desc)
2953 first = 0;
2954 }
87307ba1
SZ
2955 } else {
2956 break;
2957 }
f647ad3d 2958 }
9f60d74b
SZ
2959 adapter->next_tx_to_clean = first;
2960 adapter->num_tx_desc_avail = num_avail;
2961
2962 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2963 adapter->tx_dd_head = 0;
2964 adapter->tx_dd_tail = 0;
2965 }
2966
2967 if (!EM_IS_OACTIVE(adapter)) {
2968 ifp->if_flags &= ~IFF_OACTIVE;
2969
2970 /* All clean, turn off the timer */
2971 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2972 ifp->if_timer = 0;
2973 }
2974}
2975
2976static void
2977em_tx_collect(struct adapter *adapter)
2978{
2979 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2980 struct em_buffer *tx_buffer;
2981 int tdh, first, num_avail, dd_idx = -1;
2982
2983 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2984 return;
2985
2986 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2987 if (tdh == adapter->next_tx_to_clean)
2988 return;
2989
2990 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2991 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2992
2993 num_avail = adapter->num_tx_desc_avail;
2994 first = adapter->next_tx_to_clean;
2995
2996 while (first != tdh) {
edbfa193
SZ
2997 logif(pkt_txclean);
2998
9f60d74b
SZ
2999 num_avail++;
3000
4e499730 3001 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
3002 if (tx_buffer->m_head) {
3003 ifp->if_opackets++;
3004 bus_dmamap_unload(adapter->txtag,
3005 tx_buffer->map);
3006 m_freem(tx_buffer->m_head);
3007 tx_buffer->m_head = NULL;
3008 }
3009
3010 if (first == dd_idx) {
3011 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3012 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3013 adapter->tx_dd_head = 0;
3014 adapter->tx_dd_tail = 0;
3015 dd_idx = -1;
3016 } else {
3017 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3018 }
3019 }
3020
3021 if (++first == adapter->num_tx_desc)
3022 first = 0;
3023 }
3024 adapter->next_tx_to_clean = first;
9c80d176 3025 adapter->num_tx_desc_avail = num_avail;
984263bc 3026
9f60d74b 3027 if (!EM_IS_OACTIVE(adapter)) {
9c80d176 3028 ifp->if_flags &= ~IFF_OACTIVE;
afa68aa1 3029
9c80d176
SZ
3030 /* All clean, turn off the timer */
3031 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3032 ifp->if_timer = 0;
3033 }
3034}
984263bc 3035
9c80d176
SZ
3036/*
3037 * When Link is lost sometimes there is work still in the TX ring
3038 * which will result in a watchdog, rather than allow that do an
3039 * attempted cleanup and then reinit here. Note that this has been
3040 * seens mostly with fiber adapters.
3041 */
3042static void
3043em_tx_purge(struct adapter *adapter)
3044{
3045 struct ifnet *ifp = &adapter->arpcom.ac_if;
3046
3047 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 3048 em_tx_collect(adapter);
9c80d176
SZ
3049 if (ifp->if_timer) {
3050 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 3051 ifp->if_timer = 0;
9c80d176
SZ
3052 em_init(adapter);
3053 }
f647ad3d 3054 }
984263bc
MD
3055}
3056
984263bc 3057static int
9c80d176 3058em_newbuf(struct adapter *adapter, int i, int init)
984263bc 3059{
9c80d176
SZ
3060 struct mbuf *m;
3061 bus_dma_segment_t seg;
3062 bus_dmamap_t map;
9ccd8c1f 3063 struct em_buffer *rx_buffer;
9c80d176
SZ
3064 int error, nseg;
3065
3066 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3067 if (m == NULL) {
3068 adapter->mbuf_cluster_failed++;
3069 if (init) {
3070 if_printf(&adapter->arpcom.ac_if,
3071 "Unable to allocate RX mbuf\n");
984263bc 3072 }
9c80d176 3073 return (ENOBUFS);
984263bc 3074 }
9c80d176 3075 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 3076
9c80d176
SZ
3077 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3078 m_adj(m, ETHER_ALIGN);
9ccd8c1f 3079
9c80d176
SZ
3080 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3081 adapter->rx_sparemap, m,
3082 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 3083 if (error) {
9c80d176
SZ
3084 m_freem(m);
3085 if (init) {
3086 if_printf(&adapter->arpcom.ac_if,
3087 "Unable to load RX mbuf\n");
3088 }
87307ba1 3089 return (error);
9ccd8c1f 3090 }
984263bc 3091
9c80d176
SZ
3092 rx_buffer = &adapter->rx_buffer_area[i];
3093 if (rx_buffer->m_head != NULL)
3094 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3095
3096 map = rx_buffer->map;
3097 rx_buffer->map = adapter->rx_sparemap;
3098 adapter->rx_sparemap = map;
3099
3100 rx_buffer->m_head = m;
3101
3102 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3103 return (0);
984263bc
MD
3104}
3105
984263bc 3106static int
9c80d176 3107em_create_rx_ring(struct adapter *adapter)
984263bc 3108{
9c80d176 3109 device_t dev = adapter->dev;
9ccd8c1f 3110 struct em_buffer *rx_buffer;
9c80d176
SZ
3111 int i, error;
3112
3113 adapter->rx_buffer_area =
3114 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3115 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3116
9c80d176
SZ
3117 /*
3118 * Create DMA tag for rx buffers
3119 */
3120 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3121 1, 0, /* alignment, bounds */
3122 BUS_SPACE_MAXADDR, /* lowaddr */
3123 BUS_SPACE_MAXADDR, /* highaddr */
3124 NULL, NULL, /* filter, filterarg */
3125 MCLBYTES, /* maxsize */
3126 1, /* nsegments */
3127 MCLBYTES, /* maxsegsize */
3128 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3129 &adapter->rxtag);
87307ba1 3130 if (error) {
9c80d176
SZ
3131 device_printf(dev, "Unable to allocate RX DMA tag\n");
3132 kfree(adapter->rx_buffer_area, M_DEVBUF);
3133 adapter->rx_buffer_area = NULL;
3134 return error;
3135 }
3136
3137 /*
3138 * Create spare DMA map for rx buffers
3139 */
3140 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3141 &adapter->rx_sparemap);
3142 if (error) {
3143 device_printf(dev, "Unable to create spare RX DMA map\n");
3144 bus_dma_tag_destroy(adapter->rxtag);
3145 kfree(adapter->rx_buffer_area, M_DEVBUF);
3146 adapter->rx_buffer_area = NULL;
3147 return error;
9ccd8c1f 3148 }
9c80d176
SZ
3149
3150 /*
3151 * Create DMA maps for rx buffers
3152 */
3153 for (i = 0; i < adapter->num_rx_desc; i++) {
3154 rx_buffer = &adapter->rx_buffer_area[i];
3155
3156 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
9ccd8c1f 3157 &rx_buffer->map);
87307ba1 3158 if (error) {
9c80d176
SZ
3159 device_printf(dev, "Unable to create RX DMA map\n");
3160 em_destroy_rx_ring(adapter, i);
3161 return error;
9ccd8c1f 3162 }
984263bc 3163 }
87307ba1 3164 return (0);
984263bc
MD
3165}
3166
984263bc 3167static int
9c80d176 3168em_init_rx_ring(struct adapter *adapter)
984263bc 3169{
9c80d176 3170 int i, error;
984263bc 3171
9c80d176 3172 /* Reset descriptor ring */
87307ba1 3173 bzero(adapter->rx_desc_base,
9c80d176 3174 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
87307ba1 3175
9c80d176
SZ
3176 /* Allocate new ones. */
3177 for (i = 0; i < adapter->num_rx_desc; i++) {
3178 error = em_newbuf(adapter, i, 1);
3179 if (error)
3180 return (error);
3181 }
984263bc
MD
3182
3183 /* Setup our descriptor pointers */
f647ad3d 3184 adapter->next_rx_desc_to_check = 0;
87307ba1
SZ
3185
3186 return (0);
984263bc
MD
3187}
3188
984263bc 3189static void
9c80d176 3190em_init_rx_unit(struct adapter *adapter)
984263bc 3191{
9c80d176 3192 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 3193 uint64_t bus_addr;
2d0e5700 3194 uint32_t rctl;
984263bc 3195
87307ba1
SZ
3196 /*
3197 * Make sure receives are disabled while setting
3198 * up the descriptor ring
3199 */
9c80d176
SZ
3200 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3201 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
984263bc 3202
9c80d176 3203 if (adapter->hw.mac.type >= e1000_82540) {
2d0e5700
SZ
3204 uint32_t itr;
3205
9c80d176
SZ
3206 /*
3207 * Set the interrupt throttling rate. Value is calculated
3208 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3209 */
2d0e5700
SZ
3210 if (adapter->int_throttle_ceil)
3211 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3212 else
3213 itr = 0;
3214 em_set_itr(adapter, itr);
f647ad3d 3215 }
984263bc 3216
9c80d176
SZ
3217 /* Disable accelerated ackknowledge */
3218 if (adapter->hw.mac.type == e1000_82574) {
3219 E1000_WRITE_REG(&adapter->hw,
3220 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3221 }
3222
2d0e5700
SZ
3223 /* Receive Checksum Offload for TCP and UDP */
3224 if (ifp->if_capenable & IFCAP_RXCSUM) {
3225 uint32_t rxcsum;
3226
3227 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3228 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3229 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3230 }
3231
3232 /*
3233 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3234 * long latencies are observed, like Lenovo X60. This
3235 * change eliminates the problem, but since having positive
3236 * values in RDTR is a known source of problems on other
3237 * platforms another solution is being sought.
3238 */
3239 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3240 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3241 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3242 }
3243
3244 /*
3245 * Setup the Base and Length of the Rx Descriptor Ring
3246 */
9ccd8c1f 3247 bus_addr = adapter->rxdma.dma_paddr;
9c80d176
SZ
3248 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3249 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3250 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3251 (uint32_t)(bus_addr >> 32));
3252 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3253 (uint32_t)bus_addr);
984263bc 3254
2d0e5700
SZ
3255 /*
3256 * Setup the HW Rx Head and Tail Descriptor Pointers