[dragonfly.git] / sys / dev / netif / em / if_em.h

/*
 * Copyright (c) 2001-2008, Intel Corporation
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *  3. Neither the name of the Intel Corporation nor the names of its
 *     contributors may be used to endorse or promote products derived from
 *     this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _IF_EM_H_
#define _IF_EM_H_

/* Tunables */

/*
 * EM_TXD: Maximum number of Transmit Descriptors
 * Valid Range: 256 for 82542 and 82543-based adapters
 *              256-4096 for others
 * Default Value: 256
 *   This value is the number of transmit descriptors allocated by the driver.
 *   Increasing this value allows the driver to queue more transmits. Each
 *   descriptor is 16 bytes.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define EM_MIN_TXD			256
#define EM_MAX_TXD_82543		EM_MIN_TXD
#define EM_MAX_TXD			4096
#define EM_DEFAULT_TXD			512

/*
 * EM_RXD - Maximum number of receive Descriptors
 * Valid Range: 256 for 82542 and 82543-based adapters
 *              256-4096 for others
 * Default Value: 256
 *   This value is the number of receive descriptors allocated by the driver.
 *   Increasing this value allows the driver to buffer more incoming packets.
 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
 *   descriptor. The maximum MTU size is 16110.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define EM_MIN_RXD			256
#define EM_MAX_RXD_82543		EM_MIN_RXD
#define EM_MAX_RXD			4096
#define EM_DEFAULT_RXD			512

/*
 * EM_TIDV - Transmit Interrupt Delay Value
 * Valid Range: 0-65535 (0=off)
 * Default Value: 64
 *   This value delays the generation of transmit interrupts in units of
 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
 *   efficiency if properly tuned for specific network traffic. If the
 *   system is reporting dropped transmits, this value may be set too high
 *   causing the driver to run out of available transmit descriptors.
 *
 * NOTE:
 * It is not used.  In DragonFly the TX interrupt moderation is done by
 * conditionally setting RS bit in TX descriptors.  See the description
 * in struct adapter.
 */
#define EM_TIDV				64

/*
 * EM_TADV - Transmit Absolute Interrupt Delay Value
 * (Not valid for 82542/82543/82544)
 * Valid Range: 0-65535 (0=off)
 * Default Value: 64
 *   This value, in units of 1.024 microseconds, limits the delay in which a
 *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
 *   this value ensures that an interrupt is generated after the initial
 *   packet is sent on the wire within the set amount of time.  Proper tuning,
 *   along with EM_TIDV, may improve traffic throughput in specific
 *   network conditions.
 *
 * NOTE:
 * It is not used.  In DragonFly the TX interrupt moderation is done by
 * conditionally setting RS bit in TX descriptors.  See the description
 * in struct adapter.
 */
#define EM_TADV				64

/*
 * Receive Interrupt Delay Timer (Packet Timer)
 *
 * NOTE:
 * RDTR and RADV are deprecated; use ITR instead.  They are only used to
 * workaround hardware bug on certain 82573 based NICs.
 */
#define EM_RDTR_82573			32

/*
 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
 *
 * NOTE:
 * RDTR and RADV are deprecated; use ITR instead.  They are only used to
 * workaround hardware bug on certain 82573 based NICs.
 */
#define EM_RADV_82573			64

/*
 * This parameter controls the duration of transmit watchdog timer.
 */
#define EM_TX_TIMEOUT			5

/* One for TX csum offloading desc, the other 2 are reserved */
#define EM_TX_RESERVED			3

/* Large enough for 16K jumbo frame */
#define EM_TX_SPARE			8

#define EM_TX_OACTIVE_MAX		64

/* Interrupt throttle rate */
#define EM_DEFAULT_ITR			6000

/*
 * This parameter controls whether or not autonegotation is enabled.
 *              0 - Disable autonegotiation
 *              1 - Enable  autonegotiation
 */
#define DO_AUTO_NEG			1

/*
 * This parameter control whether or not the driver will wait for
 * autonegotiation to complete.
 *              1 - Wait for autonegotiation to complete
 *              0 - Don't wait for autonegotiation to complete
 */
#define WAIT_FOR_AUTO_NEG_DEFAULT	0

/* Tunables -- End */

#define AUTONEG_ADV_DEFAULT		(ADVERTISE_10_HALF | \
					 ADVERTISE_10_FULL | \
					 ADVERTISE_100_HALF | \
					 ADVERTISE_100_FULL | \
					 ADVERTISE_1000_FULL)

#define AUTO_ALL_MODES			0

/* PHY master/slave setting */
#define EM_MASTER_SLAVE			e1000_ms_hw_default

/*
 * Micellaneous constants
 */
#define EM_VENDOR_ID			0x8086

#define EM_BAR_MEM			PCIR_BAR(0)
#define EM_BAR_FLASH			PCIR_BAR(1)

#define EM_JUMBO_PBA			0x00000028
#define EM_DEFAULT_PBA			0x00000030
#define EM_SMARTSPEED_DOWNSHIFT		3
#define EM_SMARTSPEED_MAX		15
#define EM_MAX_INTR			10

#define MAX_NUM_MULTICAST_ADDRESSES	128
#define PCI_ANY_ID			(~0U)
#define EM_FC_PAUSE_TIME		1000
#define EM_EEPROM_APME			0x400;

/*
 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
 * also optimize cache line size effect. H/W supports up to cache line size 128.
 */
#define EM_DBA_ALIGN			128

#define SPEED_MODE_BIT			(1 << 21) /* On PCI-E MACs only */

/* PCI Config defines */
#define EM_BAR_TYPE(v)			((v) & EM_BAR_TYPE_MASK)
#define EM_BAR_TYPE_MASK		0x00000001
#define EM_BAR_TYPE_MMEM		0x00000000
#define EM_BAR_TYPE_IO			0x00000001
#define EM_BAR_MEM_TYPE(v)		((v) & EM_BAR_MEM_TYPE_MASK)
#define EM_BAR_MEM_TYPE_MASK		0x00000006
#define EM_BAR_MEM_TYPE_32BIT		0x00000000
#define EM_BAR_MEM_TYPE_64BIT		0x00000004

#define EM_MAX_SCATTER			64
#define EM_TSO_SIZE			(65535 + \
					 sizeof(struct ether_vlan_header))
#define EM_MAX_SEGSIZE			4096
#define EM_MSIX_MASK			0x01F00000 /* For 82574 use */
#define ETH_ZLEN			60

#define EM_CSUM_FEATURES		(CSUM_IP | CSUM_TCP | CSUM_UDP)
#define EM_IPVHL_SIZE			1 /* sizeof(ip.ip_vhl) */
#define EM_TXCSUM_MINHL			(ETHER_HDR_LEN + EVL_ENCAPLEN + \
					 EM_IPVHL_SIZE)

/*
 * 82574 has a nonstandard address for EIAC
 * and since its only used in MSIX, and in
 * the em driver only 82574 uses MSIX we can
 * solve it just using this define.
 */
#define EM_EIAC				0x000DC

/* Used in for 82547 10Mb Half workaround */
#define EM_PBA_BYTES_SHIFT		0xA
#define EM_TX_HEAD_ADDR_SHIFT		7
#define EM_PBA_TX_MASK			0xFFFF0000
#define EM_FIFO_HDR			0x10
#define EM_82547_PKT_THRESH		0x3e0

/*
 * Bus dma allocation structure used by
 * em_dma_malloc and em_dma_free.
 */
struct em_dma_alloc {
	bus_addr_t		dma_paddr;
	void			*dma_vaddr;
	bus_dma_tag_t		dma_tag;
	bus_dmamap_t		dma_map;
};

/* Our adapter structure */
struct adapter {
	struct arpcom		arpcom;
	struct e1000_hw		hw;
	int			flags;
#define EM_FLAG_SHARED_INTR	0x0001
#define EM_FLAG_HAS_MGMT	0x0002
#define EM_FLAG_HAS_AMT		0x0004
#define EM_FLAG_HW_CTRL		0x0008

	/* DragonFly operating-system-specific structures. */
	struct e1000_osdep	osdep;
	device_t		dev;

	bus_dma_tag_t		parent_dtag;

	struct resource		*memory;
	int			memory_rid;
	struct resource		*flash;
	int			flash_rid;

	struct resource		*ioport;
	int			io_rid;

	struct resource		*intr_res;
	void			*intr_tag;
	int			intr_rid;
	int			intr_type;

	struct ifmedia		media;
	struct callout		timer;
	struct callout		tx_fifo_timer;
	int			if_flags;
	int			max_frame_size;
	int			min_frame_size;

	/* WOL register value */
	int			wol;

	/* Multicast array memory */
	uint8_t			*mta;

	/* Info about the board itself */
	uint8_t			link_active;
	uint16_t		link_speed;
	uint16_t		link_duplex;
	uint32_t		smartspeed;
	int			int_throttle_ceil;

	/*
	 * Transmit definitions
	 *
	 * We have an array of num_tx_desc descriptors (handled
	 * by the controller) paired with an array of tx_buffers
	 * (at tx_buffer_area).
	 * The index of the next available descriptor is next_avail_tx_desc.
	 * The number of remaining tx_desc is num_tx_desc_avail.
	 */
	struct em_dma_alloc	txdma;		/* bus_dma glue for tx desc */
	struct e1000_tx_desc	*tx_desc_base;
	struct em_buffer	*tx_buffer_area;
	uint32_t		next_avail_tx_desc;
	uint32_t		next_tx_to_clean;
	int			num_tx_desc_avail;
	int			num_tx_desc;
	bus_dma_tag_t		txtag;		/* dma tag for tx */
	int			spare_tx_desc;
	int			oact_tx_desc;

	/* Saved csum offloading context information */
	int			csum_flags;
	int			csum_ehlen;
	int			csum_iphlen;
	uint32_t		csum_txd_upper;
	uint32_t		csum_txd_lower;

	/*
	 * Variables used to reduce TX interrupt rate and
	 * number of device's TX ring write requests.
	 *
	 * tx_nsegs:
	 * Number of TX descriptors setup so far.
	 *
	 * tx_int_nsegs:
	 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
	 * in the last TX descriptor of the packet, and
	 * tx_nsegs will be reset to 0.  So TX interrupt and
	 * TX ring write request should be generated roughly
	 * every tx_int_nsegs TX descriptors.
	 *
	 * tx_dd[]:
	 * Index of the TX descriptors which have RS bit set,
	 * i.e. DD bit will be set on this TX descriptor after
	 * the data of the TX descriptor are transfered to
	 * hardware's internal packet buffer.  Only the TX
	 * descriptors listed in tx_dd[] will be checked upon
	 * TX interrupt.  This array is used as circular ring.
	 *
	 * tx_dd_tail, tx_dd_head:
	 * Tail and head index of valid elements in tx_dd[].
	 * tx_dd_tail == tx_dd_head means there is no valid
	 * elements in tx_dd[].  tx_dd_tail points to the position
	 * which is one beyond the last valid element in tx_dd[].
	 * tx_dd_head points to the first valid element in
	 * tx_dd[].
	 */
	int			tx_int_nsegs;
	int			tx_nsegs;
	int			tx_dd_tail;
	int			tx_dd_head;
#define EM_TXDD_MAX	64
#define EM_TXDD_SAFE	48 /* must be less than EM_TXDD_MAX */
	int			tx_dd[EM_TXDD_MAX];

	/*
	 * Receive definitions
	 *
	 * we have an array of num_rx_desc rx_desc (handled by the
	 * controller), and paired with an array of rx_buffers
	 * (at rx_buffer_area).
	 * The next pair to check on receive is at offset next_rx_desc_to_check
	 */
	struct em_dma_alloc	rxdma;		/* bus_dma glue for rx desc */
	struct e1000_rx_desc	*rx_desc_base;
	uint32_t		next_rx_desc_to_check;
	uint32_t		rx_buffer_len;
	int			num_rx_desc;
	struct em_buffer	*rx_buffer_area;
	bus_dma_tag_t		rxtag;
	bus_dmamap_t		rx_sparemap;

	/*
	 * First/last mbuf pointers, for
	 * collecting multisegment RX packets.
	 */
	struct mbuf		*fmp;
	struct mbuf		*lmp;

	/* Misc stats maintained by the driver */
	unsigned long		dropped_pkts;
	unsigned long		mbuf_alloc_failed;
	unsigned long		mbuf_cluster_failed;
	unsigned long		no_tx_desc_avail1;
	unsigned long		no_tx_desc_avail2;
	unsigned long		no_tx_map_avail;
	unsigned long		no_tx_dma_setup;
	unsigned long		watchdog_events;
	unsigned long		rx_overruns;
	unsigned long		rx_irq;
	unsigned long		tx_irq;
	unsigned long		link_irq;
	unsigned long		tx_csum_try_pullup;
	unsigned long		tx_csum_pullup1;
	unsigned long		tx_csum_pullup1_failed;
	unsigned long		tx_csum_pullup2;
	unsigned long		tx_csum_pullup2_failed;
	unsigned long		tx_csum_drop1;
	unsigned long		tx_csum_drop2;

	/* sysctl tree glue */
	struct sysctl_ctx_list	sysctl_ctx;
	struct sysctl_oid	*sysctl_tree;

	/* 82547 workaround */
	uint32_t		tx_fifo_size;
	uint32_t		tx_fifo_head;
	uint32_t		tx_fifo_head_addr;
	uint64_t		tx_fifo_reset_cnt;
	uint64_t		tx_fifo_wrk_cnt;
	uint32_t		tx_head_addr;

        /* For 82544 PCIX Workaround */
	boolean_t		pcix_82544;

	struct e1000_hw_stats	stats;
};

struct em_vendor_info {
	uint16_t	vendor_id;
	uint16_t	device_id;
	int		ret;
	const char	*desc;
};

struct em_buffer {
	struct mbuf	*m_head;
	bus_dmamap_t	map;		/* bus_dma map for packet */
};

/* For 82544 PCIX  Workaround */
typedef struct _ADDRESS_LENGTH_PAIR {
	uint64_t	address;
	uint32_t	length;
} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;

typedef struct _DESCRIPTOR_PAIR {
	ADDRESS_LENGTH_PAIR descriptor[4];
	uint32_t	elements;
} DESC_ARRAY, *PDESC_ARRAY;

#define EM_IS_OACTIVE(adapter) \
	((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc)

#define EM_INC_TXDD_IDX(idx) \
do { \
	if (++(idx) == EM_TXDD_MAX) \
		(idx) = 0; \
} while (0)

#endif /* _IF_EM_H_ */
Commit	Line	Data
9c80d176 SZ	1	/*
	2	* Copyright (c) 2001-2008, Intel Corporation
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	*
	8	* 1. Redistributions of source code must retain the above copyright notice,
	9	* this list of conditions and the following disclaimer.
	10	*
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	*
	15	* 3. Neither the name of the Intel Corporation nor the names of its
	16	* contributors may be used to endorse or promote products derived from
	17	* this software without specific prior written permission.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	* POSSIBILITY OF SUCH DAMAGE.
	30	*/
984263bc	31
9c80d176 SZ	32	#ifndef _IF_EM_H_
9c80d176 SZ	33	#define _IF_EM_H_
984263bc	34
984263bc MD	35	/* Tunables */
	36
	37	/*
1eca7b82	38	* EM_TXD: Maximum number of Transmit Descriptors
9f60d74b SZ	39	* Valid Range: 256 for 82542 and 82543-based adapters
9f60d74b SZ	40	* 256-4096 for others
984263bc MD	41	* Default Value: 256
	42	* This value is the number of transmit descriptors allocated by the driver.
	43	* Increasing this value allows the driver to queue more transmits. Each
	44	* descriptor is 16 bytes.
1eca7b82 SZ	45	* Since TDLEN should be multiple of 128bytes, the number of transmit
1eca7b82 SZ	46	* desscriptors should meet the following condition.
9c80d176	47	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc	48	*/
9f60d74b SZ	49	#define EM_MIN_TXD 256
9f60d74b SZ	50	#define EM_MAX_TXD_82543 EM_MIN_TXD
9c80d176	51	#define EM_MAX_TXD 4096
df2de25f	52	#define EM_DEFAULT_TXD 512
984263bc MD	53
984263bc MD	54	/*
1eca7b82	55	* EM_RXD - Maximum number of receive Descriptors
9f60d74b SZ	56	* Valid Range: 256 for 82542 and 82543-based adapters
9f60d74b SZ	57	* 256-4096 for others
984263bc MD	58	* Default Value: 256
	59	* This value is the number of receive descriptors allocated by the driver.
	60	* Increasing this value allows the driver to buffer more incoming packets.
	61	* Each descriptor is 16 bytes. A receive buffer is also allocated for each
	62	* descriptor. The maximum MTU size is 16110.
1eca7b82 SZ	63	* Since TDLEN should be multiple of 128bytes, the number of transmit
1eca7b82 SZ	64	* desscriptors should meet the following condition.
9c80d176	65	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc	66	*/
9f60d74b SZ	67	#define EM_MIN_RXD 256
9f60d74b SZ	68	#define EM_MAX_RXD_82543 EM_MIN_RXD
9c80d176	69	#define EM_MAX_RXD 4096
df2de25f	70	#define EM_DEFAULT_RXD 512
984263bc MD	71
984263bc MD	72	/*
9ccd8c1f	73	* EM_TIDV - Transmit Interrupt Delay Value
984263bc MD	74	* Valid Range: 0-65535 (0=off)
	75	* Default Value: 64
	76	* This value delays the generation of transmit interrupts in units of
	77	* 1.024 microseconds. Transmit interrupt reduction can improve CPU
	78	* efficiency if properly tuned for specific network traffic. If the
	79	* system is reporting dropped transmits, this value may be set too high
	80	* causing the driver to run out of available transmit descriptors.
91e8debf SZ	81	*
	82	* NOTE:
	83	* It is not used. In DragonFly the TX interrupt moderation is done by
	84	* conditionally setting RS bit in TX descriptors. See the description
	85	* in struct adapter.
984263bc	86	*/
9c80d176	87	#define EM_TIDV 64
984263bc MD	88
984263bc MD	89	/*
87307ba1 SZ	90	* EM_TADV - Transmit Absolute Interrupt Delay Value
87307ba1 SZ	91	* (Not valid for 82542/82543/82544)
984263bc MD	92	* Valid Range: 0-65535 (0=off)
	93	* Default Value: 64
	94	* This value, in units of 1.024 microseconds, limits the delay in which a
0d366ee7	95	* transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
984263bc MD	96	* this value ensures that an interrupt is generated after the initial
984263bc MD	97	* packet is sent on the wire within the set amount of time. Proper tuning,
0d366ee7	98	* along with EM_TIDV, may improve traffic throughput in specific
984263bc	99	* network conditions.
91e8debf SZ	100	*
	101	* NOTE:
	102	* It is not used. In DragonFly the TX interrupt moderation is done by
	103	* conditionally setting RS bit in TX descriptors. See the description
	104	* in struct adapter.
984263bc	105	*/
9c80d176	106	#define EM_TADV 64
984263bc MD	107
984263bc MD	108	/*
2cc36323	109	* Receive Interrupt Delay Timer (Packet Timer)
984263bc	110	*
2cc36323 SZ	111	* NOTE:
	112	* RDTR and RADV are deprecated; use ITR instead. They are only used to
	113	* workaround hardware bug on certain 82573 based NICs.
984263bc	114	*/
2cc36323	115	#define EM_RDTR_82573 32
984263bc MD	116
984263bc MD	117	/*
0d366ee7	118	* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
2cc36323 SZ	119	*
	120	* NOTE:
	121	* RDTR and RADV are deprecated; use ITR instead. They are only used to
	122	* workaround hardware bug on certain 82573 based NICs.
984263bc	123	*/
2cc36323	124	#define EM_RADV_82573 64
984263bc MD	125
	126	/*
	127	* This parameter controls the duration of transmit watchdog timer.
	128	*/
9c80d176 SZ	129	#define EM_TX_TIMEOUT 5
9c80d176 SZ	130
dc07210e SZ	131	/* One for TX csum offloading desc, the other 2 are reserved */
dc07210e SZ	132	#define EM_TX_RESERVED 3
9c80d176 SZ	133
	134	/* Large enough for 16K jumbo frame */
	135	#define EM_TX_SPARE 8
	136
9f60d74b SZ	137	#define EM_TX_OACTIVE_MAX 64
9f60d74b SZ	138
9c80d176	139	/* Interrupt throttle rate */
3245f71e	140	#define EM_DEFAULT_ITR 6000
984263bc MD	141
984263bc MD	142	/*
984263bc MD	143	* This parameter controls whether or not autonegotation is enabled.
	144	* 0 - Disable autonegotiation
	145	* 1 - Enable autonegotiation
	146	*/
9c80d176	147	#define DO_AUTO_NEG 1
984263bc MD	148
	149	/*
	150	* This parameter control whether or not the driver will wait for
	151	* autonegotiation to complete.
	152	* 1 - Wait for autonegotiation to complete
	153	* 0 - Don't wait for autonegotiation to complete
	154	*/
9c80d176	155	#define WAIT_FOR_AUTO_NEG_DEFAULT 0
984263bc MD	156
	157	/* Tunables -- End */
	158
9c80d176 SZ	159	#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF \| \
	160	ADVERTISE_10_FULL \| \
	161	ADVERTISE_100_HALF \| \
	162	ADVERTISE_100_FULL \| \
	163	ADVERTISE_1000_FULL)
984263bc	164
9c80d176	165	#define AUTO_ALL_MODES 0
984263bc	166
9c80d176 SZ	167	/* PHY master/slave setting */
9c80d176 SZ	168	#define EM_MASTER_SLAVE e1000_ms_hw_default
984263bc	169
9c80d176 SZ	170	/*
	171	* Micellaneous constants
	172	*/
	173	#define EM_VENDOR_ID 0x8086
87307ba1	174
9c80d176 SZ	175	#define EM_BAR_MEM PCIR_BAR(0)
	176	#define EM_BAR_FLASH PCIR_BAR(1)
	177
	178	#define EM_JUMBO_PBA 0x00000028
	179	#define EM_DEFAULT_PBA 0x00000030
	180	#define EM_SMARTSPEED_DOWNSHIFT 3
	181	#define EM_SMARTSPEED_MAX 15
	182	#define EM_MAX_INTR 10
	183
	184	#define MAX_NUM_MULTICAST_ADDRESSES 128
	185	#define PCI_ANY_ID (~0U)
	186	#define EM_FC_PAUSE_TIME 1000
	187	#define EM_EEPROM_APME 0x400;
87307ba1 SZ	188
	189	/*
	190	* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
	191	* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
	192	* also optimize cache line size effect. H/W supports up to cache line size 128.
	193	*/
	194	#define EM_DBA_ALIGN 128
	195
9c80d176	196	#define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
87307ba1 SZ	197
	198	/* PCI Config defines */
	199	#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
	200	#define EM_BAR_TYPE_MASK 0x00000001
	201	#define EM_BAR_TYPE_MMEM 0x00000000
	202	#define EM_BAR_TYPE_IO 0x00000001
	203	#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
	204	#define EM_BAR_MEM_TYPE_MASK 0x00000006
	205	#define EM_BAR_MEM_TYPE_32BIT 0x00000000
	206	#define EM_BAR_MEM_TYPE_64BIT 0x00000004
	207
9c80d176 SZ	208	#define EM_MAX_SCATTER 64
	209	#define EM_TSO_SIZE (65535 + \
	210	sizeof(struct ether_vlan_header))
	211	#define EM_MAX_SEGSIZE 4096
	212	#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
	213	#define ETH_ZLEN 60
	214
	215	#define EM_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP)
002b3a05 SZ	216	#define EM_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
	217	#define EM_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
	218	EM_IPVHL_SIZE)
9c80d176	219
87307ba1	220	/*
9c80d176 SZ	221	* 82574 has a nonstandard address for EIAC
	222	* and since its only used in MSIX, and in
	223	* the em driver only 82574 uses MSIX we can
	224	* solve it just using this define.
87307ba1	225	*/
9c80d176	226	#define EM_EIAC 0x000DC
984263bc	227
9c80d176 SZ	228	/* Used in for 82547 10Mb Half workaround */
	229	#define EM_PBA_BYTES_SHIFT 0xA
	230	#define EM_TX_HEAD_ADDR_SHIFT 7
	231	#define EM_PBA_TX_MASK 0xFFFF0000
	232	#define EM_FIFO_HDR 0x10
	233	#define EM_82547_PKT_THRESH 0x3e0
984263bc	234
9ccd8c1f JS	235	/*
9ccd8c1f JS	236	* Bus dma allocation structure used by
f7b52b45	237	* em_dma_malloc and em_dma_free.
9ccd8c1f JS	238	*/
	239	struct em_dma_alloc {
	240	bus_addr_t dma_paddr;
9c80d176	241	void *dma_vaddr;
9ccd8c1f JS	242	bus_dma_tag_t dma_tag;
9ccd8c1f JS	243	bus_dmamap_t dma_map;
9ccd8c1f	244	};
984263bc	245
9c80d176 SZ	246	/* Our adapter structure */
	247	struct adapter {
	248	struct arpcom arpcom;
	249	struct e1000_hw hw;
87ab432b	250	int flags;
79878f87 SZ	251	#define EM_FLAG_SHARED_INTR 0x0001
	252	#define EM_FLAG_HAS_MGMT 0x0002
	253	#define EM_FLAG_HAS_AMT 0x0004
	254	#define EM_FLAG_HW_CTRL 0x0008
984263bc	255
9c80d176 SZ	256	/* DragonFly operating-system-specific structures. */
	257	struct e1000_osdep osdep;
	258	device_t dev;
0d366ee7	259
9c80d176	260	bus_dma_tag_t parent_dtag;
0d366ee7	261
9c80d176 SZ	262	struct resource *memory;
	263	int memory_rid;
	264	struct resource *flash;
	265	int flash_rid;
9ccd8c1f	266
9c80d176 SZ	267	struct resource *ioport;
	268	int io_rid;
	269
	270	struct resource *intr_res;
	271	void *intr_tag;
	272	int intr_rid;
053f3ae6	273	int intr_type;
9c80d176 SZ	274
	275	struct ifmedia media;
	276	struct callout timer;
	277	struct callout tx_fifo_timer;
	278	int if_flags;
	279	int max_frame_size;
	280	int min_frame_size;
	281
79878f87	282	/* WOL register value */
9c80d176	283	int wol;
2d0e5700 SZ	284
	285	/* Multicast array memory */
	286	uint8_t *mta;
984263bc MD	287
984263bc MD	288	/* Info about the board itself */
9c80d176 SZ	289	uint8_t link_active;
	290	uint16_t link_speed;
	291	uint16_t link_duplex;
	292	uint32_t smartspeed;
9c80d176	293	int int_throttle_ceil;
984263bc MD	294
984263bc MD	295	/*
87307ba1 SZ	296	* Transmit definitions
	297	*
	298	* We have an array of num_tx_desc descriptors (handled
	299	* by the controller) paired with an array of tx_buffers
	300	* (at tx_buffer_area).
	301	* The index of the next available descriptor is next_avail_tx_desc.
	302	* The number of remaining tx_desc is num_tx_desc_avail.
	303	*/
9ccd8c1f	304	struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
9c80d176	305	struct e1000_tx_desc *tx_desc_base;
9f60d74b	306	struct em_buffer *tx_buffer_area;
87307ba1 SZ	307	uint32_t next_avail_tx_desc;
87307ba1 SZ	308	uint32_t next_tx_to_clean;
9c80d176 SZ	309	int num_tx_desc_avail;
9c80d176 SZ	310	int num_tx_desc;
9ccd8c1f	311	bus_dma_tag_t txtag; /* dma tag for tx */
9c80d176	312	int spare_tx_desc;
9f60d74b	313	int oact_tx_desc;
984263bc	314
51e6819f SZ	315	/* Saved csum offloading context information */
	316	int csum_flags;
	317	int csum_ehlen;
	318	int csum_iphlen;
	319	uint32_t csum_txd_upper;
	320	uint32_t csum_txd_lower;
	321
	322	/*
9f60d74b SZ	323	* Variables used to reduce TX interrupt rate and
	324	* number of device's TX ring write requests.
	325	*
	326	* tx_nsegs:
	327	* Number of TX descriptors setup so far.
	328	*
	329	* tx_int_nsegs:
	330	* Once tx_nsegs > tx_int_nsegs, RS bit will be set
	331	* in the last TX descriptor of the packet, and
	332	* tx_nsegs will be reset to 0. So TX interrupt and
	333	* TX ring write request should be generated roughly
	334	* every tx_int_nsegs TX descriptors.
	335	*
	336	* tx_dd[]:
	337	* Index of the TX descriptors which have RS bit set,
	338	* i.e. DD bit will be set on this TX descriptor after
	339	* the data of the TX descriptor are transfered to
	340	* hardware's internal packet buffer. Only the TX
	341	* descriptors listed in tx_dd[] will be checked upon
	342	* TX interrupt. This array is used as circular ring.
	343	*
	344	* tx_dd_tail, tx_dd_head:
	345	* Tail and head index of valid elements in tx_dd[].
	346	* tx_dd_tail == tx_dd_head means there is no valid
	347	* elements in tx_dd[]. tx_dd_tail points to the position
	348	* which is one beyond the last valid element in tx_dd[].
	349	* tx_dd_head points to the first valid element in
	350	* tx_dd[].
	351	*/
	352	int tx_int_nsegs;
	353	int tx_nsegs;
	354	int tx_dd_tail;
	355	int tx_dd_head;
	356	#define EM_TXDD_MAX 64
af2ee69f	357	#define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */
9f60d74b SZ	358	int tx_dd[EM_TXDD_MAX];
	359
	360	/*
984263bc	361	* Receive definitions
87307ba1 SZ	362	*
	363	* we have an array of num_rx_desc rx_desc (handled by the
	364	* controller), and paired with an array of rx_buffers
	365	* (at rx_buffer_area).
	366	* The next pair to check on receive is at offset next_rx_desc_to_check
	367	*/
9ccd8c1f	368	struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
9c80d176	369	struct e1000_rx_desc *rx_desc_base;
87307ba1	370	uint32_t next_rx_desc_to_check;
87307ba1	371	uint32_t rx_buffer_len;
9c80d176	372	int num_rx_desc;
87307ba1	373	struct em_buffer *rx_buffer_area;
9ccd8c1f	374	bus_dma_tag_t rxtag;
9c80d176	375	bus_dmamap_t rx_sparemap;
984263bc	376
87307ba1 SZ	377	/*
	378	* First/last mbuf pointers, for
	379	* collecting multisegment RX packets.
	380	*/
	381	struct mbuf *fmp;
	382	struct mbuf *lmp;
984263bc	383
9c80d176 SZ	384	/* Misc stats maintained by the driver */
	385	unsigned long dropped_pkts;
	386	unsigned long mbuf_alloc_failed;
	387	unsigned long mbuf_cluster_failed;
	388	unsigned long no_tx_desc_avail1;
	389	unsigned long no_tx_desc_avail2;
	390	unsigned long no_tx_map_avail;
	391	unsigned long no_tx_dma_setup;
	392	unsigned long watchdog_events;
	393	unsigned long rx_overruns;
	394	unsigned long rx_irq;
	395	unsigned long tx_irq;
	396	unsigned long link_irq;
002b3a05 SZ	397	unsigned long tx_csum_try_pullup;
	398	unsigned long tx_csum_pullup1;
	399	unsigned long tx_csum_pullup1_failed;
	400	unsigned long tx_csum_pullup2;
	401	unsigned long tx_csum_pullup2_failed;
	402	unsigned long tx_csum_drop1;
	403	unsigned long tx_csum_drop2;
9c80d176 SZ	404
9c80d176 SZ	405	/* sysctl tree glue */
87307ba1 SZ	406	struct sysctl_ctx_list sysctl_ctx;
87307ba1 SZ	407	struct sysctl_oid *sysctl_tree;
984263bc	408
9c80d176 SZ	409	/* 82547 workaround */
	410	uint32_t tx_fifo_size;
	411	uint32_t tx_fifo_head;
	412	uint32_t tx_fifo_head_addr;
	413	uint64_t tx_fifo_reset_cnt;
	414	uint64_t tx_fifo_wrk_cnt;
	415	uint32_t tx_head_addr;
	416
	417	/* For 82544 PCIX Workaround */
	418	boolean_t pcix_82544;
9c80d176 SZ	419
	420	struct e1000_hw_stats stats;
	421	};
	422
	423	struct em_vendor_info {
	424	uint16_t vendor_id;
	425	uint16_t device_id;
96ced48a	426	int ret;
9c80d176 SZ	427	const char *desc;
	428	};
	429
	430	struct em_buffer {
9c80d176 SZ	431	struct mbuf *m_head;
9c80d176 SZ	432	bus_dmamap_t map; /* bus_dma map for packet */
984263bc MD	433	};
984263bc MD	434
9c80d176 SZ	435	/* For 82544 PCIX Workaround */
	436	typedef struct _ADDRESS_LENGTH_PAIR {
	437	uint64_t address;
	438	uint32_t length;
	439	} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
	440
	441	typedef struct _DESCRIPTOR_PAIR {
	442	ADDRESS_LENGTH_PAIR descriptor[4];
	443	uint32_t elements;
	444	} DESC_ARRAY, *PDESC_ARRAY;
	445
	446	#define EM_IS_OACTIVE(adapter) \
9f60d74b SZ	447	((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc)
	448
	449	#define EM_INC_TXDD_IDX(idx) \
	450	do { \
	451	if (++(idx) == EM_TXDD_MAX) \
	452	(idx) = 0; \
	453	} while (0)
9c80d176 SZ	454
9c80d176 SZ	455	#endif /* _IF_EM_H_ */