Remove upc_{control,register} syscalls and everything that has to do with it.
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD
41#include "use_npx.h"
42#include "use_isa.h"
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43#include "opt_compat.h"
44#include "opt_cpu.h"
45#include "opt_ddb.h"
46#include "opt_directio.h"
47#include "opt_inet.h"
48#include "opt_ipx.h"
49#include "opt_maxmem.h"
50#include "opt_msgbuf.h"
51#include "opt_perfmon.h"
52#include "opt_swap.h"
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53#include "opt_userconfig.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sysproto.h>
58#include <sys/signalvar.h>
59#include <sys/kernel.h>
60#include <sys/linker.h>
61#include <sys/malloc.h>
62#include <sys/proc.h>
895c1f85 63#include <sys/priv.h>
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64#include <sys/buf.h>
65#include <sys/reboot.h>
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66#include <sys/mbuf.h>
67#include <sys/msgbuf.h>
68#include <sys/sysent.h>
69#include <sys/sysctl.h>
70#include <sys/vmmeter.h>
71#include <sys/bus.h>
cb7f4ab1 72#include <sys/usched.h>
527fddf7 73#include <sys/reg.h>
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74
75#include <vm/vm.h>
76#include <vm/vm_param.h>
77#include <sys/lock.h>
78#include <vm/vm_kern.h>
79#include <vm/vm_object.h>
80#include <vm/vm_page.h>
81#include <vm/vm_map.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_extern.h>
84
4b5f931b 85#include <sys/thread2.h>
684a93c4 86#include <sys/mplock2.h>
320c681e 87#include <sys/mutex2.h>
4b5f931b 88
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89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
984263bc 95#include <machine/cpu.h>
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96#include <machine/clock.h>
97#include <machine/specialreg.h>
98#include <machine/bootinfo.h>
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99#include <machine/md_var.h>
100#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 101#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 102#include <machine/smp.h>
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103#ifdef PERFMON
104#include <machine/perfmon.h>
105#endif
106#include <machine/cputypes.h>
87cf6827 107#include <machine/intr_machdep.h>
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108
109#ifdef OLD_BUS_ARCH
21ce0dfa 110#include <bus/isa/isa_device.h>
984263bc 111#endif
87cf6827 112#include <machine_base/isa/isa_intr.h>
1f2de5d4 113#include <bus/isa/rtc.h>
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114#include <machine/vm86.h>
115#include <sys/random.h>
116#include <sys/ptrace.h>
117#include <machine/sigframe.h>
118
30c5f287 119#include <sys/machintr.h>
9284cddf 120#include <machine_base/icu/icu_abi.h>
7265a4fe 121#include <machine_base/icu/elcr_var.h>
1d6d7089 122#include <machine_base/apic/lapic.h>
ed4d621d 123#include <machine_base/apic/ioapic.h>
a3dd9120 124#include <machine_base/apic/ioapic_abi.h>
d904d4d9 125#include <machine/mptable.h>
30c5f287 126
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127#define PHYSMAP_ENTRIES 10
128
d678dc17
MN
129extern void init386(int first);
130extern void dblfault_handler(void);
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131
132extern void printcpuinfo(void); /* XXX header file */
133extern void finishidentcpu(void);
134extern void panicifcpuunsupported(void);
135extern void initializecpu(void);
136
d678dc17 137static void cpu_startup(void *);
d883128f
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138static void pic_finish(void *);
139static void cpu_finish(void *);
642a6e88 140#ifndef CPU_DISABLE_SSE
d678dc17
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141static void set_fpregs_xmm(struct save87 *, struct savexmm *);
142static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 143#endif /* CPU_DISABLE_SSE */
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144#ifdef DIRECTIO
145extern void ffs_rawread_setup(void);
146#endif /* DIRECTIO */
8a8d5d85 147static void init_locks(void);
984263bc 148
7c006a9e 149SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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150SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
151SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
984263bc 152
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153int _udatasel, _ucodesel;
154u_int atdevbase;
c2751817 155int64_t tsc_offsets[MAXCPU];
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156
157#if defined(SWTCH_OPTIM_STATS)
158extern int swtch_optim_stats;
159SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
160 CTLFLAG_RD, &swtch_optim_stats, 0, "");
161SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
162 CTLFLAG_RD, &tlb_flush_count, 0, "");
163#endif
164
39d69dae 165long physmem = 0;
984263bc 166
1876681a
SZ
167u_long ebda_addr = 0;
168
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169int imcr_present = 0;
170
2abaa030 171int naps = 0; /* # of Applications processors */
320c681e 172struct mtx dt_lock; /* lock for GDT and LDT */
2abaa030 173
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174u_int base_memory;
175
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176static int
177sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
178{
39d69dae
AH
179 u_long pmem = ctob(physmem);
180
181 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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182 return (error);
183}
184
39d69dae 185SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 186 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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187
188static int
189sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
190{
191 int error = sysctl_handle_int(oidp, 0,
12e4aaff 192 ctob(physmem - vmstats.v_wire_count), req);
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193 return (error);
194}
195
196SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
197 0, 0, sysctl_hw_usermem, "IU", "");
198
199static int
200sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
201{
202 int error = sysctl_handle_int(oidp, 0,
203 i386_btop(avail_end - avail_start), req);
204 return (error);
205}
206
207SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
208 0, 0, sysctl_hw_availpages, "I", "");
209
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210vm_paddr_t Maxmem;
211vm_paddr_t Realmem;
984263bc 212
ff1a75a1 213vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH
214vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
215
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216
217static vm_offset_t buffer_sva, buffer_eva;
218vm_offset_t clean_sva, clean_eva;
219static vm_offset_t pager_sva, pager_eva;
220static struct trapframe proc0_tf;
221
222static void
f123d5a1 223cpu_startup(void *dummy)
984263bc 224{
c9faf524 225 caddr_t v;
984263bc 226 vm_size_t size = 0;
e4846942 227 vm_offset_t firstaddr;
984263bc 228
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229 /*
230 * Good {morning,afternoon,evening,night}.
231 */
26be20a0 232 kprintf("%s", version);
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233 startrtclock();
234 printcpuinfo();
235 panicifcpuunsupported();
236#ifdef PERFMON
237 perfmon_init();
238#endif
15dc6550 239 kprintf("real memory = %ju (%ju MB)\n",
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240 (intmax_t)Realmem,
241 (intmax_t)Realmem / 1024 / 1024);
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242 /*
243 * Display any holes after the first chunk of extended memory.
244 */
245 if (bootverbose) {
246 int indx;
247
26be20a0 248 kprintf("Physical memory chunk(s):\n");
984263bc 249 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 250 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 251
26be20a0 252 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
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253 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
254 size1 / PAGE_SIZE);
255 }
256 }
257
258 /*
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259 * Allocate space for system data structures.
260 * The first available kernel virtual address is in "v".
261 * As pages of kernel virtual memory are allocated, "v" is incremented.
262 * As pages of memory are allocated and cleared,
263 * "firstaddr" is incremented.
264 * An index into the kernel page table corresponding to the
265 * virtual memory address maintained in "v" is kept in "mapaddr".
266 */
267
268 /*
269 * Make two passes. The first pass calculates how much memory is
270 * needed and allocates it. The second pass assigns virtual
271 * addresses to the various data structures.
272 */
273 firstaddr = 0;
274again:
275 v = (caddr_t)firstaddr;
276
277#define valloc(name, type, num) \
278 (name) = (type *)v; v = (caddr_t)((name)+(num))
279#define valloclim(name, type, num, lim) \
280 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
281
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282 /*
283 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
284 * For the first 64MB of ram nominally allocate sufficient buffers to
285 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
286 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
287 * the buffer cache we limit the eventual kva reservation to
288 * maxbcache bytes.
289 *
290 * factor represents the 1/4 x ram conversion.
291 */
292 if (nbuf == 0) {
293 int factor = 4 * BKVASIZE / 1024;
294 int kbytes = physmem * (PAGE_SIZE / 1024);
295
296 nbuf = 50;
297 if (kbytes > 4096)
298 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
299 if (kbytes > 65536)
300 nbuf += (kbytes - 65536) * 2 / (factor * 5);
301 if (maxbcache && nbuf > maxbcache / BKVASIZE)
302 nbuf = maxbcache / BKVASIZE;
303 }
304
305 /*
306 * Do not allow the buffer_map to be more then 1/2 the size of the
307 * kernel_map.
308 */
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309 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
310 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
f86b3b54 311 kprintf("Warning: nbufs capped at %ld\n", nbuf);
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312 }
313
948209ce 314 /* limit to 128 on i386 */
74d62460 315 nswbuf = lmax(lmin(nbuf / 4, 128), 16);
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316#ifdef NSWBUF_MIN
317 if (nswbuf < NSWBUF_MIN)
318 nswbuf = NSWBUF_MIN;
319#endif
320#ifdef DIRECTIO
321 ffs_rawread_setup();
322#endif
323
324 valloc(swbuf, struct buf, nswbuf);
325 valloc(buf, struct buf, nbuf);
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326
327 /*
328 * End of first pass, size has been calculated so allocate memory
329 */
330 if (firstaddr == 0) {
331 size = (vm_size_t)(v - firstaddr);
e4846942 332 firstaddr = kmem_alloc(&kernel_map, round_page(size));
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333 if (firstaddr == 0)
334 panic("startup: no room for tables");
335 goto again;
336 }
337
338 /*
339 * End of second pass, addresses have been assigned
340 */
341 if ((vm_size_t)(v - firstaddr) != size)
342 panic("startup: table size inconsistency");
343
e4846942
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344 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
345 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
346 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
347 (nbuf*BKVASIZE));
348 buffer_map.system_map = 1;
349 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
350 (nswbuf*MAXPHYS) + pager_map_size);
351 pager_map.system_map = 1;
984263bc 352
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353#if defined(USERCONFIG)
354 userconfig();
355 cninit(); /* the preferred console may have changed */
356#endif
357
15dc6550 358 kprintf("avail memory = %ju (%ju MB)\n",
79d182b0
MD
359 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
360 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
361 1024 / 1024);
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362
363 /*
364 * Set up buffers, so they can be used to read disk labels.
365 */
366 bufinit();
367 vm_pager_bufferinit();
d883128f
SZ
368}
369
370static void
371cpu_finish(void *dummy __unused)
372{
373 cpu_setregs();
374}
375
376static void
377pic_finish(void *dummy __unused)
378{
379 /* Log ELCR information */
380 elcr_dump();
be1519b3 381
d904d4d9
SZ
382 /* Log MPTABLE information */
383 mptable_pci_int_dump();
384
be1519b3
SZ
385 /* Finalize PIC */
386 MachIntrABI.finalize();
984263bc
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387}
388
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389/*
390 * Send an interrupt to process.
391 *
392 * Stack is set up to allow sigcode stored
393 * at top to call routine, followed by kcall
394 * to sigreturn routine below. After sigreturn
395 * resets the signal mask, the stack, and the
396 * frame pointer, it returns to the user
397 * specified pc, psl.
398 */
984263bc 399void
f123d5a1 400sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 401{
065b709a
SS
402 struct lwp *lp = curthread->td_lwp;
403 struct proc *p = lp->lwp_proc;
984263bc
MD
404 struct trapframe *regs;
405 struct sigacts *psp = p->p_sigacts;
406 struct sigframe sf, *sfp;
407 int oonstack;
408
065b709a
SS
409 regs = lp->lwp_md.md_regs;
410 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
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411
412 /* save user context */
413 bzero(&sf, sizeof(struct sigframe));
414 sf.sf_uc.uc_sigmask = *mask;
065b709a 415 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 416 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 417 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 418
ce3d8c4d
MD
419 /* make the size of the saved context visible to userland */
420 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
421
984263bc 422 /* Allocate and validate space for the signal handler context. */
4643740a 423 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 424 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS
425 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
426 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
427 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 428 } else {
984263bc 429 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 430 }
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MD
431
432 /* Translate the signal is appropriate */
433 if (p->p_sysent->sv_sigtbl) {
434 if (sig <= p->p_sysent->sv_sigsize)
435 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
436 }
437
438 /* Build the argument list for the signal handler. */
439 sf.sf_signum = sig;
440 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 441 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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442 /* Signal handler installed with SA_SIGINFO. */
443 sf.sf_siginfo = (register_t)&sfp->sf_si;
444 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
445
446 /* fill siginfo structure */
447 sf.sf_si.si_signo = sig;
448 sf.sf_si.si_code = code;
449 sf.sf_si.si_addr = (void*)regs->tf_err;
450 }
451 else {
452 /* Old FreeBSD-style arguments. */
453 sf.sf_siginfo = code;
454 sf.sf_addr = regs->tf_err;
455 sf.sf_ahu.sf_handler = catcher;
456 }
457
458 /*
459 * If we're a vm86 process, we want to save the segment registers.
460 * We also change eflags to be our emulated eflags, not the actual
461 * eflags.
462 */
463 if (regs->tf_eflags & PSL_VM) {
464 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 465 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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466
467 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
468 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
469 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
470 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
471
472 if (vm86->vm86_has_vme == 0)
473 sf.sf_uc.uc_mcontext.mc_eflags =
474 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
475 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
476
477 /*
478 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
479 * syscalls made by the signal handler. This just avoids
480 * wasting time for our lazy fixup of such faults. PSL_NT
481 * does nothing in vm86 mode, but vm86 programs can set it
482 * almost legitimately in probes for old cpu types.
483 */
484 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
485 }
486
487 /*
1b251f0a
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488 * Save the FPU state and reinit the FP unit
489 */
490 npxpush(&sf.sf_uc.uc_mcontext);
491
492 /*
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493 * Copy the sigframe out to the user's stack.
494 */
495 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
496 /*
497 * Something is wrong with the stack pointer.
498 * ...Kill the process.
499 */
b276424c 500 sigexit(lp, SIGILL);
984263bc
MD
501 }
502
503 regs->tf_esp = (int)sfp;
504 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE
505
506 /*
507 * i386 abi specifies that the direction flag must be cleared
508 * on function entry
509 */
510 regs->tf_eflags &= ~(PSL_T|PSL_D);
511
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512 regs->tf_cs = _ucodesel;
513 regs->tf_ds = _udatasel;
514 regs->tf_es = _udatasel;
dd4ad62d
MD
515
516 /*
517 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD
518 * the userland program might be using both.
519 *
520 * However, if a T_PROTFLT occured the segment registers could be
521 * totally broken. They must be reset in order to be able to
522 * return to userland.
dd4ad62d 523 */
4e7c41c5
MD
524 if (regs->tf_trapno == T_PROTFLT) {
525 regs->tf_fs = _udatasel;
526 regs->tf_gs = _udatasel;
527 }
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528 regs->tf_ss = _udatasel;
529}
530
531/*
4a22e893 532 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD
533 * VM context. Remove any items that would otherwise create a privilage
534 * issue.
4a22e893 535 *
4e7c41c5
MD
536 * XXX at the moment we allow userland to set the resume flag. Is this a
537 * bad idea?
4a22e893
MD
538 */
539int
540cpu_sanitize_frame(struct trapframe *frame)
541{
542 frame->tf_cs = _ucodesel;
543 frame->tf_ds = _udatasel;
4e7c41c5
MD
544 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
545#if 0
4a22e893 546 frame->tf_fs = _udatasel;
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MD
547 frame->tf_gs = _udatasel;
548#endif
4a22e893 549 frame->tf_ss = _udatasel;
4e7c41c5 550 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD
551 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
552 return(0);
553}
554
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MD
555int
556cpu_sanitize_tls(struct savetls *tls)
557{
558 struct segment_descriptor *desc;
559 int i;
560
561 for (i = 0; i < NGTLS; ++i) {
562 desc = &tls->tls[i];
563 if (desc->sd_dpl == 0 && desc->sd_type == 0)
564 continue;
565 if (desc->sd_def32 == 0)
566 return(ENXIO);
567 if (desc->sd_type != SDT_MEMRWA)
568 return(ENXIO);
569 if (desc->sd_dpl != SEL_UPL)
570 return(ENXIO);
571 if (desc->sd_xx != 0 || desc->sd_p != 1)
572 return(ENXIO);
573 }
574 return(0);
575}
576
4a22e893 577/*
65957d54 578 * sigreturn(ucontext_t *sigcntxp)
41c20dac 579 *
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580 * System call to cleanup state after a signal
581 * has been taken. Reset signal mask and
582 * stack state from context left by sendsig (above).
583 * Return to previous pc and psl as specified by
584 * context left by sendsig. Check carefully to
585 * make sure that the user has not modified the
586 * state to gain improper privileges.
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587 *
588 * MPSAFE
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589 */
590#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
591#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
592
593int
753fd850 594sys_sigreturn(struct sigreturn_args *uap)
984263bc 595{
065b709a 596 struct lwp *lp = curthread->td_lwp;
984263bc 597 struct trapframe *regs;
1b251f0a 598 ucontext_t uc;
984263bc 599 ucontext_t *ucp;
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600 int cs;
601 int eflags;
602 int error;
984263bc 603
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604 /*
605 * We have to copy the information into kernel space so userland
606 * can't modify it while we are sniffing it.
607 */
065b709a 608 regs = lp->lwp_md.md_regs;
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609 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
610 if (error)
611 return (error);
612 ucp = &uc;
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613 eflags = ucp->uc_mcontext.mc_eflags;
614
615 if (eflags & PSL_VM) {
616 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
617 struct vm86_kernel *vm86;
618
619 /*
620 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
621 * set up the vm86 area, and we can't enter vm86 mode.
622 */
065b709a 623 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 624 return (EINVAL);
065b709a 625 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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626 if (vm86->vm86_inited == 0)
627 return (EINVAL);
628
629 /* go back to user mode if both flags are set */
630 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 631 trapsignal(lp, SIGBUS, 0);
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632
633 if (vm86->vm86_has_vme) {
634 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
635 (eflags & VME_USERCHANGE) | PSL_VM;
636 } else {
637 vm86->vm86_eflags = eflags; /* save VIF, VIP */
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638 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
639 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 640 }
4e7c41c5 641 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
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642 tf->tf_eflags = eflags;
643 tf->tf_vm86_ds = tf->tf_ds;
644 tf->tf_vm86_es = tf->tf_es;
645 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 646 tf->tf_vm86_gs = tf->tf_gs;
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647 tf->tf_ds = _udatasel;
648 tf->tf_es = _udatasel;
4e7c41c5 649#if 0
984263bc 650 tf->tf_fs = _udatasel;
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651 tf->tf_gs = _udatasel;
652#endif
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653 } else {
654 /*
655 * Don't allow users to change privileged or reserved flags.
656 */
657 /*
658 * XXX do allow users to change the privileged flag PSL_RF.
659 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
660 * should sometimes set it there too. tf_eflags is kept in
661 * the signal context during signal handling and there is no
662 * other place to remember it, so the PSL_RF bit may be
663 * corrupted by the signal handler without us knowing.
664 * Corruption of the PSL_RF bit at worst causes one more or
665 * one less debugger trap, so allowing it is fairly harmless.
666 */
667 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 668 kprintf("sigreturn: eflags = 0x%x\n", eflags);
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669 return(EINVAL);
670 }
671
672 /*
673 * Don't allow users to load a valid privileged %cs. Let the
674 * hardware check for invalid selectors, excess privilege in
675 * other selectors, invalid %eip's and invalid %esp's.
676 */
677 cs = ucp->uc_mcontext.mc_cs;
678 if (!CS_SECURE(cs)) {
26be20a0 679 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 680 trapsignal(lp, SIGBUS, T_PROTFLT);
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681 return(EINVAL);
682 }
4e7c41c5 683 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
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684 }
685
4b486183 686 /*
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687 * Restore the FPU state from the frame
688 */
3919ced0 689 crit_enter();
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690 npxpop(&ucp->uc_mcontext);
691
984263bc 692 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 693 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 694 else
065b709a 695 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 696
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SS
697 lp->lwp_sigmask = ucp->uc_sigmask;
698 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 699 crit_exit();
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700 return(EJUSTRETURN);
701}
702
703/*
704 * Machine dependent boot() routine
705 *
706 * I haven't seen anything to put here yet
707 * Possibly some stuff might be grafted back here from boot()
708 */
709void
710cpu_boot(int howto)
711{
712}
713
714/*
715 * Shutdown the CPU as much as possible
716 */
717void
718cpu_halt(void)
719{
720 for (;;)
1184892f 721 __asm__ __volatile("hlt");
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722}
723
724/*
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725 * cpu_idle() represents the idle LWKT. You cannot return from this function
726 * (unless you want to blow things up!). Instead we look for runnable threads
727 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 728 *
26a0694b 729 * The main loop is entered with a critical section held, we must release
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730 * the critical section before doing anything else. lwkt_switch() will
731 * check for pending interrupts due to entering and exiting its own
732 * critical section.
26a0694b 733 *
7d4d6fdb 734 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
7d4d6fdb 735 *
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736 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
737 * 1 to just use hlt and for debugging purposes.
984263bc 738 */
46e562ce 739static int cpu_idle_hlt = 2;
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740static int cpu_idle_hltcnt;
741static int cpu_idle_spincnt;
582fd846 742static u_int cpu_idle_repeat = 750;
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743SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
744 &cpu_idle_hlt, 0, "Idle loop HLT enable");
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745SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
746 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
747SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
748 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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749SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
750 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 751
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752static void
753cpu_idle_default_hook(void)
754{
755 /*
756 * We must guarentee that hlt is exactly the instruction
757 * following the sti.
758 */
759 __asm __volatile("sti; hlt");
760}
761
762/* Other subsystems (e.g., ACPI) can hook this later. */
763void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
764
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765void
766cpu_idle(void)
767{
be71787b 768 globaldata_t gd = mycpu;
10662728 769 struct thread *td __debugvar = gd->gd_curthread;
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770 int reqflags;
771 int quick;
a2a5ad0d 772
26a0694b 773 crit_exit();
f9235b6d 774 KKASSERT(td->td_critcount == 0);
8ad65e08 775 for (;;) {
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776 /*
777 * See if there are any LWKTs ready to go.
778 */
8ad65e08 779 lwkt_switch();
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MD
780
781 /*
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782 * When halting inside a cli we must check for reqflags
783 * races, particularly [re]schedule requests. Running
784 * splz() does the job.
785 *
786 * cpu_idle_hlt:
787 * 0 Never halt, just spin
788 *
789 * 1 Always use HLT (or MONITOR/MWAIT if avail).
790 * This typically eats more power than the
791 * ACPI halt.
792 *
793 * 2 Use HLT/MONITOR/MWAIT up to a point and then
794 * use the ACPI halt (default). This is a hybrid
795 * approach. See machdep.cpu_idle_repeat.
796 *
797 * 3 Always use the ACPI halt. This typically
798 * eats the least amount of power but the cpu
799 * will be slow waking up. Slows down e.g.
800 * compiles and other pipe/event oriented stuff.
801 *
802 *
803 * NOTE: Interrupts are enabled and we are not in a critical
804 * section.
805 *
806 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
807 * don't bother capping gd_idle_repeat, it is ok if
808 * it overflows.
a2a5ad0d 809 */
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810 ++gd->gd_idle_repeat;
811 reqflags = gd->gd_reqflags;
812 quick = (cpu_idle_hlt == 1) ||
813 (cpu_idle_hlt < 3 &&
814 gd->gd_idle_repeat < cpu_idle_repeat);
815
816 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
817 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
818 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
819 ++cpu_idle_hltcnt;
820 } else if (cpu_idle_hlt) {
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821 __asm __volatile("cli");
822 splz();
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823 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
824 if (quick)
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MD
825 cpu_idle_default_hook();
826 else
827 cpu_idle_hook();
828 }
7d4d6fdb 829 __asm __volatile("sti");
60f945af 830 ++cpu_idle_hltcnt;
8ad65e08 831 } else {
60f945af 832 splz();
c5724852 833 __asm __volatile("sti");
60f945af 834 ++cpu_idle_spincnt;
8ad65e08 835 }
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836 }
837}
838
839/*
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840 * This routine is called if a spinlock has been held through the
841 * exponential backoff period and is seriously contested. On a real cpu
842 * we let it spin.
843 */
844void
845cpu_spinlock_contested(void)
846{
847 cpu_pause();
848}
849
850/*
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851 * Clear registers on exec
852 */
853void
08f2f1bb 854exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 855{
08f2f1bb
SS
856 struct thread *td = curthread;
857 struct lwp *lp = td->td_lwp;
858 struct pcb *pcb = td->td_pcb;
bb3cd951 859 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 860
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861 /* was i386_user_cleanup() in NetBSD */
862 user_ldt_free(pcb);
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MD
863
864 bzero((char *)regs, sizeof(struct trapframe));
865 regs->tf_eip = entry;
866 regs->tf_esp = stack;
867 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
868 regs->tf_ss = _udatasel;
869 regs->tf_ds = _udatasel;
870 regs->tf_es = _udatasel;
871 regs->tf_fs = _udatasel;
4e7c41c5 872 regs->tf_gs = _udatasel;
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873 regs->tf_cs = _ucodesel;
874
875 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
876 regs->tf_ebx = ps_strings;
877
878 /*
879 * Reset the hardware debug registers if they were in use.
880 * They won't have any meaning for the newly exec'd process.
881 */
882 if (pcb->pcb_flags & PCB_DBREGS) {
883 pcb->pcb_dr0 = 0;
884 pcb->pcb_dr1 = 0;
885 pcb->pcb_dr2 = 0;
886 pcb->pcb_dr3 = 0;
887 pcb->pcb_dr6 = 0;
888 pcb->pcb_dr7 = 0;
08f2f1bb 889 if (pcb == td->td_pcb) {
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890 /*
891 * Clear the debug registers on the running
892 * CPU, otherwise they will end up affecting
893 * the next process we switch to.
894 */
895 reset_dbregs();
896 }
897 pcb->pcb_flags &= ~PCB_DBREGS;
898 }
899
900 /*
901 * Initialize the math emulator (if any) for the current process.
902 * Actually, just clear the bit that says that the emulator has
903 * been initialized. Initialization is delayed until the process
904 * traps to the emulator (if it is done at all) mainly because
905 * emulators don't provide an entry point for initialization.
906 */
08f2f1bb 907 pcb->pcb_flags &= ~FP_SOFTFP;
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908
909 /*
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910 * note: do not set CR0_TS here. npxinit() must do it after clearing
911 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
912 * in npxdna().
984263bc 913 */
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914 crit_enter();
915 load_cr0(rcr0() | CR0_MP);
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916
917#if NNPX > 0
918 /* Initialize the npx (if any) for the current process. */
919 npxinit(__INITIAL_NPXCW__);
920#endif
a02705a9 921 crit_exit();
984263bc 922
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MD
923 /*
924 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
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925 * handled in execve simply by setting the 64 bit syscall
926 * return value to 0.
90b9818c 927 */
984263bc
MD
928}
929
930void
931cpu_setregs(void)
932{
933 unsigned int cr0;
934
935 cr0 = rcr0();
936 cr0 |= CR0_NE; /* Done by npxinit() */
937 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 938 cr0 |= CR0_WP | CR0_AM;
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939 load_cr0(cr0);
940 load_gs(_udatasel);
941}
942
943static int
944sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
945{
946 int error;
947 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
948 req);
949 if (!error && req->newptr)
950 resettodr();
951 return (error);
952}
953
954SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
955 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
956
957SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
958 CTLFLAG_RW, &disable_rtc_set, 0, "");
959
960SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
961 CTLFLAG_RD, &bootinfo, bootinfo, "");
962
963SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
964 CTLFLAG_RW, &wall_cmos_clock, 0, "");
965
b13267a5 966extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 967SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 968 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
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969
970/*
971 * Initialize 386 and configure to run kernel
972 */
973
974/*
975 * Initialize segments & interrupt table
976 */
977
978int _default_ldt;
979union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
980static struct gate_descriptor idt0[NIDT];
981struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
982union descriptor ldt[NLDT]; /* local descriptor table */
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MD
983
984/* table descriptors - used to load tables by cpu */
984263bc 985struct region_descriptor r_gdt, r_idt;
984263bc 986
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MD
987#if defined(I586_CPU) && !defined(NO_F00F_HACK)
988extern int has_f00f_bug;
989#endif
990
991static struct i386tss dblfault_tss;
992static char dblfault_stack[PAGE_SIZE];
993
994extern struct user *proc0paddr;
995
996
997/* software prototypes -- in more palatable form */
998struct soft_segment_descriptor gdt_segs[] = {
999/* GNULL_SEL 0 Null Descriptor */
1000{ 0x0, /* segment base address */
1001 0x0, /* length */
1002 0, /* segment type */
1003 0, /* segment descriptor priority level */
1004 0, /* segment descriptor present */
1005 0, 0,
1006 0, /* default 32 vs 16 bit size */
1007 0 /* limit granularity (byte/page units)*/ },
1008/* GCODE_SEL 1 Code Descriptor for kernel */
1009{ 0x0, /* segment base address */
1010 0xfffff, /* length - all address space */
1011 SDT_MEMERA, /* segment type */
1012 0, /* segment descriptor priority level */
1013 1, /* segment descriptor present */
1014 0, 0,
1015 1, /* default 32 vs 16 bit size */
1016 1 /* limit granularity (byte/page units)*/ },
1017/* GDATA_SEL 2 Data Descriptor for kernel */
1018{ 0x0, /* segment base address */
1019 0xfffff, /* length - all address space */
1020 SDT_MEMRWA, /* segment type */
1021 0, /* segment descriptor priority level */
1022 1, /* segment descriptor present */
1023 0, 0,
1024 1, /* default 32 vs 16 bit size */
1025 1 /* limit granularity (byte/page units)*/ },
1026/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1027{ 0x0, /* segment base address */
1028 0xfffff, /* length - all address space */
1029 SDT_MEMRWA, /* segment type */
1030 0, /* segment descriptor priority level */
1031 1, /* segment descriptor present */
1032 0, 0,
1033 1, /* default 32 vs 16 bit size */
1034 1 /* limit granularity (byte/page units)*/ },
1035/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1036{
1037 0x0, /* segment base address */
1038 sizeof(struct i386tss)-1,/* length - all address space */
1039 SDT_SYS386TSS, /* segment type */
1040 0, /* segment descriptor priority level */
1041 1, /* segment descriptor present */
1042 0, 0,
1043 0, /* unused - default 32 vs 16 bit size */
1044 0 /* limit granularity (byte/page units)*/ },
1045/* GLDT_SEL 5 LDT Descriptor */
1046{ (int) ldt, /* segment base address */
1047 sizeof(ldt)-1, /* length - all address space */
1048 SDT_SYSLDT, /* segment type */
1049 SEL_UPL, /* segment descriptor priority level */
1050 1, /* segment descriptor present */
1051 0, 0,
1052 0, /* unused - default 32 vs 16 bit size */
1053 0 /* limit granularity (byte/page units)*/ },
1054/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1055{ (int) ldt, /* segment base address */
1056 (512 * sizeof(union descriptor)-1), /* length */
1057 SDT_SYSLDT, /* segment type */
1058 0, /* segment descriptor priority level */
1059 1, /* segment descriptor present */
1060 0, 0,
1061 0, /* unused - default 32 vs 16 bit size */
1062 0 /* limit granularity (byte/page units)*/ },
1063/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1064{ 0x0, /* segment base address */
1065 0x0, /* length - all address space */
1066 0, /* segment type */
1067 0, /* segment descriptor priority level */
1068 0, /* segment descriptor present */
1069 0, 0,
1070 0, /* default 32 vs 16 bit size */
1071 0 /* limit granularity (byte/page units)*/ },
1072/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1073{ 0x400, /* segment base address */
1074 0xfffff, /* length */
1075 SDT_MEMRWA, /* segment type */
1076 0, /* segment descriptor priority level */
1077 1, /* segment descriptor present */
1078 0, 0,
1079 1, /* default 32 vs 16 bit size */
1080 1 /* limit granularity (byte/page units)*/ },
1081/* GPANIC_SEL 9 Panic Tss Descriptor */
1082{ (int) &dblfault_tss, /* segment base address */
1083 sizeof(struct i386tss)-1,/* length - all address space */
1084 SDT_SYS386TSS, /* segment type */
1085 0, /* segment descriptor priority level */
1086 1, /* segment descriptor present */
1087 0, 0,
1088 0, /* unused - default 32 vs 16 bit size */
1089 0 /* limit granularity (byte/page units)*/ },
1090/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1091{ 0, /* segment base address (overwritten) */
1092 0xfffff, /* length */
1093 SDT_MEMERA, /* segment type */
1094 0, /* segment descriptor priority level */
1095 1, /* segment descriptor present */
1096 0, 0,
1097 0, /* default 32 vs 16 bit size */
1098 1 /* limit granularity (byte/page units)*/ },
1099/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1100{ 0, /* segment base address (overwritten) */
1101 0xfffff, /* length */
1102 SDT_MEMERA, /* segment type */
1103 0, /* segment descriptor priority level */
1104 1, /* segment descriptor present */
1105 0, 0,
1106 0, /* default 32 vs 16 bit size */
1107 1 /* limit granularity (byte/page units)*/ },
1108/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1109{ 0, /* segment base address (overwritten) */
1110 0xfffff, /* length */
1111 SDT_MEMRWA, /* segment type */
1112 0, /* segment descriptor priority level */
1113 1, /* segment descriptor present */
1114 0, 0,
1115 1, /* default 32 vs 16 bit size */
1116 1 /* limit granularity (byte/page units)*/ },
1117/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1118{ 0, /* segment base address (overwritten) */
1119 0xfffff, /* length */
1120 SDT_MEMRWA, /* segment type */
1121 0, /* segment descriptor priority level */
1122 1, /* segment descriptor present */
1123 0, 0,
1124 0, /* default 32 vs 16 bit size */
1125 1 /* limit granularity (byte/page units)*/ },
1126/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1127{ 0, /* segment base address (overwritten) */
1128 0xfffff, /* length */
1129 SDT_MEMRWA, /* segment type */
1130 0, /* segment descriptor priority level */
1131 1, /* segment descriptor present */
1132 0, 0,
1133 0, /* default 32 vs 16 bit size */
1134 1 /* limit granularity (byte/page units)*/ },
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MD
1135/* GTLS_START 15 TLS */
1136{ 0x0, /* segment base address */
1137 0x0, /* length */
1138 0, /* segment type */
1139 0, /* segment descriptor priority level */
1140 0, /* segment descriptor present */
1141 0, 0,
1142 0, /* default 32 vs 16 bit size */
1143 0 /* limit granularity (byte/page units)*/ },
1144/* GTLS_START+1 16 TLS */
1145{ 0x0, /* segment base address */
1146 0x0, /* length */
1147 0, /* segment type */
1148 0, /* segment descriptor priority level */
1149 0, /* segment descriptor present */
1150 0, 0,
1151 0, /* default 32 vs 16 bit size */
1152 0 /* limit granularity (byte/page units)*/ },
1153/* GTLS_END 17 TLS */
1154{ 0x0, /* segment base address */
1155 0x0, /* length */
1156 0, /* segment type */
1157 0, /* segment descriptor priority level */
1158 0, /* segment descriptor present */
1159 0, 0,
1160 0, /* default 32 vs 16 bit size */
1161 0 /* limit granularity (byte/page units)*/ },
efba76b4
SW
1162/* GNDIS_SEL 18 NDIS Descriptor */
1163{ 0x0, /* segment base address */
1164 0x0, /* length */
1165 0, /* segment type */
1166 0, /* segment descriptor priority level */
1167 0, /* segment descriptor present */
1168 0, 0,
1169 0, /* default 32 vs 16 bit size */
1170 0 /* limit granularity (byte/page units)*/ },
984263bc
MD
1171};
1172
1173static struct soft_segment_descriptor ldt_segs[] = {
1174 /* Null Descriptor - overwritten by call gate */
1175{ 0x0, /* segment base address */
1176 0x0, /* length - all address space */
1177 0, /* segment type */
1178 0, /* segment descriptor priority level */
1179 0, /* segment descriptor present */
1180 0, 0,
1181 0, /* default 32 vs 16 bit size */
1182 0 /* limit granularity (byte/page units)*/ },
1183 /* Null Descriptor - overwritten by call gate */
1184{ 0x0, /* segment base address */
1185 0x0, /* length - all address space */
1186 0, /* segment type */
1187 0, /* segment descriptor priority level */
1188 0, /* segment descriptor present */
1189 0, 0,
1190 0, /* default 32 vs 16 bit size */
1191 0 /* limit granularity (byte/page units)*/ },
1192 /* Null Descriptor - overwritten by call gate */
1193{ 0x0, /* segment base address */
1194 0x0, /* length - all address space */
1195 0, /* segment type */
1196 0, /* segment descriptor priority level */
1197 0, /* segment descriptor present */
1198 0, 0,
1199 0, /* default 32 vs 16 bit size */
1200 0 /* limit granularity (byte/page units)*/ },
1201 /* Code Descriptor for user */
1202{ 0x0, /* segment base address */
1203 0xfffff, /* length - all address space */
1204 SDT_MEMERA, /* segment type */
1205 SEL_UPL, /* segment descriptor priority level */
1206 1, /* segment descriptor present */
1207 0, 0,
1208 1, /* default 32 vs 16 bit size */
1209 1 /* limit granularity (byte/page units)*/ },
1210 /* Null Descriptor - overwritten by call gate */
1211{ 0x0, /* segment base address */
1212 0x0, /* length - all address space */
1213 0, /* segment type */
1214 0, /* segment descriptor priority level */
1215 0, /* segment descriptor present */
1216 0, 0,
1217 0, /* default 32 vs 16 bit size */
1218 0 /* limit granularity (byte/page units)*/ },
1219 /* Data Descriptor for user */
1220{ 0x0, /* segment base address */
1221 0xfffff, /* length - all address space */
1222 SDT_MEMRWA, /* segment type */
1223 SEL_UPL, /* segment descriptor priority level */
1224 1, /* segment descriptor present */
1225 0, 0,
1226 1, /* default 32 vs 16 bit size */
1227 1 /* limit granularity (byte/page units)*/ },
1228};
1229
1230void
f123d5a1 1231setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD
1232{
1233 struct gate_descriptor *ip;
1234
1235 ip = idt + idx;
1236 ip->gd_looffset = (int)func;
1237 ip->gd_selector = selec;
1238 ip->gd_stkcpy = 0;
1239 ip->gd_xx = 0;
1240 ip->gd_type = typ;
1241 ip->gd_dpl = dpl;
1242 ip->gd_p = 1;
1243 ip->gd_hioffset = ((int)func)>>16 ;
1244}
1245
1246#define IDTVEC(name) __CONCAT(X,name)
1247
1248extern inthand_t
1249 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1250 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1251 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1252 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1253 IDTVEC(xmm), IDTVEC(syscall),
1254 IDTVEC(rsvd0);
a64ba182 1255extern inthand_t
f9a13fc4 1256 IDTVEC(int0x80_syscall);
984263bc 1257
f7bc9806
MD
1258#ifdef DEBUG_INTERRUPTS
1259extern inthand_t *Xrsvdary[256];
1260#endif
1261
984263bc 1262void
f123d5a1 1263sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD
1264{
1265 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1266 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1267 ssd->ssd_type = sd->sd_type;
1268 ssd->ssd_dpl = sd->sd_dpl;
1269 ssd->ssd_p = sd->sd_p;
1270 ssd->ssd_def32 = sd->sd_def32;
1271 ssd->ssd_gran = sd->sd_gran;
1272}
1273
984263bc
MD
1274/*
1275 * Populate the (physmap) array with base/bound pairs describing the
1276 * available physical memory in the system, then test this memory and
1277 * build the phys_avail array describing the actually-available memory.
1278 *
1279 * If we cannot accurately determine the physical memory map, then use
1280 * value from the 0xE801 call, and failing that, the RTC.
1281 *
1282 * Total memory size may be set by the kernel environment variable
1283 * hw.physmem or the compile-time define MAXMEM.
1284 */
1285static void
1286getmemsize(int first)
1287{
b24cd69c 1288 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD
1289 int hasbrokenint12;
1290 u_int basemem, extmem;
1291 struct vm86frame vmf;
1292 struct vm86context vmc;
ff1a75a1
MD
1293 vm_offset_t pa;
1294 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1295 pt_entry_t *pte;
555da584 1296 quad_t maxmem;
984263bc
MD
1297 struct {
1298 u_int64_t base;
1299 u_int64_t length;
1300 u_int32_t type;
1301 } *smap;
28abdbbb 1302 quad_t dcons_addr, dcons_size;
984263bc 1303
984263bc
MD
1304 bzero(&vmf, sizeof(struct vm86frame));
1305 bzero(physmap, sizeof(physmap));
1306 basemem = 0;
1307
1308 /*
1309 * Some newer BIOSes has broken INT 12H implementation which cause
1310 * kernel panic immediately. In this case, we need to scan SMAP
1311 * with INT 15:E820 first, then determine base memory size.
1312 */
2ed482dc
MN
1313 hasbrokenint12 = 0;
1314 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD
1315 if (hasbrokenint12) {
1316 goto int15e820;
1317 }
1318
1319 /*
7febcc6e
MD
1320 * Perform "base memory" related probes & setup. If we get a crazy
1321 * value give the bios some scribble space just in case.
984263bc
MD
1322 */
1323 vm86_intcall(0x12, &vmf);
1324 basemem = vmf.vmf_ax;
1325 if (basemem > 640) {
26be20a0 1326 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD
1327 "truncating to < 640K\n", basemem);
1328 basemem = 636;
984263bc
MD
1329 }
1330
1331 /*
1332 * XXX if biosbasemem is now < 640, there is a `hole'
1333 * between the end of base memory and the start of
1334 * ISA memory. The hole may be empty or it may
1335 * contain BIOS code or data. Map it read/write so
1336 * that the BIOS can write to it. (Memory from 0 to
1337 * the physical end of the kernel is mapped read-only
1338 * to begin with and then parts of it are remapped.
1339 * The parts that aren't remapped form holes that
1340 * remain read-only and are unused by the kernel.
1341 * The base memory area is below the physical end of
1342 * the kernel and right now forms a read-only hole.
1343 * The part of it from PAGE_SIZE to
1344 * (trunc_page(biosbasemem * 1024) - 1) will be
1345 * remapped and used by the kernel later.)
1346 *
1347 * This code is similar to the code used in
1348 * pmap_mapdev, but since no memory needs to be
1349 * allocated we simply change the mapping.
1350 */
1351 for (pa = trunc_page(basemem * 1024);
1352 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1353 pte = vtopte(pa + KERNBASE);
984263bc
MD
1354 *pte = pa | PG_RW | PG_V;
1355 }
1356
1357 /*
1358 * if basemem != 640, map pages r/w into vm86 page table so
1359 * that the bios can scribble on it.
1360 */
b5b32410 1361 pte = vm86paddr;
984263bc
MD
1362 for (i = basemem / 4; i < 160; i++)
1363 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1364
1365int15e820:
1366 /*
1367 * map page 1 R/W into the kernel page table so we can use it
1368 * as a buffer. The kernel will unmap this page later.
1369 */
b5b32410 1370 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1371 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1372
1373 /*
1374 * get memory map with INT 15:E820
1375 */
1376#define SMAPSIZ sizeof(*smap)
1377#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1378
1379 vmc.npages = 0;
1380 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1381 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1382
1383 physmap_idx = 0;
1384 vmf.vmf_ebx = 0;
1385 do {
1386 vmf.vmf_eax = 0xE820;
1387 vmf.vmf_edx = SMAP_SIG;
1388 vmf.vmf_ecx = SMAPSIZ;
1389 i = vm86_datacall(0x15, &vmf, &vmc);
1390 if (i || vmf.vmf_eax != SMAP_SIG)
1391 break;
1392 if (boothowto & RB_VERBOSE)
26be20a0 1393 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD
1394 smap->type,
1395 *(u_int32_t *)((char *)&smap->base + 4),
1396 (u_int32_t)smap->base,
1397 *(u_int32_t *)((char *)&smap->length + 4),
1398 (u_int32_t)smap->length);
1399
1400 if (smap->type != 0x01)
1401 goto next_run;
1402
1403 if (smap->length == 0)
1404 goto next_run;
1405
1bda0d3d
MD
1406 Realmem += smap->length;
1407
1408 if (smap->base >= 0xffffffffLLU) {
9c3db322 1409 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1410 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD
1411 goto next_run;
1412 }
1413
1414 for (i = 0; i <= physmap_idx; i += 2) {
1415 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1416 if (boothowto & RB_VERBOSE) {
1417 kprintf("Overlapping or non-montonic "
1418 "memory region, ignoring "
1419 "second region\n");
1420 }
1421 Realmem -= smap->length;
984263bc
MD
1422 goto next_run;
1423 }
1424 }
1425
1426 if (smap->base == physmap[physmap_idx + 1]) {
1427 physmap[physmap_idx + 1] += smap->length;
1428 goto next_run;
1429 }
1430
1431 physmap_idx += 2;
ff1a75a1 1432 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD
1433 kprintf("Too many segments in the physical "
1434 "address map, giving up\n");
984263bc
MD
1435 break;
1436 }
1437 physmap[physmap_idx] = smap->base;
1438 physmap[physmap_idx + 1] = smap->base + smap->length;
1439next_run:
6b08710e 1440 ; /* fix GCC3.x warning */
984263bc
MD
1441 } while (vmf.vmf_ebx != 0);
1442
1443 /*
1444 * Perform "base memory" related probes & setup based on SMAP
1445 */
1446 if (basemem == 0) {
1447 for (i = 0; i <= physmap_idx; i += 2) {
1448 if (physmap[i] == 0x00000000) {
1449 basemem = physmap[i + 1] / 1024;
1450 break;
1451 }
1452 }
1453
1454 if (basemem == 0) {
1455 basemem = 640;
1456 }
1457
1458 if (basemem > 640) {
1bda0d3d
MD
1459 kprintf("Preposterous BIOS basemem of %uK, "
1460 "truncating to 640K\n", basemem);
984263bc
MD
1461 basemem = 640;
1462 }
1463
1464 for (pa = trunc_page(basemem * 1024);
1465 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1466 pte = vtopte(pa + KERNBASE);
984263bc
MD
1467 *pte = pa | PG_RW | PG_V;
1468 }
1469
b5b32410 1470 pte = vm86paddr;
984263bc
MD
1471 for (i = basemem / 4; i < 160; i++)
1472 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1473 }
1474
1475 if (physmap[1] != 0)
1476 goto physmap_done;
1477
1478 /*
1479 * If we failed above, try memory map with INT 15:E801
1480 */
1481 vmf.vmf_ax = 0xE801;
1482 if (vm86_intcall(0x15, &vmf) == 0) {
1483 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1484 } else {
1485#if 0
1486 vmf.vmf_ah = 0x88;
1487 vm86_intcall(0x15, &vmf);
1488 extmem = vmf.vmf_ax;
1489#else
1490 /*
1491 * Prefer the RTC value for extended memory.
1492 */
1493 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1494#endif
1495 }
1496
1497 /*
1498 * Special hack for chipsets that still remap the 384k hole when
1499 * there's 16MB of memory - this really confuses people that
1500 * are trying to use bus mastering ISA controllers with the
1501 * "16MB limit"; they only have 16MB, but the remapping puts
1502 * them beyond the limit.
1503 *
1504 * If extended memory is between 15-16MB (16-17MB phys address range),
1505 * chop it to 15MB.
1506 */
1507 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1508 extmem = 15 * 1024;
1509
1510 physmap[0] = 0;
1511 physmap[1] = basemem * 1024;
1512 physmap_idx = 2;
1513 physmap[physmap_idx] = 0x100000;
1514 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1515
1516physmap_done:
1517 /*
1518 * Now, physmap contains a map of physical memory.
1519 */
1520
ed721f0f 1521 base_memory = physmap[1];
17a9f566 1522 /* make hole for AP bootstrap code YYY */
ed721f0f 1523 physmap[1] = mp_bootaddress(base_memory);
984263bc 1524
1876681a
SZ
1525 /* Save EBDA address, if any */
1526 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1527 ebda_addr <<= 4;
984263bc
MD
1528
1529 /*
1530 * Maxmem isn't the "maximum memory", it's one larger than the
1531 * highest page of the physical address space. It should be
1532 * called something like "Maxphyspage". We may adjust this
1533 * based on ``hw.physmem'' and the results of the memory test.
1534 */
1535 Maxmem = atop(physmap[physmap_idx + 1]);
1536
1537#ifdef MAXMEM
1538 Maxmem = MAXMEM / 4;
1539#endif
1540
555da584
MD
1541 if (kgetenv_quad("hw.physmem", &maxmem))
1542 Maxmem = atop(maxmem);
984263bc
MD
1543
1544 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1545 (boothowto & RB_VERBOSE))
26be20a0 1546 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1547
1548 /*
1549 * If Maxmem has been increased beyond what the system has detected,
1550 * extend the last memory segment to the new limit.
1551 */
1552 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1553 physmap[physmap_idx + 1] = ptoa(Maxmem);
1554
1555 /* call pmap initialization to make new kernel address space */
1556 pmap_bootstrap(first, 0);
1557
1558 /*
1559 * Size up each available chunk of physical memory.
1560 */
1561 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1562 pa_indx = 0;
b24cd69c 1563 da_indx = 1;
984263bc
MD
1564 phys_avail[pa_indx++] = physmap[0];
1565 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH
1566 dump_avail[da_indx] = physmap[0];
1567
b5b32410 1568 pte = CMAP1;
984263bc
MD
1569
1570 /*
28abdbbb
HS
1571 * Get dcons buffer address
1572 */
bc01a404
MD
1573 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1574 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS
1575 dcons_addr = 0;
1576
1577 /*
984263bc
MD
1578 * physmap is in bytes, so when converting to page boundaries,
1579 * round up the start address and round down the end address.
1580 */
1581 for (i = 0; i <= physmap_idx; i += 2) {
1582 vm_offset_t end;
1583
1584 end = ptoa(Maxmem);
1585 if (physmap[i + 1] < end)
1586 end = trunc_page(physmap[i + 1]);
1587 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1588 int tmp, page_bad, full;
984263bc
MD
1589#if 0
1590 int *ptr = 0;
1591#else
1592 int *ptr = (int *)CADDR1;
1593#endif
b24cd69c 1594 full = FALSE;
984263bc
MD
1595
1596 /*
1597 * block out kernel memory as not available.
1598 */
1599 if (pa >= 0x100000 && pa < first)
b24cd69c 1600 goto do_dump_avail;
984263bc 1601
28abdbbb
HS
1602 /*
1603 * block out dcons buffer
1604 */
1605 if (dcons_addr > 0
1606 && pa >= trunc_page(dcons_addr)
1607 && pa < dcons_addr + dcons_size)
b24cd69c 1608 goto do_dump_avail;
28abdbbb 1609
984263bc
MD
1610 page_bad = FALSE;
1611
1612 /*
1613 * map page into kernel: valid, read/write,non-cacheable
1614 */
1615 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1616 cpu_invltlb();
984263bc
MD
1617
1618 tmp = *(int *)ptr;
1619 /*
1620 * Test for alternating 1's and 0's
1621 */
1622 *(volatile int *)ptr = 0xaaaaaaaa;
1623 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1624 page_bad = TRUE;
1625 }
1626 /*
1627 * Test for alternating 0's and 1's
1628 */
1629 *(volatile int *)ptr = 0x55555555;
1630 if (*(volatile int *)ptr != 0x55555555) {
1631 page_bad = TRUE;
1632 }
1633 /*
1634 * Test for all 1's
1635 */
1636 *(volatile int *)ptr = 0xffffffff;
1637 if (*(volatile int *)ptr != 0xffffffff) {
1638 page_bad = TRUE;
1639 }
1640 /*
1641 * Test for all 0's
1642 */
1643 *(volatile int *)ptr = 0x0;
1644 if (*(volatile int *)ptr != 0x0) {
1645 page_bad = TRUE;
1646 }
1647 /*
1648 * Restore original value.
1649 */
1650 *(int *)ptr = tmp;
1651
1652 /*
1653 * Adjust array of valid/good pages.
1654 */
1655 if (page_bad == TRUE) {
1656 continue;
1657 }
1658 /*
1659 * If this good page is a continuation of the
1660 * previous set of good pages, then just increase
1661 * the end pointer. Otherwise start a new chunk.
1662 * Note that "end" points one higher than end,
1663 * making the range >= start and < end.
1664 * If we're also doing a speculative memory
1665 * test and we at or past the end, bump up Maxmem
1666 * so that we keep going. The first bad page
1667 * will terminate the loop.
1668 */
1669 if (phys_avail[pa_indx] == pa) {
1670 phys_avail[pa_indx] += PAGE_SIZE;
1671 } else {
1672 pa_indx++;
ff1a75a1 1673 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1674 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1675 pa_indx--;
b24cd69c
AH
1676 full = TRUE;
1677 goto do_dump_avail;
984263bc
MD
1678 }
1679 phys_avail[pa_indx++] = pa; /* start */
1680 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1681 }
1682 physmem++;
b24cd69c
AH
1683do_dump_avail:
1684 if (dump_avail[da_indx] == pa) {
1685 dump_avail[da_indx] += PAGE_SIZE;
1686 } else {
1687 da_indx++;
1688 if (da_indx >= PHYSMAP_ENTRIES*2) {
1689 da_indx--;
1690 goto do_next;
1691 }
1692 dump_avail[da_indx++] = pa; /* start */
1693 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1694 }
1695do_next:
1696 if (full)
1697 break;
1698
984263bc
MD
1699 }
1700 }
1701 *pte = 0;
0f7a3396 1702 cpu_invltlb();
984263bc
MD
1703
1704 /*
1705 * XXX
1706 * The last chunk must contain at least one page plus the message
1707 * buffer to avoid complicating other code (message buffer address
1708 * calculation, etc.).
1709 */
1710 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1711 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1712 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1713 phys_avail[pa_indx--] = 0;
1714 phys_avail[pa_indx--] = 0;
1715 }
1716
1717 Maxmem = atop(phys_avail[pa_indx]);
1718
1719 /* Trim off space for the message buffer. */
1720 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1721
1722 avail_end = phys_avail[pa_indx];
1723}
1724
30c5f287
MN
1725struct machintr_abi MachIntrABI;
1726
f7bc9806
MD
1727/*
1728 * IDT VECTORS:
1729 * 0 Divide by zero
1730 * 1 Debug
1731 * 2 NMI
1732 * 3 BreakPoint
1733 * 4 OverFlow
1734 * 5 Bound-Range
1735 * 6 Invalid OpCode
1736 * 7 Device Not Available (x87)
1737 * 8 Double-Fault
1738 * 9 Coprocessor Segment overrun (unsupported, reserved)
1739 * 10 Invalid-TSS
1740 * 11 Segment not present
1741 * 12 Stack
1742 * 13 General Protection
1743 * 14 Page Fault
1744 * 15 Reserved
1745 * 16 x87 FP Exception pending
1746 * 17 Alignment Check
1747 * 18 Machine Check
1748 * 19 SIMD floating point
1749 * 20-31 reserved
1750 * 32-255 INTn/external sources
1751 */
984263bc 1752void
17a9f566 1753init386(int first)
984263bc
MD
1754{
1755 struct gate_descriptor *gdp;
1756 int gsel_tss, metadata_missing, off, x;
85100692 1757 struct mdglobaldata *gd;
984263bc
MD
1758
1759 /*
1760 * Prevent lowering of the ipl if we call tsleep() early.
1761 */
85100692 1762 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1763 bzero(gd, sizeof(*gd));
984263bc 1764
85100692 1765 gd->mi.gd_curthread = &thread0;
4e7c41c5 1766 thread0.td_gd = &gd->mi;
984263bc
MD
1767
1768 atdevbase = ISA_HOLE_START + KERNBASE;
1769
1770 metadata_missing = 0;
1771 if (bootinfo.bi_modulep) {
1772 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1773 preload_bootstrap_relocate(KERNBASE);
1774 } else {
1775 metadata_missing = 1;
1776 }
1777 if (bootinfo.bi_envp)
1778 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1779
27af435a
SZ
1780 if (boothowto & RB_VERBOSE)
1781 bootverbose++;
1782
c5cc06e3 1783 /*
10db3cc6 1784 * Default MachIntrABI to ICU
30c5f287
MN
1785 */
1786 MachIntrABI = MachIntrABI_ICU;
1e7aaefa 1787
d745d2b8
SZ
1788 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1789 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1d6d7089 1790 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
30c5f287
MN
1791
1792 /*
08771751 1793 * Some of the virtual machines do not work w/ I/O APIC
e6dee928
SZ
1794 * enabled. If the user does not explicitly enable or
1795 * disable the I/O APIC (ioapic_enable < 0), then we
1796 * disable I/O APIC on all virtual machines.
1797 */
1798 if (ioapic_enable < 0) {
1799 if (cpu_feature2 & CPUID2_VMM)
1800 ioapic_enable = 0;
1801 else
1802 ioapic_enable = 1;
1803 }
1804
1805 /*
b45759e1
MD
1806 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1807 * and ncpus_fit_mask remain 0.
c5cc06e3 1808 */
4e8e646b 1809 ncpus = 1;
c5cc06e3 1810 ncpus2 = 1;
b45759e1 1811 ncpus_fit = 1;
984263bc
MD
1812 /* Init basic tunables, hz etc */
1813 init_param1();
1814
1815 /*
1816 * make gdt memory segments, the code segment goes up to end of the
1817 * page with etext in it, the data segment goes to the end of
1818 * the address space
1819 */
1820 /*
1821 * XXX text protection is temporarily (?) disabled. The limit was
1822 * i386_btop(round_page(etext)) - 1.
1823 */
1824 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1825 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1826
984263bc
MD
1827 gdt_segs[GPRIV_SEL].ssd_limit =
1828 atop(sizeof(struct privatespace) - 1);
8ad65e08 1829 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1830 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1831 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1832
85100692 1833 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1834
84b592ba
MD
1835 /*
1836 * Note: on both UP and SMP curthread must be set non-NULL
1837 * early in the boot sequence because the system assumes
1838 * that 'curthread' is never NULL.
1839 */
984263bc
MD
1840
1841 for (x = 0; x < NGDT; x++) {
1842#ifdef BDE_DEBUGGER
1843 /* avoid overwriting db entries with APM ones */
1844 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1845 continue;
1846#endif
1847 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1848 }
1849
1850 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1851 r_gdt.rd_base = (int) gdt;
1852 lgdt(&r_gdt);
1853
73e4f7b9
MD
1854 mi_gdinit(&gd->mi, 0);
1855 cpu_gdinit(gd, 0);
6bf59cd2 1856 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 1857 safepri = TDPRI_MAX;
73e4f7b9 1858
984263bc
MD
1859 /* make ldt memory segments */
1860 /*
88181b08 1861 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD
1862 * should be spelled ...MAX_USER...
1863 */
88181b08
MD
1864 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
1865 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
b370aff7 1866 for (x = 0; x < NELEM(ldt_segs); x++)
984263bc
MD
1867 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1868
1869 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1870 lldt(_default_ldt);
17a9f566 1871 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
1872 /* spinlocks and the BGL */
1873 init_locks();
984263bc 1874
2f839e54
MD
1875 /*
1876 * Setup the hardware exception table. Most exceptions use
1877 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
1878 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
1879 * an 'interrupt trap gate', which disables interrupts on entry,
1880 * in order to be able to poll the appropriate CRn register to
1881 * determine the fault address.
1882 */
f7bc9806
MD
1883 for (x = 0; x < NIDT; x++) {
1884#ifdef DEBUG_INTERRUPTS
1885 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1886#else
1887 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1888#endif
1889 }
984263bc
MD
1890 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1891 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1892 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1893 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1894 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1895 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1896 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1897 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1898 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
1899 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1900 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1901 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1902 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1903 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1904 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 1905 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
1906 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1907 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1908 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1909 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1910 setidt(0x80, &IDTVEC(int0x80_syscall),
1911 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1912
1913 r_idt.rd_limit = sizeof(idt0) - 1;
1914 r_idt.rd_base = (int) idt;
1915 lidt(&r_idt);
1916
1917 /*
1918 * Initialize the console before we print anything out.
1919 */
1920 cninit();
1921
1922 if (metadata_missing)
26be20a0 1923 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 1924
984263bc 1925#if NISA >0
e24dd6e0 1926 elcr_probe();
984263bc
MD
1927 isa_defaultirq();
1928#endif
1929 rand_initialize();
1930
a3dd9120
SZ
1931 /*
1932 * Initialize IRQ mapping
1933 *
1934 * NOTE:
1935 * SHOULD be after elcr_probe()
1936 */
1937 MachIntrABI_ICU.initmap();
a3dd9120 1938 MachIntrABI_IOAPIC.initmap();
a3dd9120 1939
984263bc
MD
1940#ifdef DDB
1941 kdb_init();
1942 if (boothowto & RB_KDB)
1943 Debugger("Boot flags requested debugger");
1944#endif
1945
1946 finishidentcpu(); /* Final stage of CPU initialization */
1947 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1948 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1949 initializecpu(); /* Initialize CPU registers */
1950
b7c628e4
MD
1951 /*
1952 * make an initial tss so cpu can get interrupt stack on syscall!
1953 * The 16 bytes is to save room for a VM86 context.
1954 */
17a9f566
MD
1955 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
1956 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 1957 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
1958 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
1959 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 1960 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
1961 ltr(gsel_tss);
1962
1963 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
1964 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
1965 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
1966 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1967 dblfault_tss.tss_cr3 = (int)IdlePTD;
1968 dblfault_tss.tss_eip = (int) dblfault_handler;
1969 dblfault_tss.tss_eflags = PSL_KERNEL;
1970 dblfault_tss.tss_ds = dblfault_tss.tss_es =
1971 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1972 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1973 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1974 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1975
1976 vm86_initialize();
1977 getmemsize(first);
1978 init_param2(physmem);
1979
1980 /* now running on new page tables, configured,and u/iom is accessible */
1981
1982 /* Map the message buffer. */
1983 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1984 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1985
1986 msgbufinit(msgbufp, MSGBUF_SIZE);
1987
1988 /* make a call gate to reenter kernel with */
1989 gdp = &ldt[LSYS5CALLS_SEL].gd;
1990
1991 x = (int) &IDTVEC(syscall);
1992 gdp->gd_looffset = x++;
1993 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
1994 gdp->gd_stkcpy = 1;
1995 gdp->gd_type = SDT_SYS386CGT;
1996 gdp->gd_dpl = SEL_UPL;
1997 gdp->gd_p = 1;
1998 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
1999
2000 /* XXX does this work? */
2001 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2002 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2003
2004 /* transfer to user mode */
2005
2006 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2007 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2008
2009 /* setup proc 0's pcb */
b7c628e4
MD
2010 thread0.td_pcb->pcb_flags = 0;
2011 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
d8061892 2012 thread0.td_pcb->pcb_ext = NULL;
08f2f1bb 2013 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2014}
2015
8ad65e08 2016/*
17a9f566
MD
2017 * Initialize machine-dependant portions of the global data structure.
2018 * Note that the global data area and cpu0's idlestack in the private
2019 * data space were allocated in locore.
ef0fdad1
MD
2020 *
2021 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2022 *
2023 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2024 */
2025void
85100692 2026cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2027{
7d0bac62 2028 if (cpu)
a2a5ad0d 2029 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2030
f470d0c8
MD
2031 lwkt_init_thread(&gd->mi.gd_idlethread,
2032 gd->mi.gd_prvspace->idlestack,
d3d32139 2033 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2034 0, &gd->mi);
a2a5ad0d
MD
2035 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2036 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2037 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2038 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2039}
2040
0cd275af
MD
2041int
2042is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2043{
2044 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2045 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2046 return (TRUE);
2047 }
2048 return (FALSE);
2049}
2050
12e4aaff
MD
2051struct globaldata *
2052globaldata_find(int cpu)
2053{
2054 KKASSERT(cpu >= 0 && cpu < ncpus);
2055 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2056}
2057
984263bc
MD
2058#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2059static void f00f_hack(void *unused);
ba39e2e0 2060SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD
2061
2062static void
17a9f566
MD
2063f00f_hack(void *unused)
2064{
984263bc 2065 struct gate_descriptor *new_idt;
984263bc
MD
2066 vm_offset_t tmp;
2067
2068 if (!has_f00f_bug)
2069 return;
2070
26be20a0 2071 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD
2072
2073 r_idt.rd_limit = sizeof(idt0) - 1;
2074
e4846942 2075 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD
2076 if (tmp == 0)
2077 panic("kmem_alloc returned 0");
2078 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2079 panic("kmem_alloc returned non-page-aligned memory");
2080 /* Put the first seven entries in the lower page */
2081 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2082 bcopy(idt, new_idt, sizeof(idt0));
2083 r_idt.rd_base = (int)new_idt;
2084 lidt(&r_idt);
2085 idt = new_idt;
e4846942 2086 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD
2087 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2088 panic("vm_map_protect failed");
2089 return;
2090}
2091#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2092
2093int
08f2f1bb 2094ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2095{
08f2f1bb 2096 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD
2097 return (0);
2098}
2099
2100int
e9182c58 2101ptrace_single_step(struct lwp *lp)
984263bc 2102{
e9182c58 2103 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD
2104 return (0);
2105}
2106
f123d5a1 2107int
e9182c58 2108fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2109{
984263bc
MD
2110 struct trapframe *tp;
2111
d64d3805
MD
2112 if ((tp = lp->lwp_md.md_regs) == NULL)
2113 return EINVAL;
4e7c41c5 2114 regs->r_gs = tp->tf_gs;
984263bc
MD
2115 regs->r_fs = tp->tf_fs;
2116 regs->r_es = tp->tf_es;
2117 regs->r_ds = tp->tf_ds;
2118 regs->r_edi = tp->tf_edi;
2119 regs->r_esi = tp->tf_esi;
2120 regs->r_ebp = tp->tf_ebp;
2121 regs->r_ebx = tp->tf_ebx;
2122 regs->r_edx = tp->tf_edx;
2123 regs->r_ecx = tp->tf_ecx;
2124 regs->r_eax = tp->tf_eax;
2125 regs->r_eip = tp->tf_eip;
2126 regs->r_cs = tp->tf_cs;
2127 regs->r_eflags = tp->tf_eflags;
2128 regs->r_esp = tp->tf_esp;
2129 regs->r_ss = tp->tf_ss;
984263bc
MD
2130 return (0);
2131}
2132
2133int
e9182c58 2134set_regs(struct lwp *lp, struct reg *regs)
984263bc 2135{
984263bc
MD
2136 struct trapframe *tp;
2137
e9182c58 2138 tp = lp->lwp_md.md_regs;
984263bc
MD
2139 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2140 !CS_SECURE(regs->r_cs))
2141 return (EINVAL);
4e7c41c5 2142 tp->tf_gs = regs->r_gs;
984263bc
MD
2143 tp->tf_fs = regs->r_fs;
2144 tp->tf_es = regs->r_es;
2145 tp->tf_ds = regs->r_ds;
2146 tp->tf_edi = regs->r_edi;
2147 tp->tf_esi = regs->r_esi;
2148 tp->tf_ebp = regs->r_ebp;
2149 tp->tf_ebx = regs->r_ebx;
2150 tp->tf_edx = regs->r_edx;
2151 tp->tf_ecx = regs->r_ecx;
2152 tp->tf_eax = regs->r_eax;
2153 tp->tf_eip = regs->r_eip;
2154 tp->tf_cs = regs->r_cs;
2155 tp->tf_eflags = regs->r_eflags;
2156 tp->tf_esp = regs->r_esp;
2157 tp->tf_ss = regs->r_ss;
984263bc
MD
2158 return (0);
2159}
2160
642a6e88 2161#ifndef CPU_DISABLE_SSE
984263bc 2162static void
f123d5a1 2163fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2164{
c9faf524
RG
2165 struct env87 *penv_87 = &sv_87->sv_env;
2166 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2167 int i;
2168
2169 /* FPU control/status */
2170 penv_87->en_cw = penv_xmm->en_cw;
2171 penv_87->en_sw = penv_xmm->en_sw;
2172 penv_87->en_tw = penv_xmm->en_tw;
2173 penv_87->en_fip = penv_xmm->en_fip;
2174 penv_87->en_fcs = penv_xmm->en_fcs;
2175 penv_87->en_opcode = penv_xmm->en_opcode;
2176 penv_87->en_foo = penv_xmm->en_foo;
2177 penv_87->en_fos = penv_xmm->en_fos;
2178
2179 /* FPU registers */
2180 for (i = 0; i < 8; ++i)
2181 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD
2182}
2183
2184static void
f123d5a1 2185set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2186{
c9faf524
RG
2187 struct env87 *penv_87 = &sv_87->sv_env;
2188 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2189 int i;
2190
2191 /* FPU control/status */
2192 penv_xmm->en_cw = penv_87->en_cw;
2193 penv_xmm->en_sw = penv_87->en_sw;
2194 penv_xmm->en_tw = penv_87->en_tw;
2195 penv_xmm->en_fip = penv_87->en_fip;
2196 penv_xmm->en_fcs = penv_87->en_fcs;
2197 penv_xmm->en_opcode = penv_87->en_opcode;
2198 penv_xmm->en_foo = penv_87->en_foo;
2199 penv_xmm->en_fos = penv_87->en_fos;
2200
2201 /* FPU registers */
2202 for (i = 0; i < 8; ++i)
2203 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2204}
642a6e88 2205#endif /* CPU_DISABLE_SSE */
984263bc
MD
2206
2207int
e9182c58 2208fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2209{
d64d3805
MD
2210 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2211 return EINVAL;
642a6e88 2212#ifndef CPU_DISABLE_SSE
984263bc 2213 if (cpu_fxsr) {
e9182c58
SZ
2214 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2215 (struct save87 *)fpregs);
984263bc
MD
2216 return (0);
2217 }
642a6e88 2218#endif /* CPU_DISABLE_SSE */
e9182c58 2219 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2220 return (0);
2221}
2222
2223int
e9182c58 2224set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2225{
642a6e88 2226#ifndef CPU_DISABLE_SSE
984263bc
MD
2227 if (cpu_fxsr) {
2228 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2229 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2230 return (0);
2231 }
642a6e88 2232#endif /* CPU_DISABLE_SSE */
e9182c58 2233 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2234 return (0);
2235}
2236
2237int
e9182c58 2238fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2239{
d64d3805
MD
2240 struct pcb *pcb;
2241
e9182c58 2242 if (lp == NULL) {
984263bc
MD
2243 dbregs->dr0 = rdr0();
2244 dbregs->dr1 = rdr1();
2245 dbregs->dr2 = rdr2();
2246 dbregs->dr3 = rdr3();
2247 dbregs->dr4 = rdr4();
2248 dbregs->dr5 = rdr5();
2249 dbregs->dr6 = rdr6();
2250 dbregs->dr7 = rdr7();
d64d3805
MD
2251 return (0);
2252 }
2253 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2254 return EINVAL;
2255 dbregs->dr0 = pcb->pcb_dr0;
2256 dbregs->dr1 = pcb->pcb_dr1;
2257 dbregs->dr2 = pcb->pcb_dr2;
2258 dbregs->dr3 = pcb->pcb_dr3;
2259 dbregs->dr4 = 0;
2260 dbregs->dr5 = 0;
2261 dbregs->dr6 = pcb->pcb_dr6;
2262 dbregs->dr7 = pcb->pcb_dr7;
984263bc
MD
2263 return (0);
2264}
2265
2266int
e9182c58 2267set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2268{
e9182c58 2269 if (lp == NULL) {
984263bc
MD
2270 load_dr0(dbregs->dr0);
2271 load_dr1(dbregs->dr1);
2272 load_dr2(dbregs->dr2);
2273 load_dr3(dbregs->dr3);
2274 load_dr4(dbregs->dr4);
2275 load_dr5(dbregs->dr5);
2276 load_dr6(dbregs->dr6);
2277 load_dr7(dbregs->dr7);
e9182c58
SZ
2278 } else {
2279 struct pcb *pcb;
2280 struct ucred *ucred;
2281 int i;
2282 uint32_t mask1, mask2;
2283
984263bc
MD
2284 /*
2285 * Don't let an illegal value for dr7 get set. Specifically,
2286 * check for undefined settings. Setting these bit patterns
2287 * result in undefined behaviour and can lead to an unexpected
2288 * TRCTRAP.
2289 */
2290 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2291 i++, mask1 <<= 2, mask2 <<= 2)
2292 if ((dbregs->dr7 & mask1) == mask2)
2293 return (EINVAL);
2294
e9182c58
SZ
2295 pcb = lp->lwp_thread->td_pcb;
2296 ucred = lp->lwp_proc->p_ucred;
2297
984263bc
MD
2298 /*
2299 * Don't let a process set a breakpoint that is not within the
2300 * process's address space. If a process could do this, it
2301 * could halt the system by setting a breakpoint in the kernel
2302 * (if ddb was enabled). Thus, we need to check to make sure
2303 * that no breakpoints are being enabled for addresses outside
2304 * process's address space, unless, perhaps, we were called by
2305 * uid 0.
2306 *
2307 * XXX - what about when the watched area of the user's
2308 * address space is written into from within the kernel
2309 * ... wouldn't that still cause a breakpoint to be generated
2310 * from within kernel mode?
2311 */
e9182c58 2312
895c1f85 2313 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD
2314 if (dbregs->dr7 & 0x3) {
2315 /* dr0 is enabled */
88181b08 2316 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2317 return (EINVAL);
2318 }
e9182c58 2319
984263bc
MD
2320 if (dbregs->dr7 & (0x3<<2)) {
2321 /* dr1 is enabled */
88181b08 2322 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2323 return (EINVAL);
2324 }
e9182c58 2325
984263bc
MD
2326 if (dbregs->dr7 & (0x3<<4)) {
2327 /* dr2 is enabled */
88181b08 2328 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2329 return (EINVAL);
2330 }
e9182c58 2331
984263bc
MD
2332 if (dbregs->dr7 & (0x3<<6)) {
2333 /* dr3 is enabled */
88181b08 2334 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2335 return (EINVAL);
2336 }
2337 }
e9182c58 2338
984263bc
MD
2339 pcb->pcb_dr0 = dbregs->dr0;
2340 pcb->pcb_dr1 = dbregs->dr1;
2341 pcb->pcb_dr2 = dbregs->dr2;
2342 pcb->pcb_dr3 = dbregs->dr3;
2343 pcb->pcb_dr6 = dbregs->dr6;
2344 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2345
984263bc
MD
2346 pcb->pcb_flags |= PCB_DBREGS;
2347 }
2348
2349 return (0);
2350}
2351
2352/*
2353 * Return > 0 if a hardware breakpoint has been hit, and the
2354 * breakpoint was in user space. Return 0, otherwise.
2355 */
2356int
2357user_dbreg_trap(void)
2358{
2359 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2360 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2361 int nbp; /* number of breakpoints that triggered */
2362 caddr_t addr[4]; /* breakpoint addresses */
2363 int i;
2364
2365 dr7 = rdr7();
2366 if ((dr7 & 0x000000ff) == 0) {
2367 /*
2368 * all GE and LE bits in the dr7 register are zero,
2369 * thus the trap couldn't have been caused by the
2370 * hardware debug registers
2371 */
2372 return 0;
2373 }
2374
2375 nbp = 0;
2376 dr6 = rdr6();
2377 bp = dr6 & 0x0000000f;
2378
2379 if (!bp) {
2380 /*
2381 * None of the breakpoint bits are set meaning this
2382 * trap was not caused by any of the debug registers
2383 */
2384 return 0;
2385 }
2386
2387 /*
2388 * at least one of the breakpoints were hit, check to see
2389 * which ones and if any of them are user space addresses
2390 */
2391
2392 if (bp & 0x01) {
2393 addr[nbp++] = (caddr_t)rdr0();
2394 }
2395 if (bp & 0x02) {
2396 addr[nbp++] = (caddr_t)rdr1();
2397 }
2398 if (bp & 0x04) {
2399 addr[nbp++] = (caddr_t)rdr2();
2400 }
2401 if (bp & 0x08) {
2402 addr[nbp++] = (caddr_t)rdr3();
2403 }
2404
2405 for (i=0; i<nbp; i++) {
2406 if (addr[i] <
88181b08 2407 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD
2408 /*
2409 * addr[i] is in user space
2410 */
2411 return nbp;
2412 }
2413 }
2414
2415 /*
2416 * None of the breakpoints are in user space.
2417 */
2418 return 0;
2419}
2420
2421
2422#ifndef DDB
2423void
2424Debugger(const char *msg)
2425{
26be20a0 2426 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD
2427}
2428#endif /* no DDB */
2429
984263bc
MD
2430#ifdef DDB
2431
2432/*
2433 * Provide inb() and outb() as functions. They are normally only
2434 * available as macros calling inlined functions, thus cannot be
2435 * called inside DDB.
2436 *
2437 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2438 */
2439
2440#undef inb
2441#undef outb
2442
2443/* silence compiler warnings */
2444u_char inb(u_int);
2445void outb(u_int, u_char);
2446
2447u_char
2448inb(u_int port)
2449{
2450 u_char data;
2451 /*
2452 * We use %%dx and not %1 here because i/o is done at %dx and not at
2453 * %edx, while gcc generates inferior code (movw instead of movl)
2454 * if we tell it to load (u_short) port.
2455 */
2456 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2457 return (data);
2458}
2459
2460void
2461outb(u_int port, u_char data)
2462{
2463 u_char al;
2464 /*
2465 * Use an unnecessary assignment to help gcc's register allocator.
2466 * This make a large difference for gcc-1.40 and a tiny difference
2467 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2468 * best results. gcc-2.6.0 can't handle this.
2469 */
2470 al = data;
2471 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2472}
2473
2474#endif /* DDB */
8a8d5d85
MD
2475
2476
2477
2478#include "opt_cpu.h"
8a8d5d85
MD
2479
2480
2481/*
2482 * initialize all the SMP locks
2483 */
2484
97359a5b 2485/* critical region when masking or unmasking interupts */
b1af91cb 2486struct spinlock_deprecated imen_spinlock;
8a8d5d85 2487
8a8d5d85 2488/* critical region for old style disable_intr/enable_intr */
b1af91cb 2489struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2490
2491/* critical region around INTR() routines */
b1af91cb 2492struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2493
2494/* lock region used by kernel profiling */
b1af91cb 2495struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2496
2497/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2498struct spinlock_deprecated com_spinlock;
8a8d5d85 2499
8a8d5d85 2500/* lock regions around the clock hardware */
b1af91cb 2501struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2502
2503/* lock around the MP rendezvous */
b1af91cb 2504struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2505
2506static void
2507init_locks(void)
2508{
2509 /*
b5d16701 2510 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD
2511 * This uses a LOGICAL cpu ID, ie BSP == 0.
2512 */
8a8d5d85 2513 cpu_get_initial_mplock();
41a01a4d 2514 /* DEPRECATED */
8a8d5d85 2515 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD
2516 spin_lock_init(&intr_spinlock);
2517 spin_lock_init(&mpintr_spinlock);
2518 spin_lock_init(&imen_spinlock);
2519 spin_lock_init(&smp_rv_spinlock);
2520 spin_lock_init(&com_spinlock);
2521 spin_lock_init(&clock_spinlock);
41a01a4d
MD
2522
2523 /* our token pool needs to work early */
2524 lwkt_token_pool_init();
8a8d5d85 2525}